5 4 3 2 1

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D D

Iris2 Schematics
Skylake-U
C 2015/05/20 C

REV : A00

B B

A DY : None Installed Iris SKL UMA A

UMA: UMA only installed Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

OPS: DISCRTE OPTIMUS installed Title

Cover Page
Size Document Number Rev
A3
Iris2 SKL-U X02
Date: Tuesday, September 08, 2015 Sheet 1 of 105
5 4 3 2 1
 5 4 3 2 1

Project code: CHARGER

BQ24770RUYR 44
Iris-2 14 --> 4PD02V010001 INPUTS OUTPUTS
PCB P/N: 14236-SF
Revision:A00 Iris2 SKL-U Block Diagram AD+
BT+
DCBATOUT

Thermal SYSTEM DC/DC

NUVOTON SMBUS RT6576DGQW-GP 45
IO Board: 14927 NCT7718W 79
Vinafix.com INPUTS OUTPUTS
3D3V_AUX_S5
DDR3L 5V_PWR_2
D D
1600 DCBATOUT 5V_S5
DDR3L 1333/1600MHz Channel A
GPU SODIMM A 3D3V_S5

AMD Intel CPU 12 CPU Core Power

VRAM(DDR3L) *4
MESO-LE (14"/15") PCIe x 4 Skylake U NCP81208MNTXG 46~50
33
2GB (Single Rank)
(23x23) 25W NCP81382MNTXG x 2
4GB (Dual Rank)
81,82,83,84
DDR3L 28W (UMA only) DDR3L
NCP81382MNTXG (23e)
76,77,78,79,80
15W (UMA&DIS) 1600
DDR3L 1333/1600MHz Channel B NCP81253MNTBG
DIS only SODIMM B INPUTS OUTPUTS
13 DCBATOUT VCC_CORE
SKL PCH-LP DCBATOUT +VCCGT
DCBATOUT +VCCGT (23e)
10 USB 2.0/1.1 ports
VGA Conn. VGA DP/VGA Converter LAN 10/100
6 USB 3.0 ports
REALTEK RTD2168-CGT PCIe x 1 RJ45 DCBATOUT+VCCSA
56 56 High Definition Audio RealTek RTL8106E
3 SATA ports 30
Conn.
Co-lay DDR3L SUS
6 PCIE ports TPS51716RUKR 51
HDMI LPC I/F INPUTS OUTPUTS
HDMI V1.4a
57 ACPI 5.0
PCB LAYER
DCBATOUT 1D35V_S3
L1:Top
C
PCIe x 1 NGFF WLAN L2:VCC 0D65V_S0 C

L3:Signal
14.0"/15.6" (HD) eDP 802.11b/g/n L4:Signal CPU VCCIO 1V
USB2.0 x 1 802.11ac L5:VCC TPS22961DNYT 52
BT 4.0 1x1 61 L6:Signal INPUTS OUTPUTS
L7:GND 3D3V_S5 +VCCIO_VR
L8:bottom

LPC BUS CPU VCCPRIM_CORE

LPC debug port
Camera (HD) 65 1V
USB2.0 x 1
52
52
D-MIC INPUTS OUTPUTS
SMBUS Thermal 1D0V_PWR VCCPRIM_CORE
NUVOTON
KBC NCT7718W 26
SMSC
CPU DCDC-V1D00A
HDA SY8208DQNC 53

CODEC MEC1404-NU-GP Fan Control INPUTS OUTPUTS

2CH SPEAKER 24 BCD
(2CH 2W/4ohm) AP2113MTR 26 DCBATOUT 1D0V_S5
Realtek HDA
ALC3246-CG SPI LDO-V1D5V
S-1339D15-M5001 54
27
B
FAN INPUTS OUTPUTS B
PS2 Int. 26
MIC_IN/GND 3D3V_S5 1D5V_S0
SPI Flash ROM KB HSIO PWR
8MB 25 17 LDO-V1D8V
HP_R/L APL5930KAI-TRG 54
29 INPUTS OUTPUTS
Universal Jack INPUTS OUTPUTS
1D0V_S5 +VCCMPHYGTAON_1P0_LS_SIP
Flash ROM 3D3V_S5 1D8V_S5
USB2(USB2.0) USB2.0 x 1
4MB 25 VCCSTG 5V/3V S0
M5938ARD1U 40 G5016KD1U 40
IO Board NON Precision Touchpad
I2C INPUTS OUTPUTS INPUTS OUTPUTS
(14927-SB) 65
1D0V_S5 +V1.00DX 5V_S5 5V_S0
3D3V_S5 3D3V_S0

USB2.0 x 1 VCCST EOPIO/EDRAM (23e)

USB3(USB2.0) M5938ARD1U 40 TPS22961DNYT 41
SATA(Gen3) x 1 9.5 mm HDD INPUTS OUTPUTS INPUTS OUTPUTS
60 +V1.00U_CPU
1D0V_S5 +V_EDRAM_VR
1D0V_S5 1D0V_S5 +V_EOPIO_VR

3D3V VGA
AO3419L 86
SATA(Gen1) x 1 ODD INPUTS OUTPUTS
3D3V_S0 3D3V_VGA_S0
A 60 A
Left side
USB2.0 x 1
USB1(USB3.0) CardReader Iris SKL UMA

USB3.0 x 1 SD 3.0 SD Card Slot Wistron Corporation

USB2.0 x 1 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Realtek Taipei Hsien 221, Taiwan, R.O.C.
RTS5170 33
Title
Block Diagram
Size Document Number Rev
C Iris2 SKL-U A00
Date: Tuesday, May 26, 2015 Sheet 2 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU

Vinafix.com
D D

C C

(Blanking)

B B

A Iris SKL UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
(Reserved)
Size Document Number Rev
A3
Iris2 SKL-U A00
Date: Tuesday, May 26, 2015 Sheet 3 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU

#544669 CRB Rev0.52
+VCCST_CPU

1
R419
+VCCSTG = 1.0 V +VCCSTG = 1.0 V
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1KR2J-1-GP
+VCCSTG

2
R420 +VCCSTG
PCH_THERMTRIP
D 1
DY 2 H_THERMTRIP# [40] D

1
R401 Do Not Stuff XDP_TMS 1 DY 2
[PECI] and [PROCHOT#] Rb 1KR2J-1-GP XDP_TDI Do Not Stuff 1 DY 2 R421
Impedance control: 50 ohm TP401 CPU1D 4 OF 20 Do Not Stuff R422
Do Not Stuff XDP_TDO_CPU 1 DY 2

2
1 H_CATERR# D63 SKYLAKE_ULT Do Not Stuff R423
CATERR# PH in P.99
[24] H_PECI A54 PECI
499R2F-2-GP 1 R403 2 H_PROCHOT#_R C65 JTAG
[24,44,46] H_PROCHOT# PROCHOT#
PCH_THERMTRIP C63 PCH_JTAG_TDI 1 2
Ra THERMTRIP#
Do Not Stuff TP402 1SKTOCC# A65 SKTOCC# PROC_TCK B61 XDP_TCLK [99] 51R2J-2-GP R408
[99] XDP_BPM[3:0] CPU MISC D60 XDP_TDI [99] PCH_JTAG_TDO 1 2
XDP_BPM0 PROC_TDI 51R2J-2-GP R409
C55 BPM#[0] PROC_TDO A61 XDP_TDO_CPU [99]
#543016 Rev0.7: Ra = 500 ohm / Rb = 1k ohm XDP_BPM1 D55 BPM#[1] PROC_TMS C60 XDP_TMS [99] PCH_JTAG_TMS 1 2
#544669 Rev0.52: XDP_BPM2 B54 B59 XDP_TRST# [99] 51R2J-2-GP R416
BPM#[2] PROC_TRST#
Ra = 56 ohm (TO BE CHANGED TO 100 OHMS) / Rb = 62 ohm and 150 ohmXDP_BPM3 C56 BPM#[3]
XDP_TCK_JTAGX 1 DY 2
Do Not Stuff R417
TP403 1 GPP_E3/CPU_GP0 A6 B56 PCH_JTAG_TCK [99]
Do Not Stuff GPP_E3/CPU_GP0 PCH_JTAG_TCK
[24,55] TOUCH_PANEL_INTR# A7 GPP_E7/CPU_GP1 PCH_JTAG_TDI D59 PCH_JTAG_TDI [99]
R404 1 2 Do Not Stuff TOUCHPAD_INTR# XDP_TRST# R402 2 Do Not Stuff
[24,65] INT_TP#
GPP_B4/CPU_GP3
BA5 GPP_B3/CPU_GP2 PCH_JTAG_TDO A56 PCH_JTAG_TDO [99]
XDP_TCLK R406
1 DY
Do Not Stuff TP404 1 AY5 GPP_B4/CPU_GP3 PCH_JTAG_TMS C59 PCH_JTAG_TMS [99] 1 2 51R2J-2-GP
C61 XDP_TRST# [99] PCH_JTAG_TCK R407 1 DY 2 Do Not Stuff
CPU_POPIRCOMP PCH_TRST#
2 1 AT16 PROC_POPIRCOMP JTAGX A59 XDP_TCK_JTAGX [99]
49D9R2F-GP 2 R412 1 PCH_POPIRCOMP AU16
49D9R2F-GP 2 R413 EDRAM_OPIO_RCOMP H66 PCH_OPIRCOMP
1 OPCE_RCOMP
49D9R2F-GP 2 R414 1 EOPIO_RCOMP H65
49D9R2F-GP R415 OPC_RCOMP

SKYLAKE-GP
C C

071.SKYLA.000U

(#543016) PROCHOT# Routing Guidelines

B B

M1,2,3,4,5: <3 inches

M6: 1-11 inches
MCPU: 0.3-1.5 inches
Mt <0.3 mils
Main route(M1+M2+M3+M4+M5+M6+MCPU): 1-12 inches

A Iris SKL UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CPU_(JTAG/CPU SIDE BAND)
Size Document Number Rev
A3 X02
Iris2 SKL-U
Date: W ednesday, September 09, 2015 Sheet 4 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU

DDR3L ball type: Interleaved Type
[12] M_A_DQ[63:0]
[13] M_B_DQ[63:0]

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D D

CPU1C 3 OF 20
CPU1B 2 OF 20

SKYLAKE_ULT M_A_DQ32 AY39 SKYLAKE_ULT AN45

M_A_DQ0 M_A_DQ33 DDR0_DQ[32]/DDR1_DQ[0] DDR1_CKN[0] M_B_CLK#0 [13]
AL71 AU53 AW39 AN46
M_A_DQ1 DDR0_DQ[0] DDR0_CKN[0] M_A_CLK#0 [12] M_A_DQ34 DDR0_DQ[33]/DDR1_DQ[1] DDR1_CKN[1] M_B_CLK#1 [13]
AL68 AT53 AY37 AP45
M_A_DQ2 DDR0_DQ[1] DDR0_CKP[0] M_A_CLK0 [12] M_A_DQ35 DDR0_DQ[34]/DDR1_DQ[2] DDR1_CKP[0] M_B_CLK0 [13]
AN68 AU55 AW37 AP46
M_A_DQ3 DDR0_DQ[2] DDR0_CKN[1] M_A_CLK#1 [12] M_A_DQ36 DDR0_DQ[35]/DDR1_DQ[3] DDR1_CKP[1] M_B_CLK1 [13]
AN69
DDR0_DQ[3] DDR0_CKP[1]
AT55
M_A_CLK1 [12] M_A_DQ[32:39] BB39
DDR0_DQ[36]/DDR1_DQ[4]
M_A_DQ[0:7] M_A_DQ4 AL70 M_A_DQ37 BA39 AN56
M_A_DQ5 DDR0_DQ[4] M_A_DQ38 DDR0_DQ[37]/DDR1_DQ[5] DDR1_CKE[0] M_B_CKE0 [13]
AL69 BA56 BA37 AP55
M_A_DQ6 DDR0_DQ[5] DDR0_CKE[0] M_A_CKE0 [12] M_A_DQ39 DDR0_DQ[38]/DDR1_DQ[6] DDR1_CKE[1] M_B_CKE1 [13]
AN70 BB56 BB37 AN55
M_A_DQ7 DDR0_DQ[6] DDR0_CKE[1] M_A_CKE1 [12] M_A_DQ40 DDR0_DQ[39]/DDR1_DQ[7] DDR1_CKE[2]
AN71 AW56 AY35 AP53
M_A_DQ8 DDR0_DQ[7] DDR0_CKE[2] M_A_DQ41 DDR0_DQ[40]/DDR1_DQ[8] DDR1_CKE[3]
AR70 AY56 AW35
M_A_DQ9 DDR0_DQ[8] DDR0_CKE[3] M_A_DQ42 DDR0_DQ[41]/DDR1_DQ[9]
AR68 AY33 BB42
M_A_DQ10 DDR0_DQ[9] M_A_DQ43 DDR0_DQ[42]/DDR1_DQ[10] DDR1_CS#[0] M_B_CS#0 [13]
AU71 AU45 AW33 AY42
M_A_DQ11 DDR0_DQ[10] DDR0_CS#[0] M_A_CS#0 [12] M_A_DQ44 DDR0_DQ[43]/DDR1_DQ[11] DDR1_CS#[1] M_B_CS#1 [13]
AU68
DDR0_DQ[11] DDR0_CS#[1]
AU43
M_A_CS#1 [12] M_A_DQ[40:47] BB35
DDR0_DQ[44]/DDR1_DQ[12] DDR1_ODT[0]
BA42
M_B_DIMB_ODT0 [13]
M_A_DQ[8:15] M_A_DQ12 AR71 AT45 M_A_DQ45 BA35 AW42
M_A_DQ13 DDR0_DQ[12] DDR0_ODT[0] M_A_DIMA_ODT0 [12] M_A_DQ46 DDR0_DQ[45]/DDR1_DQ[13] DDR1_ODT[1] M_B_DIMB_ODT1 [13]
AR69 AT43 BA33
M_A_DQ14 DDR0_DQ[13] DDR0_ODT[1] M_A_DIMA_ODT1 [12] M_A_DQ47 DDR0_DQ[46]/DDR1_DQ[14] M_B_A5
AU70 BB33 AY48
M_A_DQ15 DDR0_DQ[14] M_A_A5 M_B_DQ32 DDR0_DQ[47]/DDR1_DQ[15] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] M_B_A9
AU69 BA51 AU40 AP50
M_B_DQ0 DDR0_DQ[15] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] M_A_A9 M_B_DQ33 DDR1_DQ[32]/DDR1_DQ[16] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] M_B_A6
AF65 BB54 AT40 BA48
M_B_DQ1 DDR1_DQ[0]/DDR0_DQ[8]DDR0_DQ[16] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] M_A_A6 M_B_DQ34 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] M_B_A8
AF64 BA52 AT37 BB48
M_B_DQ2 DDR1_DQ[1]/DDR0_DQ[9]DDR0_DQ[17] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] M_A_A8 M_B_DQ35 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] M_B_A7
AK65 AY52 AU37 AP48
M_B_DQ3 DDR1_DQ[2]/DDR0_DQ[10]DDR0_DQ[18] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] M_A_A7 M_B_DQ36 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
AK64
DDR1_DQ[3]/DDR0_DQ[11]DDR0_DQ[19] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
AW52 M_B_DQ[32:39] AR40
DDR1_DQ[36]/DDR1_DQ[20] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
AP52 M_B_BS2 [13]
M_B_DQ[0:7] M_B_DQ4 AF66 AY55 M_B_DQ37 AP40 AN50 M_B_A12
DDR1_DQ[4]/DDR0_DQ[12]DDR0_DQ[20] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] M_A_BS2 [12] DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
M_B_DQ5 AF67 AW54 M_A_A12 M_B_DQ38 AP37 AN48 M_B_A11
M_B_DQ6 DDR1_DQ[5]/DDR0_DQ[13]DDR0_DQ[21]DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] M_A_A11 M_B_DQ39 DDR1_DQ[38]/DDR1_DQ[22] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] M_B_A15
AK67 BA54 AR37 AN53
M_B_DQ7 DDR1_DQ[6]/DDR0_DQ[14]DDR0_DQ[22]DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] M_A_A15 M_B_DQ40 DDR1_DQ[39]/DDR1_DQ[23] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# M_B_A14
AK66 BA55 AT33 AN52
M_B_DQ8 DDR1_DQ[7]/DDR0_DQ[15]DDR0_DQ[23] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# M_A_A14 M_B_DQ41 DDR1_DQ[40]/DDR1_DQ[24] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
AF70 AY54 AU33
M_B_DQ9 DDR1_DQ[8]/DDR0_DQ[24] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] M_B_DQ42 DDR1_DQ[41]/DDR1_DQ[25] M_B_A13
AF68 AU30 BA43
M_B_DQ10 DDR1_DQ[9]/DDR0_DQ[25] M_A_A13 M_B_DQ43 DDR1_DQ[42]/DDR1_DQ[26] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
AH71 AU46 AT30 AY43 M_B_CAS# [13]
M_B_DQ11 DDR1_DQ[10]/DDR0_DQ[26] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] M_B_DQ44 DDR1_DQ[43]/DDR1_DQ[27] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]
AH68
DDR1_DQ[11]/DDR0_DQ[27] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]
AU48 M_A_CAS# [12] M_B_DQ[40:47] AR33
DDR1_DQ[44]/DDR1_DQ[28] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
AY44 M_B_WE# [13]
M_B_DQ[8:15] M_B_DQ12 AF71 AT46 M_B_DQ45 AP33 AW44
DDR1_DQ[12]/DDR0_DQ[28] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] M_A_WE# [12] DDR1_DQ[45]/DDR1_DQ[29] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] M_B_RAS# [13]
M_B_DQ13 AF69 AU50 M_A_RAS# [12] M_B_DQ46 AR30 BB44 M_B_BS0 [13]
M_B_DQ14 DDR1_DQ[13]/DDR0_DQ[29] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] M_B_DQ47 DDR1_DQ[46]/DDR1_DQ[30] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] M_B_A2
AH70 AU52 M_A_BS0 [12] AP30 AY47
M_B_DQ15 DDR1_DQ[14]/DDR0_DQ[30] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] M_A_A2 M_A_DQ48 DDR1_DQ[47]/DDR1_DQ[31] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
AH69 AY51 AY31 BA44 M_B_BS1 [13]
M_A_DQ16 DDR1_DQ[15]/DDR0_DQ[31] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] M_A_DQ49 DDR0_DQ[48]/DDR1_DQ[32] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] M_B_A10
BB65 AT48 M_A_BS1 [12] AW31 AW46
M_A_DQ17 DDR0_DQ[16]/DDR0_DQ[32] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] M_A_A10 M_A_DQ50 DDR0_DQ[49]/DDR1_DQ[33] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] M_B_A1
AW65 AT50 AY29 AY46
M_A_DQ18 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] M_A_A1 M_A_DQ51 DDR0_DQ[50]/DDR1_DQ[34] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] M_B_A0
C AW63
DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
BB50 M_A_DQ[48:55] AW29
DDR0_DQ[51]/DDR1_DQ[35] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
BA46 C
M_A_DQ[16:23] M_A_DQ19 AY63 AY50 M_A_A0 M_A_DQ52 BB31 BB46 M_B_A3
M_A_DQ20 DDR0_DQ[19]/DDR0_DQ[35] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] M_A_A3 M_A_DQ53 DDR0_DQ[52]/DDR1_DQ[36] DDR1_MA[3] M_B_A4
BA65 BA50 BA31 BA47
M_A_DQ21 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[3] M_A_A4 M_A_DQ54 DDR0_DQ[53]/DDR1_DQ[37] DDR1_MA[4]
AY65 BB52 BA29
M_A_DQ22 DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[4] M_A_DQ55 DDR0_DQ[54]/DDR1_DQ[38] M_A_DQS_DN4
BA63 BB29 BA38
M_A_DQ23 DDR0_DQ[22]/DDR0_DQ[38] M_A_DQS_DN0 M_A_DQ56 DDR0_DQ[55]/DDR1_DQ[39] DDR0_DQSN[4]/DDR1_DQSN[0] M_A_DQS_DP4 M_A_DQS4
BB63 AM70 AY27 AY38
M_A_DQ24 DDR0_DQ[23]/DDR0_DQ[39] DDR0_DQSN[0] M_A_DQS_DP0 M_A_DQS0 M_A_DQ57 DDR0_DQ[56]/DDR1_DQ[40] DDR0_DQSP[4]/DDR1_DQSP[0] M_A_DQS_DN5
BA61 AM69 AW27 AY34
M_A_DQ25 DDR0_DQ[24]/DDR0_DQ[40] DDR0_DQSP[0] M_A_DQS_DN1 M_A_DQ58 DDR0_DQ[57]/DDR1_DQ[41] DDR0_DQSN[5]/DDR1_DQSN[1] M_A_DQS_DP5 M_A_DQS5
AW61 AT69 AY25 BA34
M_A_DQ26 DDR0_DQ[25]/DDR0_DQ[41] DDR0_DQSN[1] M_A_DQS_DP1 M_A_DQS1 M_A_DQ59 DDR0_DQ[58]/DDR1_DQ[42] DDR0_DQSP[5]/DDR1_DQSP[1] M_B_DQS_DN4
BB59
DDR0_DQ[26]/DDR0_DQ[42] DDR0_DQSP[1]
AT70 M_A_DQ[56:63] AW25
DDR0_DQ[59]/DDR1_DQ[43] DDR1_DQSN[4]/DDR1_DQSN[2]
AT38
M_A_DQ[24:31] M_A_DQ27 AW59 AH66 M_B_DQS_DN0 M_A_DQ60 BB27 AR38 M_B_DQS_DP4 M_B_DQS4
M_A_DQ28 DDR0_DQ[27]/DDR0_DQ[43] DDR1_DQSN[0]/DDR0_DQ[2] M_B_DQS_DP0 M_A_DQ61 DDR0_DQ[60]/DDR1_DQ[44] DDR1_DQSP[4]/DDR1_DQSP[2] M_B_DQS_DN5
BB61
DDR0_DQ[28]/DDR0_DQ[44] DDR1_DQSP[0]/DDR0_DQ[2]
AH65 M_B_DQS0 BA27
DDR0_DQ[61]/DDR1_DQ[45] DDR1_DQSN[5]/DDR1_DQSN[3]
AT32
M_A_DQ29 AY61 AG69 M_B_DQS_DN1 M_A_DQ62 BA25 AR32 M_B_DQS_DP5 M_B_DQS5
M_A_DQ30 DDR0_DQ[29]/DDR0_DQ[45] DDR1_DQSN[1]/DDR0_DQ[3] M_B_DQS_DP1 M_A_DQ63 DDR0_DQ[62]/DDR1_DQ[46] DDR1_DQSP[5]/DDR1_DQSP[3] M_A_DQS_DN6
BA59
DDR0_DQ[30]/DDR0_DQ[46] DDR1_DQSP[1]/DDR0_DQ[3]
AG70 M_B_DQS1 BB25
DDR0_DQ[63]/DDR1_DQ[47] DDR0_DQSN[6]/DDR1_DQSN[4]
BA30
M_A_DQ31 AY59 BA64 M_A_DQS_DN2 M_B_DQ48 AU27 AY30 M_A_DQS_DP6 M_A_DQS6
M_B_DQ16 DDR0_DQ[31]/DDR0_DQ[47] DDR0_DQSN[2]/DDR0_DQSN[4] M_A_DQS_DP2 M_A_DQS2 M_B_DQ49 DDR1_DQ[48] DDR0_DQSP[6]/DDR1_DQSP[4] M_A_DQS_DN7 1D35V_S3
AT66 AY64 AT27 AY26
M_B_DQ17 DDR1_DQ[16]/DDR0_DQ[48] DDR0_DQSP[2]/DDR0_DQSP[4] M_A_DQS_DN3 M_B_DQ50 DDR1_DQ[49] DDR0_DQSN[7]/DDR1_DQSN[5] M_A_DQS_DP7 M_A_DQS7
AU66 AY60 AT25 BA26
M_B_DQ18 DDR1_DQ[17]/DDR0_DQ[49] DDR0_DQSN[3]/DDR0_DQSN[5] M_A_DQS_DP3 M_A_DQS3 M_B_DQ51 DDR1_DQ[50] DDR0_DQSP[7]/DDR1_DQSP[5] M_B_DQS_DN6
AP65
DDR1_DQ[18]/DDR0_DQ[50] DDR0_DQSP[3]/DDR0_DQSP[5]
BA60 M_B_DQ[48:55] AU25
DDR1_DQ[51] DDR1_DQSN[6]
AR25

1
M_B_DQ[16:23] M_B_DQ19 AN65 AR66 M_B_DQS_DN2 M_B_DQ52 AP27 AR27 M_B_DQS_DP6 M_B_DQS6
DDR1_DQ[19]/DDR0_DQ[51] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQ[52] DDR1_DQSP[6]
M_B_DQ20 AN66
DDR1_DQ[20]/DDR0_DQ[52] DDR1_DQSP[2]/DDR0_DQSP[6]
AR65 M_B_DQS_DP2 M_B_DQS2 M_B_DQ53 AN27
DDR1_DQ[53] DDR1_DQSN[7]
AR22 M_B_DQS_DN7 R505
M_B_DQ21 AP66 AR61 M_B_DQS_DN3 M_B_DQ54 AN25 AR21 M_B_DQS_DP7 M_B_DQS7 470R2F-GP
DDR1_DQ[21]/DDR0_DQ[53] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQ[54] DDR1_DQSP[7]
M_B_DQ22 AT65
DDR1_DQ[22]/DDR0_DQ[54] DDR1_DQSP[3]/DDR0_DQSP[7]
AR60 M_B_DQS_DP3 M_B_DQS3 M_B_DQ55 AP25
DDR1_DQ[55]
M_B_DQ23 AU65 M_B_DQ56 AT22 AN43

2
M_B_DQ24 DDR1_DQ[23]/DDR0_DQ[55] M_B_DQ57 DDR1_DQ[56] DDR1_ALERT# DDR1_PAR TP502 Do Not Stuff R504
AT61 AW50 AU22 AP43 1
M_B_DQ25 DDR1_DQ[24]/DDR0_DQ[56] DDR0_ALERT# DDR0_PAR TP501 Do Not Stuff M_B_DQ58 DDR1_DQ[57] DDR1_PAR SM_DRAMRST#
AU61 AT52 1 AU21 AT13 1 2 DDR3_DRAMRST# [12,13]
M_B_DQ26 DDR1_DQ[25]/DDR0_DQ[57] DDR0_PAR M_B_DQ59 DDR1_DQ[58] DRAM_RESET# SM_RCOMP_0
AP60
DDR1_DQ[26]/DDR0_DQ[58] M_B_DQ[56:63] AT21
DDR1_DQ[59] DDR_RCOMP[0]
AR18 1 R501 2 121R2F-GP Do Not Stuff
M_B_DQ[24:31] M_B_DQ27 AN60 AY67 M_B_DQ60 AN22 AT18 SM_RCOMP_1 1 R502 2 80D6R2F-L-GP
DDR1_DQ[27]/DDR0_DQ[59] DDR_VREF_CA V_SM_VREF_CNT [42] DDR1_DQ[60] DDR_RCOMP[1]
M_B_DQ28 AN61 AY68 M_B_DQ61 AP22 AU18 SM_RCOMP_2 1 R503 2 100R2F-L1-GP-U
DDR1_DQ[28]/DDR0_DQ[60] DDR0_VREF_DQ M_VREF_DQ_DIM0 [42] DDR1_DQ[61] DDR_RCOMP[2]
M_B_DQ29 AP61 BA67 M_B_DQ62 AP21
DDR1_DQ[29]/DDR0_DQ[61] DDR1_VREF_DQ M_VREF_DQ_DIM1 [42] DDR1_DQ[62]
M_B_DQ30 AT60 M_B_DQ63 AN21 DDR CH - B

2
M_B_DQ31 DDR1_DQ[30]/DDR0_DQ[62] DDR1_DQ[63]
AU60
DDR1_DQ[31]/DDR0_DQ[63] DDR_VTT_CNTL
AW67 #543016
DDR CH - A SM_PGCNTL [51]
SKYLAKE-GP
SKYLAKE-GP DYD502
Do Not Stuff
071.SKYLA.000U Do Not Stuff

1
071.SKYLA.000U Layout Note:
Design Guideline:
SM_RCOMP keep routing length less than 500 mils.
DQ Bit Swapping is allowed within the same byte, and Byte Swapping is allowed within the same channel.
Clock (CLK and CLK#) and Strobe (DQS and DQS#) differential signal swapping within a pair is not allowed. Also differential close to CPU
B B
clock pair to clock pair swapping within a channel is not allowed.

M_B_A0 M_B_A[15:0] [13]

M_A_A0 M_A_A[15:0] [12] M_B_A1
M_A_A1 M_B_A2
M_A_A2 M_B_A3
PDG: DDR/ODT M_A_A3
M_A_A4
M_B_A4
M_B_A5
M_A_A5 M_B_A6
M_A_A6 M_B_A7
M_A_A7 M_B_A8
M_A_A8 M_B_A9
M_A_A9 M_B_A10
M_A_A10 M_B_A11
M_A_A11 M_B_A12
M_A_A12 M_B_A13
M_A_A13 M_B_A14
M_A_A14 M_B_A15
M_A_A15

M_A_DQS_DN[7:0] [12] M_B_DQS_DN[7:0] [13]

M_B_DQS_DN0
M_A_DQS_DN0 M_B_DQS_DN1
M_A_DQS_DN1 M_B_DQS_DN2
M_A_DQS_DN2 M_B_DQS_DN3
M_A_DQS_DN3 M_B_DQS_DN4
M_A_DQS_DN4 M_B_DQS_DN5
M_A_DQS_DN5 M_B_DQS_DN6
M_A_DQS_DN6 M_B_DQS_DN7
M_A_DQS_DN7
M_B_DQS_DP[7:0] [13]
M_B_DQS_DP0
M_B_DQS_DP1
M_B_DQS_DP2
M_A_DQS_DP[7:0] [12]
M_A_DQS_DP0 M_B_DQS_DP3
M_A_DQS_DP1 M_B_DQS_DP4
M_A_DQS_DP2 M_B_DQS_DP5
M_A_DQS_DP3 M_B_DQS_DP6
A M_A_DQS_DP4 M_B_DQS_DP7 A
M_A_DQS_DP5
M_A_DQS_DP6
M_A_DQS_DP7

Iris SKL UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(DDR)
Size Document Number Rev
A2 A00
Iris2 SKL-U
Date: Wednesday, September 09, 2015 Sheet 5 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU CPU1S 19 OF 20

RESERVED SIGNALS-1
[99] CFG[19:0] SKYLAKE_ULT
CFG0 E68 BB68 RSVD_TP_BB68 1
CFG1 CFG[0] RSVD_TP_BB68 RSVD_TP_BB69 TP603 Do Not Stuff
B67 BB69 1
CFG2 CFG[1] RSVD_TP_BB69 TP604 Do Not Stuff
D65
CFG3 CFG[2] RSVD_TP_AK13
D67 AK13 1
CFG4 CFG[3] RSVD_TP_AK13 RSVD_TP_AK12 TP605 Do Not Stuff
E70 AK12 1
CFG5 CFG[4] RSVD_TP_AK12 TP606 Do Not Stuff
C68
CFG6 CFG[5]
D68 BB2
CFG7 CFG[6] RSVD_BB2
C67 BA3
CFG8 CFG[7] RSVD_BA3
F71
CFG9 CFG[8]

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G69
CFG10 CFG[9] TP5_AU5
F70 AU5 1
CFG11 CFG[10] TP5 TP6_AT5 TP607 Do Not Stuff
G68 AT5 1
CFG12 CFG[11] TP6 TP608 Do Not Stuff
H70
CFG13 CFG[12]
G71
CFG14 CFG[13]
D H69 D5 D
CFG15 CFG[14] RSVD_D5
G70 D4
CFG[15] RSVD_D4
B2
CFG16 RSVD_B2
E63 C2
CFG17 CFG[16] RSVD_C2
F63
CFG[17]
B3
CFG18 RSVD_B3
E66 A3
CFG19 CFG[18] RSVD_A3
F66
CFG[19]
AW1
49D9R2F-GP CFG_RCOMP RSVD_AW1
2 1 R601 E60
CFG_RCOMP
E1
RSVD_E1
[99] ITP_PMODE E8 E2
ITP_PMODE RSVD_E2
AY2 BA4
RSVD_AY2 RSVD_BA4
AY1 BB4
RSVD_AY1 RSVD_BB4
D1 A4
RSVD_D1 RSVD_A4
D3 C4
RSVD_D3 RSVD_C4
K46 BB5 TP4_BB5 1
RSVD_K46 TP4 TP609 Do Not Stuff
K45
RSVD_K45
A69
RSVD_A69
AL25 B69
RSVD_AL25 RSVD_B69
AL27
RSVD_AL27
AY3
RSVD_AY3
C71
RSVD_C71
B70 D71
RSVD_B70 RSVD_D71
C70
RSVD_C70
F60
RSVD_F60
C54
RSVD_C54
A52 D54
RSVD_A52 RSVD_D54
1 RSVD_TP_BA70 BA70 AY4 TP1_AY4 1
Do Not Stuff TP601 RSVD_TP_BA68 RSVD_TP_BA70 TP1 TP2_BB3 TP610 Do Not Stuff
1 BA68 BB3 1
Do Not Stuff TP602 RSVD_TP_BA68 TP2 TP611 Do Not Stuff
J71 AY71 VSS_AY71 1 R602 2 #54469 CRB.
RSVD_J71 VSS_AY71 ZVM# Do Not Stuff 1
J68 AR56

Do Not Stuff TP612

1
1
RSVD_F65
RSVD_G65
F65
G65
RSVD_J68

VSS_F65
VSS_G65
RSVD_TP_AW71
RSVD_TP_AW70
ZVM#

RSVD_AW71
RSVD_AW70
AW71
AW70
RSVD_TP_AW71
RSVD_TP_AW70
1
1
TP616 Do Not Stuff

TP614 Do Not Stuff +VCCST_CPU

CFG TERMINATIONS #544669 Rev0.52 (CRB)
Do Not Stuff TP613 TP615 Do Not Stuff 20140807 david
C F61 AP56 MSM# 1 C
RSVD_F61 MSM# TP617 Do Not Stuff
E61 C64
RSVD_E61 PROC_SELECT#
PROC_SELECT# 1 2
R603
SKYLAKE-GP 100KR2J-1-GP

PCH strap pin: 071.SKYLA.000U

CFG3
1

[BDW Only]PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)

R604
Do Not Stuff 0 : ENABLED
DY
CFG[3] SET DFX ENABLED BIT IN DEBUG INTERFACE MSR
2

1 : DISABLED

(#543016)
CFG4
1

DISPLAY PORT PRESENCE STRAP

R605
1KR2J-1-GP
0 : ENABLED
CFG[4]
An external Display Port device is connected to the Embedded Display Port.
2

1 : DISABLED (Default)
No Physical Display Port attached to Embedded DisplayPort*. No connect for disable.

SKL(#543016):
Processor strap CFG[4] should be pulled low to enable embedded DisplayPort*
B B

A A

Iris SKL UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(RESERVED)
Size Document Number Rev
A2 A00
Iris2 SKL-U
Date: Wednesday, September 09, 2015 Sheet 6 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU

CPU1L 12 OF 20 CPU1M 13 OF 20
VCC_CORE VCC_CORE +VCCGT
CPU POWER 1 OF 4
+VCCGT CPU POWER 2 OF 4
A30 G32 N70
VCC_A30 VCC_G32 VCCGT
A34 G33 A48 N71
VCC_A34 SKYLAKE_ULT VCC_G33 VCCGT SKYLAKE_ULT VCCGT +VDDQ_CPU_CLK 1D35V_S3
A39 G35 A53 R63
VCC_A39 VCC_G35 VCCGT VCCGT
A44 G37 A58 R64
VCC_A44 VCC_G37 VCCGT VCCGT
AK33 G38 A62 R65
VCC_AK33 VCC_G38 VCCGT VCCGT
AK35 G40 A66 R66
VCC_AK35 VCC_G40 VCCGT VCCGT

1
AK37 G42 AA63 R67
VCC_AK37 VCC_G42 VCCGT VCCGT C722
AK38 J30 AA64 R68 DY

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VCC_AK38 VCC_J30 VCCGT VCCGT Do Not Stuff
AK40 J33 AA66 R69

2
VCC_AK40 VCC_J33 VCCGT VCCGT

1
AL33 J37 AA67 R70
VCC_AL33 VCC_J37 VCCGT VCCGT C719 +VCCIO
AL37 J40 AA69 R71
VCC_AL37 VCC_J40 VCCGT VCCGT CPU1N 14 OF 20
AL40 K33 AA70 T62 SC1U10V2KX-1GP

2
VCC_AL40 VCC_K33 VCCGT VCCGT +VCCIO(ICCMAX.=2.73A
AM32 K35 AA71 U65 CPU POWER 3 OF 4
VCC_AM32 VCC_K35 VCCGT VCCGT
AM33 K37 AC64 U68
VCC_AM33 VCC_K37 VCCGT VCCGT
AM35 K38 AC65 U71 AU23 AK28
D VCC_AM35 VCC_K38 VCCGT VCCGT VDDQ_AU23 VCCIO D
AM37 K40 AC66 W63 AU28 AK30
VCC_AM37 VCC_K40 VCCGT VCCGT VDDQ_AU28 SKYLAKE_ULT VCCIO
AM38 K42 AC67 W64 AU35 AL30
VCC_AM38 VCC_K42 VCCGT VCCGT VDDQ_AU35 VCCIO
G30 K43 AC68 W65 AU42 AL42
VCC_G30 VCC_K43 VCCGT VCCGT VDDQ_AU42 VCCIO
AC69 W66 BB23 AM28
Do Not Stuff TP701 +VCCCOREG0 VCCGT VCCGT VDDQ_BB23 VCCIO
1 K32 E32 AC70 W67 BB32 AM30
VCCG0 RSVD_K32 VCC_SENSE VCC_SENSE [46] VCCGT VCCGT VDDQ_BB32 VCCIO +VCCSA
E33 AC71 W68 BB41 AM42
Do Not Stuff TP702 +VCCCOREG1 VSS_SENSE VSS_SENSE [46] VCCGT VCCGT VDDQ_BB41 VCCIO
1 AK32 J43 W69 BB47
VCCG1 RSVD_AK32 H_CPU_SVIDALRT# VCCGT VCCGT +VDDQ_CPU_CLK VDDQ_BB47
B63 J45 W70 BB51 AK23
VIDALERT# H_CPU_SVIDCLK VCCGT VCCGT VDDQ_BB51 VCCSA
AB62 A63 J46 W71 AK25
3A +V_EDRAM_VR
P62
V62
VCCOPC_AB62
VCCOPC_P62
VIDSCK
VIDSOUT
D64 H_CPU_SVIDDAT +VCCSTG J48
J50
VCCGT
VCCGT
VCCGT
VCCGT
Y62 SC10U6D3V3MX-GP2 1 C715
+VCCST_CPU AM40
VCCSA
VCCSA
G23
G25
VCCOPC_V62 +VCCFUSEPRG VCCGT +VCCGT VDDQC VCCSA
G20 1 R703 2 J52 G27
VCCSTG_G20 Do Not Stuff VCCGT SC1U10V2KX-1GP 2 VCCSA
H63 J53 AK42 1 C716 0.04 A A18 G28
140mA +V1.8S_EDRAM
R702 1 23e 2 VCC_EDRAM_FUSEPRG G61
VCC_OPC_1P8_H63
J55
J56
VCCGT
VCCGT
VCCGTX_AK42
VCCGTX_AK43
AK43
AK45
+VCCSTG
A22
VCCST VCCSA
VCCSA
J22
J23
Do Not Stuff VCC_OPC_1P8_G61 VCCGT VCCGTX_AK45 Do Not Stuff VCCSTG_A22 VCCSA
J58 AK46 2 1 C717 J27
VCCSENSE_EDRAM_VR VCCGT VCCGTX_AK46 VCCSA
+V_EDRAM_VR VSSSENSE_EDRAM_VR
AC63
VCCOPC_SENSE
J60
VCCGT VCCGTX_AK48
AK48 DY 1D35V_S3
AL23
VCCPLL_OC VCCSA
K23
AE63 K48 AK50 K25
VSSOPC_SENSE VCCGT VCCGTX_AK50 VCCSA
K50 AK52 K20 K27
VCCGT VCCGTX_AK52 SCD1U16V2KX-3GP2 VCCPLL_K20 VCCSA
AE62 K52 AK53 1 C718 K21 K28
3A +V_EOPIO_VR
AG62
VCCEOPIO
VCCEOPIO
K53
VCCGT
VCCGT
VCCGTX_AK53
VCCGTX_AK55
AK55
VCCPLL_K21 VCCSA
VCCSA
K30
C701

C702

K55 AK56
VCCGT VCCGTX_AK56
1

VCCSENSE_EOPIO_VR AL63 K56 AK58 #544669 CRB. +V1.00U_CPU AM23 VCCIO_VR_FB

VSSSENSE_EOPIO_VR VCCEOPIO_SENSE VCCGT VCCGTX_AK58 VCCIO_SENSE VSSIO_VR_FB
23e 23e AJ62
VSSEOPIO_SENSE
K58
VCCGT VCCGTX_AK60
AK60
VSSIO_SENSE
AM22
K60 AK70
2

VCCGT VCCGTX_AK70
Do Not Stuff

Do Not Stuff

1D35V_S3 +VDDQ_CPU_CLK

C720

C721
L62
VCCGT VCCGTX_AL43
AL43 0.12 A VSSSA_SENSE
H21 VSSSA_SENSE [46]

1
L63 AL46 R705 H20 VCCSA_SENSE [46]
SKYLAKE-GP VCCGT VCCGTX_AL46 VCCSA_SENSE
L64 AL50
VCCGT VCCGTX_AL50
071.SKYLA.000U L65 AL53 1 2

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
2

2
VCCGT VCCGTX_AL53
L66 AL56
VCCGT VCCGTX_AL56 Do Not Stuff SKYLAKE-GP
L67 AL60
VCCGT VCCGTX_AL60 +VCCIO
L68
VCCGT VCCGTX_AM48
AM48 071.SKYLA.000U (#543016 SKL U/Y PDG rev1.0)
L69 AM50
+V_EOPIO_VR VCCGT VCCGTX_AM50
L70 AM52
+V_EDRAM_VR VCCGT VCCGTX_AM52
L71 AM53
VCCGT VCCGTX_AM53

1
M62 AM56
VCCGT VCCGTX_AM56 R733
N63 AM58
VCCGT VCCGTX_AM58 100R2F-L1-GP-U
C703

C704

N64 AU58
VCCGT VCCGTX_AU58
1

N66 AU63
R724 VCCGT VCCGTX_AU63
23e 23e N67 BB57

2
Do Not Stuff VCCGT VCCGTX_BB57
23e N69 BB66
2

VCCGT VCCGTX_BB66
Do Not Stuff

Do Not Stuff

VCCIO_VR_FB
[46] VCCGT_SENSE J70 AK62
2

VCCGT_SENSE VCCGTX_SENSE VSSIO_VR_FB

[46] VSSGT_SENSE J69 AL61
VCCSENSE_EDRAM_VR VSSGT_SENSE VSSGTX_SENSE

1
VSSSENSE_EDRAM_VR
SKYLAKE-GP R730
100R2F-L1-GP-U
1

R725
071.SKYLA.000U

2
Do Not Stuff VCC_CORE
23e
2

1
R719
100R2F-L1-GP-U
+V_EOPIO_VR
C C

2
+VCCSA
VCC_SENSE [46]
1

VSS_SENSE [46]
R729

1
Do Not Stuff
23e

1
R735
R720 Layout Note: 100R2F-L1-GP-U
2

100R2F-L1-GP-U 1. Place close to CPU

VCCSENSE_EOPIO_VR
2. VCC_SENSE/ VSS_SENSE

2
VSSSENSE_EOPIO_VR

2
impedance=50 ohm VCCSA_SENSE
3. Length match<25mil VSSSA_SENSE
1

Layout Note:
SVID DATA

1
R731 The total Length of Data and Clock (from CPU to each VR) must be equal (±0.1 inch).
Do Not Stuff +VCCGT R734
23e Route the Alert signal between the Clock and the Data signals. 100R2F-L1-GP-U
2

2
1
+VCCST_CPU
R721
100R2F-L1-GP-U

2
1

CLOSE TO CPU VCCGT_SENSE [46]

R726 VSSGT_SENSE [46]
100R2F-L1-GP-U #544669

1
2

R709 R722
H_CPU_SVIDDAT 1 2 100R2F-L1-GP-U
VR_SVID_DATA [46]
Do Not Stuff

2
+VCCST_CPU

SVID CLOCK #544669

1

CLOSE TO VR
R723
DY Do Not Stuff
2

R732
H_CPU_SVIDCLK 1 2 VR_SVID_CLK [46]
Do Not Stuff
SVID_543016:
B B

+VCCST_CPU

#544669
1

CLOSE TO CPU
R727
56R2J-4-GP
2

R728
H_CPU_SVIDALRT# 2 1 VR_SVID_ALERT# [46]
220R2J-L2-GP

A A

Iris SKL UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU(VCC_CORE)
Size Document Number Rev
A1
Iris2 SKL-U A00
Date: Wednesday, September 09, 2015 Sheet 7 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU

Strap pin:
Port B /
Vinafix.com
Sampled at rising edge of PCH_PWROK
D
Port C Detected D

0 = Port B is not detected.

DDPB_CTRLDATA * 1 = Port B is detected.

0 = Port C is not detected.

DDPC_CTRLDATA CPU1A 1 OF 20
* 1 = Port C is detected.
E55 SKYLAKE_ULT C47
[56,57] HDMI_CRT_N0 DDI1_TXN[0] EDP_TXN[0] eDP_TX_CPU_N0 [55]
These two signals have weak internal pull-down. [56,57] HDMI_CRT_P0 F55 DDI1_TXP[0] EDP_TXP[0] C46 eDP_TX_CPU_P0 [55]
[56,57] HDMI_CRT_N1 E58 DDI1_TXN[1] EDP_TXN[1] D46 eDP_TX_CPU_N1 [55]
[56,57] HDMI_CRT_P1 F58 DDI1_TXP[1] EDP_TXP[1] C45 eDP_TX_CPU_P1 [55]
[57] HDMI_DATA0# F53 A45
HDMI/CRT [57] HDMI_DATA0 G53
DDI1_TXN[2]
DDI1_TXP[2]
EDP_TXN[2]
EDP_TXP[2] B45
[57] HDMI_CLK# F56 DDI1_TXN[3] EDP_TXN[3] A47
[57] HDMI_CLK G56 DDI1_TXP[3] EDP_TXP[3] B47

C50 DDI2_TXN[0] DDI EDP_AUXN E45 eDP_AUX_CPU_N [55]

D50 EDP F45
DDI2_TXP[0] EDP_AUXP eDP_AUX_CPU_P [55]
C52 DDI2_TXN[1]
D52 B52 EDP_DISP_UTIL 1
DDI2_TXP[1] EDP_DISP_UTIL TP801 Do Not Stuff
A50 DDI2_TXN[2]
B50 DDI2_TXP[2] DDI1_AUXN G50 PCH_DPB_AUXN [56]
D51 DDI2_TXN[3] DDI1_AUXP F50 PCH_DPB_AUXP [56]
C51 DDI2_TXP[3] DDI2_AUXN E48
3D3V_S0 F48
DDI2_AUXP
DDI3_AUXN G46
DISPLAY SIDEBANDS
RN801 DDI3_AUXP F46 R804
C L13 C
2 3 CPU_DP1_CTRL_CLK HDMI [57] CPU_DP1_CTRL_CLK
[57] CPU_DP1_CTRL_DATA L12
GPP_E18/DDPB_CTRLCLK
GPP_E19/DDPB_CTRLDATA
Strap
GPP_E13/DDPB_HPD0 L9 CPU_HDMI_HPD 1 2 CPU_DP1_HPD [56,57]
1 4 CPU_DP1_CTRL_DATA L7 Do Not Stuff
CPU_DP2_CTRL_CLK GPP_E14/DDPC_HPD1 SIO_EXT_SMI#_R
N7 GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 L6 SIO_EXT_SMI#_R [24]
CPU_DP2_CTRL_DATA N8 Strap N9 CPU_CRT_HPD 1 CRT 2
SRN2K2J-1-GP GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 R803 Do Not Stuff
GPP_E17/EDP_HPD L10 EDP_HPD [55]
3D3V_S0 Check +VCCIO Do Not Stuff N11 GPP_E22/DDPD_CTRLCLK
RN803 R801
TP802 1 DDPD_CTRLDATA N12 GPP_E23/DDPD_CTRLDATA
Strap EDP_BKLTEN R12 L_BKLT_EN [24]
EDP_BKLTCTL R11 L_BKLT_CTRL [55]
2 3 CPU_DP2_CTRL_DATA 1 2 EDP_COMP E52 U13 EDP_VDD_EN [55]
CPU_DP2_CTRL_CLK EDP_RCOMP EDP_VDDEN
1 DY 4
24D9R2F-L-GP
SKYLAKE-GP
Do Not Stuff
071.SKYLA.000U
(#543016) The Skylake U/Y processor supports only two DDI ports - Port 1 and Port 2.

3D3V_S0
(#543016) eDP_RCOMP Guideline
Signal Trace Isolation Resistor Length
Width Spacing Value SIO_EXT_SMI#_R 1 R802 2 10KR2J-3-GP

eDP_RCOMP 20 mils 25 mils 24.9 Ω ±1% Max = 100 mils

B B

(#543016) DDI Disabling and Termination Guidelines

Port Strap Enable Port Disable Port
PU to 3.3 V with 2.2-k
Port 1 DDPB_CTRLDATA ±5% resistor NC
PU to 3.3 V with 2.2-k
Port 2 DDPC_CTRLDATA ±5% resistor NC

A Iris SKL UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Design Guideline:
Skylake processor signal eDP_RCOMP should be connected to the VCCIO rail via a single 24.9 ±1% Ω resistor. Title

CPU_(DISPLAY)
Size Document Number Rev
A3 A00
Iris2 SKL-U
Date: W ednesday, September 09, 2015 Sheet 8 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU

Vinafix.com
D D

C C

(Blanking)

B B

A Iris SKL UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
(Reserved)
Size Document Number Rev
A3 A00
Iris2 SKL-U
Date: Tuesday, May 26, 2015 Sheet 9 of 105
5 4 3 2 1
 D

A00
Wistron Corporation

Rev

105
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

of
CPU_(Power CAP1)

10
Sheet
Iris2 SKL-U
1

1
Tuesday, May 26, 2015
Document Number
Iris SKL UMA

A2

Date:
Size
Title
2

2
(#543016 PDG)

22U 0603 x 8
PC1098

Do Not Stuff
DY

1 2
PC1097

Do Not Stuff
DY
3

3
1 2
PC1068

Do Not Stuff
DY

1 2
PC1067

Do Not Stuff
DY

1 2
PC1066

Do Not Stuff
DY

1 2
DY

1 2
PC1065

Do Not Stuff
PC1061 Do Not Stuff
DY
DY

1 2
1 2
PC1054

Do Not Stuff
PC1060 Do Not Stuff
10U 0603 x 4

DY

DY

1 2 1 2
PC1059 Do Not Stuff
PC1053

Do Not Stuff
DY
1 2
PC1058 SC10U6D3V3MX-GP 1 2
DY
PC1064

PC1052
1 2 1 2 SC22U6D3V3MX-1-GP

22U 0603 x28

PC1057 SC10U6D3V3MX-GP Do Not Stuff
1 2
DY

1 1 2 2

PC1051
SC22U6D3V3MX-1-GP
PC1056 PC1063 SC10U6D3V3MX-GP Do Not Stuff
1D35V_S3

1 2
DY

1 1 2 2

PC1050
SC22U6D3V3MX-1-GP
PC1055 PC1062 SC10U6D3V3MX-GP Do Not Stuff
Vinafix.com

1 2

PC1095 PC1096
SC22U6D3V3MX-1-GP
4

4
22U 0603 x 22

PC1049
SC22U6D3V3MX-1-GP 1 2

PC1081
SC22U6D3V3MX-1-GP Do Not Stuff
1 2

DY
1 2 1 2

PC1048
SC22U6D3V3MX-1-GP

PC1080

PC1094
SC22U6D3V3MX-1-GP Do Not Stuff

DY
1 2
1 2 1 2

PC1047

PC1078 PC1079

PC1092 PC1093
SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP
1 2 1 2 1 2
PC1019 PC1020

SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP Do Not Stuff

DY
1 2

PC1046
SC22U6D3V3MX-1-GP 1 2 1 2

PC1030
SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP

VCCSA

PC1076 PC1077

PC1090 PC1091
1 2 SC22U6D3V3MX-1-GP Do Not Stuff

DY
1 2 1 2
1 2 1 2
PC1009

PC1018

PC1029

PC1045
SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP

+VCCSA
1 2 1 2 1 2 1 2
1 2 1 2
PC1007 PC1008

PC1016 PC1017

PC1027 PC1028
SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP

PC1075

PC1089
SC22U6D3V3MX-1-GP Do Not Stuff

DY
1 2 1 2 1 2
1 2 1 2
SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP

PC1042 PC1043

PC1073 PC1074

PC1087 PC1088
SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP
1 2 1 2 1 2
1 2 1 2 1 2
PC1005 PC1006

PC1014 PC1015

PC1025 PC1026
SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP
IccMax current-10ms max = 34 A

+VCCPRIM_CORE
1 2 1 2 1 2

IccMax current-10ms max[A] = 67 A

1 2 1 2 1 2
SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP

PC1034 PC1041

PC1071 PC1072

PC1085 PC1086
1 2 SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP

PC1039
1 2 1 2 1 2 SC22U6D3V5MX-2GP

SLICED GT
PC1004 1 2 1 2 1 2

PC1013

PC1024
SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP 1 2
SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP

PC1038
SC22U6D3V5MX-2GP
1 2 1 2 1 2
Main Func = CPU

1 2 1 2 1 2

PC1002 PC1003

PC1011 PC1012

PC1022 PC1023
SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP
5

5
PC1033

PC1070

PC1084
U-line 23e 28W

SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP

+VCCIO(ICCMAX.=2.73A)
1 2 1 2 1 2
CORE

1 2 1 2 1 2
SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP

U-line 23e 28W

PC1031 PC1032

PC1044 PC1069

PC1082 PC1083
SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP

DY
1 2 1 2 1 2
1 2 1 2 1 2

PC1001

PC1010

PC1021
SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP 1 2
SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP
PC1037 Do Not Stuff
1 2 1 2 1 2
1 2 1 2 1 2
1 2
PC1036 SC22U6D3V3MX-1-GP

VCC_CORE

+VCCIO

+VCCGT
1 2
PC1035 SC22U6D3V3MX-1-GP

A
 5 4 3 2 1

Main Func = CPU

C1138,C1148,C1150 DY ( Based on OPI ) UNSLICED GT
+VCCGT
VCCIO
+VCCIO

+VCCIO(ICCMAX.=2.73A)
1

1
C1136 C1138 C1147 C1148 C1149 C1150 1U 0402 x 6
DY DY DY

Vinafix.com
2

1
SC1U10V2KX-1GP

Do Not Stuff

SC1U10V2KX-1GP

Do Not Stuff

SC1U10V2KX-1GP

Do Not Stuff
C1151 C1152 C1153 C1154
DY

2
SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

Do Not Stuff
D D

GTUS 20141114 Alden

PCH DERIVED RAILS +VCCGT

+V_VCCGTUS_VR can merge to +VCCGT

+VCCPGPPA(ICCMAX.=0.05A)
1D0V_S5 +V1.00A_SIP
+V1.8A_SIP +VCCPGPPA
R1117 R1111
1 2 1 DY 2 PC1104 PC1105

1
+VCCF24NS_1P0_L PC1106 PC1107

SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP
Do Not Stuff
+V3.3A_SIP Do Not Stuff

SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP
R1125 1 2 Do Not Stuff

2
+VCC24TBT_1P0

2
2014/12/09 modify R1109
R1122 1 2 Do Not Stuff 1 2
+VCCPRIM_1P0 3D3V_S5_PCH
short pad Do Not Stuff
R1112 1 2 Do Not Stuff
+VCCF100_1P0_L 1 R1110 2 +VCCPRTCPRIM_3P3
R1115
R1114 1 2 Do Not Stuff Do Not Stuff 1 2
+VCCF135_1P0
+VCCPGPPB
R1121 1 2 Do Not Stuff
Current? Do Not Stuff

+VCCFHV
TBD 1 R1116 2

R1133 1 2 Do Not Stuff Do Not Stuff +VCCPGPPC

+VCCMPHYAON_1P0
C 1 R1123 2 C
R1134 1 2 Do Not Stuff
+VCCDTS_1P0 Do Not Stuff +VCCPGPPE

R1130 1 2 Do Not Stuff 1 R1124 2

+VCC19P2_1P0
Do Not Stuff +VCCPRIM_3P3
R1131 1 2 Do Not Stuff
+VCCF100OC_1P0_L 1 R1127 2

R1132 1 2 Do Not Stuff Do Not Stuff +VCCPSPI

1 R1126 2

Do Not Stuff

+VCCPGPPG

1 R1128 2

Do Not Stuff
+VCCSA 3 PAD SHARING +VCCPRIM_CORE
+V1.8A_SIP
R1104 R1136
1 DY Do Not
2
Stuff
1 DY 2
+V1.00A_SIP Do Not Stuff
R1105
+VCCMPHYGTAON_1P0(ICCMAX.=3.5A)
1 DY Do Not
2
Stuff

VCCPRIM_CORE
R1103 +VCCMPHYGTAON_1P0_LS_SIP +VCCMPHYGTAON_1P0_LS_SIP
1 2 +VCCAPLLEBB_1P0 +VCCMPHYGTAON_1P0_LS_SIP +VCCSRAM_1P0
R1101 +VCCMPHYGTAON_1P0_LS_SIP +VCCAMPHYPLL_1P0_L R1106
C1174
SC1U10V2KX-1GP

Do Not Stuff C1182 1 2 R1102 1 2

1

1 2

1
C1180

C1173

C1172
B B
DY

SC1U10V2KX-1GP
0R3J-0-U-GP 0R5J-5-GP

Do Not Stuff
+VCCPRIM_CORE +VCCIO

Do Not Stuff

SC1U10V2KX-1GP
0R3J-0-U-GP C1181

C1176

C1175
DY

SC1U10V2KX-1GP
2

1
Do Not Stuff

Do Not Stuff
R1107 DY DY

2
1 DY Do Not
2
Stuff

+V3.3A_SIP +VCCPAZIO

CAP TBD 1 R1135 2

Do Not Stuff
+V1.8A_SIP
R1118
1 DY 2
Do Not Stuff

VCC_CORE +VCCAMPHYPLL_1P0_L +VCCAMPHYPLL_1P0 +V1.00A_SIP +VCCAPLL_1P0

R1119 R1120
+V3.3A_SIP +VCCPGPPD_TCH +VCCPGPPD 1 2 1 2

1 R1108 2 R1113
0R3J-0-U-GP 0R3J-0-U-GP
1

1
C1101 C1102 C1103 C1116 C1117
1U 0402 x 5 Do Not Stuff 1 2 DY C1184
0R3J-0-U-GP Do Not Stuff
2

2
+V1.8A_SIP +V1.8A +V1.8A_SIP
SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

A R1129 A

1 DY 2 2 R1139 1

Do Not Stuff Do Not Stuff

+VCCPGPPD_TCH
Iris SKL UMA
U-line 23e 28W +V1.8A_SIP +VCCPGPPF
R1138
IccMax current-10ms max = 34 A
2 1 Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
1

0R3J-0-U-GP Taipei Hsien 221, Taiwan, R.O.C.

DY C1183
Do Not Stuff Title
2

CPU_(Power CAP2)
Size Document Number Rev
A2
Iris2 SKL-U A00
Date: Tuesday, May 26, 2015 Sheet 11 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = DDR SODIMM

SA0_DIMA
SA1_DIMA Note:
SA0 DIM0 = 0, SA1_DIM0 = 0

1
R1202 R1201
SO-DIMMA SPD Address is 0xA0
DM1 SO-DIMMA TS Address is 0x30

Do Not Stuff

Do Not Stuff
[5] M_A_A[15:0]
M_A_A0 98 NP1

2
M_A_A1 A0 NP1
97 NP2
M_A_A2 A1 NP2

Vinafix.com
96
M_A_A3 A2
95 110 M_A_RAS# [5]
M_A_A4 A3 RAS#
92 113 M_A_WE# [5]
M_A_A5 A4 WE#
91 115 M_A_CAS# [5]
M_A_A6 A5 CAS#
90
M_A_A7 A6
D 86 114 M_A_CS#0 [5] D
M_A_A8 A7 CS0#
89 121 M_A_CS#1 [5]
M_A_A9 A8 CS1#
85
M_A_A10 A9
107 73 M_A_CKE0 [5]
M_A_A11 A10/AP CKE0
84 74 M_A_CKE1 [5]
M_A_A12 A11 CKE1
83
M_A_A13 A12
119 101 M_A_CLK0 [5]
M_A_A14 A13 CK0 1D35V_S3
80 103 M_A_CLK#0 [5]
M_A_A15 A14 CK0#
78
A15
79 102 M_A_CLK1 [5]
[5] M_A_BS2 A16/BA2 CK1
104 M_A_CLK#1 [5]
CK1#
109 10U 0603 x 3
[5] M_A_BS0 BA0
108 11 1U 0402 x 2

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
TC1201
[5] M_A_BS1 BA1 DM0

Do Not Stuff

C1207

C1208

C1209
Layout Note: [5] M_A_DQ[63:0] 28 0.1U 0402 x 5

1
M_A_DQ3 DM1
5 46
M_A_DQ1 DQ0 DM2
Place these caps 7
DQ1 DM3
63 DY
M_A_DQ4 15 136
close to VREF_CA

2
M_A_DQ7 DQ2 DM4
M_A_DQ[0:7] 17
DQ3 DM5
153
M_A_DQ2 4 170
M_VREF_CA_DIMMA M_A_DQ6 DQ4 DM6
6 187
M_A_DQ0 DQ5 DM7
16
M_A_DQ5 DQ6
18 200 PCH_SMBDATA [13,18,56,65,99]
M_A_DQ9 DQ7 SDA
21 202 PCH_SMBCLK [13,18,56,65,99]
M_A_DQ13 DQ8 SCL
23
M_A_DQ14 DQ9 3D3V_S0
33 198
M_A_DQ10 DQ10 EVENT#
M_A_DQ[8:15] 35

SC1U10V2KX-1GP

SC1U10V2KX-1GP
DQ11
1

M_A_DQ8

C1212

C1213
22 199

1
C1201 C1218 C1202 M_A_DQ12 DQ12 VDDSPD
24
M_A_DQ15 DQ13 SA0_DIMA
34 197
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
2

1
M_A_DQ11 DQ14 SA0 SA1_DIMA
36 201

2
M_A_DQ20 DQ15 SA1 C1203
M_A_DQ16
39
DQ16 DY
41 77

2
DQ17 NC#1

Do Not Stuff
M_A_DQ[16:23] M_A_DQ23 51 122
M_A_DQ19 DQ18 NC#2 1D35V_S3
53 125
M_A_DQ21 DQ19 NC#/TEST
40
M_A_DQ17 DQ20
42 75
M_A_DQ22 DQ21 VDD1
50 76
M_A_DQ18 DQ22 VDD2
52 81
Layout Note: M_A_DQ25 57
DQ23 VDD3
82
M_A_DQ28 DQ24 VDD4
Place these caps 59
DQ25 VDD5
87
M_A_DQ26

C1220

C1221

C1222

C1210

C1211
M_A_DQ[24:31] 67 88

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
close to VREF_DQ M_A_DQ30 DQ26 VDD6
C 69 93 C

1
M_A_DQ24 DQ27 VDD7
56 94
M_VREF_DQ_DIMMA M_A_DQ29 DQ28 VDD8
58 99
M_A_DQ31 DQ29 VDD9
68 100

2
M_A_DQ27 DQ30 VDD10
70 105
M_A_DQ32 DQ31 VDD11
129 106
M_A_DQ33 DQ32 VDD12
131 111
M_A_DQ34 DQ33 VDD13
141 112
M_A_DQ35 DQ34 VDD14
M_A_DQ[32:39] 143 117
1

M_A_DQ36 DQ35 VDD15

130 118
C1204 C1206 M_A_DQ37 DQ36 VDD16
C1205

DY 132
DQ37 VDD17
123
Do Not Stuff

M_A_DQ38 140 124

Layout Note:
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
2

M_A_DQ39 DQ38 VDD18

142
M_A_DQ40 DQ39
147
DQ40 VSS
2 Place these Caps near DIMM1.
M_A_DQ41 149 3
M_A_DQ46 DQ41 VSS
157 8
M_A_DQ47 DQ42 VSS
M_A_DQ[40:47] 159
DQ43 VSS
9
M_A_DQ44 146 13
M_A_DQ45 DQ44 VSS
148 14
M_A_DQ43 DQ45 VSS 0D675V_S0
158 19
M_A_DQ42 DQ46 VSS
160 20
M_A_DQ53 DQ47 VSS
163 25
M_A_DQ49 DQ48 VSS
Layout Note: M_A_DQ[48:55] M_A_DQ55
165
175
DQ49 VSS
26
31
M_A_DQ54 DQ50 VSS
Place these caps 177 32 1U 0402 x 3

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP
M_A_DQ52 DQ51 VSS

C1214

C1215

C1216
close to VTT1 and 164 37

1
M_A_DQ48 DQ52 VSS
166 38
VTT2. M_A_DQ51 DQ53 VSS
174 43
M_A_DQ50 DQ54 VSS
176 44

2
M_A_DQ61 DQ55 VSS
181 48
M_A_DQ56 DQ56 VSS
183 49
M_A_DQ62 DQ57 VSS
M_A_DQ[56:63] 191
DQ58 VSS
54
M_A_DQ63 193 55
M_A_DQ60 DQ59 VSS
180 60
M_A_DQ57 DQ60 VSS
182 61
M_A_DQ58 DQ61 VSS
192 65
M_A_DQ59 DQ62 VSS
194 66
DQ63 VSS
[5] M_A_DQS_DN[7:0] 71
M_A_DQS_DN0 VSS
10 72
M_A_DQS_DN1 DQS0# VSS
27
DQS1# VSS
127 Place these Caps near DIMM1.
M_A_DQS_DN2 45 128
B M_A_DQS_DN3 DQS2# VSS B
62 133
M_A_DQS_DN4 DQS3# VSS
135 134
M_A_DQS_DN5 DQS4# VSS
152 138
M_A_DQS_DN6 DQS5# VSS
169 139
M_A_DQS_DN7 DQS6# VSS
186 144
DQS7# VSS
[5] M_A_DQS_DP[7:0] 145
M_A_DQS_DP0 VSS
12 150
M_A_DQS_DP1 DQS0 VSS
29 151
M_A_DQS_DP2 DQS1 VSS
47 155
M_A_DQS_DP3 DQS2 VSS
64 156
M_A_DQS_DP4 DQS3 VSS
137 161
M_A_DQS_DP5 DQS4 VSS
154 162
M_A_DQS_DP6 DQS5 VSS
171 167
M_A_DQS_DP7 DQS6 VSS
188 168
DQS7 VSS
172
M_A_DIMA_ODT0 VSS
116 173
[5] M_A_DIMA_ODT0 M_A_DIMA_ODT1 ODT0 VSS
120 178
[5] M_A_DIMA_ODT1 ODT1 VSS
179
VSS
M_VREF_CA_DIMMA 126 184
VREF_CA VSS
Layout Note: M_VREF_DQ_DIMMA 1
VREF_DQ VSS
185
189
VSS
All VREF traces should [5,13] DDR3_DRAMRST#
30
RESET# VSS
190
have width=20mil; 195
VSS
196
spacing=20 mil VSS
0D675V_S0 203 205
1

VTT1 VSS
204 206
ED1217 VTT2 VSS
DY
Do Not Stuff

DDR3-204P-108-GP-U

62.10017.X41
2

close to dimm

A A

Iris SKL UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

DDR3-SODIMM1
Size Document Number Rev
A2 A00
Iris2 SKL-U
Date: Wednesday, September 09, 2015 Sheet 12 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = DDR SODIMM

DM2
[5] M_B_A[15:0]
M_B_A0 98 NP1
M_B_A1 A0 NP1
97 NP2
M_B_A2 A1 NP2 3D3V_S0
96
M_B_A3 A2
95 110 M_B_RAS# [5]
M_B_A4 A3 RAS#
92 113 M_B_WE# [5]
M_B_A5 A4 WE#
91 115 M_B_CAS# [5]

1
M_B_A6 A5 CAS#

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90
M_B_A7 A6 R1302
86 114 M_B_CS#0 [5]
A7 CS0#
M_B_A8
M_B_A9
89
A8 CS1#
121 M_B_CS#1 [5] DM2 10KR2J-3-GP
85
M_B_A10 A9
107 73 M_B_CKE0 [5]

2
M_B_A11 A10/AP CKE0
D 84 74 M_B_CKE1 [5] D
M_B_A12 A11 CKE1
83
M_B_A13 A12
119 101 M_B_CLK0 [5]
M_B_A14 A13 CK0 SA1_DIMB
80 103 M_B_CLK#0 [5]
M_B_A15 A14 CK0#
78
A15 SA0_DIMB
79 102 M_B_CLK1 [5]
[5] M_B_BS2 A16/BA2 CK1
104 M_B_CLK#1 [5]
CK1#
109
[5] M_B_BS0 BA0

1
108 11
[5] M_B_BS1 BA1 DM0 R1301
[5] M_B_DQ[63:0]
M_B_DQ10 DM1
28 Note:

Do Not Stuff
5 46
M_B_DQ11 DQ0 DM2 SO-DIMMB SPD Address is 0xA4
M_VREF_CA_DIMMB Layout Note: M_B_DQ[8:15] M_B_DQ13
7
15
DQ1 DM3
63
136 SO-DIMMB TS Address is 0x34

2
M_B_DQ15 DQ2 DM4
Place these caps 17
DQ3 DM5
153
M_B_DQ9 4 170
close to VREF_CA M_B_DQ14 DQ4 DM6
6 187
M_B_DQ12 DQ5 DM7
16
M_B_DQ8 DQ6
18 200 PCH_SMBDATA [12,18,56,65,99]
M_B_DQ4 DQ7 SDA
21 202 PCH_SMBCLK [12,18,56,65,99]
1

M_B_DQ0 DQ8 SCL

23
M_B_DQ2 DQ9 3D3V_S0
DM2C1308 DM2C1306DM2 C1309
M_B_DQ3
33
DQ10 EVENT#
198
M_B_DQ[0:7] 35
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
2

M_B_DQ1 DQ11
22 199
M_B_DQ5 DQ12 VDDSPD
24

1
M_B_DQ6 DQ13 SA0_DIMB
34 197
M_B_DQ7 DQ14 SA0 SA1_DIMB C1311
M_B_DQ16
36
DQ15 SA1
201 DY Do Not Stuff
39

2
M_B_DQ17 DQ16
41 77
M_B_DQ18 DQ17 NC#1
M_B_DQ[16:23] 51
DQ18 NC#2
122
1D35V_S3
M_B_DQ19 53 125
M_B_DQ20 DQ19 NC#/TEST
40
M_B_DQ21 DQ20 1D35V_S3
42 75
M_B_DQ22 DQ21 VDD1
50 76
M_B_DQ23 DQ22 VDD2
52 81
M_B_DQ31 DQ23 VDD3
57 82
M_B_DQ25 DQ24 VDD4
59 87 10U 0603 x 3
M_VREF_DQ_DIMMB Layout Note: M_B_DQ[24:31] M_B_DQ29 67
DQ25 VDD5
88 1U 0402 x 2

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
M_B_DQ27 DQ26 VDD6

C1317

C1318

C1323
Place these caps 69
DQ27 VDD7
93 0.1U 0402 x 5

1
M_B_DQ24 56 94 DM2 DM2
close to VREF_DQ M_B_DQ28 DQ28 VDD8
M_B_DQ26
58
DQ29 VDD9
99 DM2
68 100

2
M_B_DQ30 DQ30 VDD10
C 70 105 C
M_B_DQ33 DQ31 VDD11
129 106
DQ32 VDD12
1

M_B_DQ36 131 111

M_B_DQ34 DQ33 VDD13
C1305

DM2 C1302 DY DM2C1310 141 112

DQ34 VDD14
Do Not Stuff

M_B_DQ[32:39] M_B_DQ39 143 117

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
2

M_B_DQ37 DQ35 VDD15

130 118
M_B_DQ32 DQ36 VDD16
132 123
M_B_DQ35 DQ37 VDD17
140 124
M_B_DQ38 DQ38 VDD18
142

SC1U10V2KX-1GP

SC1U10V2KX-1GP
M_B_DQ45 DQ39

C1322

C1321
147 2
DQ40 VSS

1
M_B_DQ41 149 3
M_B_DQ42 DQ41 VSS
M_B_DQ43
157
DQ42 VSS
8 DM2 DM2
M_B_DQ[40:47] 159 9

2
M_B_DQ40 DQ43 VSS
146 13
M_B_DQ44 DQ44 VSS
148 14
M_B_DQ46 DQ45 VSS
158 19
M_B_DQ47 DQ46 VSS
160 20
M_B_DQ51 DQ47 VSS
163 25
M_B_DQ49 DQ48 VSS
165 26
M_B_DQ55 DQ49 VSS
M_B_DQ[48:55] 175
DQ50 VSS
31
M_B_DQ48 177 32
M_B_DQ52 DQ51 VSS
164 37
M_B_DQ53 DQ52 VSS
166 38
M_B_DQ54 DQ53 VSS

C1315

C1314

C1316

C1312

C1313
174 43

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
M_B_DQ50 DQ54 VSS
176 44
DQ55 VSS

1
M_B_DQ58 181 48
M_B_DQ56 DQ56 VSS
M_B_DQ60
183
DQ57 VSS
49 DM2 DM2 DM2 DM2 DM2
M_B_DQ[56:63] 191 54

2
M_B_DQ59 DQ58 VSS
193 55
M_B_DQ57 DQ59 VSS
180 60
M_B_DQ61 DQ60 VSS
182 61
M_B_DQ62 DQ61 VSS
192 65
M_B_DQ63 DQ62 VSS
194 66
DQ63 VSS
[5] M_B_DQS_DN[7:0] 71
M_B_DQS_DN1 VSS
10 72
M_B_DQS_DN0 DQS0# VSS
M_B_DQS_DN2
27
45
DQS1# VSS
127
128
Layout Note:
M_B_DQS_DN3 DQS2# VSS
62
DQS3# VSS
133 Place these Caps near DIMM2.
M_B_DQS_DN4 135 134
M_B_DQS_DN5 DQS4# VSS
152 138
M_B_DQS_DN6 DQS5# VSS
169 139
B M_B_DQS_DN7 DQS6# VSS B
186 144
DQS7# VSS
[5] M_B_DQS_DP[7:0] 145
M_B_DQS_DP1 VSS
12 150
M_B_DQS_DP0 DQS0 VSS
29 151
M_B_DQS_DP2 DQS1 VSS
47 155
M_B_DQS_DP3 DQS2 VSS
64 156
M_B_DQS_DP4 DQS3 VSS
137 161
M_B_DQS_DP5 DQS4 VSS
154 162
M_B_DQS_DP6 DQS5 VSS
171 167
M_B_DQS_DP7 DQS6 VSS
188 168
DQS7 VSS 0D675V_S0
172
VSS
116 173
[5] M_B_DIMB_ODT0 ODT0 VSS
120 178
[5] M_B_DIMB_ODT1 ODT1 VSS
179
VSS
M_VREF_CA_DIMMB 126 184
VREF_CA VSS
1 185 1U 0402 x 3

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP
M_VREF_DQ_DIMMB VREF_DQ VSS

C1307

C1304

C1303
Layout Note: 189

1
VSS
30 190
[5,12] DDR3_DRAMRST# RESET# VSS
All VREF traces should VSS
195 DM2 DM2 DM2
have width=20mil; 196

2
VSS
0D675V_S0 203 205
VTT1 VSS
1

spacing=20 mil 204 206

ED1301 VTT2 VSS
DY
Do Not Stuff

DDR3-204P-259-GP
2

62.10024.S11
DM2
Place these Caps near DIMM2.
close to dimm

A A

Iris SKL UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
DDR3-SODIMM2
Size Document Number Rev
A2 A00
Iris2 SKL-U
Date: Wednesday, September 09, 2015 Sheet 13 of 105
5 4 3 2 1
 5 4 3 2 1

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D D

C
(Blanking) C

B B

Iris SKL UMA

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
(Reserved)_SODIMM _SODIMM4
Size Document Number Rev
A4 A00
Iris2 SKL-U
Date: Tuesday, May 26, 2015 Sheet 14 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = PCH

3D3V_S0
CPU1I 9 OF 20

SKYLAKE_ULT R1503

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CSI-2
W IFI_RF_EN 1 2
A36 C37 10KR2J-3-GP
CSI2_DN0 CSI2_CLKN0
B36 CSI2_DP0 CSI2_CLKP0 D37
D C38 CSI2_DN1 CSI2_CLKN1 C32 D
D38 CSI2_DP1 CSI2_CLKP1 D32
C36 CSI2_DN2 CSI2_CLKN2 C29
D36 CSI2_DP2 CSI2_CLKP2 D29 DC resistance < 0.5ohm.
A38 CSI2_DN3 CSI2_CLKN3 B26
B38 CSI2_DP3 CSI2_CLKP3 A26 R1501
C31 E13 CSI2_COMP 1 2
CSI2_DN4 CSI2_COMP W IFI_RF_EN
D31 CSI2_DP4 GPP_D4/FLASHTRIG B7 W IFI_RF_EN [61]
C33 CSI2_DN5 100R2F-L1-GP-U
D33 CSI2_DP5 EMMC
A31 CSI2_DN6
B31 CSI2_DP6 GPP_F13/EMMC_DATA0 AP2
A33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP1 [#545659 Rev0.7]
B33 CSI2_DP7 GPP_F15/EMMC_DATA2 AP3
GPP_F16/EMMC_DATA3 AN3 GPP_F: VCCPGPPF = 1.8V Only
A29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN1
B29 CSI2_DP8 GPP_F18/EMMC_DATA5 AN2
C28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM4
D28 CSI2_DP9 GPP_F20/EMMC_DATA7 AM1
A27 CSI2_DN10
B27 CSI2_DP10 GPP_F21/EMMC_RCLK AM2
C27 CSI2_DN11 GPP_F22/EMMC_CLK AM3
D27 CSI2_DP11 GPP_F12/EMMC_CMD AP4 R1502
AT1 EMMC_RCOMP 1 2
EMMC_RCOMP
SKYLAKE-GP 200R2F-L-GP
C C

071.SKYLA.000U

B B

A Iris SKL UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(CS-2/EMMC)
Size Document Number Rev
A3 A00
Iris2 SKL-U
Date: W ednesday, September 09, 2015 Sheet 15 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = PCH

#543016:
CPU1H 8 OF 20
220 nF nominal capacitors are recommended for Gen 3.
100 nF nominal capacitors are recommended for Gen 2. SKYLAKE_ULT
SSIC / USB3
PCIE/USB3/SATA

USB3_1_RXN
H8
USB30_RX_CPU_N1 [36]
(#545659) The xHCI controller supports USB Debug port on all USB3.0 capable ports.
G8
USB3_1_RXP USB30_RX_CPU_P1 [36]
[76] PEG_RX_CPU_N0 H13 C13 USB30_TX_CPU_N1 [36]
[76] PEG_RX_CPU_P0 Do Not Stuff G13
PCIE1_RXN/USB3_5_RXN
PCIE1_RXP/USB3_5_RXP
USB3_1_TXN
USB3_1_TXP
D13 USB30_TX_CPU_P1 [36]
USB1 (USB3.0 Port1)
[76] PEG_TX_GPU_N0 C1606 1 2OPS PEG_TX_CPU_N0 B17
C1605 1 PEG_TX_CPU_P0 PCIE1_TXN/USB3_5_TXN
[76] PEG_TX_GPU_P0 2OPS A17 J6
Do Not Stuff PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_1_RXN
H6
USB3_2_RXP/SSIC_1_RXP
[76] PEG_RX_CPU_N1 G11 B13
Do Not Stuff PCIE2_RXN/USB3_6_RXN USB3_2_TXN/SSIC_1_TXN
[76] PEG_RX_CPU_P1 F11 A13
C1608 1 PEG_TX_CPU_N1 PCIE2_RXP/USB3_6_RXP USB3_2_TXP/SSIC_1_TXP
[76] PEG_TX_GPU_N1 2OPS D16
C1607 1 PEG_TX_CPU_P1 PCIE2_TXN/USB3_6_TXN
[76] PEG_TX_GPU_P1 2OPS C16 J10

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Do Not Stuff PCIE2_TXP/USB3_6_TXP USB3_3_RXN/SSIC_2_RXN
H10
GPU [76] PEG_RX_CPU_N2 H16
PCIE3_RXN
USB3_3_RXP/SSIC_2_RXP
USB3_3_TXN/SSIC_2_TXN
B15
[76] PEG_RX_CPU_P2 Do Not Stuff G16 A15
C1610 1 PEG_TX_CPU_N2 PCIE3_RXP USB3_3_TXP/SSIC_2_TXP
[76] PEG_TX_GPU_N2 2OPS D17
C1609 1 PEG_TX_CPU_P2 PCIE3_TXN
[76] PEG_TX_GPU_P2 2OPS C17 E10
Do Not Stuff PCIE3_TXP USB3_4_RXN
F10
USB3_4_RXP
[76] PEG_RX_CPU_N3 G15 C15
D Do Not Stuff PCIE4_RXN USB3_4_TXN D
[76] PEG_RX_CPU_P3 F15 D15
C1612 1 PEG_TX_CPU_N3 PCIE4_RXP USB3_4_TXP
[76] PEG_TX_GPU_N3 2OPS B19
C1611 1 PEG_TX_CPU_P3 PCIE4_TXN
[76] PEG_TX_GPU_P3 2OPS A19 AB9 USB_CPU_PN0 [36]
Do Not Stuff PCIE4_TXP USB2N_1
USB2P_1
AB10 USB_CPU_PP0 [36]
USB1 (USB2.0 port1)
[61] PCIE_RX_CPU_N5 F16
SCD1U16V2KX-3GP PCIE5_RXN
[61] PCIE_RX_CPU_P5 E16 AD6 USB_CPU_PN1 [37]
[61] PCIE_TX_CON_N5 C1601 1 2 PCIE_TX_CPU_N5 C19
PCIE5_RXP USB2N_2
AD7 USB_CPU_PP1 [37]
USB2 (IO BD/ USB2.0 Port2)
WLAN [61] PCIE_TX_CON_P5 C1602 1 2 PCIE_TX_CPU_P5 D19
PCIE5_TXN
PCIE5_TXP
USB2P_2
SCD1U16V2KX-3GP AH3 USB_CPU_PN2 [37]
[31] PCIE_RX_CPU_N6 G18
PCIE6_RXN
USB2N_3
USB2P_3
AJ3 USB_CPU_PP2 [37]
USB3 (IO BD/USB2.0 Port3)
[31] PCIE_RX_CPU_P6 SCD1U16V2KX-3GP F18
C1603 1 PCIE_TX_CPU_N6 PCIE6_RXP
[31] PCIE_TX_CON_N6 2 D20 AD9 USB_CPU_PN3 1
LAN [31] PCIE_TX_CON_P6 C1604 1 2 PCIE_TX_CPU_P6 C20
PCIE6_TXN
PCIE6_TXP
USB2N_4
USB2P_4
AD10 USB_CPU_PP3 1
TP1601
TP1602
Do Not Stuff
Do Not Stuff
SCD1U16V2KX-3GP
[60] SATA_RX_CPU_N0 F20 AJ1 USB_CPU_PN4 [55]
[60] SATA_RX_CPU_P0 E20
PCIE7_RXN/SATA0_RXN USB2N_5
AJ2 USB_CPU_PP4 [55]
CAMERA (USB2.0 Port5)
HDD1 [60] SATA_TX_CPU_N0 B21
PCIE7_RXP/SATA0_RXP
PCIE7_TXN/SATA0_TXN
USB2
USB2P_5
[60] SATA_TX_CPU_P0 A21 AF6 USB_CPU_PN5 [33]
PCIE7_TXP/SATA0_TXP USB2N_6
USB2P_6
AF7 USB_CPU_PP5 [33]
Card Reader (USB2.0 Port6)
[60] SATA_RX_CPU_N1 G21
ODD [60] SATA_RX_CPU_P1 F21
PCIE8_RXN/SATA1A_RXN
AH1 USB_CPU_PN6 [55]
[60] SATA_TX_CPU_N1 D21
PCIE8_RXP/SATA1A_RXP
PCIE8_TXN/SATA1A_TXN
USB2N_7
USB2P_7
AH2 USB_CPU_PP6 [55]
Touch Panel (USB2.0 Port7)
[60] SATA_TX_CPU_P1 C21
PCIE8_TXP/SATA1A_TXP 3D3V_S0
AF8 USB_CPU_PN7 [61]
E22
PCIE9_RXN
USB2N_8
USB2P_8
AF9 USB_CPU_PP7 [61]
WLAN (USB2.0 Port8)
1. Trace Width: 4 mils min (breakout) 12-15 mils (trace) E23
PCIE9_RXP
B23 AG1
Layout Note: Note: Must maintain low DC resistance routing (<0.1 ohm).
A23
PCIE9_TXN USB2N_9
AG2
R1608
2. Isolation Spacing: At least 12 mils to any adjacent PCIE9_TXP USB2P_9
DC resistance < 0.5ohm. SATA_ODD_DA# 2 1
high speed I/O. F25
PCIE10_RXN USB2N_10
AH7 ZPODD
E25 AH8
PCIE10_RXP USB2P_10 Do Not Stuff
D23
PCIE10_TXN USBCOMP Unused SATA[3:0]GP pins must be terminated to either
C23 AB6 1 R1603 2 113R2F-GP
PCIE10_TXP USB2_COMP
AG3 3.3V rail or GND using 8.2K
to 10K
on the 3D3V_S0
PCIE_RCOMPN USB2_ID motherboard. Either pull-up or pull-down is acceptable.
F5 AG4
R1604 1 PCIE_RCOMPP PCIE_RCOMPN USB2_VBUSSENSE
2 E5
100R2F-L1-GP-U PCIE_RCOMPP
A9
GPP_E9/USB2_OC0# USB_OC1# USB_OC0# [35] SATA_ODD_PRSNT# R1609 1
[99] XDP_PRDY# D56 C9 2 Do Not Stuff
PROC_PRDY# GPP_E10/USB2_OC1# USB_OC2#
[99] XDP_PREQ#
PIRQA#
D61
PROC_PREQ# GPP_E11/USB2_OC2#
D9
USB_OC3#
ODD / ZPODD
BB11 B9
GPP_A7/PIRQA# GPP_E12/USB2_OC3# USB_OC3# [24]
E28 J1 (#543016) When used as DEVSLP, no external pull-up or pull-down 3D3V_S0
PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 HDD_DEVSLP [60]
E27 J2 SIO_EXT_SCI#_R [24] termination required from SATA Host DEVSLP.
3D3V_S0 PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1
D24 J3 SATA_ODD_DA# [60] R1610
PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2
C24
PCIE11_TXP/SATA1B_TXP GPP_E0/SATAXPCIE0/SATAGP0 SIO_EXT_SCI#_R
E30 H2 2 1
PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 3D3V_S5_PCH
F30 H3 SATA_ODD_PRSNT# [60]
PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2 3D3V_S0
A25 G4
PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2 RN802 10KR2J-3-GP
B25
PCIE12_TXP/SATA2_TXP USB_OC2#
H1 SATA_LED#_R [24,64] 8 1
10KR2J-3-GP 2 GPP_E8/SATALED#
1R1607 PIRQA# USB_OC3# 7 2
R1601 USB_OC0# 6 3
SKYLAKE-GP GPP_E0/SATAXPCIE0/SATAGP0 Do Not Stuff USB_OC1#
1 DY 2 5 4
071.SKYLA.000U
R1602 SRN10KJ-6-GP
GPP_E2/SATAXPCIE2/SATAGP2 Do Not Stuff 3D3V_S0
1 DY 2
C C
R1606
SATA_LED#_R 2 1
10KR2J-3-GP

(#543016) Unused SATAGP[2:0]/GPP_E[2:0] pins must be terminated to either 3.3 V rail or GND
PCIE Table USB 2.0 Table using 8.2 KΩ to 10 KΩ on the motherboard. (#543611)
Do not use both pull-up and pull-down. Either pull-up or pull-down is acceptable. The SATALED# signal is open-collector and requires a weak external pull-up (8.2 kΩ to 10 kΩ) to Vcc3_3.
Port Device Share BUS Pair Device

1 N/A USB3.0_3 0 USB3.0 port1

2 N/A USB3.0_4 1 USB2.0 Port2 (Debug Port/IOBD)

3 WLAN 2 USB2.0 Port3 (IOBD)

4 LAN 3 X

5(L0~L3) GPU 4 CAMERA

6(L3) HDD SATA0 5 Card Reader

6(L2) ODD SATA1 6 Touch Panel

6(L0~L1) N/A 7 WLAN

#545659 (SKL_PCH_U_Y_EDS Rev0.7)

B B

A A

Iris SKL UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(PCIE/SATA/USB)
Size Document Number Rev
A1
Iris2 SKL-U A00
Date: Wednesday, September 09, 2015 Sheet 16 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = PCH

3D3V_S5
PCH strap pin:At which pinout for SKL?
R1709
On Die DSW VR Enable
1 2 AC_PRESENT +V3.3A_SIP +VCCPDSW_3P3

10KR2J-3-GP
1 R1712 2 Low = Disable
DY Do Not Stuff DSWVRMEN High = Enable (default)
+VCCPDSW_3P3 3D3V_S5 *
R1703 This signal has no integrated pull-up/pull-down.
1 R1711

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2
1 2 PCH_WAKE#
1KR2J-1-GP Do Not Stuff
R1713
R1723
Layout note: 3 PAD SHARING [24,31,40,55,61,68,76] PLT_RST# 1 2 PCH_PLTRST#
D 1 2 PCH_BATLOW# D

1
10KR2J-3-GP Do Not Stuff

1
RTC_AUX_S5 +VCCPRIM_3P3 R1715 C1701
Do Not Stuff DY DY Do Not Stuff
R1730 #544669 (CRB): 330k. [#543016 Rev0.7]

2
330KR2J-L1-GP EXT_PWR_GATE#: Due to a bug on A0, a temporary pull-up resistor will be required to overcome the internal 20k

2
1
1 2 SM_INTRUDER# pull-down that is active during the early portion of the power up sequence
R1701
3KR2J-2-GP CPU1K 11 OF 20

SYSTEM POWER MANAGEMENT

2
AT11 SIO_SLP_S0# [40]
SKYLAKE_ULT GPP_B12/SLP_S0#
AP15 SIO_SLP_S3# [24,27,40,51,52,54]
PCH_PLTRST# GPD4/SLP_S3#
AN10 BA16 SIO_SLP_S4# [24,40,51]
XDP_DBRESET# GPP_B13/PLTRST# GPD5/SLP_S4# SIO_SLP_S5# 3D3V_S5_PCH
[99] XDP_DBRESET# B5 AY16 1
SYS_RESET# GPD10/SLP_S5# TP1703 Do Not Stuff
[99] PM_RSMRST# AY17
RSMRST#
DY H_CPUPWRGD SLP_SUS#
AN15
SLP_LAN#
SIO_SLP_SUS# [24,40,53,54]
Do Not Stuff
1 R411 2 A68 AW15 1
[40] H_THERMTRIP_EN PROCPWRGD SLP_LAN# R1731
#544669 Rev0.52 CRB: H_VCCST_PWRGD_R 1 2 60D4R2F-GP H_VCCST_PWRGD B65 BB17 GPD9/SLP_WLAN# 1 TP1704 Do Not Stuff
R1734 VCCST_PWRGD GPD9/SLP_WLAN# SIO_SLP_A# TP1705 Do Not Stuff EXT_PWR_GATE#
No PL resistor on THERMTRIP#. AN16 1 2 1
SYS_PWROK GPD6/SLP_A# TP1706 Do Not Stuff
[24] SYS_PWROK B6
H_CPUPWRGD R1706 PM_PCH_PWROK SYS_PWROK
[24,26,40] RESET_OUT# 1 2 Do Not Stuff BA20 BA15 SIO_PWRBTN# [24,99]
PM_RSMRST# R1704 0R2J-2-GP PCH_DPWROK PCH_PWROK GPD3/PWRBTN# AC_PRESENT 20KR2J-L2-GP
1 2 BB20 AY15
DSW_PWROK GPD1/ACPRESENT PCH_BATLOW#
NON DS3 ME_SUS_PWR_ACK_R AR13 GPD0/BATLOW#
AU13
BATLOW#:

1
[20] ME_SUS_PWR_ACK_R GPP_A13/SUSWARN#/SUSPWRDNACK
R1733 1 2 10KR2J-3-GP PM_RSMRST# SUSACK#_R AP11 Pull-up required even if not implemented.
GPP_A15/SUSACK#
R1732 1 2 10KR2J-3-GP PM_PCH_PWROK R405 DY for OBFF disable AU11 PME# 1
PCH_WAKE# GPP_A11/PME# SM_INTRUDER# TP1707 Do Not Stuff AC_PRESENT
DY Do Not Stuff
R1707 GPD2/LAN_WAKE#
BB15
WAKE# INTRUDER#
AP16
+VCCPDSW_3P3 1 2 10KR2J-3-GP AM15
R1717 SYS_PWROK GPD2/LAN_WAKE# EXT_PWR_GATE#
2 DY 1 Do Not Stuff 2 AW17 AM10 EC1707

1
GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# GPP_B2/VRALERT#
AT15
GPD7/USB2_WAKEOUT# GPP_B2/VRALERT#
AM11 1
TP1708 Do Not Stuff
DY

Do Not Stuff
(PDG#543016)

2
WAKE#: Ensure that WAKE# signal Trise (Maximum) is <100 ns. SKYLAKE-GP

R1710 GPD2/LAN_WAKE#
071.SKYLA.000U
[24] EC_WAKE# 1 2

Do Not Stuff

C C
3D3V_S5
+VCCMPHYGTAON_1P0 2015/04/20 modify

Do Not Stuff
U1702 C1703 D1702
A K PWR_CHG_ACOK [24,44]
1 5

1
NC#1 VCC
SKL: 1.0V [24,27,40,51,52,54] SIO_SLP_S3# 2
A DY 3D3V_S5 RB751V-40H-GP

SCD1U16V2KX-3GP
+VCCMPHYGTAON_1P0(ICCMAX.=3.5A) 83.R2004.G8F

2
3 4 C1702
GND Y +VCCSTG 3D3V_AUX_S5 Q1702

1
1D0V_S5 +VCCMPHYGTAON_1P0_LS_SIP 4 3 AC_PRESENT
74LVC1G07GW-GP R1720
R1724
73.01G07.0HG 2015/02/10 modify 5 2 PM_RSMRST#_R 1NON DS32 PM_RSMRST#
R1737

2
1 2 NON DS3

1
1 NON DS3
2 PM_RSMRST#_M 6 1 0R2J-2-GP
Do Not Stuff U1701 R1722
100KR2J-1-GP 100KR2J-1-GP 2N7002KDW-GP
1

R1735 1 5 84.2N702.A3F
NC#1 VCC
1 2 C1704 Dis-wire with XDP_PM_RSMRST_PWRGD_XDP 2nd = 84.2N702.E3F

2
SC10U10V5KX-2GP 2 3rd = 75.00601.07C Modify on 20150204
[24,40] ALL_SYS_PWRGD
2

Do Not Stuff A
4th = 84.DMN66.03F
3 4 H_VCCST_PWRGD_R
GND Y

1
74LVC1G07GW-GP
73.01G07.0HG EC1708
SCD01U50V2KX-1GP

2
1
R1716
DY 2

Do Not Stuff

1
R1719

1
Do Not Stuff
DY
DY EC1709
Do Not Stuff VCCST_PWRGD / HWM201:

2
B B

XDP_DBRESET#
SYS_PWROK
PLT_RST#
RESET_OUT#
3V_5V_POK

DS3 BOM Option

NON DS3

1
R1708 DY DY DY DY DY
ME_SUS_PWR_ACK_R 1 2 SUSACK#_R EC1706 EC1702 EC1703 EC1704 EC1705
0R2J-2-GP PCH_DPWROK R1718 1 DS3 2 Do Not Stuff 3V_5V_POK [40,45,53,54]

2
Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff
RN1702
2 3 SUSACK#_R
[24] SUSACK# DS3
2

1 4 ME_SUS_PWR_ACK_R
[24] ME_SUS_PWR_ACK
DS3 R1725
Do Not Stuff Do Not Stuff
1

#543016 Rev0.7
1. VCCST_PWRGD is only 1.0 V tolerant.
3D3V_AUX_S5 R1727
100KR2J-1-GP
2. VCCST_PWRGD must go low during Sx pwr states, regardless of the voltage level of VCCST
1 2
NON DS3
2

R1726
10KR2J-3-GP

1KR2J-1-GP
Q1701
1

R1702
4 3 PM_RSMRST# 1 2 PCH_RSMRST# [24]
R1728
3V_5V_POK# 5 2 3V_5V_POK_C 1 2 3V_5V_POK [40,45,53,54]
NON DS3 EC1711 EC1712
6 1
1

0R2J-2-GP DY DY
2N7002KDW-GP DS3
Do Not Stuff

Do Not Stuff

A R1729 1 SIO_SLP_SUS# A
2
2

Do Not Stuff

84.2N702.A3F
2nd = 84.2N702.E3F Iris SKL UMA
3rd = 75.00601.07C
4th = 84.DMN66.03F
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CPU_(POWER MANAGEMENT)
Size Document Number Rev
A2 A00
Iris2 SKL-U
Date: Wednesday, September 09, 2015 Sheet 17 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = PCH PCH strap pin: PCH Prim

PCH strap pin: PCH Prim
eSPI or LPC Sampled at rising edge of RSMRST# 3D3V_S5_PCH
BOOT HALT 3D3V_S5_PCH
SML0ALERT# / This signal has a weak internal pull-down. 3D3V_S5_PCH

1
0 = LPC Is selected for EC. SPI0_MOSI 0 = ENABLED
GPP_C5

1
1 = eSPI Is selected for EC. DY R1822 1 = DISABLED
Do Not Stuff WEAK INTERNAL PU DY R1824 RN1807
This signal has a weak internal pull-down. Do Not Stuff SML1_SMBDATA 8 1
This signal has a weak internal pull-up. SML1_SMBCLK 7 2

2
SML0_SMBDATA 6 3

2
GPP_C5/SML0ALERT# SML0_SMBCLK 5 4
SPI_SI_CPU

Vinafix.com

1
SRN2K2J-4-GP

1
DY R1823
Do Not Stuff DY R1825 R1820
Do Not Stuff 150KR2F-L-GP
D PCH Prim GPP_B23/SML1ALERT# 2 1 D

2
PCH Prim SKL MOW 2014WW52 requirement

2
3D3V_S5_PCH
3D3V_S5_PCH PLACE WITHIN 1.1 INCH OF PCH GPP_C2/SMBALERT# 2 R1817 1
(#543016)Optional, can be left as OPEN/No-Connect. 2K2R2J-2-GP
R1826
1

1 2 SPI_SI_CPU SRN2K2J-1-GP
[99] SPI0_MOSI_XDP
1

R1835 XDPDo Not Stuff

R1834 1KR2J-1-GP MEM_SMBCLK 3 2
1KR2J-1-GP R1827 MEM_SMBDATA 4 1
1 2 SPI_WP_CPU
[99] XDP_SPI0_IO2
2

XDPDo Not Stuff RN1811

2

SPI_HOLD_CPU LPC_LAD[3..0] 20140820 DAIVD

[24,68] LPC_LAD[3..0]
RN1806
1

LPC_LAD2 8 1 LPC_LAD2_R
R1836 LPC_LAD1 7 2 LPC_LAD1_R
SPI_WP_CPU LPC_LAD3 LPC_LAD3_R
DY Do Not Stuff
LPC_LAD0
6 3
LPC_LAD0_R
5 4
2

SRN0J-7-GP-U
3D3V_S0 CPU1E 5 OF 20
Resister value will check later
SPI - FLASH
SMBUS, SMLINK
R2021 3D3V_S5_PCH
[24,25] SPI_CLK_ROM 10R2F-L-GP 1 2 R1806 SPI_CLK_CPU AV2 SKYLAKE_ULT R7 MEM_SMBCLK
SIO_RCIN# 10R2F-L-GP R1807 SPI_SO_CPU SPI0_CLK GPP_C0/SMBCLK MEM_SMBDATA
1 2 [24,25] SPI_SO_ROM 1 2 AW3 R8
10KR2J-3-GP 10R2F-L-GP R1808 SPI_SI_CPU SPI0_MISO GPP_C1/SMBDATA GPP_C2/SMBALERT#
[24,25] SPI_SI_ROM 1 2 AV3 Strap R10
10R2F-L-GP R1809 SPI_WP_CPU SPI0_MOSI GPP_C2/SMBALERT# R1814
R2032 [25] SPI_WP_ROM 1 2 AW2
10R2F-L-GP R1811 SPI_HOLD_CPU SPI0_IO2 SML0_SMBCLK SUS_STAT#/LPCPD#
SERIRQ
[25] SPI_HOLD_ROM 1 2
SPI_CS_CPU_N0
AU4
SPI0_IO3 GPP_C3/SML0CLK
R9
SML0_SMBDATA
2 DY 1
1 2 [24,25] SPI_CS_ROM_N0 Do Not Stuff 1 2 R1812 AU3 W2
10KR2J-3-GP Do Not Stuff R1816 SPI_CS_CPU_N1 SPI0_CS0# GPP_C4/SML0DATA GPP_C5/SML0ALERT# Do Not Stuff
[25] SPI_CS_ROM_N1 1 2 AU2 W1
AU1
SPI0_CS1# Strap GPP_C5/SML0ALERT# 3D3V_S0
SPI0_CS2# SML1_SMBCLK
SERIRQ PH: GPP_C6/SML1CLK
W3 SML1_SMBCLK [24,26,79]
R1818
PDG: 8.2k V3 SML1_SMBDATA 8K2R2F-1-GP
SPI - TOUCH GPP_C7/SML1DATA SML1_SMBDATA [24,26,79]
AM7 GPP_B23/SML1ALERT# CLKRUN#_R 1 2
CRB: 10k Do Not Stuff TP1801 CPU_D1_TP GPP_B23/SML1ALERT#/PCHHOT#
1 M2
Do Not Stuff TP1802 CPU_D2_TP GPP_D1/SPI1_CLK
1 M3
Do Not Stuff TP1803 CPU_D3_TP GPP_D2/SPI1_MISO
1 J4
Do Not Stuff TP1804 CPU_D4_TP GPP_D3/SPI1_MOSI 20140820 DAIVD
1 V1
Do Not Stuff TP1805 CPU_D5_TP GPP_D21/SPI1_IO2
1 V2
Do Not Stuff TP1806 CPU_D6_TP GPP_D22/SPI1_IO3 LPC_LAD0_R
1 M1 LPC AY13
GPP_D0/SPI1_CS# GPP_A1/LAD0/ESPI_IO0 LPC_LAD1_R
C BA13 C
GPP_A2/LAD1/ESPI_IO1 LPC_LAD2_R
BB13
C LINK GPP_A3/LAD2/ESPI_IO2 LPC_LAD3_R
AY12
GPP_A4/LAD3/ESPI_IO3 LPC_LFRAME#_R 3D3V_S0
[61] CL_CLK G3 BA12 2 1 R1801 LPC_LFRAME# [24,68]
CL_CLK GPP_A5/LFRAME#/ESPI_CS# SUS_STAT#/LPCPD# Do Not Stuff
[61] CL_DATA G2 BA11
CL_DATA GPP_A14/SUS_STAT#/ESPI_RESET#
[61] CL_RST# G1
CL_RST# RN1810
AW9 PCI_CLK_LPC0 3 2
GPP_A9/CLKOUT_LPC0/ESPI_CLK 3D3V_S0
RCIN#: [24] SIO_RCIN# AW13 AY9 PCI_CLK_LPC1 4 1
GPP_A0/RCIN# GPP_A10/CLKOUT_LPC1 CLKRUN#_R R1819
Frequency to Avoid: 33 MHz AW11 1 2 Do Not Stuff CLKRUN# [24]
GPP_A8/CLKRUN# SRN10KJ-5-GP
[24] SERIRQ AY11
GPP_A6/SERIRQ
2N7002KDW-GP
SKYLAKE-GP MEM_SMBDATA 6 1 PCH_SMBDATA [12,13,56,65,99]
071.SKYLA.000U
84.2N702.A3F 5 2
1

Do Not Stuff

20140820 DAIVD 2nd = 84.2N702.E3F

CRT
EC1805

DY PCI_CLK_LPC0 R1828 1 2 Do Not Stuff 3rd = 75.00601.07C 4 3

CLK_DP2VGA [56]
4th = 84.DMN66.03F
2

Q1801
PCI_CLK_LPC0
LPC
R1804 1 2 Do Not Stuff CLK_PCI_LPC [68]
PCI_CLK_LPC1 R1805 1 2 33R2J-2-GP CLK_PCI_LPC_MEC [24] PCH_SMBCLK [12,13,56,65,99]

MEM_SMBCLK

EC1804
Do Not Stuff
1
EC1801
Do Not Stuff

EC1802
Do Not Stuff
DY

2
3D3V_S0
DY DY

2
SRN10KJ-6-GP

1 8 CLKREQ_PCIE#5
2 7 CLKREQ_PEG#0
3 6 CLKREQ_PCIE#1
4 5
B B

RN1812
RTC_X1
R1810 C1801
1 2 RTC_X2 XTAL24_IN 1 2 XTAL24_IN_R 2 1
1 8 CLKREQ_PCIE#3 R1815 10MR2J-L-GP
2 7 CLKREQ_PCIE#4 Do Not Stuff
X1802 SC15P50V2JN-L-GP
3 6 CLKREQ_PCIE#2

1
4 5
1 4 X1801

1
RN1813 XTAL-24MHZ-81-GP
R1802
SRN10KJ-6-GP 1MR2J-1-GP 82.30004.841
Swap on 2014/12/24

1
2 3

4
C1804 C1803
C1802

2
SC5P50V2CN-2GP SC5P50V2CN-2GP

2
XTAL24_OUT 2 1
CPU1J 10 OF 20

XTAL-32D768KHZ-68-GP SC15P50V2JN-L-GP
CLOCK SIGNALS
82.30001.G01
[76] PEG_CLK_CPU# D42
CLKOUT_PCIE_N0 SKYLAKE_ULT
GPU [76] PEG_CLK_CPU
[79] CLKREQ_PEG#0
CLKREQ_PEG#0
C42
AR10
CLKOUT_PCIE_P0
GPP_B5/SRCCLKREQ0#
2rd = 82.30001.G11

WLAN [61] PEG_CLK1_CPU#

[61] PEG_CLK1_CPU
B42
A42
CLKOUT_PCIE_N1
CLKOUT_PCIE_P1 CLKOUT_ITPXDP#
F43 PCIE_CLK_XDP_N [99]
SUSCLK_R
CLKREQ_PCIE#1 AT7 E43
[61] CLKREQ_PCIE#1 PCIE_CLK_XDP_P [99]

2
GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P RTC_AUX_S5
D41 BA17 SUSCLK_R R1813 1 2 Do Not Stuff DY EC1803
[31] PEG_CLK2_CPU# CLKOUT_PCIE_N2 GPD8/SUSCLK SUS_CLK [24]
LAN [31] PEG_CLK2_CPU C41

1
CLKOUT_PCIE_P2 +VCCF24NS_1P0_L

Do Not Stuff
AT8 E37 XTAL24_IN
[31] CLKREQ_PCIE#2 GPP_B7/SRCCLKREQ2# XTAL24_IN
E35 XTAL24_OUT +V1.05S_AXCK_LCPLL

2
1
XTAL24_OUT
D40
CLKOUT_PCIE_N3 XCLK_BIASREF
C40 E42 1 R1803 2 RN1901
CLKREQ_PCIE#3 CLKOUT_PCIE_P3 XCLK_BIASREF 2K7R2F-GP
AT10 SRN20KJ-1-GP
GPP_B8/SRCCLKREQ3# RTC_X1
AM18
RTCX1 RTC_X2 Intel recommend: 2.71k ohm 5%
B40 AM20
CLKOUT_PCIE_N4 RTCX2
A40

3
4
CLKREQ_PCIE#4 CLKOUT_PCIE_P4 SRTC_RST#
AU8 AN18
GPP_B9/SRCCLKREQ4# SRTCRST# RTC_RST# Q1901
AM16
A RTCRST# A
E40 [24] RTCRST_ON G
CLKOUT_PCIE_N5 SRTC_RST#
E38 1
CLKREQ_PCIE#5 CLKOUT_PCIE_P5 RTC_RST#
AU7 D
GPP_B10/SRCCLKREQ5# R1902

SC1U10V2KX-1GP

2
10KR2J-3-GP S

1
G1901

C1901
1

1
Iris SKL UMA
Do Not Stuff

2N7002K-2-GP C1902
2

1
EC1808

Do Not Stuff

Do Not Stuff

Do Not Stuff
SKYLAKE-GP SC1U10V2KX-1GP
DY 84.2N702.J31

EC1806

EC1807
071.SKYLA.000U 2ND = 84.2N702.031 DY DY
Wistron Corporation
2

2
3rd = 84.07002.I31

2
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
(#514849)
Taipei Hsien 221, Taiwan, R.O.C.

Title

Layout: Place at the open door area.

Size
CPU_(LPC/SPI/SMBUS/CL/CLK)
Document Number Rev
A2 A00
Iris2 SKL-U
Date: Wednesday, September 09, 2015 Sheet 18 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = PCH

Vinafix.com
D D

CPU1G 7 OF 20

AUDIO
SKYLAKE_ULT
HDA_SYNC BA22
HDA_BITCLK HDA_SYNC/I2S0_SFRM
AY22 HDA_BLK/I2S0_SCLK
HDA_SDOUT BB22 SDIO/SDXC
HDA_SDO/I2S0_TXD
[27] HDA_SDIN0 BA21 HDA_SDI0/I2S0_RXD
AY21 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB11
HDA_RST# AW22 AB13
HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0
J5 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 AB12
AY20 I2S1_SFRM GPP_G3/SD_DATA2 W12
AW20 I2S1_TXD GPP_G4/SD_DATA3 W11
W10 R1903
GPP_G5/SD_CD# KB_LED_BL_DET
AK7 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK W8 1 2 Do Not Stuff KB_LED_BL_DET_R [65]
AK6 GPP_F0/I2S2_SCLK GPP_G7/SD_WP W7
AK9 GPP_F2/I2S2_TXD
[24,79,85] DGPU_PW ROK AK10 GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BA9
BB9 CPU_A16_TP 1 TP1902
GPP_A16/SD_1P8_SEL Do Not Stuff

1
DY H5 AB7 SD_RCOMP 1 R1901 2
EC2001 GPP_D19/DMIC_CLK0 SD_RCOMP
D7 GPP_D20/DMIC_DATA0
2 200R2F-L-GP
Do Not Stuff

R2052 1 UMA 2 DGPU_PW ROK D8 AF13

100KR2J-1-GP DGPU_PW ROK GPP_D17/DMIC_CLK1 GPP_F23
C8 GPP_D18/DMIC_DATA1
[27] SPKR SPKR AW5
C GPP_B14/SPKR C

PCH strap pin: SKYLAKE-GP

PCH strap pin: 071.SKYLA.000U
Flash Descriptor Security Overide/ NO REBOOT
3D3V_S0
Intel ME Debug Mode Do Not Stuff
Low = Default Low = Enable (Default) R2006
HDA_SDOUT
* HDA_SPKR
* 1 DY 2 SPKR
High = Enable High = Disable
The internal pull-down is disabled after
PLTRST# deasserts The internal pull-down is disabled after
PLTRST# deasserts

[27] HDA_CODEC_BITCLK R1907 1 2 33R2J-2-GP HDA_BITCLK

[27] HDA_CODEC_SYNC R1908 1 2 Do Not Stuff HDA_SYNC

[27] HDA_CODEC_RST# R1911 1 2 Do Not Stuff HDA_RST#

EC1901
1 2 HDA_CODEC_BITCLK
B B
DY R1912
[27] HDA_CODEC_SDOUT 1 2 33R2J-2-GP HDA_SDOUT
Do Not Stuff
[24] ME_FW P_EC R1909 1 2 1KR2J-1-GP

HDA_CODEC_RST#
1

DY EC1902
Do Not Stuff
2

A Iris SKL UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(AUDIO/SDIO/SDXC)
Size Document Number Rev
A3 A00
Iris2 SKL-U
Date: W ednesday, September 09, 2015 Sheet 19 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = PCH 3D3V_S0

Do Not Stuff
RN2009 RN2007
1 4 DGPU_HOLD_RST# I2C0_SCL 1 4
2 DY 3 DGPU_PWR_EN I2C0_SDA 2 DY 3

Do Not Stuff
RN2008
CPU1F 6 OF 20 I2C1_SCL 1 4
I2C1_SDA 2 DY 3
LPSS ISH
SKYLAKE_ULT
USB_UART_SEL_D9 1 TP2006 Do Not Stuff Do Not Stuff
[76] DGPU_HOLD_RST# AN8 P2
GPP_B15/GSPI0_CS# GPP_D9/ISH_SPI_CS# DGPU_HOLD_RST#

Vinafix.com
AP7 P3
VRAM_ID1 GPP_B16/GSPI0_CLK GPP_D10/ISH_SPI_CLK
AP8 P4 (PDG#543016) Ensure that all I2C interface on-board terminations are pulled up
GPP_B18/GSPI0_MOSI GPP_B17/GSPI0_MISO GPP_D11/ISH_SPI_MISO RTC_DET#
AR7 P1 RTC_DET# [25] to the same voltage rail as the device/end point.
GPP_B18/GSPI0_MOSI GPP_D12/ISH_SPI_MOSI

1
3D3V_S0 DY Strap
EC2002 AM5 M4 I2C0_SDA
[55] DBC_PANEL_EN GPP_B19/GSPI1_CS# GPP_D5/ISH_I2C0_SDA
D AN7 N3 I2C0_SCL D

2
GPP_B20/GSPI1_CLK GPP_D6/ISH_I2C0_SCL

Do Not Stuff
AP5
TP2008 GPP_B22/GSPI1_MOSI GPP_B21/GSPI1_MISO I2C1_SDA
1 AN5 N1
Do Not Stuff GPP_B22/GSPI1_MOSI GPP_D7/ISH_I2C1_SDA I2C1_SCL
N2
51KR2J-1-GP R2048 LPSS_UART2_RXD GPP_D8/ISH_I2C1_SCL
2 1 AB1
51KR2J-1-GP R2049 LPSS_UART2_TXD GPP_C8/UART0_RXD 1.8V Only
2 1 [61] BLUETOOTH_EN AB2 AD11
GPP_C9/UART0_TXD GPP_F10/I2C5_SDA/ISH_I2C2_SDA
[60] SATA_ODD_PWRGT W4 AD12
51KR2J-1-GP R2046 LPSS_UART2_CTS# BOARD_ID2 GPP_C10/UART0_RTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL
2 1 AB3
GPP_C11/UART0_CTS#
LPSS_UART2_RXD AD1 U1 DGPU_PWR_EN [85,86]
3D3V_S0 LPSS_UART2_TXD GPP_C20/UART2_RXD GPP_D13/ISH_UART0_RXD/SML0BDATA UART0_TXD TP2007 Do Not Stuff
AD2 U2 1
GPP_C21/UART2_TXD GPP_D14/ISH_UART0_TXD/SML0BCLK UART0_RTS# TP2010 Do Not Stuff
[24] SIO_EXT_WAKE# AD3 U3 1
LPSS_UART2_CTS# GPP_C22/UART2_RTS# GPP_D15/ISH_UART0_RTS# UART0_CTS# TP2011 Do Not Stuff
AD4 U4 1
GPP_C23/UART2_CTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT#
R1910 1 2 10KR2J-3-GP BLUETOOTH_EN AC1 UART1_RXD 1 TP2012 Do Not Stuff 3D3V_S0
GPP_C12/UART1_RXD/ISH_UART1_RXD UART1_TXD TP2013 Do Not Stuff (PDG#543016) If the UART/GPIO functionality is also not used,
U7 AC2 1
R1914 1 2 2K2R2J-2-GP DBC_PANEL_EN PTP[65]
[65]
I2C0_SDA_TCH_PAD
I2C0_SCL_TCH_PAD U6
GPP_C16/I2C0_SDA
GPP_C17/I2C0_SCL
GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
AC3 UART1_RTS# 1 TP2014 Do Not Stuff the signals can be left as no-connect.
AB4 UART1_CTS# 1
GPP_C15/UART1_CTS#/ISH_UART1_CTS#

1
2015/05/13 DVT2 modify U8
GPP_C18/I2C1_SDA
TP2015Do Not Stuff
PCH Prim U9 AY8 PROJECT_ID1 R2027
GPP_C19/I2C1_SCL GPP_A18/ISH_GP0 PROJECT_ID2 10KR2J-3-GP
BA8
PCH strap pin: AH9
GPP_A19/ISH_GP1
BB7 KB_DET#
KB_DET# [65]
3D3V_S5_PCH GPP_F4/I2C2_SDA GPP_A20/ISH_GP2 BOARD_ID3
AH10 BA7

2
GPP_F5/I2C2_SCL GPP_A21/ISH_GP3 KB_DET#
No Reboot Sampled at rising edge of PCH_PWROK AY7
GPP_A22/ISH_GP4 VRAM_ID2
AH11 AW7

1
GPP_F6/I2C3_SDA GPP_A23/ISH_GP5
AH12 AP13 PANEL_SIZE_ID [55]
0 = Disable “No Reboot” mode. R2007 GPP_F7/I2C3_SCL GPP_A12/BM_BUSY#/ISH_GP6
GSPI0_MOSI / DY
GPP_B18 1 = Enable “No Reboot” mode (PCH will disable the TCO Do Not Stuff AF11
GPP_F8/I2C4_SDA 3D3V_S0 3D3V_S0 GPP_A19 GPP_A18
Timer system reboot feature). This function is useful AF12
GPP_F9/I2C4_SCL BIOS strap pin:
when running ITP/XDP. 2

GPP_B18/GSPI0_MOSI SKYLAKE-GP PROJECT_ID2 PROJECT_ID1

PROJECT Strap pin
The signal has a weak internal pull-down.
1

1
DY R2019 071.SKYLA.000U R2015 R2017 Iris2 X 0
Do Not Stuff Do Not Stuff
Do Not Stuff DY
3D3V_S0
LOVE LAND
LOVE LAND X 1
2

2
PROJECT_ID1 PROJECT_ID2
For debug USB/UART:
Tulip X X

1
C C
RN2010
R2016 R2018
I2C0_SDA_TCH_PAD 5V_S5 10KR2J-3-GP Do Not Stuff
1 4 DY

5
2 DY 3 I2C0_SCL_TCH_PAD DB2 Iris2

2
1
Do Not Stuff
LPSS_UART2_TXD 2
LPSS_UART2_RXD 3 20.F1897.004
4
3D3V_S5_PCH 3D3V_S0
EVT_0925
3D3V_S0
2015/05/6 DVT2 modify

1
R2039 1 DY 2 Do Not Stuff ACES-CON4-37-GP R2025

1
R2040 1 RTC_DET# ME_SUS_PWR_ACK_R [17]
2 10KR2J-3-GP GPP_C11
R2041 1 2 10KR2J-3-GP SIO_EXT_WAKE# 1LPSS_UART2_CTS# R2005 BIOS strap pin: EXO Do Not Stuff BIOS strap pin: GPP_A21
OPS Do Not Stuff

2
BIOS UMA/DIS Strap pin BOARD_ID2 BIOS UMA/DIS Strap pin BOARD_ID3
TP2009 BOARD_ID3

2
Do Not Stuff
BOARD_ID2 UMA 0 MESO 0
PCH strap pin:

1
R2026

1
1
No Reboot Sampled at rising edge of PCH_PWROK
R2008
DIS MESODo Not Stuff EXO 1
Intel has removed EHCI controller from BDW 10KR2J-3-GP
UMA

2
GSPI0_MOSI / 0 = Disable “No Reboot” mode. and proposed to use UART interface for Win7 debug.
GPP_B18 1 = Enable “No Reboot” mode (PCH will disable the TCO

2
Timer system reboot feature). This function is useful
when running ITP/XDP.

The signal has a weak internal pull-down.

3D3V_S0 3D3V_S0

1
R2053 R2023 GPP_A23 GPP_B17
VRAM_4G Do Not Stuff VRAM_2G Do Not Stuff BIOS strap pin:
B BIOS VRAM Size Strap pin VRAM_ID2 VRAM_ID1 B

2
VRAM_ID2 VRAM_ID1
1G 0 0

1
R2054 R2024 2G 0 1
VRAM_1G / 2GDo Not Stuff VRAM_1G / 4G Do Not Stuff

4G 1 0

2
A A

Iris SKL UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(LPSS/ISH)
Size Document Number Rev
A2 A00
Iris2 SKL-U
Date: Wednesday, September 09, 2015 Sheet 20 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = PCH

+VCCPRIM_1P0
CPU1O 15 OF 20
CPU POWER 4 OF 4

AB19 RTC_AUX_S5
VCCPRIM_1P0
AB20 AK15 +VCCPGPPA
+VCCPRIM_CORE VCCPRIM_1P0 SKYLAKE_ULT VCCPGPPA C2119 C2118

Vinafix.com
P18 AG15 +VCCPGPPB
VCCPRIM_1P0 VCCPGPPB

Do Not Stuff

SCD1U16V2KX-3GP
Y16 +VCCPGPPC

1
VCCPGPPC

C2117
2.57A AF18 Y15 DY

SC1U10V2KX-1GP
VCCPRIM_CORE VCCPGPPD +VCCPGPPD
AF19 T16 +VCCPGPPE
VCCPRIM_CORE VCCPGPPE
V20 1.8V Only AF16 +VCCPGPPF

2
VCCPRIM_CORE VCCPGPPF
D V21 AD15 +VCCPGPPG D
+VCCDSW_1P0 VCCPRIM_CORE VCCPGPPG
C2120 AL1 V19 +VCCPRIM_3P3
DCPDSW_1P0 VCCPRIM_3P3_V19
1

+VCCMPHYAON_1P0
DY K17
VCCMPHYAON_1P0 VCCPRIM_1P0_T1
T1 +VCCDTS_1P0
L1
2

VCCMPHYAON_1P0
Do Not Stuff

+VCCMPHYGTAON_1P0_LS_SIP
N15
VCCATS_1P8
AA1 +V1.8A_SIP CAP need close to VCCRTC
VCCMPHYGT_1P0_N15 +VCCPRTCPRIM_3P3
N16 AK17
VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3 +VCCPRTC_3P3
N17
VCCMPHYGT_1P0_N17
P15 AK19
+VCCAMPHYPLL_1P0 VCCMPHYGT_1P0_P15 VCCRTC_AK19
P16 BB14
VCCMPHYGT_1P0_P16 VCCRTC_BB14
K15 BB10 VCCRTCEXT C2112 1 2 SCD1U16V2KX-3GP
VCCAMPHYPLL_1P0 DCPRTC
L15
+VCCAPLL_1P0 VCCAMPHYPLL_1P0
A14 +VCC19P2_1P0
VCCCLK1
V15
+V1.00A_SIP VCCAPLL_1P0
K19 +VCCF100_1P0_L
VCCCLK2
AB17
VCCPRIM_1P0_AB17
Y18 L21 +VCCF135_1P0
+VCCPDSW_3P3 VCCPRIM_1P0_Y18 VCCCLK3 +VCCPRTC_3P3
AD17 N20 RTC_AUX_S5
VCCDSW_3P3_AD17 VCCCLK4 +VCCF100OC_1P0_L
AD18
+VCCPAZIO VCCDSW_3P3_AD18
AJ17 L19 +VCCF24NS_1P0_L
VCCDSW_3P3_AJ17 VCCCLK5
AJ19 A10 +VCC24TBT_1P0 1 R2106 2
VCCHDA VCCCLK6

+VCCPSPI AJ16 AN11 V0.85A_VID0 1 TP2101 Do Not Stuff Do Not Stuff

VCCSPI GPP_B0/CORE_VID0
AN13 V0.85A_VID1 1 TP2102 Do Not Stuff
GPP_B1/CORE_VID1
+VCCSRAM_1P0 AF20
VCCSRAM_1P0
AF21
VCCSRAM_1P0
T19
VCCSRAM_1P0
T20
+VCCPRIM_3P3 VCCSRAM_1P0
AJ21
+VCCFHV VCCPRIM_3P3_AJ21
AK20
VCCPRIM_1P0_AK20
071.SKYLA.000U
+VCCAPLLEBB_1P0 N18
VCCAPLLEBB

C C
SKYLAKE-GP

+VCCPRIM_1P0 +VCCPRIM_CORE +VCCDSW_1P0 +VCCMPHYAON_1P0 +VCCPRIM_3P3 +VCCPGPPC +VCCPGPPE +V1.8A_SIP +VCCPRTCPRIM_3P3 +VCC24TBT_1P0
C2101

C2102

C2103

C2104

C2105

C2106

C2107

C2108

C2109

C2116
1

1
Do Not Stuff

Do Not Stuff

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

Do Not Stuff

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP
DY DY DY DY C2110 DY C2111

Do Not Stuff

Do Not Stuff
2

2
+VCCF100_1P0_L +VCCF24NS_1P0_L +VCCF100OC_1P0_L
Do Not Stuff

B B
Do Not Stuff

C2113 C2115 C2114

1

SC22U6D3V5MX-2GP
DY DY
2

A A

Iris SKL UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(POWER1)
Size Document Number Rev
A2 A00
Iris2 SKL-U
Date: Tuesday, May 26, 2015 Sheet 21 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = PCH

Vinafix.com
D D

CPU1T 20 OF 20
SKYLAKE_ULT
SPARE

AW69 RSVD_AW69 RSVD_F6 F6

AW68 RSVD_AW68 RSVD_E3 E3
AU56 RSVD_AU56 RSVD_C11 C11
AW48 RSVD_AW48 RSVD_B11 B11
C7 RSVD_C7 RSVD_A11 A11
RSVD_U12 U12 D12
RSVD_U11 RSVD_U12 RSVD_D12
U11 RSVD_U11 RSVD_C12 C12
C2202

C2201

H11 RSVD_H11 RSVD_F52 F52

1

1
Do Not Stuff

Do Not Stuff

DY DY
2

SKYLAKE-GP
C C
071.SKYLA.000U

SKL MOW 2014WW52 requirement

B B

Iris SKL UMA

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(RSVD)
Size Document Number Rev
A4 A00
Iris2 SKL-U
Date: Tuesday, May 26, 2015 Sheet 22 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = PCH

CPU1P 16 OF 20

Do Not Stuff
GND 1 OF 3

SKYLAKE_ULT
Vinafix.com CPU1Q 17 OF 20 CPU1R 18 OF 20
TP2307 1NCTF_A5 A5 AL65
VSS VSS GND 2 OF 3
D A67 VSS VSS AL66 GND 3 OF 3 D
TP2301 1NCTF_A70 A70 AM13 F8 L18
VSS VSS SKYLAKE_ULT VSS VSS
AA2 VSS VSS AM21 AT63 VSS VSS BA49 G10 VSS VSS L2
AA4 AM25 AT68 BA53 G22 SKYLAKE_ULT L20
Do Not Stuff VSS VSS VSS VSS VSS VSS
AA65 VSS VSS AM27 AT71 VSS VSS BA57 G43 VSS VSS L4
AA68 VSS VSS AM43 AU10 VSS VSS BA6 G45 VSS VSS L8
AB15 VSS VSS AM45 AU15 VSS VSS BA62 G48 VSS VSS N10
AB16 VSS VSS AM46 AU20 VSS VSS BA66 G5 VSS VSS N13
AB18 AM55 AU32 BA71 NCTF_BA71 1 TP2303 G52 N19
VSS VSS VSS VSS VSS VSS
AB21 VSS VSS AM60 AU38 VSS VSS BB18 G55 VSS VSS N21
AB8 AM61 AV1 BB26 Do Not Stuff G58 N6
VSS VSS VSS VSS VSS VSS
AD13 VSS VSS AM68 AV68 VSS VSS BB30 G6 VSS VSS N65
AD16 VSS VSS AM71 AV69 VSS VSS BB34 G60 VSS VSS N68
AD19 VSS VSS AM8 AV70 VSS VSS BB38 G63 VSS VSS P17
AD20 VSS VSS AN20 AV71 VSS VSS BB43 G66 VSS VSS P19
AD21 VSS VSS AN23 AW10 VSS VSS BB55 H15 VSS VSS P20
AD62 VSS VSS AN28 AW12 VSS VSS BB6 H18 VSS VSS P21
AD8 VSS VSS AN30 AW14 VSS VSS BB60 H71 VSS VSS R13
AE64 VSS VSS AN32 AW16 VSS VSS BB64 J11 VSS VSS R6
AE65 AN33 AW18 BB67 Do Not Stuff J13 T15
VSS VSS VSS VSS NCTF_BB70 1 TP2304 VSS VSS
AE66 VSS VSS AN35 AW21 VSS VSS BB70 J25 VSS VSS T17
AE67 AN37 AW23 C1 NCTF_C1 1 TP2308 J28 T18
VSS VSS VSS VSS VSS VSS
AE68 VSS VSS AN38 AW26 VSS VSS C25 J32 VSS VSS T2
AE69 AN40 AW28 C5 Do Not Stuff J35 T21
VSS VSS VSS VSS VSS VSS
AF1 VSS VSS AN42 AW30 VSS VSS D10 J38 VSS VSS T4
AF10 VSS VSS AN58 AW32 VSS VSS D11 J42 VSS VSS U10
AF15 VSS VSS AN63 AW34 VSS VSS D14 J8 VSS VSS U63
AF17 VSS VSS AP10 AW36 VSS VSS D18 K16 VSS VSS U64
AF2 VSS VSS AP18 AW38 VSS VSS D22 K18 VSS VSS U66
C AF4 AP20 D25 K22 U67 C
VSS VSS VSS VSS VSS
AF63 VSS VSS AP23 AW41 VSS VSS D26 K61 VSS VSS U69
AG16 VSS VSS AP28 AW43 VSS VSS D30 K63 VSS VSS U70
AG17 VSS VSS AP32 AW45 VSS VSS D34 K64 VSS VSS V16
AG18 VSS VSS AP35 AW47 VSS VSS D39 K65 VSS VSS V17
AG19 VSS VSS AP38 AW49 VSS VSS D44 K66 VSS VSS V18
AG20 VSS VSS AP42 AW51 VSS VSS D45 K67 VSS VSS W13
AG21 VSS VSS AP58 AW53 VSS VSS D47 K68 VSS VSS W6
AG71 VSS VSS AP63 AW55 VSS VSS D48 K70 VSS VSS W9
AH13 VSS VSS AP68 AW57 VSS VSS D53 K71 VSS VSS Y17
AH6 VSS VSS AP70 AW6 VSS VSS D58 L11 VSS VSS Y19
AH63 VSS VSS AR11 AW60 VSS VSS D6 L16 VSS VSS Y20
AH64 VSS VSS AR15 AW62 VSS VSS D62 L17 VSS VSS Y21
AH67 VSS VSS AR16 AW64 VSS VSS D66
AJ15 VSS VSS AR20 AW66 VSS VSS D69
AJ18 VSS VSS AR23 AW8 VSS VSS E11
AJ20 VSS VSS AR28 AY66 VSS VSS E15
AJ4 AR35 B10 E18 SKYLAKE-GP
VSS VSS VSS VSS
AK11 VSS VSS AR42 B14 VSS VSS E21
AK16 VSS VSS AR43 B18 VSS VSS E46
AK18 AR45 B22 E50 [#543016 Rev0.9] 071.SKYLA.000U
VSS VSS VSS VSS
AK21 VSS VSS AR46 B30 VSS VSS E53
AK22 VSS VSS AR48 B34 VSS VSS E56
AK27 VSS VSS AR5 B39 VSS VSS E6
AK63 VSS VSS AR50 B44 VSS VSS E65
AK68 VSS VSS AR52 B48 VSS VSS E71
AK69 VSS VSS AR53 B53 VSS VSS F1
AK8 VSS VSS AR55 B58 VSS VSS F13
AL2 VSS VSS AR58 B62 VSS VSS F2
B Do Not Stuff B
AL28 VSS VSS AR63 B66 VSS VSS F22
AL32 AR8 TP2302 1NCTF_B71 B71 F23
VSS VSS TP2305 VSS VSS
AL35 VSS VSS AT2 1NCTF_BA1 BA1 VSS VSS F27
AL38 AT20 Do Not Stuff BA10 F28
VSS VSS VSS VSS
AL4 VSS VSS AT23 BA14 VSS VSS F32
AL45 VSS VSS AT28 BA18 VSS VSS F33
AL48 AT35 TP2306 1NCTF_BA2 BA2 F35
VSS VSS Do Not Stuff VSS VSS
AL52 VSS VSS AT4 BA23 VSS VSS F37
AL55 VSS VSS AT42 BA28 VSS VSS F38
AL58 VSS VSS AT56 BA32 VSS VSS F4
AL64 VSS VSS AT58 BA36 VSS VSS F40
F68 VSS VSS F42
BA45 VSS VSS BA41
SKYLAKE-GP

071.SKYLA.000U
SKYLAKE-GP

071.SKYLA.000U

A Iris SKL UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(VSS)
Size Document Number Rev
A3 A00
Iris2 SKL-U
Date: Tuesday, May 26, 2015 Sheet 23 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = KBC 3D3V_S5

MODEL_ID_DET(GPIO07) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE
3D3V_S5 PCB VERSION A/D(PIN98) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE
3D3V_S5 3D3V_S5_KBC 3D3V_S5_KBC TBD 100.0K 10.0K(64.10025.6DL) 3.0V
M00 (SA) 100.0K 10.0K 3.0V R2442 TBD 100.0K 22.1K(64.22125.6DL) 2.702V

1
32K4R2F-1-GP Iris2_SKL_UMA 100.0K 32.4K(64.32425.6DL) 2.492V

1
1D0V_S5 R2443 X00 (SB) 100.0K 20.0K 2.75V TBD 100.0K 49.9K(64.49925.6DL) 2.201V
R2402 3D3V_S5 1 R2446 2 64K9R2F-1-GP MODEL_ID Iris2_SKL_DIS 100.0K 64.9K(64.64925.6DL) 2.001V
1 2 EC_VTT PCB_REV X01 (SC) 100.0K 33.0K 2.48V Love_land_DIS 100.0K 93.1K(64.93125.6DL) 1.709V

2
20140814 DAVID Do Not Stuff Love_land_UMA 100.0K 120K(64.12035.6DL) 1.499V

2
Do Not Stuff C2406 R2462 X02 (SD) 100.0K 47.0K 2.24V TBD 100.0K 200K(64.20035.6DL) 1.099V
R2474

2
MODEL_ID

Do Not Stuff
SCD1U16V2KX-3GP
2
+VCCSTG BOARD_ID 2 1BOARD_ID_R A00 (1) 100.0K 64.9K 2.0V
R2440

1
3D3V_S5_KBC

2
1 DY 2 Do Not Stuff Reserved 100.0K 76.8 1.87V R2441
C2408 R2444 C2407 100KR2F-L1-GP

2
Do Not Stuff 100KR2F-L1-GP Reserved 100.0K 100.0K 1.65V

SCD1U16V2KX-3GP

1
+V1.00U_CPU If don't need RTC alarm wake up,

SCD1U16V2KX-3GP
Vinafix.com
R2492

2
can change to 3D3V_AUX_S5

C2420

C2412

C2411

C2410

C2414

C2413

C2417
Reserved 100.0K 143.0K 1.358V

2
1

1
C2421

C2416

C2415
1 DY 2

1
DY Reserved 100.0K 174.0K 1.204V
Do Not Stuff DY EC_AGND

SCD1U16V2KX-3GP 2

SCD1U16V2KX-3GP 2

SCD1U16V2KX-3GP 2

SCD1U16V2KX-3GP 2

SCD1U16V2KX-3GP 2

SCD1U16V2KX-3GP 2

Do Not Stuff 2
Reserved 100.0K 215.0K 1.048V

SCD1U16V2KX-3GP 2

SCD1U16V2KX-3GP 2

Do Not Stuff 2
EC_AGND

C2423
Layout Note:

1
3D3V_AUX_S5 RTC_AUX_S5
D D
Need very close to EC
R2472

SCD1U16V2KX-3GP
2
2

2
Do Not Stuff
DY R2473
Do Not Stuff

1
ECVBAT 3D3V_S5_KBC
RN2402

1
EC_AGND 3D3V_AUX_KBC_33
C2428 SMBCLK1 3 2
SMBDA1 4 1

2
SCD1U16V2KX-3GP
SRN4K7J-8-GP

122

103
3D3V_S5_KBC 3D3V_S5_KBC

43
82

19
65
5
KBC24
54

VBAT

VTR
VTR
VTR
VTR
VTR
VTR
VTR_33_18 3D3V_S5_KBC
[65] KSO[0..16]
2

RN2412
1 8 KSI7 R2450 KSO0 2 3D3V_S0
KSI4 KSO1 GPIO027/KSO00/PVT_IO1 SMBDA1
2 7 100KR2J-1-GP 14 8 SMBDA1 [43,44]
KSI2 KSO2 GPIO015/KSO01/PVT_CS# GPIO007/SMB01_DATA/SMB01_DATA18 SMBCLK1 3D3V_S0 PCH_ALW_ON R2495 1
3 6 15 9 SMBCLK1 [43,44] DS3 2 Do Not Stuff
KSI1 KSO3 GPIO016/KSO02/PVT_SCLK GPIO010/SMB01_CLK/SMB01_CLK18 SMBDA2
4 5 16 11
1

GPIO017/KSO03/PVT_IO0 GPIO012/SMB02_DATA/SMB02_DATA18

2
KSO4 37 12 SMBCLK2 PBAT_PRES# R2415 1 2 10KR2J-3-GP
KSO9 KSO5 GPIO045/BCM_INT1#/KSO04 GPIO013/SMB02_CLK/SMB02_CLK18 R2430
38 89 SYS_PWROK [17]
SRN10KJ-6-GP KSO6 GPIO046/BCM_DAT1/KSO05 GPIO130/SMB03_DATA/SMB03_DATA18 L_BKLT_EN_EC SIO_EXT_SCI# R2411
39 91 10KR2J-3-GP 1 2 Do Not Stuff SIO_EXT_SCI#_R [16]
RN2409 KSO7 GPIO047/BCM_CLK1/KSO06 GPIO131/SMB03_CLK/SMB03_CLK18 TOUCH_PANEL_INTR# R2429 1
50 96 SIO_SLP_SUS# [17,40,53,54] DY 2 Do Not Stuff
GPIO025/KSO07/PVT_IO2 GPIO141/SMB04_DATA/SMB04_DATA18
2

1 8 KSI0 KSO8 46 97 PBAT_PRES# PBAT_PRES# [43,44] SIO_EXT_SMI# R2412 1 2 Do Not Stuff SIO_EXT_SMI#_R [8]

1
KSI3 R2449 KSO9 GPIO055/PWM2/KSO08/PVT_IO3 GPIO142/SMB04_CLK/SMB04_CLK18 D2403 Touch Panel PH internally.
2 7 68
KSI5 KSO10 GPIO102/KSO09/CR_STRAP FAN1_TACH R2457 1
3 6 DY Do Not Stuff 72 40 A K FAN_TACH1 [26] DY 2 Do Not Stuff USB_OC3# [16]
KSI6 KSO11 GPIO106/KSO10 GPIO050/TACH0
4 5 74 41
3D3V_S5_KBC KSO12 75
GPIO110/KSO11 MEC1404 GPIO051/TACH1 LID_CL_SIO# [64]
1

KSO13 GPIO111/KSO12 RB751V-40H-GP

76
GPIO112/PS2_CLK1A/KSO13 GPIO053/PWM0
44 BKLGT_PWM [65] 2015/1/14 mofidy
SRN10KJ-6-GP KSO14 77 45 BEEP [27] 83.R2004.G8F
KSO15 GPIO113/PS2_DAT1A/KSO14 GPIO054/PWM1 R2427
RN2410 RN2403 86
KSO5 KSO14 KSO16 GPIO125/KSO15 DGPU_PWROK_KBC 3D3V_S5
1 8
KSO7
1 8
KSO0 CAP_LED#
92
GPIO132/KSO16 GPIO056/PWM3
47 1 OPS 2
Do Not Stuff
DGPU_PWROK [19,79,85]
2 7 2 7 93 34 SUSACK# [17]
KSO12 KSO2 GPIO140/KSO17 GPIO030/BCM_INT0#/PWM4
3 6 3 6 [65] KSI[0..7] 35 EC_WAKE# [17] RN2405
KSO16 KSO1 KSI0 GPIO031/BCM_DAT0/PWM5
4 5 4 5 98 36 PS_ID [43] 1 8
KSI1 GPIO143/KSI0/DTR# GPIO032/BCM_CLK0/PWM6
99 4 PCIE_WAKE# [31] 2 7
KSI2 GPIO144/KSI1/DCD# GPIO002/PWM7 L_BKLT_EN_EC
6 2 1 R2435 L_BKLT_EN [8] LID_CL_SIO# 3 6
SRN100KJ-5-GP SRN100KJ-5-GP KSI3 GPIO005/SMB00_DATA/SMB00_DATA18/KSI2 BAT1_LED# Do Not Stuff
7 1 Q2412 [65] TP_EN# 4 5
GPIO006/SMB00_CLK/SMB00_CLK18/KSI3 GPIO157/LED0/TST_CLK_OUT

1
RN2411 RN2404 KSI4 104 106 BAT2_LED# eDP backlight Control from PCH
KSO15 KSO3 KSI5 GPIO147/KSI4/DSR# GPIO156/LED1 R2436 BAT1_LED#
1 8 1 8 105 70 SIO_SLP_S3# [17,27,40,51,52,54] 1 6 BATT_WHITE_LED# [64]
KSO13 KSO8 KSI6 GPIO150/KSI5/RI# GPIO104/LED2 100KR2J-1-GP SRN100KJ-5-GP
2 7 2 7 107
KSO11 KSO6 KSI7 GPIO151/KSI6/RTS#
3 6 3 6 108 80 ME_FWP_EC [19] 3D3V_S5 2 5 3D3V_S5
KSO10 KSO4 GPIO152/KSI7/CTS# GPIO116/TFDP_DATA/UART_RX
4 5 4 5 81 HOST_DEBUG_TX [61]

2
GPIO117/TFDP_CLK/UART_TX 3D3V_AUX_S5 BAT2_LED#
[65] CLK_TP_SIO 78 [64] CHG_AMBER_LED# 3 4
GPIO114/PS2_CLK0 PTP_DIS#
[65] DAT_TP_SIO 79
GPIO115/PS2_DAT0 GPIO035/SB-TSI_CLK
90 Need very close to EC

1
SRN100KJ-5-GP SRN100KJ-5-GP [17,99] SIO_PWRBTN# 52 94 PECI_EC 1 2
GPIO026/PS2_CLK1B GPIO033/PECI_DAT/SB_TSI_DAT H_PECI [4] 2N7002KDW-GP

Do Not Stuff
[17] PCH_RSMRST# 88 R2437 R2453
GPIO127/PS2_DAT1B ECVBAT

C2405
[18,68] LPC_LAD[3..0] 95 EC_VTT 43R2J-GP 1KR2J-1-GP Q2412 and Q2413 merge 84.2N702.A3F
VREF_CPU

1
LPC_LAD0 59
GPIO040/LAD0 2nd = 84.2N702.E3F

2
LPC_LAD1 60 101 ICSP_CLOCK DY

2
GPIO041/LAD1 GPIO145/ICSP_CLOCK 3rd = 75.00601.07C
LPC_LAD2 61 102 ICSP_DATA +3VLP 24014/12/23 modify

2
LPC_LAD3 GPIO042/LAD2 GPIO146/ICSP_DATA ICSP_CLR
C R2410 62
GPIO043/LAD3 ICSP_MCLR
87 4th = 84.DMN66.03F C
[18,68] LPC_LFRAME# 58 R2452
PCH_PLTRST#_EC GPIO044/LFRAME# EC_MUTE# 100KR2J-1-GP
[17,31,40,55,61,68,76] PLT_RST# 2 1 56 119 EC_MUTE# [27]

1
GPIO064/LRESET# BGPO/GPIO004
2

2
[18] CLK_PCI_LPC_MEC 57 120 +3VLP
GPIO034/PCI_CLK SYSPWR_PRES/GPIO003
Do Not Stuff C2402 DY [18] CLKRUN# 63
GPIO067/CLKRUN# VCI_OUT/GPIO036
121 ALWON ALWON [40]
DGPU_PWROK Do Not Stuff [18] SERIRQ 55 126 VCI_IN1# R2455
1

GPIO063/SER_IRQ VCI_IN1#/GPIO162 3D3V_AUX_S5

2 R2510 1 SIO_EXT_SMI# 10 127 POWER_SW_IN#
EC2401 GPIO011/SMI#/EMI_INT# VCI_IN0#/GPIO163
DY Do Not Stuff TP_EN# 49 128 ACAV_IN R2469 2 1 Do Not Stuff PWR_CHG_ACOK [17,44] 100KR2J-1-GP

1
GPIO060/KBRST VCI_OVRD_IN/GPIO164
1

DY [18] SIO_RCIN# 53
GPIO061/LPCPD#

2
SIO_EXT_SCI# 66 23
GPIO100/EC_SCI# GPIO160/DAC_0
Do Not Stuff

24 FAN1_DAC_1 [26] R2424

2

SATA_LED# 10R2F-L-GP GPIO161/DAC_1 Vref = 1.117

[64] SATA_LED# [18,25] SPI_CLK_ROM 1 2R2485 EC_SPI_CLK 32 22 20KR2F-L-GP
10R2F-L-GP GPIO126/SHD_SCLK DAC_VREF 3D3V_S5_KBC temp around 85 3D3V_S0
[18,25] SPI_SI_ROM 1 2R2486 EC_SPI_MOSI 28 SCD1U16V2KX-3GP C2429 1 2
10R2F-L-GP GPIO133/SHD_IO0
[18,25] SPI_SO_ROM 1 2R2487 EC_SPI_MISO 29 85 CMP_VOUT0 CMP_VOUT0 [26] Modify on 2014/12/09

1
R2477 1 SWHDLED SATA_LED# GPIO134/SHD_IO1 GPIO124/CMP_VOUT0 CMP_VIN0 R2470
[16,64] SATA_LED#_R 2 30 20 2 1 Do Not Stuff CMP_VIN0_R [26]
GPIO135/SHD_IO2 GPIO020/CMP_VIN0

2
Do Not Stuff [18] RTCRST_ON 31 25 VCREF0
R2490 EC_SPI_CS0# GPIO136/SHD_IO3 GPIO165/CMP_VREF0 R2489
[18,25] SPI_CS_ROM_N0 1 2 27
Do Not Stuff GPIO123/SHD_CS# CMP_VOUT1
83
Layout Note: [17,40,51] SIO_SLP_S4# 67
GPIO120/CMP_VOUT1
21 GPU_PWR_LEVEL [79]
100KR2J-1-GP
GPIO101/SPI_CLK GPIO021/CMP_VIN1

1
Need very close to EC [43] AC_DIS 69 26 LCD_TST

1
GPIO103/SPI_IO0 GPIO166/CMP_VREF1/UART_CLK

1
[41] PCH_ALW_ON 71 R2448 C2409 CAP_LED# S
GPIO105/SPI_IO1 CMP_STRAP0 10KR2F-2-GP SCD01U50V2KX-1GP
[17] ME_SUS_PWR_ACK 42 118
R2431 GPIO052/SPI_IO2 GPIO024/CMP_STRAP0
[4,65] INT_TP# 1 2 Do Not Stuff PTP_INT#_EC 33 117 PANEL_BKEN_EC [55] D CAP_LED#_S [65]

2
R2491 GPIO062/SPI_IO3 GPIO023/ADC6/A20M
[31] PM_LAN_ENABLE 1 2 Do Not Stuff LAN_EN 3 116 SIO_EXT_WAKE# [20]

2
GPIO001/SPI_CS#/32KHZ_OUT GPIO022/ADC5 MODEL_ID
109 3D3V_S0 G
USB_EN# GPIO153/ADC4 I_ADP R2421 2 2N7002K-2-GP
13 110 1 AD_IA [44]
R2481 RESET_IN#/GPIO014 GPIO154/ADC3 Q2414
[17,40] ALL_SYS_PWRGD 2 1 Do Not Stuff RUNPWROK 48 111 BOARD_ID 330R2J-3-GP 84.2N702.J31
GPIO057/VCC_PWRGD GPIO155/ADC2
VSS_VBAT

ALL_SYS_PWRGD assert, 73 113 I_SYS Need very close to EC 2ND = 84.2N702.031

SC2200P50V2KX-2GP
[17,26,40] RESET_OUT# GPIO107/RESET_OUT# VR_CAP GPIO122/ADC1
R2428 114 I_BATT 3rd = 84.07002.I31
delay 10ms; RESET_OUT# assert. GPIO121/ADC0

1
Do Not Stuff XTAL2
AVSS

C2435
[18] SUS_CLK 2 DY 1 125
XTAL2
115 4th = 84.2N702.W31
VSS
VSS
VSS
VSS
VSS

XTAL1 ADC_VREF 3D3V_S5_KBC

123
XTAL1 R2471

2
MEC1404-NU-GP BOARD_ID 2 DY 1 CMP_VIN0_R [26]
124

84
51
17
64
100

112

18

071.01404.000E Do Not Stuff For T8 TEMP test

2

C2422 EC_AGND
EC_AGND

SCD1U16V2KX-3GP
R2458
VR_CAP

Do Not Stuff
3D3V_S5_KBC

2
EC LCD test
1

R2422
Power Switch Logic(PSL)

2
XTAL_KBC_2 I_SYS 2 1 P_SYS [44,46]
[55] EC_BRIGHTNESS R2456 1 2 Do Not Stuff R2493
1

C2418 10KR2F-2-GP 330R2J-3-GP

SC2200P50V2KX-2GP
1
R2419 2 Do Not Stuff SC1U10V2KX-1GP EC_AGND CMP_STRAP0

C2427
[55] LCD_TST_R 1
2

1
X2401 ECVBAT
1 2

2
[55] LCD_TST_EN R2461 1 2 Do Not Stuff LCD_TST

2
XTAL-32D768KHZ-83-GP
R2451 EVT1_1021
2

2
C2424

EVT1 2014/10/20 C2425 100KR2J-1-GP

R2445
SC12P50V2JN-3GP

SC12P50V2JN-3GP

082.30003.0131 EC_AGND
R2432
1 2
1

1
2rd = 82.30001.C01 R2423 [64] KBC_PWRBTN# 1 2 POWER_SW_IN#
I_BATT 2 1 boost_mon [44]
Do Not Stuff C2426
1KR2J-1-GP

1
330R2J-3-GP
Layout Note:

SC2200P50V2KX-2GP
SC1U10V2KX-1GP

C2441

1
，C = 10p
B B

2
Microchip: Use CL=9p Xtal EC_AGND Connect GND and AGND planes via either
0R resistor or connect directly.

2
Layout Note:
Need very close to EC
EC_AGND

2015/1/14 mofidy
D2402
LID_CL_SIO# K DY A TOUCH_PANEL_INTR# [4,55]
Do Not Stuff
Do Not Stuff
3D3V_S5 3D3V_S5_KBC
EC_GPIO47 High Active X00_0811 D2405
PTP_DIS# K PTP A
Change pin define TP_LOCK# [65]
2

3D3V_S5_KBC
R2418 R2434 Do Not Stuff
Do Not Stuff 3D3V_S5_KBC
100KR2J-1-GP
R2478
Do Not Stuff
1 DY 2 R2479
Do Not Stuff
EVT1 2014/10/21
1

USB_EN# 1 2 USB_PWR_EN# [35] DB3

R2420
2

Q2408 EC debug 7
2

CMP_VOUT1 1 2 CMP_VOUT1_R G EC debug R2476 2 1 Do Not Stuff 3D3V_AUX_KBC_R 1

R2416
Do Not Stuff

Do Not Stuff
R2414

Do Not Stuff D H_PROCHOT#_EC 1 2 DY ICSP_CLOCK R2463 2 EC debug1 Do Not Stuff ICSP_CLK_R 2

H_PROCHOT# [4,44,46]
X00_0805
1

ICSP_DATA R2464 2 1 Do Not Stuff ICSP_DATA_R 3D3V_S5_KBC

3 EC debug
1
1

C2419 R2417 S EC debug 4 3D3V_S5_PCH

1
1

DY DY Do Not Stuff C2403 HOST_DEBUG_TX R2466 2 EC debug1 Do Not Stuff E51_TXD_R 5

Do Not Stuff

Do Not Stuff

2N7002K-2-GP DY Do Not Stuff ICSP_CLR R2465 2 1 Do Not Stuff ICSP_MCLR_R 6

2

84.2N702.J31 EC debug 8
2

2ND = 84.2N702.031

2
1
3rd = 84.07002.I31 Do Not Stuff RN2603
4th = 84.2N702.W31
Do Not Stuff Do Not Stuff DS3

Do Not Stuff

3
4
SMBDA2 6 1 SML1_SMBDATA [18,26,79]

Do Not Stuff 5 2
2nd = 84.2N702.E3F DS3
3rd = 75.00601.07C 4 3
4th = 84.DMN66.03F
Q2604

SMBCLK2

A A
SML1_SMBCLK [18,26,79]

NON DS3
SMBDA2 Do Not Stuff 2 1 R2438 SML1_SMBDATA

NON DS3
SMBCLK2 Do Not Stuff 2 1 R2439 SML1_SMBCLK

Iris SKL UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
KBC SMSC 1404
Size Document Number Rev
A1
Iris2 SKL-U A00
Date: Wednesday, September 09, 2015 Sheet 24 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = SPI Flash

8M:72.25Q64.K01
4M:72.25Q32.H01
SPI Flash ROM1(8M) for PCH 3D3V_S5_PCH 3D3V_S5_PCH

Vinafix.com

1
D C2501 D
Do Not Stuff DY C2502

4
3
SCD1U16V2KX-3GP

2
R2501 RN2501
4K7R2J-2-GP DY Do Not Stuff Single SPI shared flash connection (SPI Quad I/O mode)

1
2
SPI25 3D3V_S5_PCH

[18,24] SPI_CS_ROM_N0 1 CS# VCC 8

[18,24] SPI_SO_ROM R2507 1 2 10R2F-L-GP SPI_SO_ROM_R 2 7 SPI_HOLD_ROM_R R2503 1 2 10R2F-L-GP
DO/IO1 HOLD#/IO3 SPI_HOLD_ROM [18]
R2508 1 2 10R2F-L-GP SPI_W P_ROM_R 3 6 SPI_CLK_ROM_R R2505 1 2 10R2F-L-GP SPI_CLK_ROM [18,24]
[18] SPI_W P_ROM WP#/IO2 CLK
4 5 SPI_SI_ROM_R R2506 1 2 10R2F-L-GP SPI_SI_ROM [18,24]
GND DI/IO0
1

1
W 25Q64FVSSIQ-GP
EC2502 DY 72.25Q64.K01 EC2501 DY DY EC2503
Do Not Stuff Do Not Stuff Do Not Stuff
2

2
SPI Flash ROM2(4M) for PCH 3D3V_S5_PCH 3D3V_S5_PCH
C C

1
C2505
Do Not Stuff DY C2504
2

4
3

SCD1U16V2KX-3GP

2
R2515 RN2502
4K7R2J-2-GP DY Do Not Stuff
Refer to "NCPE985x/ NPCE995x board design reference guide"
1

1
2

Source QUAD/DUAL fast read DUAL fast read SFDP

SPI252 3D3V_S5_PCH

[18] SPI_CS_ROM_N1 1 CS# VCC 8 72.25Q64.K01 O O O

[18,24] SPI_SO_ROM R2513 1 2 10R2F-L-GP SPI1_SO_ROM_R 2 7 SPI1_HOLD_ROM_R R2509 1 2 10R2F-L-GP
DO/IO1 HOLD#/RESET#/IO3 SPI_HOLD_ROM [18]
R2514 1 2 10R2F-L-GP SPI1_W P_ROM_R 3 6 SPI1_CLK_ROM_R R2511 1 2 10R2F-L-GP SPI_CLK_ROM [18,24]
[18] SPI_W P_ROM WP#/IO2 CLK
4 5 SPI1_SI_ROM_R R2512 1 2 10R2F-L-GP SPI_SI_ROM [18,24] 72.25647.00A O O O
GND DI/IO0
1

1
W 25Q32FVSSIQ-GP 072.25B64.0001 O O O
EC2504 DY 72.25Q32.H01 EC2506 DY DY EC2505
Do Not Stuff Do Not Stuff Do Not Stuff
2

2
SPI 4MB
B B

Main Func = RTC

+RTC_VCC 3D3V_AUX_S5 RTC_AUX_S5

AFTP2502 1 +RTC_VCC
D2501
1

RTC1 R2502 3
1KR2J-1-GP
1 2 1 RTC_PW R 2
PWR
1

GND 2
NP1 DY C2503
NP1 BAS40C-2-GP Do Not Stuff
NP2
2

NP2
75.00040.07D

BAT-060003HA002M213ZL-GP-U1 AFTP2501
2nd = 75.00040.C7D
1
62.70014.001 3rd = 75.00040.A7D
2nd = 62.70001.061
3rd = 20.F2316.002 Q2505
A G Iris SKL UMA A
1

D RTC_DET# [20]
R2504
10MR2J-L-GP S Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
2N7002K-2-GP Taipei Hsien 221, Taiwan, R.O.C.
2

84.2N702.J31
2ND = 84.2N702.031 Title
3rd = 84.07002.I31
4th = 84.2N702.W31 Flash/RTC
Size Document Number Rev
A3 A00
Iris2 SKL-U
Date: W ednesday, September 09, 2015 Sheet 25 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = Thermal Sensor

Fan controller1
5V_S0
R2605 FAN261
Do Not Stuff
1 DY 2 FON# 1 8

SC4D7U6D3V3KX-GP
3D3V_S0 3D3V_S0 FSM# GND

C2611
5V_S0 2 7
FAN_VCC1 VIN GND

Vinafix.com
3 6

SCD1U16V2KX-3GP
VOUT GND

1
C2605
[24] FAN1_DAC_1 4 5
VSET GND

2
1
2
APL5606AKI-TRG-GP
D RN2602 74.05606.A71 D
T8 Do Not Stuff
Layout Note: 2rd = 74.02113.0E1
3D3V_S0 Need 10 mil trace width.
Do Not Stuff 3rd = 74.03940.A71

4
3
6 1 THM_SML1_DATA
[18,24,79] SML1_SMBDATA
FAN1
R2606
C2601

Do Not Stuff 5 2 5
Do Not Stuff

2nd = 84.2N702.E3F DY [24] FAN_TACH1 1 2 FAN_TACH1_C 3

1

3rd = 75.00601.07C 4 3 2
DY T8 C2602 4th = 84.DMN66.03F Do Not Stuff
FAN_VCC1
Do Not Stuff Q2601 1
2

4
THM_SML1_CLK

C2603
D2601

Do Not Stuff
ETY-CON3-8-GP

1
Do Not Stuff
C2604 20.F1841.003
Layout Note: Do Not Stuff DY DY 2nd = 20.F1295.003
[18,24,79] SML1_SMBCLK
Signal Routing Guideline: DY

2
AFTP2803 1
Trace width = 15mil

A
Do Not Stuff
NCT7718_DXP
Q2603 THM26
Do Not Stuff
Do Not Stuff

1 8 THM_SML1_CLK
C2606 C2607 VDD SCL THM_SML1_DATA
T8 B DY Do Not Stuff
T8 Do Not Stuff
2
D+ SDA
7
NCT7718_ALERT#
3 T8 6
2

T_CRIT# D- ALERT#
4 5
E

1
T_CRIT_A# GND

Do Not Stuff

Do Not Stuff
NCT7718_DXN 1FAN_TACH1_C

C2608

C2609
AFTP2802
FAN_TACH1 AFTP2801 1FAN_VCC1
DY DY
2.System Sensor, Put on palm rest Do Not Stuff

2
Do Not Stuff FAN_VCC1
1

EC2602 EC2601

1
R2601 DY
DY Do Not Stuff Q2602 DY

Do Not Stuff

Do Not Stuff
Layout Note:

2
[17,24,40] RESET_OUT# G
2

C2812 close U2801

D
C PURE_HW_SHUTDOWN# [40] C
THERM_SYS_SHDN# S

Do Not Stuff
CMP_VOUT0

C2610
Layout Note: 2N7002K-2-GP
1
R2612
DY 2
Do Not Stuff
84.2N702.J31
DY
Both DXN and DXP routing 10 mil trace width and 10 mil spacing.

2
2ND = 84.2N702.031
3rd = 84.07002.I31 need to check with NTD team Barkley 1404 test result
4th = 84.2N702.W31
3D3V_S0

R2603 1 T8 2 Do Not Stuff NCT7718_ALERT#

R2604 2 Do Not Stuff T_CRIT# 3D3V_S5_KBC

1 T8
R2607 1 2 10KR2J-3-GP

R2602
THERM_SYS_SHDN# 1 2 CMP_VOUT0 [24]
Do Not Stuff
Close to KBC
Close to Thermal sensor VD_IN1 for system thermal sensor
3D3V_AUX_S5 3D3V_S5_KBC
1

1
Do Not Stuff

R2608
R2609

DY 25K5R2F-GP
2

CMP_VIN0_R [24]
2015/05/6 DVT2 modify
1

B C2612 B
1

R2610 SCD1U16V2KX-3GP
NTC-100K-8-GP C2613
2

SC100P50V2JN-3GP
2

R2611
VD_IN1_C 1 2

Do Not Stuff

GPU thermal sensor

3D3V_VGA_S0 3D3V_VGA_S0

R2613 1GPU T8 2 Do Not Stuff GPU_ALERT#

C2615
Do Not Stuff

R2614 Do Not Stuff GPU_T_CRIT#

GPU_T8 1GPU T8 2
1

DY C2616
Do Not Stuff
2

[79] GPU_DPLUS THM262

GPU T8
1 8 SMB_CLK_VGA_R [79]
1

C2614 VDD SCL

2 7 SMB_DATA_VGA_R [79]
D+ SDA GPU_ALERT#
GPU T8 Do Not Stuff GPU_T_CRIT#
3
D- ALERT#
6
4 5
2

T_CRIT# GND
Do Not Stuff

Do Not Stuff
C2617

C2618

Do Not Stuff
DY DY
2

A [79] GPU_DMINUS 3D3V_VGA_S0 A

Do Not Stuff
Q2605
G

DY D PURE_HW_SHUTDOWN#
R2615 Iris SKL UMA
1GPU T8 2 GPU_T_CRIT_R# S

Do Not Stuff
Do Not Stuff Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Do Not Stuff Taipei Hsien 221, Taiwan, R.O.C.
Layout Note: 2ND = 84.2N702.031
Title
Both DXN and DXP routing 10 mil trace width and 10 mil spacing. 3rd = 84.07002.I31
4th = 84.2N702.W31 THERMAL NCT7718W/Fan
Size Document Number Rev
A2
Iris2 SKL-U A00
Date: Wednesday, September 09, 2015 Sheet 26 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = Audio

1
R2731
2
Vinafix.com
+3V_AVDD
D Do Not Stuff D

ALC3234 and ALC3246 [29] LINE1_VREFO_R MIC2_VREFO [29]

3D3V_S0 25mA CPVDD
[29] LINE1_VREFO_L AUD_AGND
R2701
1 2 Reserved for ALC3234
moat
Do Not Stuff

SC2D2U10V3KX-1GP

SC4D7U6D3V3KX-GP
1D8V_S0 [29] AUD_HP1_JACK_L
R2724 EC2707 1 2 DY Do Not Stuff

1
[29] AUD_HP1_JACK_R EC2706 Do Not Stuff
1 3246 2
Do Not Stuff R2711 EC2705
1 2 DY Do Not Stuff

1 C2705
1 2 DY
EC2704 Do Not Stuff
C2701 C2704
100KR2J-1-GP moat EC2703
1 2 DY Do Not Stuff

C2702
1 2 DY

1
1 2

SCD1U16V2KX-3GP

2
1
C2724
SC4D7U6D3V3KX-GP SC1U10V2KX-1GP +5V_AVDD 5V_S0

2
Close pin36 AUD_AGND

2
CPVDD R2703

1
C2703

AUD_VREF
1 2

LDO1_CAP
+5V_AVDD
1.5A

CPVEE
SC1U10V2KX-1GP
R2706

CBN
5V_S0 +5V_PVDD C2710 Do Not Stuff
AUD_AGND

1
C2711 1 2
R2702
Do Not Stuff
Layout Note:

SCD1U16V2KX-3GP

SC4D7U6D3V3KX-GP
1 2

2
Do Not Stuff Place close to Pin 26

36

35

34

33

32

31

30

29

28

27

26

25
C2706 C2707 C2708 C2709 HDA27
1

1
R2704
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

CPVEE

HPOUT-L/PORT-I-L

LINE1-VREFO-L

MIC2-VREFO

LDO1-CAP

AVDD1

AVSS1
CPVDD

CBN

HPOUT-R/PORT-I-R

LINE1-VREFO-R

VREF
SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP
1 2
Do Not Stuff
2

CBP AUD_AGND 5V_S5 AUD_AGND Layout Note:

37
CBP LINE2_L/PORT-E-L
24 moat Tied at point only under
AUD_AGND 38 23 Codec or near the Codec
AVSS2 LINE2_R/PORT-E-R R2725 1 3246 2 Do Not Stuff
C2712 1 2 SC10U6D3V3MX-GP LDO2_CAP 39 22
AUD_AGND LDO2-CAP LINE1_L/PORT-C-L LINE1_L [29] 3D3V_S5
40 21
Layout Note: Layout Note: +3V_1D5V_AVDD AVDD2 LINE1_R/PORT-C-R LINE1_R [29]
Close pin41 Close pin46 41 20 V3D3_STB R2712 1 2 Do Not Stuff
+5V_PVDD PVDD1 NC#20
C
moat AUD_SPK_L+ 42 19 MIC_CAP C2713 1 2 SC10U6D3V3MX-GP Width>40mil, to improve Headpohone Crosstalk noise C
[29] AUD_SPK_L+ SPK-OUT-L+ MIC-CAP AUD_AGND
1D8V_S0 Layout Note: AUD_SPK_L-
Change it to sharp will be better.
+3V_1D5V_AVDD Speaker trace width >40mil @ 2W4ohm speaker power [29] AUD_SPK_L-
43
SPK-OUT-L-
71.03234.003
MIC2_R/PORT-F-R/SLEEVE
18
SLEEVE [29] Layout Note: Add 2 vias (>0.5A) when trace layer change.
AUD_SPK_R- 44 17
[29] AUD_SPK_R- SPK-OUT-R- MIC2_L/PORT-F-L/RING RING2 [29] R2723
3D3V_S0 1D5V_S0 R2713 1 3246 2
[29] AUD_SPK_R+
AUD_SPK_R+ 45
SPK-OUT-R+ 3246:071.03246.0003 MONO-OUT
16 AUD_PC_BEEP_3246 1 3246 2 AUD_PC_BEEP_R moat
Do Not Stuff Do Not Stuff
R2705 1 2 Do Not Stuff +5V_PVDD 46 15 JDREF R2707 1 DY 2 Do Not Stuff AUD_AGND
R2708 PVDD2 SPDIFO/FRONT_JD/JD3/GPIO3

GPIO0/DMIC-DATA
moat
1

GPIO1/DMIC-CLK
R2710 1DY 2 Do Not Stuff 1 2 EAPD# 47 14
C2715 [24] EC_MUTE# PDB MIC2/LINE2_JD/JD2

SDATA-OUT
SC4D7U6D3V3KX-GP Do Not Stuff COMBO-GPI 48 13 AUD_SENSE_A 1 2 AUD_SENSE
+3V_AVDD
2

SPDIF-OUT/GPIO2 HP/LINE1_JD/JD1 AUD_SENSE [29]

LDO3-CAP
AVDD2:

SDATA-IN
R2709

DVDD-IO

PCBEEP
RESET#
Close pin40 +3V_AVDD 49 200KR2F-L-GP R2722
+1.8VD@3246 GND Layout Note:

DVDD

SYNC
DVSS

BCLK
+1.5VD@3234 AUD_AGND R2728
AUD_SENSE_A 2 1
Place close to Pin 13
2 DY 1
ALC3234-CG-GP 100KR2J-1-GP

10

11

12
Do Not Stuff
+3V_AVDD +3V_AVDD +3.3VD@3234
AUD_PC_BEEP R2715 1 2AUD_PC_BEEP_R follow Pin1 Power setting@3246

LDO3_CAP

I2C_SDA@3246

I2C_SCL@3246
TP2702 1
Azalia I/F EMI Do Not Stuff
DMIC_DATA_R

C2718

C2719
C2717

1
EC2701
Do Not Stuff

C2716
SC4D7U6D3V3KX-GP

SCD1U16V2KX-3GP
1

1
HDA_CODEC_SDOUT

2
HDA_CODEC_BITCLK
DY

HDA_CODEC_RST#_R
2

2
EC2708 EC2709

SCD1U16V2KX-3GP
SC4D7U6D3V3KX-GP
1

DY DY
Do Not Stuff

Do Not Stuff
2

Do Not Stuff 1 R2714 2 DMIC_DATA_R

[55] DMIC_DATA
Do Not Stuff 1 R2716 2 DMIC_CLK_R

2
[55] DMIC_CLK
Do Not Stuff 1 R2719 CODEC_SDOUT_R

R2721
2
2

[19] HDA_CODEC_SDOUT

Do Not Stuff
B B
C2723 DY Do Not Stuff 1 R2720 2 CODEC_BITCLK_R
[19] HDA_CODEC_BITCLK
Do Not Stuff
1

1
Do Not Stuff 1 R2718 2 HDA_CODEC_SDIN0
[19] HDA_SDIN0
Close pin3 HDA_CODEC_SYNC
[19] HDA_CODEC_SYNC

HDA_CODEC_RST#
[19] HDA_CODEC_RST#
D2701
RN2701 HDA_SPKR_R 2
[19] SPKR 2 3 C2720
1 4 3 AUD_PC_BEEP_C 1 2AUD_PC_BEEP_R
[24] BEEP
KBC_BEEP_R 1 SCD1U16V2KX-3GP
SRN1KJ-7-GP

1
BAT54C-7-F-3-GP R2717
2K2R2J-2-GP

2015/1/14 modify for Beep waveform 75.00054.E7D

2
1D8V_S5 1D8V_S0
Q2702 2nd = 83.R2003.W81
Do Not Stuff
3rd = 75.00054.A7D
150mA 3246
S 4th = 83.R2003.V81
D

D
1

3246C2722 G
1

1
3246 R2726 C2721
G

Do Not Stuff
Do Not Stuff 3246C2714 DY
2

Do Not Stuff

Do Not Stuff
2

2
2

1 R2727 2 1D8V_EN_R#
3246
Do Not Stuff
1D8V_EN#

Q2701 Do Not Stuff

[17,24,40,51,52,54] SIO_SLP_S3# G 3246 2nd = 84.00102.031

A A
D 3rd = 84.03413.B31
S

Do Not Stuff
Iris SKL UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Audio Codec ALC3246

Size Document Number Rev
A2
Iris2 SKL-U A00
Date: Wednesday, September 09, 2015 Sheet 27 of 105
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

B B

A A

Iris SKL UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)
Size Document Number Rev
A1
Iris2 SKL-U A00
Date: Tuesday, May 26, 2015 Sheet 28 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = Audio

Layout Note: Speaker

Speaker trace width >40mil @ 2W4ohm speaker power
Vinafix.com SPK1
5
Do Not Stuff 2 R2904 1 AUD_SPK_R+_C 1
[27] AUD_SPK_R+
D D
Do Not Stuff 2 R2903 1 AUD_SPK_R-_C 2
[27] AUD_SPK_R- Do Not Stuff
[27] AUD_SPK_L+ 2 R2902 1 AUD_SPK_L+_C 3
Do Not Stuff 2 R2901 1 AUD_SPK_L-_C 4 CONN Pin Net name
[27] AUD_SPK_L-
6
Pin1 SPK_R+
ACES-CON4-29-GP
Pin2 SPK_R-
20.F1639.004
Pin3 SPK_L+
2nd = 20.F1804.004

1
SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP
Pin4 SPK_L-

EC2901

EC2902

EC2903

EC2904
2

2
AUD_SPK_L-_C 1 AFTP2901
AUD_SPK_L+_C 1 AFTP2902
AUD_SPK_R-_C 1 AFTP2903
AUD_SPK_R+_C 1 AFTP2904

2015/09/08 modify (EMI suggest)

C C

RN2901
Universal Jack (Moved to I/O Board)
[27] MIC2_VREFO 1 4
2 3

SRN2K2J-1-GP Do Not Stuff

[27] RING2 2 R2906 1 RING2_R
RING2_R [66]
R2908 1 2 10R2F-L-GP AUD_HP1_JACK_L1 Do Not Stuff 2 R2907 1 AUD_PORTA_L_R_B AUD_PORTA_L_R_B [66]
[27] AUD_HP1_JACK_L C2907 1
[27] LINE1_L 2 LINE1-L_C R2922 1 2 1KR2J-1-GP
SC4D7U6D3V3KX-GP R2912 1 2 4K7R2J-2-GP JACK_PLUG
[27] LINE1_VREFO_L JACK_PLUG [66]
R2910 1 2 10R2F-L-GP AUD_HP1_JACK_R1 Do Not Stuff 2 R2909 1 AUD_PORTA_R_R_B AUD_PORTA_R_R_B [66]
[27] AUD_HP1_JACK_R C2908 1
[27] LINE1_R 2 LINE1-L_R R2921 1 2 1KR2J-1-GP Do Not Stuff 2 R2911 1 SLEEVE_R
SLEEVE_R [66]
SC4D7U6D3V3KX-GP R2913 1 2 4K7R2J-2-GP
[27] LINE1_VREFO_R

Do Not Stuff
EC2908

Do Not Stuff
EC2907

Do Not Stuff

EC2906

Do Not Stuff

EC2905
1

R29191
Do Not Stuff
[27] SLEEVE

1
Do Not Stuff
R2920

DY
2 DY

2
DY DY DY DY
2

2
Delay circuit
B B
(JACK_PLUG_DET: on IO Board)

AUD_AGND AUD_AGND

JACK_PLUG 10 mils R2923 1 2 Do Not Stuff 10 mils

AUD_SENSE [27]

1
DY C2902
Do Not Stuff

2
AUD_AGND

A Iris SKL UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Audio IO
Size Document Number Rev
A3
Iris2 SKL-U A00
Date: W ednesday, September 09, 2015 Sheet 29 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = Audio

Vinafix.com
D D

C C

(Blanking)

B B

Iris SKL UMA

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
(Reserved)
Size Document Number Rev
A4
Iris2 SKL-U A00
Date: Tuesday, May 26, 2015 Sheet 30 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = LAN

Layout:
For RTL8111G(S) Ca: colse to Pin8
* Place Ca~Cd close to each VDD10 pin-- 8, 30, 3, 22 Cb close to Pin30
For RTL8106E
* Place Ca,Cb close to each VDD10 pin-- 8, 30
R3101 Vinafix.com
Cc: close to Pin3
Cd: close to Pin22 LAN CHIP (10/100/1000M & 10/100M co-lay)
Ra
REGOUT 1 2 VDD10
C3101,R3101:
D 8111G D

8111G/LAN_SW
Only for

C3108
Do Not Stuff

C3115 Do Not Stuff

C3112 SCD1U16V2KX-3GP

C3119 SCD1U16V2KX-3GP

C3123 Do Not Stuff

C3122 Do Not Stuff

8111G/LAN_SW
LAN_SW

LAN_SW
RTL8111 LDO mode. R3102 C3102
L3101 La 2K49R2F-GP PCIE_RX_CON_P6 1 2 SCD1U16V2KX-3GP PCIE_RX_CPU_P6 [16]

1
C3118 1 2 Ca Cb Cc Cd RTL8111GUS-CG RTL8111G-CGT RTL8106EUS-CG RTL8106E-CG 1 2 PCIE_RX_CON_N6 1 2 SCD1U16V2KX-3GP PCIE_RX_CPU_N6 [16]
8111G Do Not Stuff C3107
LAN_SW PCIE_TX_CON_P6 [16]
2

2
Ch Ci Cj 71.08111.W03 71.08111.U03 71.08106.003 071.08106.0003
PCIE_TX_CON_N6 [16]
Do Not Stuff
Do Not Stuff
Do Not Stuff
SWR mode LDO mode SWR mode LDO mode PEG_CLK2_CPU [18]
PEG_CLK2_CPU# [18]

3D3V_LAN_S5

LANXOUT
10/100/1000M 10/100/1000M 10/100M 10/100M

LANXIN
VDD10
LED0 1 TP3103 Do Not Stuff

RSET
LED1 1 TP3102 Do Not Stuff
Layout: LED2 1 TP3101 Do Not Stuff
For RTL8111G(S)
* Place Ce and Cf close to each VDD33 pin-- 11, 32

32
31
30
29
28
27
26
25
For RTL8106E LOM31
* Place Cg and Cf close to each VDD33 pin-- 23, 32

AVDD33

AVDD10
CKXTAL2
CKXTAL1
LED0
(GPO) LED1/GPO
(LED1) LED2
RSET
33
GND
3D3V_LAN_S5 VDDREG

2 C3104
40 mils R3104 1 2 Do Not Stuff 1 (NC) REGOUT 24 REGOUT
1
SC1U10V2KX-1GP
[32] LAN_MDI0P MDIP0 VDDREG C3114 1
2 (DVDD33) VDDREG 23 2 SCD1U16V2KX-3GP
1

C3113 C3117 [32] LAN_MDI0N VDD10 MDIN0 VDD10 3D3V_S0

3 22
AVDD10 (NC) (NC) DVDD10
1
Do Not Stuff

SCD1U16V2KX-3GP
8111G/LAN_SW

C3103 PCIE_WAKE#
LAN_SW [32] LAN_MDI1P
4
MDIP1 071.08106.0003 LANWAKE# 21 PCIE_WAKE# [24]
SCD1U16V2KX-3GP

8106E Cf: close to Pin32 LAN_SW 5 20 ISOLATE# 2 1

2

1
[32] LAN_MDI1N MDIN1 ISOLATE# PLT_RST#_LAN
Ce Cf Ce: close to Pin11 C3124 Ck Cl 6
MDIP2 (NC) (071.08106.0003) 19 R3109
2

[32] LAN_MDI2P PERST#

1
Do Not Stuff
Cg C3110 7 18 PCIE_RX_CON_N6 1KR2J-1-GP
Cg: close to Pin23 Do Not Stuff [32] LAN_MDI2N VDD10 MDIN2 (NC) HSON PCIE_RX_CON_P6 R3113
8 17

2
AVDD10 HSOP 15KR2J-1-GP

AVDD33 (NC)
MDIP3 (NC)
MDIN3 (NC)

REFCLK_N
REFCLK_P
CLKREQ#
X5R

2
HSIN
HSIP
C
RTL8106E-CGT-GP
RTL8107E-CG PN:071.08106.0003 C
Manual: :071.08106.0003

9
10
11
12
13
14
15
16
RTL8111G-CGT (71.08111.U03/LDO Mode): 10/100/1000M < 252 mW.
3D3V_LAN_S5 RTL8106E-CG (071.8107E.0A03): 10/100M <70mW.
3D3V_LAN_S5
[32] LAN_MDI3P 3D3V_S5
1
2

[32] LAN_MDI3N
R3103
3D3V_LAN_S5
RN3102 LAN_CLKREQ_LAN# PCIE_WAKE#
DY 1 2

1
Do Not Stuff C3109 C3111 PCIE_TX_CON_P6
DY DY PCIE_TX_CON_N6
PEG_CLK2_CPU 10KR2J-3-GP
BQ402_1 4
3

2
PEG_CLK2_CPU#

Do Not Stuff

Do Not Stuff
Do Not Stuff 3D3V_LAN_S5
Layout:
Q3104 Do Not Stuff 3D3V_LAN_S5
PLT_RST#_LAN
C3004: close to Pin32
[17,24,40,55,61,68,76] PLT_RST#
E DY C
C3005: close to Pin11

1
C3116
R3110 R3112 DY
1 2 LANXOUT 1 2 Do Not Stuff

1
Do Not Stuff R3108

2
SC15P50V2JN-L-GP
3D3V_LAN_S5 rise time must be controlled DY Do Not Stuff

CLK_LAN_REQ#_EN
between 0.5 mS and 100 mS.

2
4

3
3D3V_S5 3D3V_LAN_S5 X3101
Q3101 XTAL-25MHZ-181-GP
DMP2130L-7-GP
85mA
S

B
1

2
D Do Not Stuff
D

82.30020.G71 Q3103 Do Not Stuff

1

[18] CLKREQ_PCIE#2 C E LAN_CLKREQ_LAN#

1

B C3121 R3106 B
DY
G

1
10KR2J-3-GP C3105 C3120 R3105
SCD1U16V2KX-3GP

C3125
2

Do Not Stuff
SC1U10V2KX-1GP
R3111 DY 1 2
2

LANXIN 1 2 Do Not Stuff

2

1 2 PM_LAN_ENABLE_C
SC15P50V2JN-L-GP
LAN_ENABLE_R_C

20KR2J-L2-GP 84.02130.031
2nd = 84.00102.031

Q3102
3rd = 84.03413.B31
G
[24] PM_LAN_ENABLE
1

D
R3107
100KR2J-1-GP S

2N7002K-2-GP
2

BOM Option 1.0V

Source Ra Ch Cc Cd Ce La Ci Cj Ck Cl Cg

RTL8111G-CGT LDO
8111G O O O O O X X X X X X
(71.08111.U03)

A RTL8111GUS-CG A
SWR X X O O O O O O O O X
(71.08111.W03)/ LAN_SW
RTL8106EUS-CG
(71.08106.003)
Iris SKL UMA

RTL8106E-CG Wistron Corporation

8106E LDO X X X X X X X X X X O 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
(071.08106.0003) Taipei Hsien 221, Taiwan, R.O.C.

Title

LAN RTL8106
Size Document Number Rev
A2
Iris2 SKL-U A00
Date: Wednesday, September 09, 2015 Sheet 31 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = LAN

LAN TransFormer (10/100/1000M & 10/100M co-lay)

Vinafix.com
D U3101 D

LAN_MDI0P 1 10 LAN_MDI0P
MCT0 LAN_MDI0N IN1 NC#10 LAN_MDI0N
2 IN2 NC#9 9
MCT1 3 8
MCT2 LAN_MDI1P GND GND LAN_MDI1P
4 IN3 NC#7 7
XF3102 Do Not Stuff MCT3 LAN_MDI1N 5 DY 6 LAN_MDI1N
IN4 NC#6

[31] LAN_MDI3N 12 1CT:1CT

1 MDO3-
1 2
EC3108 DY Do Not Stuff 3 MCT0 Do Not Stuff
Do Not Stuff

4
3
2
1
[31] LAN_MDI3P 11 2 MDO3+
1 2 RN3101
EC3107 DY Do Not Stuff 10 SRN75J-1-GP
U3102
[31] LAN_MDI2N 8 10/100/1000
1CT:1CT
5 MDO2-
1 2 LAN_MDI2P 1 10 LAN_MDI2P

5
6
7
8
EC3106 IN1 NC#10
DY Do Not Stuff 4 MCT1 LAN_MDI2N 2 IN2 NC#9 9 LAN_MDI2N
3 GND GND 8

MCT
[31] LAN_MDI2P 7 6 MDO2+ LAN_MDI3P 4 7 LAN_MDI3P
LAN_MDI3N IN3 NC#7 LAN_MDI3N
1
EC3105
2 5 IN4 DY NC#6 6
DY Do Not Stuff 9

1
Do Not Stuff C3101 Do Not Stuff
SC100P3KV8JN-2-GP
XF3101 Do Not Stuff

2
9 78.1013N.1AL
C C

[31] LAN_MDI1N 7 6 MDO1-

1 2
EC3104 DY Do Not Stuff 4 MCT2

[31] LAN_MDI1P 8 5 MDO1+

1CT:1CT
1 2
EC3103 DY Do Not Stuff 10

MDO0-
LOM_TCT

[31] LAN_MDI0N 11 2
1 2
EC3102 DY Do Not Stuff 3 MCT3
20140806 david
[31] LAN_MDI0P 12 1 MDO0+
1CT:1CT
1 2
EC3101 DY Do Not Stuff RJ45
XFORM-12P-48-GP
9 CHASSIS#9
68.68167.30D MDO0+ 1 MDO0+
1

C3106 MDO0- 2
SCD01U50V2KX-1GP MDO1+ MDO0-
3 MDO1+
Layout note: Layout note: MDO2+ 4
2

MDO2- MDO2+
5
30 mil spacing between MDI differential pairs. 30 mil spacing between MDI differential pairs. MDO1- 6
MDO2-
MDO3+ MDO1-
7 MDO3+
Follow Reference Schematic 0.01uF~0.4uF MDO3- 8 MDO3-
10 CHASSIS#10
RJ45
B RJ45-8P-184-GP B

022.10001.0C41

Layout:
Place near RJ45
Do Not Stuff AFTP3107 1 MDO0+
Do Not Stuff AFTP3102 1 MDO0-
Do Not Stuff AFTP3101 1 MDO1+
Do Not Stuff AFTP3103 1 MDO2+
Do Not Stuff AFTP3104 1 MDO2-
Do Not Stuff AFTP3106 1 MDO1-
Do Not Stuff AFTP3105 1 MDO3+
Do Not Stuff AFTP3108 1 MDO3-

A Iris SKL UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

XFOM&RJ45
Size Document Number Rev
A3
Iris2 SKL-U A00
Date: W ednesday, September 09, 2015 Sheet 32 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = Card Reader Card Reader Power SW (CPU Only)

Card Reader IC (USB 2.0)
3D3V_S0 3D3V_CARD_S0

C3306
C3305
Vinafix.com SDREFG 1 2

1
USB_SD USB_SD

SC4D7U6D3V3KX-GP

SCD1U16V2KX-3GP
C3302 SC1U10V2KX-1GP

C3304
V18
1 2 USB_SD

2
D D
SC1U10V2KX-1GP
USB_SD The maximum range of the PMOS output current in RTS5170 (Card Reader IC) is 400mA

Remove 2014/12/23

24

23
4

7
U3301

V18

CARD_3V3

SDREG

XD_D7
XD_CD#
3V3_IN
SD_WP 8 15 SD_CLK
SP1 SP8
9 16
SD_D1 SP2 SP9 SD_CMD
10 18
SD_D0 SP3 SP10
11 19
SP4 SP11 SD_D3
SD_CD#
12
SP5 USB_SD SP12
20
SD_D2
13 21
SP6 SP13
14 22
SP7 SP14

GPIO0
RREF

GND
DM
DP
RTS5170-GR-GP

2
3

17

25
71.05170.003

R3304

RREF
1 2 USB_CARD_PN5
Do Not Stuff

1
USB_CARD_PP5 CR_GPIO0 1 TP3301 3D3V_CARD_S0
USB_CARD_PP5
[16] USB_CPU_PP5
USB_SD R3302
A00 modify 2015/06/05 USB_CARD_PN5 6K2R2F-GP
[16] USB_CPU_PN5

1
C3303 USB_SD

SCD1U16V2KX-3GP
DY C3301
Do Not Stuff

2
R3303
1 2
Do Not Stuff

C C

Co-lay from CPU and Card Reader IC

3D3V_CARD_S0

3D3V_CARD_S0

CARD1
400mA
4 10 SD_CD#
C3307 VDD 10 SD_WP
Remove 2014/12/23 11
11

1
SCD1U16V2KX-3GP
12 1 AFTP3301

SC4D7U6D3V3KX-GP
SD_D0 12

C3308
DY C3309 7 13
Do Not Stuff SD_D1 DAT0 13
8 14

2
SD_D2 DAT1 14
9 15
SD_D3 DAT2 15
1
CD/DAT3
NP1
NP1
NP2
SD_CMD NP2
2
CMD
3
SD_CLK VSS1
5 6
CLK VSS2

CARDBUS11P-SKT-9-GP

B
020.I0002.0001 B

2rd = 020.I0004.0001
For EMI Reserved (Close to CARD1)
SD_CLK

SD_WP

SD_CMD 1 AFTP3302
SD_D0 SD_CLK 1 AFTP3303
SD_CD# 1 AFTP3304
SD_WP 1 AFTP3305
SD_CD# SD_D0 1 AFTP3306
SD_D1 1 AFTP3307
SD_D2 1 AFTP3308
SD_CMD SD_D3 1 AFTP3309
3D3V_CARD_S0 1 AFTP3310

SD_D3

SD_D2

SD_D1

EC3305

EC3307

EC3304

EC3308

EC3306

EC3302

EC3303
1

1
Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff
DY DY DY DY DY DY DY DY EC3301
Do Not Stuff

2
A A

Iris SKL UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size
Card Reader-RTS5170
Document Number Rev
A2
Iris2 SKL-U A00
Date: Wednesday, September 09, 2015 Sheet 33 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = USB3.0 Port1

Vinafix.com
D D

C C

(Blanking)

B B

Iris SKL UMA

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)
Size Document Number Rev
A4
Iris2 SKL-U A00
Date: Tuesday, May 26, 2015 Sheet 34 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = USB3.0 Port1

Main Func = USB2.0 Port2
Main Func = USB2.0 Port3
Layout Note: Close USB1
Vinafix.com USB30_VCCC

USB3.0 Port1 2A
D D

Do Not Stuff
USB30_VCCC

R3501

C3507

C3508
1

1
5V_S5 TC3501
U3504 DY C3512 C3513 DY Do Not Stuff
Do Not Stuff

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
2

2
5 1

SC1U10V2KX-1GP
SCD1U16V2KX-3GP
2
IN OUT
GND 2
1

[24] USB_PW R_EN# 4 EN# OC# 3 USB_OC0# [16]

C3510
SC1U10V2KX-1GP Active Low
2

G524B2T11U-GP
074.00524.0C9F

USB20_VCCA
5V_S5
U3503
Layout Note: Close CON1
5 1 USB20_VCCA
IN OUT
GND 2 USB2.0 Port2 (IO Board)
1

4 3
C3505
[24] USB_PW R_EN# EN#
Active Low
OC# USB_OC0# [16] 2A
SC1U10V2KX-1GP
2

1
G524B2T11U-GP

R3503

SC1U10V2KX-1GP C3506
1

1
C
074.00524.0C9F C3503 C3514 C3509 C
DY DY DY

SCD1U16V2KX-3GP

2
Do Not Stuff

Do Not Stuff
2
Do Not Stuff
B B

A Iris SKL UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

USB switch
Size Document Number Rev
Iris2 SKL-U A00
Date: W ednesday, September 09, 2015 Sheet 35 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = USB3.0 Port1

USB2.0 Port2 and USB2.0 Port3 are on IOBD
USB3.0 Port1
USB30_VCCC 1 AFTP3401
USB_CON_PN0 1 AFTP3402
USB_CON_PP0 1 AFTP3403
U3402
USB1
USB30_RX_CON_N1 1 10 USB30_RX_CON_N1

TR3404
Vinafix.com USB30_RX_CON_P1 2
3
LINE_1 NC#10
LINE_2 NC#9
GND DY GND
9
8
USB30_RX_CON_P1 USB30_VCCC 1 VBUS D-
D+
2
3
USB_CON_PN0
USB_CON_PP0
[16] USB_CPU_PN0 1 2 USB_CON_PN0 USB30_TX_CON_N1 4 7 USB30_TX_CON_N1
USB30_TX_CON_P1 LINE_3 NC#7 USB30_TX_CON_P1 USB30_RX_CON_N1
D 5 LINE_4 NC#6 6 5 STDA_SSRX- D
[16] USB_CPU_PP0 4 3 USB_CON_PP0 USB30_RX_CON_P1 6 7
STDA_SSRX+ GND_DRAIN
FILTER-4P-137-GP Do Not Stuff USB30_TX_CON_N1 8
USB30_TX_CON_P1 STDA_SSTX-
Do Not Stuff 9 STDA_SSTX+ GND 10
68.01012.20B GND 11
2nd = 75.00107.073 12 CHASSIS#12 GND 4
A00 modify 2015/06/05 U3403 13 CHASSIS#13
1 AFTP6217
USB_CON_PN0 1 6 USB30_VCCC
I/O1 I/O4 SKT-USB13-111-GP
2 GND DY VDD 5
22.10339.S21

1
USB_CON_PP0 3 4
I/O2 I/O3 C3405
DY
Do Not Stuff

2
Do Not Stuff
Do Not Stuff

C3404

1 2 USB30_TX_CPU_P1_C 2 R3408 1 USB30_TX_CON_P1 [16] USB30_RX_CPU_P1 2 R3410 1 USB30_RX_CON_P1

[16] USB30_TX_CPU_P1
SCD1U16V2KX-3GP Do Not Stuff Do Not Stuff
USB30_TX_CON_P1

C3402

C3401
USB30_TX_CON_N1

1
C C
DY DY
A00 modify 2015/06/05 A00 modify 2015/06/05

2
Do Not Stuff

Do Not Stuff
C3403
R3409
1 2 USB30_TX_CPU_N1_C 2 1 USB30_TX_CON_N1 [16] USB30_RX_CPU_N1 2 R3411 1 USB30_RX_CON_N1
[16] USB30_TX_CPU_N1
SCD1U16V2KX-3GP Do Not Stuff Do Not Stuff

B B

A Iris SKL UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

USB30
Size Document Number Rev
A3
Iris2 SKL-U A00
Date: W ednesday, September 09, 2015 Sheet 36 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = USB2.0

Vinafix.com
D
USB2 (USB2.0) CMC D

TR3701
[16] USB_CPU_PN1 4 3 USB_CON_PN1 USB_CON_PN1 [66]

[16] USB_CPU_PP1 1 2 USB_CON_PP1 USB_CON_PP1 [66]

68.01012.20B
FILTER-4P-137-GP

A00 modify 2015/06/05

Layout Note:
Close to CON1

USB3 (USB2.0) CMC

C TR3702 C

[16] USB_CPU_PN2 1 2 USB_CON_PN2 USB_CON_PN2 [66]

[16] USB_CPU_PP2 4 3 USB_CON_PP2 USB_CON_PP2 [66]

68.01012.20B
FILTER-4P-137-GP

Layout Note:
A00 modify 2015/06/05 Close to CON1

B B

USB ESD Diode

EU3701 USB20_VCCA

USB_CON_PP1 1 6 USB_CON_PN1
I/O1 I/O4
2 GND VDD 5

USB_CON_PP2
DY USB_CON_PN2
3 I/O2 I/O3 4
1

C3701

Do Not Stuff Do Not Stuff

DY
2

Do Not Stuff
Layout Note:
Close to CON1

A Iris SKL UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

USB20
Size Document Number Rev
A3
Iris2 SKL-U A00
Date: W ednesday, September 09, 2015 Sheet 37 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = USB3.0 Port1

Vinafix.com
D D

C C

(Blanking)

B B

Iris SKL UMA

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)
Size Document Number Rev
A4
Iris2 SKL-U A00
Date: Tuesday, May 26, 2015 Sheet 38 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = USB3.0 Port1

Vinafix.com
D D

C C

(Blanking)

B B

Iris SKL UMA

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)
Size Document Number Rev
A4
Iris2 SKL-U A00
Date: Tuesday, May 26, 2015 Sheet 39 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = Power Plane & Sequence Power Good R4035

3D3V_S0 3D3V_S5

1 2 2015/05/13 DVT2 modify

1
R4034 VR_EN_off 3D3V_S0

Do Not Stuff
R4038
Do Not Stuff
3D3V_AUX_S5 R4011 D5402 DY DY

Do Not Stuff

1
[51] 1D35V_VTT_PWRGD 1 2 1D35V_VTT_PWRGD_R 2

2
Do Not Stuff Q4005 R4005
1 DY
R4004
2 PS_S3CNTRL
ROSA Run Power SIO_SLP_S3# 1DY
R4027
2 SIO_SLP_S3#_R 1
DY 3 DY Do Not Stuff
Do Not Stuff
1KR2J-1-GP

2
Do Not Stuff Do Not Stuff 2nd = 84.2N702.E3F

Vinafix.com
D G S Do Not Stuff ALL_SYS_PWRGD [17,24]
20150420 modify by Alden D4002

4
ALL_SYS_PWRGD_EN 1 R4028 2 1 R4002 2
5V_S5 VR_EN [46]
Q4001 1
5V_S0 3D3V_S5 3D3V_S5_KBC
Do Not Stuff DY DY
D
Do Not Stuff
1 U4001 5V_S0 RSMRST_PWRGD# 3
Do Not Stuff Do Not Stuff
Do Not Stuff Do Not Stuff
D

3
2nd = 84.2N702.E3F S G D 2
3rd = 75.00601.07C 15

1
GND R4032
4th = 84.DMN66.03F
1
VIN1#1 VOUT1#14
14 5V_S0 Comsumption R4031
Do Not Stuff
2 13 100KR2J-1-GP
R4010 1 2 3V5V_S0_ON 3
VIN1#2 VOUT1#13
12 3V5V_CT1 Peak current 5A DY
[17,24,27,51,52,54] SIO_SLP_S3#

1
Do Not Stuff ON1 CT1 3D3V_S0
4 11 [#543016] Optional, Added for addition system robustness
VBIAS GND
3D3V_S0

C4005
SC10U10V5KX-2GP
[17,24,26] RESET_OUT# 5V_S5 5 10 3V5V_CT2

2
ON2 CT2
3D3V_S5 6 9

2
VIN2#6 VOUT2#9 R4029 RSMRST_PWRGD#
7 8 [53] 1D0V_S5_PWRGD 1 2
VIN2#7 VOUT2#8
3D3V_S0 Comsumption Do Not Stuff
[54] 1D8V_S5_PWROK R4030 1 2
Peak current 2.5A

C4002
SC470P50V2KX-3GP

C4001
SC470P50V2KX-3GP

SC10U10V5KX-2GP
TPS22966DPUR-GP Do Not Stuff

C4004
74.22966.093 [17,45,53,54] 3V_5V_POK R4033 1 DY 2
Do Not Stuff
NON DS3: PH 3V_5V_POK to 3D3V_AUX_S5 at page17

2
3D3V_S0

H_THERMTRIP# [4]

1
R4016
DY Do Not Stuff
VCCSTG_EN
3D3V_S5
Q4002 U4003

2
Do Not Stuff R4015 1 DY 2 PM_SLP_S0_STG# 1 5

E
[17] SIO_SLP_S0# Do Not Stuff A VCC
H_THERMTRIP_EN
Do Not Stuff R4017 1 DY PM_SLP_S3_STG# Do Not Stuff
[17] H_THERMTRIP_EN B DY [17,24,27,51,52,54] SIO_SLP_S3#
2 2
B DY
Do Not Stuff
3 4 VCCSTG_EN

C
GND Y
R4007
C4003

1
[17,24,31,55,61,68,76] PLT_RST# 1 DY 2 Do Not Stuff Do Not Stuff

1
DY C4008 2015/02/06 modify 2ND = 73.7SZ08.EAH

K
Do Not Stuff DY 3RD = 73.01G08.L04 R4013

2
Do Not Stuff
1

D4004 R4014 1 DY 2 Do Not Stuff DY Do Not Stuff

2
R4003 DY Do Not Stuff
Do Not Stuff
DY

2
C C

A
2

VCCSTG_EN_D
3 PURE_HW_SHUTDOWN# [26] VCCSTG and VCCIO
1 +VCCIO +VCCSTG
[45] 3V_5V_EN
D4001 +VCCIO(ICCMAX = 2.73A) +VCCSTG(ICCMAX.=0.16A)
1

BAS16PT-GP U4002 Trise=10US < TR < 65US

R4048
1

2
Do Not Stuff
R4006 C4009
83.00016.F11 2015/02/04 mofidy
20KR2J-L2-GP

R4019
RISING TIME2 1 8 1 2
GATE VOUT#8
SC4D7U6D3V3KX-GP

DY VCCSTG_EN_R 2 7 Do Not Stuff

2

R4020 EN VOUT#7
3 6
2

GND VOUT#6
1 DY 2 4 5

1
Do Not Stuff 5V_S5 VBIAS VOUT#5
R4012
VCCIO can merge with VCCSTG
VCCSTG_EN 1 DY
DY VIN
9 1D0V_S5
2

1
Do Not Stuff
R4009
1 2 ALWON [24] Do Not Stuff Do Not Stuff DY C4016 DY C4007

1
Do Not Stuff

2
10KR2J-3-GP VIL > 0.7 V, VIH < 2 V C4029 DY VCCSTG should only ramp up equal to or after VCCST.
Rds(on) = 11 mΩ @ VDD = 4 V Do Not Stuff Do Not Stuff

2
Ids(max) 10 A

EOPIO and EDRAM 5V_S5 1D0V_S5

U4004
+V_EDRAM_VR
+V_EDRAM_VR Need to Check V1.8A
V_EDRAM_EOPIO_R 2 R4021 Voltage = 1.0 V ± 50 mV 1D8V_S5 +V1.8A
1
VIN#1 VOUT#8
8 1 23e Do Not Stuff
2 7
3
VIN#2 VOUT#7
6 Imax = 6 A Imax = 3.2 A
VBIAS VOUT#6
[17,24,27,51,52,54] SIO_SLP_S3# R4018 1 DY 2 EN_EDRAM_VR 4
ON GND
5 Rds on = 4.65mohm TRISE = 240 us R4037
Do Not Stuff

R4042 1 23e 1D0V_S5 23e VIN#9

9 1D0V_S5 1 NON2DS3
[17,24] ALL_SYS_PWRGD 2
Do Not Stuff C4017 C4021

1
Do Not Stuff V_EDRAM_EOPIO_R 1D8V_S5 0R6J-3-GP
Do Not Stuff
+V_EOPIO_VR Q4003

SC22U6D3V5MX-2GP

SC1U10V2KX-1GP
B [#543977 Rev1.1] PDDG change to ALL_SYS_PWRGD Do Not Stuff B

2
1

950mA DS3
1

1
C4015 23e C4011 Do Not Stuff C4010 Voltage = 1.0 V ± 50 mV S
Do Not Stuff

2015/09/03 modify
Do Not Stuff

23e DY Imax = 2.8 A D

2

D
2

G
TRISE = 240 us DS3 C4019

1
DS3 R4039 C4020

G
V_EDRAM_EOPIO_R +V_EOPIO_VR

Do Not Stuff
Do Not Stuff DS3 C4018 DY

Do Not Stuff
Do Not Stuff
R4040

2
2
1 2 1D8A_EN_R#
R4022 2 23e 1 DS3
Do Not Stuff Do Not Stuff

1D8A_EN#
Q4004 Do Not Stuff

[17,24,53,54] SIO_SLP_SUS# G DS3 2nd = 84.00102.031

D 3rd = 84.03413.B31
MANAGEMENT RAIL POWER GENERATION VCCST, VCCSTG, and VCCPLL can remain powered during S4 and S5 power states for board VR optimization.
S

VCCST Do Not Stuff

1

C4006 VIL > 0.7 V, VIH < 2 V

K

Do Not Stuff DY Rds(on) = 11 mΩ @ VDD = 4 V

3D3V_S5
DY D4003
Ids(max) 10 A V1.8S
2

Do Not Stuff
Do Not Stuff

C4014
A

3D3V_S5 +V1.8A +V1.8S_EDRAM

1

+V1.00U_CPU_LS +V1.00U_CPU Q4006

VCCSTU_EN_D

DY Do Not Stuff
2015/05/13 DVT2 modify U4006
R4025 100mA
2

S
1

RISING TIME 1 8 1 2 23e D

GATE VOUT#8

D
U4005 R4026 VCCSTU_EN_R 2 7 Do Not Stuff
EN VOUT#7

G
DY Do Not Stuff 3 6

1
GND VOUT#6 C4026 R4044
1 5 4 5 23e

G
2

1
NC#1 VCC VBIAS VOUT#5
Do Not Stuff

23eDo Not Stuff 23e C4022 Do Not Stuff C4027

2

2
1
R4008

Do Not Stuff
Do Not Stuff
Do Not Stuff
[17,24,51] SIO_SLP_S4# 2 9 1D0V_S5 R4041 23e

2
A 5V_S5 VIN C4012
DY DY 2nd = 84.00102.031

2
A VCCSTU_EN SC10U10V5KX-2GP 1D8S_EN_R# A
3 4 1 23e 2
2
1

GND Y M5938ARD1U-GP 3rd = 84.03413.B31

1

EC4001 C4013

1D8S_EN#
1

Do Not Stuff
SC10U10V5KX-2GP

Do Not Stuff DY +VCCSTG +VCCST_CPU Q4007

074.05938.0093
2

Do Not Stuff R4024 [17,24,27,51,52,54] SIO_SLP_S3# G

Do Not Stuff

VCCSTU_EN 1 2 0.04 A
2

Do Not Stuff Iris SKL UMA

23e D
1

R4045
R4023 1 2 DY C4028 1 DY 2 S
Do Not Stuff Do Not Stuff Wistron Corporation
2

Do Not Stuff Do Not Stuff 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
+V1.00U_CPU
Title
R4036
1
Do Not Stuff
2 Power Plane Enable
Size Document Number Rev
A2
Iris2 SKL-U A00
Date: Wednesday, September 09, 2015 Sheet 40 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = Power Plane & Sequence

Vinafix.com
3D3V_S5 3D3V_S5_PCH
D
R4101 D
1 2
NON DS3
0R5J-5-GP

3D3V_S5 Obs reason:

For new project,
pls help to use cost down version
SY6288C10CAC for instead.
C4102

1
3D3V_S5_PCH

Do Not Stuff
2

DS3 U4101
C C
1 GND OUT#8 8
2 IN#2 OUT#7 7
DS3 3 IN#3 OUT#6 6
[24] PCH_ALW_ON 1 2 DS3_PWRCTL 4 EN DS3 OC# 5
R4102 C4101

1
Do Not Stuff

Do Not Stuff
Do Not Stuff
Do Not Stuff (OBS)

2
DS3
RdsON: 100m ohm

DS3

B B

Iris SKL UMA

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Connected_Standby(1/2)+DS3
Size Document Number Rev
A4
Iris2 SKL-U A00
Date: Wednesday, September 09, 2015 Sheet 41 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = DIMM1

Main Func = DIMM2

Vinafix.com Layout Note:

Place Close DIMM1
D D

VREF CIRCUITRY DDR_VREF_S3 1D35V_S3

1
R4210
Do Not Stuff R4201
1K8R2F-GP
DY

2
1 R4202 2
Layout Note: [5] M_VREF_DQ_DIM0
2R2F-GP
M_VREF_DQ_DIMMA
Place Close DIMMs

1
DDR_VREF_S3 C4202 R4209
1D35V_S3 SCD022U16V2KX-3GP 1K8R2F-GP

2
+V_VREF_PATH1

2
1

1
1
R4204 R4211
Do Not Stuff R4206 24D9R2F-L-GP
1K8R2F-GP
DY
SA_DIMM_VREFDQ
2

2
2
2R2F-GP
1 R4208 2
C DIMM1 M_VREF_CA_DIMMA V_SM_VREF_CNT [5]
C

1
C4201
SCD022U16V2KX-3GP Layout Note:

2
1
Place Close DIMM2
R4203 +V_VREF_PATH3

1
1K8R2F-GP
R4207
24D9R2F-L-GP DDR_VREF_S3 1D35V_S3
2

2
1

1
R4205 R4212
Do Not Stuff R4216
Do Not Stuff

DY DM2 1K8R2F-GP
SA_DIMM_VREFDQ
2

2
R4213
1 DM2 2
DIMM2 M_VREF_CA_DIMMB [5] M_VREF_DQ_DIM1
2R2F-GP
M_VREF_DQ_DIMMB

1
DM2 C4203
SCD022U16V2KX-3GP
R4214
1K8R2F-GP
DM2

2
+V_VREF_PATH2

2
1
R4215
B B
DM224D9R2F-L-GP

2
A Iris SKL UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Connected_Standby(2/2)
Size Document Number Rev
A3
Iris2 SKL-U A00
Date: W ednesday, September 09, 2015 Sheet 42 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = ADT Input 5V_S5

1
PR4302 3D3V_S5
PQ4302 84.T3904.H11
15KR2F-GP PR4303

E
10KR2J-3-GP

1
PQ3802_1 B LMBT3904LT1G-GP 3D3V_S5

1
2
2
PD4302

1
PR4309 PSID_DISABLE#_R_C LBAV99LT1G-1-GP
100KR2J-1-GP PR4304
Layout Note: Vinafix.com 75.00099.O7D
2nd = 75.00099.K7D
2K2R2J-2-GP

G
1

3
PSID Layout width > 25mil

2
84.05067.031 3rd = 75.00099.Q7D
PR4305
D
PS_ID_R PR4317 1 2 PS_ID_R2 D S PS_ID_R1 1 2
4th = 75.00099.D7D D
PS_ID [24]

20150713 Alden Do Not Stuff 33R2J-2-GP

PQ4301
EL4304

1
DMN5L06K-7-GP
1 2 DY PD4303 PR4306
JGND Do Not Stuff 1 DY 2
0R5J-5-GP
Do Not Stuff
Pin Definition: TBD EL4303

3
1 2

0R5J-5-GP
60ohm@100MHz
DCIN1
DCR=0.02 ohm
8 Max current = 6000mA
6 1 AFTP3806
5 1 AFTP3803 +DC_IN AD+
4 PU4301
3 20150908 Alden 1 S
S
D
D
8

PC4305

PC4303

PC4304

PC4306
2 2 7

SC10U25V5KX-GP
SCD01U50V2KX-1GP
1

Do Not Stuff

Do Not Stuff
PC4302 PC4301 3 S D 6

240KR3-GP
K
1

1
+DC_IN_C EL4301 PR4314 SCD1U50V3KX-GP G D
EC4302

1 DY 4 5

PR4307
SCD1U25V2KX-GP
1

SC1U50V5ZY-1-GP-U
7 1 2 PD4301 DY DY
EC4301 0R5J-5-GP 3K3R6J-GP P6SBMJ24APT-GP

2
2

2
ACES-CON6-63-GP SI7121DN-T1-GE3-GP

A
1
Do Not Stuff

20.F2132.006 PR4312 PQ3809_D

EL4302 DY Do Not Stuff 84.2N702.A3F PQ4305

1
R2
1 2 2nd = 84.2N702.E3F PQ4304 E Id=-9.6A
JGND JGND 0R5J-5-GP 3rd = 75.00601.07C C AD_OFF_L B PR4308
Qg=-25nC
2

R1
4th = 84.DMN66.03F B R1 C AD_OFF_R 47KR3J-L-GP
PQ4306
E Rdson=18~30mohm
3 4 R2 PDTA124EU-1-GP

2
PDTC124EU-1-GP 84.00124.K1K
AC_IN#_G 2 5 84.00124.H1K 2nd = 84.05124.A11
2nd = 84.05124.011
C 1 6 C

2N7002KDW-GP
1

PR4313
Do Not Stuff
2

TP4301 1 AC_IN_KBC#
Do Not Stuff

[24] AC_DIS

AFTP3801 1 +DC_IN_C
AFTP3802 1 PS_ID_R
AFTP3805 1 +DC_IN_C

B B

Main Func = M-BAT Input

Placement: Close to Batt Connector

BT+

SMBCLK1
PBAT_PRES#

SMBDA1

20140812 DAVID
K
1

EC4308
DY DY EC4307 DY PD4304
Batt Connecter
Do Not Stuff

Do Not Stuff Do Not Stuff

2

BATT1 D4304 D4305 D4306

9 LBAV99LT1G-1-GP LBAV99LT1G-1-GP LBAV99LT1G-1-GP

RN4302
1 75.00099.O7D 75.00099.O7D 75.00099.O7D
4 5 2
1

3 6 PBAT_SMBCLK1 3
[24,44] SMBCLK1
2 7 PBAT_SMBDAT1 4
[24,44] SMBDA1
1 8 PBAT_PRES1# 5
[24,44] PBAT_PRES#
1 R4301 2SYS_PRES1# 6
7 3D3V_S5_KBC
SRN100J-4-GP Do Not Stuff 8
10 2nd = 75.00099.K7D 2nd = 75.00099.K7D 2nd = 75.00099.K7D
A SYN-CON8-9-GP-U A
3rd = 75.00099.Q7D 3rd = 75.00099.Q7D 3rd = 75.00099.Q7D
20.81153.008
4th = 75.00099.D7D 4th = 75.00099.D7D 4th = 75.00099.D7D
2

EC4309 EC4310 EC4306

1

1
Do Not Stuff

Do Not Stuff

Do Not Stuff

DY 1 AFTP3906
DY DY 1 AFTP3909
1

1 AFTP3910 Iris SKL UMA

2

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
PBAT_PRES1# 1 AFTP3902 Taipei Hsien 221, Taiwan, R.O.C.
PBAT_SMBDAT1 1 AFTP3903
PBAT_SMBCLK1 1 AFTP3904 Title
BT+ 1 AFTP3905
BT+
BT+
1
1
AFTP3908
AFTP3907 Size Document Number
DCIN Rev
SYS_PRES1# 1 AFTP3901 A2
Iris2 SKL-U X02
Date: Wednesday, September 09, 2015 Sheet 43 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = Charger

AD+ PU4405 +SDC_IN CHARGER_SRC

PR4426
8 D S 1 1 2
7 D S 2
6 D S 3
D01R3721F-GP-U
5 D G 4

1
PG4406 PG4402
PR4435 Do Not Stuff Do Not Stuff

SI7121DN-T1-GE3-GP Vinafix.com 100KR2J-1-GP

2
2
84.07121.037

1
D PR4421 D
PR4418 2nd = 84.06675.030 AD+_G_2 Do Not Stuff
3K3R6J-GP 2 DY 1

2
Battery type PR4444 Setting

2
PR4423 1 PC4428

DC_IN_D
2
10KR2F-2-GP SCD1U25V2KX-GP
3S 287K 17.05V
PQ4407

Do Not Stuff
AD+_G_1

PC4418
SCD1U25V2KX-GP
4S 309K 18.178V

PC4416
3 4

2
ACOK_IN 2 5
DY

1
1 6

1
BT+
2N7002KDW-GP
PD4405 A K 84.2N702.A3F BQ24770_AGND
CH035H-40PT0-GP 83.1R504.B8F 2nd = 84.DM601.03F
3rd = 84.2N702.E3F
AD+ 4th = 84.2N702.F3F BQ24770_AGND
PD4406 A K PWR_CHG_1 1 2 PWR_CHG_VCC
PC4410
CH035H-40PT0-GP 83.1R504.B8F PR4403 10R5J-GP
SC1U25V3KX-1-GP

1
1
CHARGER_SRC

SCD1U25V2KX-GP
PC4433
AD+ PC4421
SCD1U25V2KX-GP
PU4406:

2
VacDET=2.4V PC4432 PWR_CHG_BTST1 1 2

PWR_CHG_ACP
2

PWR_CHG_ACN

PC4413
Acok setting=2.4*((PR4444+PR4411)/PR4411)

Do Not Stuff

PC4425

PC4411

PC4427

PC4407

PC4434
2
Setting=18.178v BQ24770_AGND DY SCD047U25V3KX-3-GP
main source: 84.03660.037
1

1
BQ24770_AGND PR4425

2
PR4444
KBC FOR DT MODE Do Not Stuff

K
+SDC_IN

SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP PC4408
309KR2F-GP PU4406

2
PD4401 FDMS3660S-GP
CHECK EE PULL HIGH

PWR_CHG_BTST 1
BQ24770_AGND CH035H-40PT0-GP 2
2

1
83.1R504.B8F 3

1
PR4439 PU4401 1 4

A
DCBATOUT

SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP
4K02R2F-GP 10

ACP

ACN
3D3V_S5_KBC 28 9
VCC PWR_CHG_REGN
Do Not Stuff

7
2
1

PC4403

PC4430

PC4409
C DY PR4411 8 6 C
47KR2F-GP PWR_CHG_CMSRC 3 25 5
CMSRC BTST

1
2
1

PC4402

4
PR4432 PR4414 ACDRV PWR_CHG_REGN +VCHGR
24 1 2
84.03660.037
2

2
Do Not Stuff Do Not Stuff REGN PD4402 V8P10-5300M3-86A-GP
DY DY PWR_CHG_ACDET 6 PC4422 1
ACDET Change to 84.03660.037 PL4401

SC10U25V5KX-GP

SC10U25V5KX-GP
ACAV_IN BQ24770_AGND SC2D2U10V3KX-1GP
2

BQ24770_AGNDH=ACIN 26 PWR_CHG_HIDRV 1 2 1 2 3
HIDRV

PC4440
ACOK_IN 2 1 PWR_CHG_ACOK 5 68.2R210.20C PR4443
L=UNAC ACOK

PR4427

Do Not Stuff

PC4441
SC10U25V5KX-GP

PC4439

PC4415
PR4430 Do Not Stuff COIL-2D2UH-11-GP D01R2512F-3-GP 2

1
BT+

PC4420
PG4401 27 PWR_CHG_PHASE
PHASE

1
Do Not Stuff
2 1 PWR_SCL 12 PC4442
[24,43] SMBCLK1 SCL
DY DY 83.8R010.A87

2
Do Not Stuff

Do Not Stuff
Do Not Stuff PG4408 23 PWR_CHG_LODRV SC10U25V5KX-GP

2
LODRV

PG4407

PG4403
2 1 PWR_SDA 11 PU4403
[24,43] SMBDA1

2
SDA S D
1 8

SC10U25V5KX-GP
22 DCBATOUT_SNUB 2 S D 7 PC4424
Do Not Stuff

1
BQ24770_IADP GND S D
2 1 7 3 6
[24] AD_IA IADP

Do Not Stuff
PR4466 Do Not Stuff BATDRV# 4 G D 5
Discharge Current Monitor

Do Not Stuff
BQ24770_IDCHG

PC4406
[24] BOOST_MON
2 1 8
IBAT PWR_CHG_SRP PWR_CHG_SRP_R
DY
PR4434 Do Not Stuff 20 PR4438 1 2 Do Not Stuff DY
BQ24770_PMON SRP
2 1 9

2
[24,46] P_SYS PR4467 Do Not Stuff PMON SI7121DN-T1-GE3-GP
SC100P50V2JN-3GP
PC4435

SC100P50V2JN-3GP
PC4436

SC100P50V2JN-3GP
PC4437

System Power Monitor

PR4469 19 PWR_CHG_SRN PR4417 1 2 Do Not Stuff PC4429
0R0402-PAD 1 PROCHOT#_BQ24770 SRN
2 10 1 2
84.07121.037
1

PROCHOT# PWR_CHG_BAT
These pins can be floating BAT
17 2 1 BT+

1
if they are not in use. PR4413 PC4401 SCD1U25V2KX-GP PC4412 2nd = 84.06675.030
Do Not Stuff 15 PR4408 SCD1U25V2KX-GP SCD1U25V2KX-GP
IADP=40*V(acp_acn) or 80*V(acp_acn)
2

PWR_CHG_CMPIN BATPRES# PBAT_PRES# [24,43]

1 DY 2CHG_CMPIN_1 13 20R3F-L-GP

2
IDCHG=8*V(srn-srp) or 16*V(srn-srp) CMPIN PWR_CHG_BATDRV BATDRV#
18 1 2

1
PWR_CHG_CMPOUT BATDRV#
1 DY 2CHG_CMPOUT_1 14 PC4438 PWR_CHG_SRN_R
CMPOUT ILIM
PR4415 Do Not Stuff
ILIM
21 PR4409 SC1U25V3KX-1-GP BQ24770_AGND BQ24770_AGND
16 1KR2F-3-GP
GND

[4,24,46] H_PROCHOT#

2
CELL
Do Not Stuff TP4401 1PWR_CHG_CMPIN
PWR_CHG_REGN BQ24770RUYR-3-GP PWR_CHG_REGN
29

Do Not Stuff TP4402 1PWR_CHG_CMPOUT

AD+
1

1
B BQ24770_AGND B
100KR2J-1-GP
PR4416

PR4449 PR4470 PWR_CHG_REGN

100KR2J-1-GP 074.24770.0B03 100KR2J-1-GP
1

2
CHARGER_CELL_PIN

1
PR4406 1 2 Do Not Stuff
PR4410
2

1 100KR2J-1-GP

DY PR4471

2
1

BQ24770_AGND Do Not Stuff PWR_CHG_ACOK

PWR_CHG_ACOK [17,24]
PR4433

1
Do Not Stuff
DY
2
E PQ4408_E

PR4404
H_PROCHOT# [4,24,46] 120KR2J-GP
2

2
PD4403 PR4455 84.2N702.A3F
1N4148WS-7-F-GP Do Not Stuff 2nd = 84.DM601.03F
K APD4403_A B LMBT3906LT1G-1-GP 3rd = 84.2N702.E3F
PQ4408 4th = 84.2N702.F3F
PQ4405
1

PD4403_K
C

PQ4405_3 3 4
PR4462
2

84.T3906.E11 PQ4408_C 2 PQ4405_2 PQ4405_5

PR4458 1 2 5
Do Not Stuff
1

1 6
Do Not Stuff
PC4404
SC1U10V2KX-1GP
1

2N7002KDW-GP
2

PR4451 PR4463
680KR2F-GP Do Not Stuff DY
DCBATOUT
PQ4405_6
2

2 PWR_CHG_ACOK

PR4405
100KR2F-L1-GP
1

PR4450
1
10KR2F-2-GP

A A

CHECK EE
2

follow custormer circuits. 3D3V_S5

Iris SKL UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CHARGER
Size Document Number Rev
A2
Iris2 SKL-U A00
Date: Wednesday, September 09, 2015 Sheet 44 of 105
5 4 3 2 1
 A B C D E

Main Func = 3D3V_5V

Vinafix.com 3D3V_AUX_S5
4 4

1
DCBATOUT PWR_DCBATOUT_5V
PR4501
Do Not Stuff DY PG4520
2 1

2
PR4530 PR4504 Do Not Stuff
PG4536
2 DY 1 PWR_5V_EN1_R 1 2 PWR_5V_EN1 2 1

Do Not Stuff Do Not Stuff

2
Do Not Stuff
PG4518
PR4507 2 1
Do Not Stuff
DCBATOUT PWR_DCBATOUT_3D3V Do Not Stuff
PR4506 PG4534

1
PG4525 2 1
2 1 1 2 PWR_3D3V_EN2
[40] 3V_5V_EN
Do Not Stuff
Do Not Stuff PG4542
Do Not Stuff
PG4521 2 1
2 1
Do Not Stuff
Do Not Stuff PG4543
PG4524 2 1
2 1
Do Not Stuff
Do Not Stuff
PG4531
2 1
DCBATOUT
Do Not Stuff

PWR_DCBATOUT_3D3V

PC4528 PC4509
PC4525 PC4519 PC4531
SC4D7U25V5KX-GP
1

PWR_DCBATOUT_5V
Do Not Stuff

Do Not Stuff
1

1
SCD1U50V3KX-GP

SCD01U50V2KX-1GP
DY
3 Design Current=3.5A DY 3
2

5.25A<OCP>6.3A

2
PC4530 PC4529 PC4527
PU4504
8
7
6
5

5
6
7
8

1
SIS412DN-T1-GE3-GP

SCD1U50V3KX-GP

SC4D7U25V5KX-GP

SC10U25V5KX-GP
SIS412DN-T1-GE3-GP

D
D
D
D
5V_S5
D
D
D
D

2rd = 074.06576.0043 PU4501 5V_PWR

84.00412.037

12
PG4527

2
PU4503 2 1

VIN
PC4535 PR4528
Design Current=6.85A Do Not Stuff

G
S
S
S
2 1PWR_3D3V_VBST2_11 2 PWR_3D3V_VBST2 PC4516 PG4519
S
S
S
G

3D3V_S5 3D3V_PWR 1D5R3-GP PR4524 10.275A<OCP>12.33A 2 1

1
2
3
4

4
3
2
1
PG4526 9 17 PWR_5V_VBST1 1 2 PWR_5V_VBST1_1 1 2
SCD1U50V3KX-GP VBST2 VBST1
2 1 1D5R3-GP Do Not Stuff
3D3V_PWR 68.3R310.20A PWR_3D3V_DRVH2 10 16 PWR_5V_DRVH1 SCD1U50V3KX-GP 68.2R210.20B 5V_PWR PG4538
PL4502 DRVH2 DRVH1 PL4501
Do Not Stuff 2 1
PG4517 1 2 PWR_3D3V_LL2 8 18 PWR_5V_LL1 1 2
IND-3D3UH-57GP SW2 SW1
2 1 Do Not Stuff
1

PWR_3D3V_DRVL2 11 15 PWR_5V_DRVL1 IND-2D2UH-46-GP-U PG4537

1
DRVL2 DRVL1
Do Not Stuff 2 1

5
6
7
8
PG4528 PR4533 DY PU4502 PR4529 PG4532 PC4518
8
7
6
5

D
D
D
D

SIS780DN-T1-GE3-GP
PC4517 PT4502 PG4535 Do Not Stuff PWR_5V_VO1 Do Not Stuff
2 1
VO1
14 DY Do Not Stuff
1

1
Do Not Stuff
D
D
D
D

PU4505 PG4533
2
1

Do Not Stuff
SE220U6D3VM-38-GP

Do Not Stuff

Do Not Stuff SIS412DN-T1-GE3-GP PWR_3D3V_FB2 4 2 PWR_5V_FB1 DY PT4501 2 1

2
VFB2 VFB1
Do Not Stuff

PG4522 DY
1PWR_3D3V_SNUB

SE220U6D3VM-38-GP
2

2
G
2 1 4 79.22710.3KL Do Not Stuff
2

2
S
S
S
84.00412.037 PG4523

1PWR_5V_SNUB
Do Not Stuff PWR_3D3V_EN2 6 20 PWR_5V_EN1 2 1
S
S
S
G

3
2
1
EN2 EN1
PG4529
1
2
3
4

2 1 Do Not Stuff
3V_FEEDBACK

PWR_3D3V_CS2 5 1 PWR_5V_CS1 PG4541

CS2 CS1 TP4501
Do Not Stuff 2 1
1

1
Do Not Stuff
PR4517 PWR_5V_VCLK 1 PR4531
79.22710.3KL PC4520
DY 127KR2F-GP VCLK
19
150KR2F-L-GP PC4536
Do Not Stuff
DY PG4540
2

Do Not Stuff Do Not Stuff 2 1

2
7 21
2

2
PGOOD GND
Do Not Stuff
VREG3

VREG5
PG4545
2 1
1

1
2 TPS51225RUKR-GP Do Not Stuff 2
3

13

PR4512 PR4535 PR4525 PG4544

1
3D3V_PWR_2
6K98R2F-GP DYDo Not Stuff 3D3V_S5
5V_PWR_2 Do Not Stuff DY PR4527
2 1

PR4534 15K4R2F-GP Do Not Stuff

PWR_5V_FB1_R
2

1 2

1 2
PWR_3D3V_FB2_R
1
Do Not Stuff

PC4523

2
1

DYDo Not Stuff PC4526

PC4524
SC1U6D3V3KX-2GP Do Not Stuff
PC4522 DY
DY
2

2
SC4D7U6D3V3KX-GP
2

2
2
1

1
PR4523 PR4526
10KR2F-2-GP 9K76R2F-1-GP
[17,40,53,54] 3V_5V_POK
PH at Page40 Close to VFB Pin (pin2)
2

2
3D3V_PWR_2 3D3V_AUX_S5
PR4532
1 2
Close to VFB Pin (pin5)
Do Not Stuff

I/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L

I/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L Inductor: CHIP CHOKE 2.2U PCMC063T-2R2MN 18mohm/20mohm Isat =14Arms 68.2R210.20B
Inductor: CHIP IND 3.3UH PCMC063T-3R3MN Cyntec 28mohm/30mohm Isat =13.5Arms 68.3R310.20A O/P capCHIP CAP EL 220U 6.3V M6.3*4.4 /Chemi-con/ 18mOhm / 79.22710.3KL
O/P capCHIP CAP EL 220U 6.3V M6.3*4.4 /Chemi-con/ 18mOhm / 79.22710.3KL H/S:SIS412 / 24mOhm/30mOhm@4.5Vgs / 84.00412.037
H/S:SIS412 / 24mOhm/30mOhm@4.5Vgs / 84.00412.037 L/S:SIS780 / 14.5mOhm/17.5mOhm@4.5Vgs / 84.00780.037
L/S:SIS412 / 24mOhm/30mOhm@4.5Vgs / 84.00412.037
1 1

Iris SKL UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

DCDC-3D3V&5V
Size Document Number Rev
A2
Iris2 SKL-U A00
Date: Wednesday, September 09, 2015 Sheet 45 of 105
A B C D E
 5 4 3 2 1

Main Func = CPU_CORE

PR4611
48D7KR2F-GP
1 2

PC4632

Vinafix.com 1

SC1KP50V2KX-1GP
2

PR4602
D PC4602 81208_AGND D
1 2 PWR_VCCSA_COMP_R 1 2 PWR_VCCSA_CSN [50]
PC4607

2
SC4700P50V2KX-1GP
1K5R2F-2-GP SCD015U25V2KX-GP

PC4604 PC4606 PR4606

1
SC15P50V2JN-2-GP SCD015U25V2KX-GP NTC-100K-1-GP-U

1
1 2 PR4609
PC4603 14K3R2F-GP 69.60028.011

2
SC1KP50V2KX-1GP

1
PWR_VCCSA_VSN_R 1 2 1 2 PWR_VCCSA_CSN_NTC
81208_AGND
PR4605 PR4612
[7] VSSSA_SENSE PR4604 1 2 Do Not Stuff 1 2 1 2 PWR_VCCSA_CSP [50]
8K06R3F-AS-GP 3D3V_S0
825R2F-GP PR4613 107KR2F-GP

2
PC4605 2 1

1
SC1KP50V2KX-1GP
PR4608 PC4609 SC220P50V2KX-3GP PR4614

1
2K8R2F-GP 1 2 DY Do Not Stuff
[7] VCCSA_SENSE PR4607 1 2 Do Not Stuff 1 2

2
81208_AGND PR4670 1 2 Do Not Stuff VR_RDY 1 AFTP4601
PWR_VCCSA_VSP_R 1 2 1 2
PR4616 PR4630 1 2 Do Not Stuff
0R0402-PAD PC4608 VR_EN [40]
SC1KP50V2KX-1GP +VCCST_CPU
PWR_VCCSA_VSP_RC PR4671 1 2 0R0402-PAD PSYS
[24,44] P_SYS

PR4615 2 1 20KR2F-L-GP

Do Not Stuff
PR4622

100R2F-L1-GP-U
PR4623

1
PC4610
81208_AGND SCD1U25V2KX-GP +VCCST_CPU +VCCSTG Check +VCCST_CPU or +VCCSTG

2
[7] VCCGT_SENSE PR4617 1 2 Do Not Stuff

1
45D3R2F-L-GP
PR4621
DY

1
PC4611 [#543016]
SC1KP50V2KX-1GP

1
C PR4619 C
[7] VSSGT_SENSE PR4618 1 2 Do Not Stuff 2 1 1KR2F-3-GP PR4624 PR4669
Do Not Stuff
VR_SVID_CLK [7] DY DY Do Not Stuff
PWR_VCCGT_VSN_R 1 2 VR_SVID_ALERT# [7]

2
PC4612 SC2200P50V2KX-2GP PG4601 VR_SVID_DATA [7]
Do Not Stuff

[50]

[47,48,50]
PR4668

PWR_VCCSA_PWM
2 1

PWR_VCORE_DRVON
1

PR4665

PR4666

PR4667
1 2 H_PROCHOT# [4,24,44]
PR4625 100R2F-L1-GP-U
37D4R2F-GP
81208_AGND

PWR_VCORE_VR_RDY
1

PWR_VCCSA_CSP1B
PWR_VCCSA_COMP
2

PWR_VCCSA_IOUT

49D9R2F-GP

0R0402-PAD

10R2F-L-GP
PWR_VCCGT_VSN

PWR_VCCSA_VSN
PWR_VCCGT_VSP

PWR_VCCSA_VSP
PR4626 PC4613 2 SC470P50V2KX-3GP

PWR_VCCSA_ILIM
1

PWR_VCORE_EN

1
PWR_VCCGT_FB_R 634R3F-GP PR4627
1 2 1 2 PWR_VCORE_CSP [47]
1

PR4628 113KR2F-1-GP 8K06R3F-AS-GP

PR4632
2

PC4614
SC470P50V2KX-3GP 1 2 81208_AGND
PR4629
2

2
81208_AGND
26K1R2F-2-GP 1 2 PWR_VCORE_CSNNTC
1

PWR_VCORE_VRHOT#
PWR_VCORE_ALERT#

2
PR4631 14KR2F-GP

49

48
47
46
45
44
43
42
41
40
39
38
37

PWR_VCORE_SCLK

PWR_VCORE_SDIO
PC4617 4K75R2F-1-GP 1 2 PU4601
1

1
SC10P50V2JN-4GP PR4633

PSYS
VSP_1B
VSN_1B
COMP_1B
ILIM_1B
CSN_1B
CSP_1B
IOUT_1B
VR_RDY
GND

VSN_2PH
VSP_2PH

EN
PWR_VCCGT_ILIM_R

PC4615 PC4634 PC4616 NTC-100K-1-GP-U

2

SC470P50V2KX-3GP SCD022U16V2KX-3GP SC3300P50V2KX-1GP

69.60028.011
2

2
PWR_VCCGT_COMP_R
1

PR4634 81208_AGND PWR_VCORE_CSN [47]

1
1 2 PC4618 PWR_VCCGT_IOUT 1 36
SC3300P50V2KX-1GP PWR_VCCGT_DIFFOUT IOUT_2PH PWM_1B
2 35 1 2
2

PR4638 NTC-220K-5-GP-U PWR_VCCGT_FB DIFFOUT_2PH DRVON PR4635

3 34
PR4637 165KR2F-GP PWR_VCCGT_COMP FB_2PH SCLK
4 33
PWR_VCCGT_ILIM COMP_2PH ALERT# 57K6R2F-GP
[48] PWR_VCCGT_CSPA 1 2 2 1 1 PR4639 2 1 PR4640 2 5 32
48K7R3F-1-GP PWR_VCCGT_CSCOMP ILIM_2PH SDIO SCD01U50V2KX-1GP
6 31
1

PC4620 12K4R2F-GP PWR_VCCGT_CSSUM CSCOMP_2PH VR_HOT# PWR_VCORE_IOUT PC4633 81208_AGND

7 30
75KR2F-GP SC1KP50V2KX-1GP PC4621 PWR_VCCGT_CSREF CSSUM_2PH IOUT_1A PWR_VCORE_CSP_1A PC4601 PWR_VCORE_COMP_R
PR4641 DY Do Not Stuff
8
CSREF_2PH CSP_1A
29 1 2 1 2 1 2
9 28 SC1KP50V2KX-1GP PR4636
2

CSP2_2PH CSN_1A PWR_VCORE_ILIM

[48] PWR_VCCGT_CSPB 1 23e 2 10
CSP1_2PH ILIM_1A
27
PWR_VCORE_COMP PC4622 PC4619 1K54R2F-GP
11 26 1 2

ROSC_COREGT
TSENSE_2PH COMP_1A

ADDR_VBOOT
B Do Not Stuff 12 25 PWR_VCORE_VSN 2 1PWR_VCORE_VSN_R SC15P50V2JN-2-GP 81208_AGND B

TSENSE_1PH
ICCMAX_2PH
VRMP VSN_1A

ROSC_SAUS
PR4643 2 1 Do Not Stuff

ICCMAX_1A
ICCMAX_1B
23e

PWM1_2PH
PWM2_2PH
[48] PWR_VCCGT_CSNB
5V_S5 SC1KP50V2KX-1GP
PWR_VCORE_VRMP

PWM_1A

VSP_1A
1 2 PR4645 1 2 Do Not Stuff VSS_SENSE [7]
1

PR4644
VCC
1

1
[48] PWR_VCCGT_CSNA PR4646 2 1 10R2F-L-GP PR4642 422R2F-2-GP PC4625
PC4623 PC4624 1KR2F-3-GP SC1KP50V2KX-1GP
SCD047U25V2KX-GP Do Not Stuff
22 NCP81208MNTXG-4-GP PR4647
23e
2

13
14
15
16
17
18
19
20
21
22
23
24

2
1 2 PR4648 1 2 Do Not Stuff VCC_SENSE [7]
2

PWR_VCCGT_CSP2 3K83R2F-GP
1

PWR_VCORE_VCC_R

PWR_VCORE_ROSC_SAUS

PC4626 PWR_VCCGT_CSP1 PWR_VCORE_VSP 2PWR_VCORE_VSP_RC PWR_VCORE_VSP_R

PWR_VCORE_ROSC_COREGT

1 1 2
SCD01U50V2KX-1GP PWR_VCCGT_TSENSE PR4649
2

2K49R2F-GP PC4627 PR4650

DCBATOUT PWR_VCORE_TSENSE SC1KP50V2KX-1GP 2 1 PWR_VCORE_NTC
PR4651 81208_AGND PWR_VCORE_PWM [47]
[48] PWR_VCCGT_CSPA 1 2 PR4601 PWR_VCORE_ADDR_BOOT

2
PWR_VCCSA_ICCMAX Do Not Stuff
1 2 1KR2F-3-GP

1
4K87R2F-GP PWR_VCORE_ICCMAX PR4652
1 23e 2 PWR_VCCGT_ICCMAX PC4628 12K7R2F-GP PR4653
[48] PWR_VCCGT_CSPB
1

SCD1U25V2KX-GP NTC-100K-1-GP-U

2
PR4654 PC4629 69.60028.011

2
Do Not Stuff SCD01U50V2KX-1GP PR4658 PR4660
2

1
PR4655 PR4663

1
PWR_VCCGT_NTC 1 2 PR4662

15K8R2F-GP

10KR2F-2-GP
U22 15W U23e 28W

48D7KR2F-GP

90K9R2F-GP
Do Not Stuff 81208_AGND 81208_AGND
2

5V_S5
1

2
1

PR4637 47K (64.47025.55L) 73K (64.73225.55L) PR4656 PR4657

NTC-100K-1-GP-U PR4661 PC4630 2D2R2F-GP PR4664 PR4659
PR4641 Dummy 73K (64.73225.55L) 12K7R2F-GP SCD1U25V2KX-GP 1 2 24KR2F-GP 24KR2F-GP
2

PR4640 12.4K (64.12425.6DL) 16.5K (64.16525.6DL)

69.60028.011
2

2
1
1

PR4662 49.9K (64.49925.6DL) 100K (64.10035.6DL) PC4631

SC1U10V2KX-1GP 81208_AGND
2

PR4658 88.7K (64.88725.6DL) 90.9K (64.90925.6DL)

81208_AGND PWR_VCCGT_PWMB [48]
PR4635 61.9K (64.61925.6DL) 60.4K (64.60425.6DL) 81208_AGND 81208_AGND 81208_AGND
PWR_VCCGT_PWMA [48]
PR4628 118K (64.11835.6DL) 113K (64.11305.6DL)
A A
PR4643 Dummy 10R (64.10R05.6DL)

PR4654 Dummy 4.87K (64.48715.6DL)

PC4624 Dummy D047U (78.47322.2FL)

Iris SKL UMA
PR4642 1K (64.10015.6DL) Dummy

PR4602 1.5K (64.15015.6DL) 10K (64.10025.6DL) Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
PC4602 15n (78.15322.2FL) 1kP (78.10224.2FL)
Taipei Hsien 221, Taiwan, R.O.C.

Title
NCP81208MN_CPU_VCORE(1/3)
Size Document Number Rev
A2 Iris2 SKL-U A00
Date: Wednesday, September 09, 2015 Sheet 46 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU_CORE

DCBATOUT

Vinafix.com

SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP

SCD1U25V2KX-GP
PC4710

1
D PC4702 PC4703 PC4701 PC4704 PC4705 D

2
PR4701
1 2 PW R_VCORE_BOOT_RC

PWR_VCORE_BOOT
3D9R3-GP

1
5V_S5 PC4706
SCD22U25V3KX-GP
PR4702

2
2D2R2F-GP

25
26
27
28
29
30

33

35
1
2 1 PW R_VCORE_VCC PU4701

THWN

VIN
VIN
VIN
VIN
VIN
VIN

GH

BOOT
1
PC4708 VCC_CORE
SC1U10V2KX-1GP 6
2
C VCC PW R_VCORE_PHASED C
PHASED 34 PL4701
7 VCCD PHASEF 32
1

PC4707 12 PW R_VCORE_SW 1 2
SC2D2U10V2KX-GP VSW#12
5 13
2

CGND VSW#13
VSW#14 14 COIL-D15UH-2-GP
VSW#15 15
[46] PW R_VCORE_PW M
4 PWM VSW#16 16 68.R1510.20A
17 PT4701
PR4704 PW R_VCORE_DISB# 2 VSW#17
1 2 DISB# VSW#18 18

1
[46,48,50] PW R_VCORE_DRVON

SE330U2VDM-L-GP
Do Not Stuff 36 ZCD_EN

1
5V_S5 PG4707 PG4708

2
Do Not Stuff

Do Not Stuff
3 PR4703

1
SMOD# Do Not Stuff
DY
GL#10
GL#11

PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
GL#8
GL#9

2
NCP81382MNTXG-3-GP PW R_VCORE_SNUB
8
9
10
11

19
20
21
22
23
24
31
37

1
PC4709
PW R_VCORE_GL Do Not Stuff
DY

2
Confirm with EE:
22uF/0805 total 32pcs (DY 5 pcs)
B B
[46] PW R_VCORE_CSP

[46] PW R_VCORE_CSN

A Iris SKL UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
NCP81382MN_CPU_VCORE(2/3)
Size Document Number Rev
A3 Iris2 SKL-U A00
Date: W ednesday, September 09, 2015 Sheet 47 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU_CORE

DCBATOUT

DCBATOUT

SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP

SCD1U25V2KX-GP
PC4811

Vinafix.com

1
PC4802 PC4803 PC4804 PC4805 PC4806

1
PT4804
DY

Do Not Stuff
2

2
D D

PR4802
1 2
For acoustic noice

PWR_VCCGT_BOOTA
3D9R3-GP PWR_VCCGT_BOOTA_RC

5V_S5

1
PC4809
SCD22U25V3KX-GP
PR4803

2
2D2R2F-GP

25
26
27
28
29
30

33

35
1
2 1 PWR_VCCGT_VCCA PU4801

THWN

VIN
VIN
VIN
VIN
VIN
VIN

GH

BOOT
1

PC4808
SC1U10V2KX-1GP 6 +VCCGT
2

VCC PWR_VCCGT_PHASEDA
34 PL4801
PHASED
7 32
1

VCCD PHASEF
PC4807 12 PWR_VCCGT_SWA 1 2 Confirm with EE:
SC2D2U10V2KX-GP VSW#12 COIL-D15UH-2-GP
5 13
22uF/0805 total 35pcs (DY 5 pcs)
2

CGND VSW#13
VSW#14
14 68.R1510.20A
15
VSW#15

1 PT4801
4 16
[46] PWR_VCCGT_PWMA PWM VSW#16
17
PR4808 PWR_VCCGT_DISB#_A VSW#17
1 2 2 18

2
[46,47,50] PWR_VCORE_DRVON DISB# VSW#18
Do Not Stuff 36

1
5V_S5 ZCD_EN PG4808 PG4809

Do Not Stuff

Do Not Stuff
3 PR4804

2
SMOD# Do Not Stuff
DY
GL#10
GL#11

PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
GL#8
GL#9

79.33719.L01

SE330U2VDM-L-GP
C C

2
NCP81382MNTXG-3-GP
8
9
10
11

19
20
21
22
23
24
31
37
PWR_VCCGT_SNUB_1

1
PWR_VCCGT_GL1
PC4810
Do Not Stuff
DY

2
[46] PWR_VCCGT_CSPA

[46] PWR_VCCGT_CSNA

DCBATOUT
Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff
PC4812
1

1
PC4820 PC4829 PC4830 PC4828 PC4827
23e 23e 23e 23e 23e 23e
2

2
B B

PR4805
1 23e 2
PWR_VCCGT_BOOTB

Do Not Stuff PWR_VCCGT_BOOTB_RC

5V_S5
1

PC4845

PR4806
23e Do Not Stuff
2

Do Not Stuff
25
26
27
28
29
30

33

35
1

2 23e 1 PWR_VCCGT_VCCB PU4802

THWN

VIN
VIN
VIN
VIN
VIN
VIN

GH

BOOT
1

PC4847 23e
Do Not Stuff 6
2

VCC PWR_VCCGT_PHASEDB +VCCGT

34 PL4802
PHASED
7 32
1

VCCD PHASEF
PC4846 PWR_VCCGT_SWB
23e
Do Not Stuff
23e VSW#12
12 1 2
5 13 Do Not Stuff
2

CGND VSW#13
VSW#14
14 Do Not Stuff
15
VSW#15
4 16
[46] PWR_VCCGT_PWMB PWM VSW#16

1 PT4802

1 PT4803
PR4809 17
PWR_VCCGT_DISB#_B VSW#17
1 23e 2 2
DISB# 23e VSW#18
18
2

[46,47,50] PWR_VCORE_DRVON
Do Not Stuff 36
1

ZCD_EN PG4815 PG4816

Do Not Stuff

Do Not Stuff

5V_S5 3 PR4807
1

SMOD# Do Not Stuff

DY DY DY
GL#10
GL#11

2
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
GL#8
GL#9

Do Not Stuff

Do Not Stuff
Do Not Stuff
8
9
10
11

19
20
21
22
23
24
31
37

PWR_VCCGT_SNUB_2
A A
1

PWR_VCCGT_GL2
PC4814
Do Not Stuff
DY
2

Iris SKL UMA

Wistron Corporation
[46] PWR_VCCGT_CSPB 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
[46] PWR_VCCGT_CSNB NCP81382MN_CPU_VCCGT(3/3)
Size Document Number Rev
A2 Iris2 SKL-U A00
Date: Wednesday, September 09, 2015 Sheet 48 of 105
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

B B

A A

Iris SKL UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
NCP81210MN_CPU_VCCGTUS
Size Document Number Rev
A2 Iris2 SKL-U A00
Date: Tuesday, May 26, 2015 Sheet 49 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU_CORE

DCBATOUT DCBATOUT_+VCCSA
Vinafix.com
PG5023
D 2 1 D

Do Not Stuff
PG5024
2 1

Do Not Stuff

DCBATOUT_+VCCSA

PC5029 PC5027 PC5002

1
SC10U25V5KX-GP

SC10U25V5KX-GP

SCD1U25V2KX-GP
5
6
7
8
PR5013

2
D
D
D
D
1 2 PW R_VCCSA_BST_RC PU5002
SIS412DN-T1-GE3-GP #544669 Intel CRB Rev0.53
2D2R3-1-U-GP +VCCSA(ICCMAX.=6A)
PWR_VCCSA_BST

G
S
S
S
PC5008
SCD22U25V3KX-GP PW R_+VCCSA +VCCSA

4
3
2
1
2
PW R_+VCCSA
C PU5001 PG5026 C

PL5001 2 1
1 8 PW R_VCCSA_DRVH
BST DRVH PW R_VCCSA_SW Do Not Stuff
2 PWM SW 7 1 2
[46] PW R_VCCSA_PW M 3 6 PG5025
[46,47,48] PW R_VCORE_DRVON EN GND
5V_S5 4 VCC DRVL 5 IND-D47UH-22-GP 2 1

1
9 Do Not Stuff
GND
1

PR5014 PG5028
PC5001 Do Not Stuff 2 1
DY

5
6
7
8

2
SC2D2U10V3KX-1GP NCP81253MNTBG-GP-U
2

D
D
D
D
074.81253.00E3 PU5003 Do Not Stuff

2
PG5021 PG5022

PWR_VCCSA_SNUB
SIS412DN-T1-GE3-GP PG5027

Do Not Stuff

Do Not Stuff
2 1

1
Do Not Stuff

G
S
S
S
PG5030
2 1

4
3
2
1
PW R_VCCSA_DRVL Do Not Stuff
PG5029

1
2 1
PC5031
DY Do Not Stuff Do Not Stuff

2
PG5031
2 1

Do Not Stuff
B B

Confirm with EE:

[46] PW R_VCCSA_CSP 22uF/0805 total 20pcs (DY 5 pcs)

[46] PW R_VCCSA_CSN

A Iris SKL UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
NCP81253MN_CPU_VCCSA
Size Document Number Rev
A3 Iris2 SKL-U A00
Date: W ednesday, September 09, 2015 Sheet 50 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = VDDQ

DCBATOUT +PWR_SRC_1D35V
Vinafix.com
PG5103
D D
2 1

Do Not Stuff
PG5104
2 1

Do Not Stuff
PG5105
2 1

Do Not Stuff
PG5106
2 1 1D35V_PWR 1D35V_S3
+PWR_SRC_1D35V
Do Not Stuff
PG5124
5V_S5 PG5108
2 1
2 1
Do Not Stuff PC5112
PC5109 PC5111 PC5114 Do Not Stuff
PG5109

2
Do Not Stuff
SC4D7U25V5KX-GP

SC4D7U25V5KX-GP
1

SC4D7U25V5KX-GP
3D3V_S0 PC5113 2 1
DY

1
PC5101 SCD1U50V3KX-GP Do Not Stuff

1
2

2
SC1U6D3V3KX-2GP PG5110

2
1

2 1
DY PR5104 PU5102
Do Not Stuff

5
6
7
8
Do Not Stuff PR4605_2
PG5111

D
D
D
D
2 1

SIS412DN-T1-GE3-GP
PU5101
2

20 12 PC5119
[40] 1D35V_VTT_PWRGD PGOOD V5IN Do Not Stuff
SCD1U50V3KX-GP Design Current=9.8A PG5112
PR5109 1 2 Do Not Stuff DDR_VTT_PG_CTRL_R 17 PR5105
[5] SM_PGCNTL S3 14.7A<OCP>17.64A 2 1

G
S
S
S
15 PWR_1D35V_VBST 1 2 1 2
PR5110 VBST
2 1 Do Not Stuff PWR_1D35V_EN 16 Do Not Stuff

4
3
2
1
[17,24,27,40,52,54] SIO_SLP_S3# S5 2D2R3-1-U-GP
DY PWR_1D35V_VREF PWR_1D35V_DRVH
PG5113
6 14
VREF DRVH
1

C 1D35V_PWR 2 1 C
PL5101
PR5103
Do Not Stuff
10KR2F-2-GP 13 PWR_1D35V_SW 1 2
SW PG5114
2 1
2

COIL-D68UH-5-GP

5
6
7
8

PC5121
PWR_1D35V_REFIN 8 11 PWR_1D35V_DRVL
30K1R2F-L-GP

REFIN DRVL Do Not Stuff

1
D
D
D
D

Do Not Stuff
2

Do Not Stuff
PG5115

1
PU5103 DY PC5123 PC5124 PC5125 PC5126 PC5127 PC5128
PC5103

PC5102

PC5120
10

PG5107
PGND
1

2 1

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

Do Not Stuff

Do Not Stuff

SC22U6D3V5MX-2GP
PWR_1D35V_MODE 19 SIS780DN-T1-GE3-GP DY PR5112 DY DY DY EC5101
MODE
1

PR5108 Do Not Stuff Do Not Stuff

2 PR5101

Do Not Stuff

2
12KR2F-L-GP

1
G
4 PG5116

2
1

SCD1U16V2KX-3GP
S
S
S
PWR_1D35V_TRIP 18 9 PWR_1D35V_VDDQS
SCD1U16V2KX-3GP
2

TRIP VDDQSNS 2 1
PR5102

PWR_1D35V_VDDQS
154KR2F-GP
SCD01U50V2KX-1GP

3
2
1
1

+0D675V_DDR_P TPS51216_PHS_SET
PR4601_1

2 Do Not Stuff
PWR_1D35V_VTTREF VLDOIN
PC5115

5 PG5117
VTTREF
1

1
3
0R0402-PAD

SC10U6D3V3MX-GP
2

VTT
1

PC5118 PC5122 2 1
DY
PR5106

1
Do Not Stuff
SCD22U10V2KX-1GP Do Not Stuff
PC5116

PC5117
1 Do Not Stuff
2

2
VTTSNS
21 DY
SCD1U16V2KX-3GP

PG5118
2

GND
4
2

2
VTTGND 2 1
7
GND
Do Not Stuff
TPS51716RUKR-GP
PG5119
74.51716.073 1D35V_PWR 2 1

Do Not Stuff
PG5120

1
+0D675V_DDR_P 0D675V_S0 PC5104
PG5101 DDR_VREF_S3 PR5107 2 1
SC1U6D3V3KX-2GP
2 1 1 2 PWR_1D35V_EN
Do Not Stuff

2
PR5111 [17,24,40] SIO_SLP_S4#
PG5123
Do Not Stuff PWR_1D35V_VTTREF 1 2 Do Not Stuff PC5106
2 1

1
PG5102 DY
2 1 Do Not Stuff
Do Not Stuff

Do Not Stuff
PG5121

2
Do Not Stuff
2 1

B Do Not Stuff B
PG5122
2 1

Do Not Stuff

State S3 S5 VDDR VTTREF VTT I/P cap: 10U 25V K0805 X5R/ 78.10622.51L
Inductor: CHIP CHOKE 0.68UH PCMC063T-R68 5~5.5mohm Isat =25Arms 68.R6810.20B
S0 Hi Hi On On On
O/P cap:CHIP CAP C 22U 6.3V M0805 X5R / 78.22610.51L
S3 Lo Hi On On Off(Hi-Z) H/S:SIS412 / 24mOhm/30mOhm@4.5Vgs / 84.00412.037
S4/S5 Lo Lo Off Off Off L/S:SIS780 / 14.5mOhm/17.5mOhm@4.5Vgs / 84.00780.037

A A
20140728 david

Iris SKL UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

MEM&MEMVTT
Size Document Number Rev
C Iris2 SKL-U A00
Date: Wednesday, September 09, 2015 Sheet 51 of 105
5 4 3 2 1
 A B C D E

VCCIO
Vinafix.com

1
4 C5203 4

K
Do Not Stuff DY D5201

2
DY Do Not Stuff

A
Cyntec. 2.5mm×2.0mmX1.2mm

PWR_VCCIO_EN_R
DCR: 59m Ohm
2015/05/13 DVT2 modify
VCCSTG and VCCIO Idc : 3 A , Isat : 3A
+VCCIO

+VCCIO(ICCMAX = 2.73A)
PU5201

2
Do Not Stuff

R5202
RISING TIME3 1 8
PW R_VCCIO_EN GATE VOUT#8
DY 2 EN VOUT#7 7
3 GND VOUT#6 6
4 5

1
5V_S5 VBIAS VOUT#5

VIN 9 1D0V_PW R
[17,24,27,40,51,54] SIO_SLP_S3# 1 R5201 2

1
SC10U10V5KX-2GP
Do Not Stuff M5938ARD1U-GP C5202 C5204

1
SC10U10V5KX-2GP

2
3 VIL > 0.7 V, VIH < 2 V C5201 DY 3
Rds(on) = 11 mΩ @ VDD = 4 V Do Not Stuff 074.05938.0093

2
Ids(max) 10 A

Power modify 2015/02/09

Design Current=1.8A
2.7A<OCP>3.24A
VCCPRIM_CORE
2.57A
2 2

1D0V_PW R
VCCPRIM_CORE
0.95 V PG5211
2 1

Do Not Stuff
PG5212
2 1

Do Not Stuff
PG5213
2 1

Do Not Stuff
PG5214
2 1

Do Not Stuff

Iris SKL UMA

1
Wistron Corporation 1

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

DCDC-0D975V_VCCIO
Size Document Number Rev
A3
Iris2 SKL-U A00
Date: W ednesday, September 09, 2015 Sheet 52 of 105

A B C D E
 5 4 3 2 1

Main Func = 1D0V

DCBATOUT PW R_DCBATOUT_1D0V 1D0V_PW R 1D0V_S5

PG5310 PG5305
2 1 2 1

Do Not Stuff
PG5309
Vinafix.com Do Not Stuff
PG5306
2 1 2 1
D D
Do Not Stuff Do Not Stuff
PG5308 PG5307
2 1 2 1
Do Not Stuff Do Not Stuff
PG5304 PG5303
2 1 2 1
Do Not Stuff Do Not Stuff
PG5301
2 1

Do Not Stuff
PG5302
2 1

Do Not Stuff

PW R_DCBATOUT_1D0V

Design Current =5.92A

PU5301
MAG. 7*7*3 8.88A<OCP<10.66A
DCR: 8.9mOhm
1

C PC5301 C
PC5310 3D3V_S5 Idc : 11 A , Isat : 22A
SC10U25V5KX-GP

PR5302
2

8 6 PW R_1D0V_BOOT 1 2 PW R_1D0V_BOOT_R 1 2 PC5305 PW R_1D0V_LX

IN BS
SC10U25V5KX-GP

SCD1U50V3KX-GP 1D0V_PW R

1
PH at Page40 0R0603-PAD
PR5304 DY
Do Not Stuff 10 PW R_1D0V_LX 1 2
LX PL5301
PR5310
2 68.R681A.10A
PW R_1D0V_PG PW R_1D0V_FB IND-D68UH-36-GP
[40] 1D0V_S5_PW RGD 1 2 2 PG FB 4

1
Do Not Stuff PC5302

PC5307

PC5308

PC5303
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
3D3V_S5

Do Not Stuff
1 2 PR5308 PW R_1D0V_ILMT 3 ILMT BYP 7 DY
0R0402-PAD PR5303

2
1 PW R_1D0V_BYP 1 2
EN

1
9 5 PW R_1D0V_LDO Do Not Stuff PR5301 PC5306
GND LDO

SC220P50V2KX-3GP
68KR2F-GP
R1

2
SY8208DQNC-GP-U

2
1

1
PR5309 74.08208.K73 PC5304 PC5309
1 DS3 2 PW R_1D0V_EN SC1U10V2KX-1GP

SC2D2U10V3KX-1GP
[17,24,40,54] SIO_SLP_SUS#

2
Do Not Stuff

1
1

PC5311 PR5305
R2
1

PR5311 PR5307 100KR2F-L1-GP

B [17,40,45,54] 3V_5V_POK NON
1 DS32 DY DY Do Not Stuff B
Do Not Stuff

0R2J-2-GP
2

2
2

Vo=0.6x(1+R1/R2)
=1.05 V

[#543016] VCCPrim_Core must ramp equal to or before VccPrim_1p0 supply

I/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L

Inductor: CHIP CHOKE 2.2U PCMC063T-2R2MN 18~20mohm Isat =14Arms 68.2R210.20B
O/P cap: CHIP CAP EL 330U 2.5V M6.3*4.4 3.5Arms Chemi-con/ 79.3371V.6CL
H/S:SIS412DN-T1-GE3 / 24mOhm/30mOhm@4.5Vgs / 84.00412.037
L/S:SIS412DN-T1-GE3 / 24mOhm/30mOhm@4.5Vgs / 84.00412.037 Iris SKL UMA
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
DCDC-V1D00A
Size Document Number Rev
A3 Iris2 SKL-U A00
Date: W ednesday, September 09, 2015 Sheet 53 of 105

5 4 3 2 1
 5 4 3 2 1

Main Func = 1D5V

S-1339D15-M5001 for 1D5V_S0

3D3V_S5
Vinafix.com
D D

SC1U10V2KX-1GP
PC5408
2
Design Current = 16mA

PU5402 1D5V_PW R 1D5V_S0

PG5404
1 IN OUT 5 1 2
2 GND
[17,24,27,40,51,52] SIO_SLP_S3# PR5405 1 2PW R_1D5V_EN 3 4 Do Not Stuff
Do Not Stuff EN NC#4
PC5407

PC5409
SC1U10V2KX-1GP
DY TLV70215DBVR-GP
74.70215.03F

Do Not Stuff
2

2
2rd = 74.01339.B3F

C C

APL5930 for 1D8V_S5

5V_S5 3D3V_S5

Design Current = 665mA

3D3V_S5 PC5401
PC5403
SC1U6D3V3KX-2GP

SC10U6D3V3MX-GP
1

1
1

PR5402
Do Not Stuff 1D8V_PW R
2

2
PH at Page40
DY PU5401
2

5 1D8V_PW R 1D8V_S5
VIN#5
6 VCNTL VOUT#4 4 PG5405
[40] 1D8V_S5_PW ROK PR5408 1 2 Do Not Stuff PW R_1D8V_POK 7 3
PW R_1D8V_EN POK VOUT#3 1 2
8 EN FB 2
B B
PR5406 9 VIN#9 GND 1
Do Not Stuff
[17,40,45,53] 3V_5V_POK 1 2 PR5403 PC5405 PG5406
Do Not Stuff
1

1
NON DS3 APL5930KAI-TRG-GP PC5404 PC5402
PC5406

16K5R2F-2-GP

SC68P50V2JN-1GP
0R2J-2-GP
PR5401 DY DY 74.05930.03D DY 1 2

Do Not Stuff

SC22U6D3V5MX-2GP
Do Not Stuff
2ND = 74.G9731.03D
2

2
Do Not Stuff

1.8V_RUN_FB
[#544669 Rev0.53] PG5407
2

2
PR5407
1 2
[17,24,40,53] SIO_SLP_SUS# 1 2
Do Not Stuff
DS3
Do Not Stuff

1
PR5404
13K3R2F-L1-GP

2 Vout=0.8V*(R1+R2)/R2

A Iris SKL UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

LDO-V1D5V&V1D8V
Size Document Number Rev
A3 Iris2 SKL-U A00
Date: W ednesday, September 09, 2015 Sheet 54 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = LCD LCDVDD_LCD LCDVDD INVERTER POWER Main Func = CAM
R5523
1 2 DCBATOUT DCBATOUT_LCD
LCD1 0R5J-5-GP
41 EE note: Never change R5211 to short pad after MP 800mA
F5503
1 1 2

2 LCDVDD_LCD R5518 POLYSW-1D1A24V-GP-U C5515

DCBATOUT_LCD

SC1KP50V2KX-1GP
3 DBC_EN_R 1 2 C5535
Trace width = 80mil DBC_PANEL_EN [20]
4
69.50007.A31 DY EE note: Never change R5229 to short pad after MP

C5538
5 100R2J-2-GP
Reserved for one time fuse: 69.43001.201

2
1

1
EC5504 Do Not Stuff

Vinafix.com
6
C5536 3D3V_S0 3D3V_CAMERA_S0
7
DBC_EN_R
DY 3D3V_S0
8

SC1U10V2KX-1GP
2

2
SCD1U16V2KX-3GP

Do Not Stuff
9 EDP_HPD_CONN
LCD_TST_C R5532
10
D 11 eDP_AUX_CON_P 1 2 D

1
12 eDP_AUX_CON_N
13 LCD For ESD R5521 RN5504 0R5J-5-GP

1
14 eDP_TX_CON_N0 10KR2J-3-GP DMIC_DATA_EDP 2 3 DMIC_DATA [27]
15 eDP_TX_CON_P0 DMIC_CLK_EDP 1 4 DMIC_CLK [27] EC5503 DY C5539
16 SC4D7U6D3V3KX-GP
R5525

2
Do Not Stuff
17 eDP_TX_CON_N1 SRN33J-5-GP-U

1
eDP_TX_CON_P1 PANEL_SIZE_ID_CONN PANEL_SIZE_ID
18 1 DY 2 PANEL_SIZE_ID [20]

EC5501

EC5502
19 DY DY

Do Not Stuff

Do Not Stuff
20 LCD_BRIGHTNESS Do Not Stuff For AUDIO Grade B or C selection.

2
1
21 BLON_OUT_C 20140815 david
22 PANEL_SIZE_ID_CONN R5526
23
24 PU/PD FOR AUX CHANNEL DY Do Not Stuff
Layout Note: Reduce the stubs.
25

2
26 MIC_GND SKL PDG (#543016):
27 DMIC_CLK_EDP Recommends having a pull-up resistor of 100 kΩ for AUXN
28 DMIC_DATA_EDP
and a pull-down resistor of 100 kΩ for AUXP
29
30 USB_CAMERA_PN4 Camera between the AC capacitor and the connector,
31 USB_CAMERA_PP4 to assist source detection by the sink device.
32 3D3V_CAMERA_S0
33
34 USB_CON_PN6 eDP_AUX_CON_P R5528 1 DY 2 Do Not Stuff
35 USB_CON_PP6
eDP_AUX_CON_N R5529 1 2 Do Not Stuff
36
TP_RS
DY 3D3V_S0 TR5501
37
38 TP_RESET Touch Panel USB_CAMERA_PN4 3 4 USB_CPU_PN4 [16]
39
40 USB_CAMERA_PP4 2 1 USB_CPU_PP4 [16]
TPAN_VDD
Layout Note: RN5502
42 1 8 BKLT_CTRL
Colse to LCD1. 2 7 BLON_OUT_C FILTER-4P-137-GP-U
3 6 EDP_HPD 68.01012.20B
4 5
ACES-CON40-18-GP 1 R5531 2 R5524 1 DY 2 Do Not Stuff
A00 modify 2015/09/08 (EMI suggest)
Do Not Stuff SRN100KJ-5-GP
20.K0678.040
D5503
RN5503 1 eDP_BKLT_CTRL
C MIC_GND LCD_TST_C 1 8 C
LCD_TST_R [24]
LCD_BRIGHTNESS 2 7 BKLT_CTRL 3
A00 modify 2015/06/05 BLON_OUT_C 3 6 PANEL_BKEN_EC [24]
EDP_HPD_CONN 4 5 2
EDP_HPD [8] EC_BRIGHTNESS [24]
SRN100J-4-GP
BAT54C-7-F-3-GP EC (BIST MODE)
75.00054.E7D
3D3V_S0 5V_S0 2nd = 83.R2003.W81
3rd = 75.00054.A7D
4th = 83.R2003.V81
Main Func = TS

1
C5508 1 2 SCD1U16V2KX-3GP eDP_TX_CON_N0
[8] eDP_TX_CPU_N0 TPAN_VDD

R5522
Do Not Stuff
[8] eDP_TX_CPU_P0 C5532 1 2 SCD1U16V2KX-3GP eDP_TX_CON_P0 DY R5527
Do Not Stuff
Touch Do Not Stuff
Touch Panel

2
C5534 1 2 SCD1U16V2KX-3GP eDP_TX_CON_N1 F5502 Do Not Stuff
[8] eDP_TX_CPU_N1
C5537 2 SCD1U16V2KX-3GP eDP_TX_CON_P1
[8] eDP_TX_CPU_P1 1 1 DY 2

R5537
TPAN_VDD_F R5520 2 1 Do Not Stuff TP_RS 1 2 TOUCH_PANEL_INTR# [4,24]

1
[8] eDP_AUX_CPU_N C5533 1 2 SCD1U16V2KX-3GP eDP_AUX_CON_N Touch Touch Do Not Stuff

1
eDP_AUX_CON_P

C5543
[8] eDP_AUX_CPU_P C5531 1 2 SCD1U16V2KX-3GP DY DY

Do Not Stuff
C5541

2
Brightness EE note: Never change R5232 to short pad after MP Do Not Stuff

2
Reserved for one time fuse: 69.43001.201 2015/05/20 Iris SKL no support Touch panel function
1 R5530 2 eDP_BKLT_CTRL
[8] L_BKLT_CTRL
R5538
Do Not Stuff
TP_RESET 1 Touch
2 PLT_RST# [17,24,31,40,61,68,76]

LCDVDD

1
DY Do Not Stuff
2015/05/20 Iris SKL no support Touch panel function C5540
Do Not Stuff
D5502

2
[8] EDP_VDD_EN 1

3 LCDVDD_EN
USB_CON_PN6 1 R5535 2 USB_CPU_PN6 [16]
[24] LCD_TST_EN 2
2

B 3D3V_S0 Do Not Stuff B

R5506
BAT54C-7-F-3-GP 100KR2J-1-GP
75.00054.E7D U5501
2nd = 83.R2003.W81 LCDVDD
1

1 5
EN VIN#5
3rd = 75.00054.A7D 2
GND
3 4
VOUT VIN#4
1

4th = 83.R2003.V81 C5505 USB_CON_PP6 1 R5536 2 USB_CPU_PP6 [16]

RT9724GB-GP SC4D7U6D3V3KX-GP
Do Not Stuff
2

Layout Note: 74.09724.09F

A00 modify 2015/06/05
Trace width = 80mil

A A

Iris SKL UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
LCD&CAM&DMC&Touch
Size Document Number Rev
A2
Iris2 SKL-U A00
Date: Wednesday, September 09, 2015 Sheet 55 of 105
5 4 3 2 1
 5 4 3 2 1

5V_HDMI_CRT_S0 5V_S0

R5409

Vinafix.com
1 2

Do Not Stuff

For DIODE in case of leakage from HDMI1

D 5V_HDMI_CRT_S0_R D
D5501
F5501
1 2 K CRT A

POLYSW-1D1A6V-9-GP-U Do Not Stuff

Do Not Stuff
69.48001.081
2ND = 69.50011.081
3RD = 69.50013.101

CRT RGB
CRT H/VSYNC
X00_0425 CRT SMBUS
CRT_DDCDATA_CON
CRT_HSYNC_CON
CRT_VSYNC_CON

C5513
Do Not Stuff
CRT_DDCCLK_CON

C5516
Do Not Stuff

C5507
Do Not Stuff
L5503

1
C5511
DP_CRT_R 1 CRT 2 Do Not Stuff CRT_R CRT_R [57] DY DY DY DY Do Not Stuff
Do Not Stuff

2
2nd = 68.00245.011

L5501
X00_0425
DP_CRT_G 2 Do Not Stuff CRT_G
1 CRT CRT_G [57]
Do Not Stuff
2nd = 68.00245.011
DP_CRT_HSYNC_CON R5511 2 Do Not Stuff
L5502
1 CRT CRT_HSYNC_CON [57]
DP_CRT_VSYNC_CON R5507 2 Do Not Stuff
DP_CRT_B CRT_B
1 CRT CRT_VSYNC_CON [57]
1 CRT 2 Do Not Stuff CRT_B [57] 5V_HDMI_CRT_S0
1 R5501

1 R5513

1 R5514

C Do Not Stuff C

C5506
Do Not Stuff

C5512
Do Not Stuff

C5509
Do Not Stuff

C5514
Do Not Stuff

C5510
Do Not Stuff

C5518
Do Not Stuff
2nd = 68.00245.011
1

1
CRT CRT CRT CRT CRT CRT
CRT
2

2
CRT CRT

4
3
Do Not Stuff 2

Do Not Stuff 2

Do Not Stuff 2

RN5501 CRT
Do Not Stuff

1
2
CRT_DDCDATA_CON

CRT_DDCCLK_CON

3D3V_S0 AVCC33

R5504 Layout note: U5502

1 CRT 2 All cap need close to chip AVCC33 CRT_PCH_HPD CRT_PCH_HPD R5517
2 CRT
1 24 1 1 CRT 2 Do Not Stuff CPU_DP1_HPD [8,57]
Do Not Stuff C5517 AVCC_33 HPD
2

Do Not Stuff C5523 VCCK_12

2 CRT
1 25
AVCC_12 SMB_SCL
2 PCH_SMBCLK [12,13,18,65,99]

1
CRT Do Not Stuff Do Not Stuff C5503 3
3D3V_S0 SMB_SDA PCH_SMBDATA [12,13,18,65,99]
2 CRT
1 5 R5510
1

Do Not Stuff 3D3V_S0 DVCC_33

2 1C5520
CRT 20 4 CRT_DDCCLK_CON [57] CRTDo Not Stuff
Do Not Stuff C5522 DVCC_33 VGA_SCL
6 CRT_DDCDATA_CON [57]
VCCK_12 VGA_SDA
2 CRT
1 19

2
Do Not Stuff VCCK_12
2 1C5501
CRT
Do Not Stuff 2 1C5504
CRT VDD_DAC_33 9 7 DP_CRT_VSYNC_CON
Do Not Stuff VDD_DAC_33 VSYNC DP_CRT_HSYNC_CON
2 1C5524
CRT 8
3D3V_S0 VDD_DAC_33 Do Not Stuff C5502 HSYNC
LDO_EN 21 15 DP_CRT_R
LDO_EN RED_P
R5503 16
C5527 1CRT 2 Do Not Stuff PCH_DPC_AUXP_U RED_N
1 CRT 2
[8] PCH_DPB_AUXP
[8] PCH_DPB_AUXN
C5528 1CRT 2 Do Not Stuff PCH_DPC_AUXN_U
26
27
AUX_P
AUX_N GREEN_P
12 DP_CRT_G X00_0429
CRT_R
C5529 1CRT 2 Do Not Stuff PCH_DPC_P0_U
CRT GREEN_N
13
CRT_G
1 AFTP5501 Do Not Stuff
[8,57] HDMI_CRT_P0 29 1 AFTP5502 Do Not Stuff
LANE0P
2

Do Not Stuff C5521 [8,57] HDMI_CRT_N0 C5526 1CRT 2 Do Not Stuff PCH_DPC_N0_U 30 10 DP_CRT_B CRT_B 1
LANE0N BLUE_P AFTP5503 Do Not Stuff
B Do Not Stuff 5V_HDMI_CRT_S0_R B
CRT C5530 1CRT 2 Do Not Stuff PCH_DPC_P1_U BLUE_N
11
CRT_DDCDATA_CON
1 AFTP5504 Do Not Stuff
[8,57] HDMI_CRT_P1 31 1 AFTP5505 Do Not Stuff
1

C5525 1CRT 2 Do Not Stuff PCH_DPC_N1_U LANE1P POL1_SDA CRT_DDCCLK_CON

[8,57] HDMI_CRT_N1 32 22 1 AFTP5506 Do Not Stuff
LANE1N POL1_SDA POL2_SCL CRT_VSYNC_CON
23 1 AFTP5507 Do Not Stuff
POL2_SCL CRT_HSYNC_CON 1 AFTP5508 Do Not Stuff
CLK_DP2VGA
X00_0505 [18] CLK_DP2VGA
CLK_XO
17
18
XI/CKIN
XO GND_DAC
14

RRX 28 33
RRX GND
1

R5519 Do Not Stuff

DY Do Not Stuff
1

R5505 Do Not Stuff

2

CRTDo Not Stuff

2

3D3V_S0 3D3V_S0 3D3V_S0 3D3V_S0

2

R5509 R5515 R5502 U5504

Do Not Stuff DY Do Not Stuff CRT Do Not Stuff CRT
1 8
A0 VCC
2 DY 7
1

A1 WP POL2_SCL
A X00_0428 POL1_SDA POL2_SCL LDO_EN
3
4
A2
VSS
SCL
SDA
6
5 POL1_SDA A
2

R5508 R5516 R5512 Do Not Stuff

Do Not Stuff CRT Do Not Stuff DY Do Not Stuff DY Do Not Stuff
Iris SKL UMA
1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CRT
Size Document Number Rev
A2
Iris2 SKL-U A00
Date: Wednesday, September 09, 2015 Sheet 56 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = HDMI

HDMI_CLK#_R 1 R5401 2 HDMI_CLK#_R_C HDMI_DATA0#_R 1 R5403 2 HDMI_DATA0#_R_C

Do Not Stuff Do Not Stuff

HDMI
Vinafix.com

1
C5402 1 2 SCD1U16V2KX-3GP HDMI_CLK#_R
[8] HDMI_CLK#

1
C5403 1 2HDMI SCD1U16V2KX-3GP HDMI_CLK_R R5416
[8] HDMI_CLK R5414 150R2J-L1-GP-U HDMI
D C5404 1 2HDMI SCD1U16V2KX-3GP HDMI_DATA0#_R 150R2J-L1-GP-U HDMI D
[8] HDMI_DATA0# C5405 SCD1U16V2KX-3GP HDMI_DATA0_R
1 2HDMI

2
[8] HDMI_DATA0

2
A00 modify 2015/06/05
HDMI_DATA1# C5409 1 2HDMI SCD1U16V2KX-3GP HDMI_DATA1#_R
HDMI_DATA1 C5406 1 2HDMI SCD1U16V2KX-3GP HDMI_DATA1_R

HDMI_DATA2# C5407 1 2HDMI SCD1U16V2KX-3GP HDMI_DATA2#_R HDMI_CLK_R 1 R5402 2 HDMI_CLK_R_C HDMI_DATA0_R 1 R5404 2 HDMI_DATA0_R_C
HDMI_DATA2 C5408 1 2HDMI SCD1U16V2KX-3GP HDMI_DATA2_R
Do Not Stuff Do Not Stuff

8
7
6
5

8
7
6
5
HDMI_DATA2#_R 1 R5405 2 HDMI_DATA2#_R_C HDMI_DATA1#_R 1 R5407 2 HDMI_DATA1#_R_C
RN5402 RN5403
SRN470J-3-GP HDMI HDMI SRN470J-3-GP Do Not Stuff Do Not Stuff

1
2
3
4

1
2
3
4

1
HDMI_PLL_GND

1
R5417
R5415 150R2J-L1-GP-U HDMI

2
150R2J-L1-GP-U HDMI
R5418

2
DY Do Not Stuff
D

2
Q5403 A00 modify 2015/06/05
C 2N7002K-2-GP 1 C

HDMI 84.2N702.J31
2ND = 84.2N702.031 HDMI_DATA2_R 1 R5406 2 HDMI_DATA2_R_C HDMI_DATA1_R 1 R5408 2 HDMI_DATA1_R_C
3rd = 84.07002.I31 Do Not Stuff
Do Not Stuff
4th = 84.2N702.W31
G

5V_S0 HDMI1
PTH10 PTH9
20140801 david PTH12 PTH7
PTH11 NP1
R5413 PTH8
HDMI_DATA2_R_C HP1 6
1 DY 2
HDMI_DATA2#_R_C
HP2 11
HP3 1 CRT_R [56]
HDMI_DATA1_R_C HP4
Do Not Stuff
HP5 7
HDMI_DATA1#_R_C HP6 12 CRT_DDCDATA_CON [56]
HDMI_DATA0_R_C HP7 2 CRT_G [56]
HP8
RN5701 HDMI_DATA0#_R_C HP9 8 5V_HDMI_CRT_S0_R
1 4 HDMI_DATA1# HDMI_CLK_R_C HP10 13 CRT_HSYNC_CON [56]
[8,56] HDMI_CRT_N1 HDMI_DATA1
[8,56] HDMI_CRT_P1 2 HDMI 3 HP11 3 CRT_B [56]
HDMI_CLK#_R_C HP12 HDMI_Manual:22.10296.981
SRN0J-6-GP HP13 9
HP14 14 CRT_VSYNC_CON [56]

1
RN5702 DDC_CLK_HDMI HP15 4 C5542

Do Not Stuff
1 4 HDMI_DATA2# 5V_HDMI_CRT_S0_R DDC_DATA_HDMI HP16 DY
[8,56] HDMI_CRT_N0 HDMI_DATA2
2 HDMI 3 HP17 10

2
[8,56] HDMI_CRT_P0
HP18 15 CRT_DDCCLK_CON [56]
B SRN0J-6-GP B
HP19 5
PTH3

1
C5401 PTH5 NP2
5V_S0 HDMI PTH6 PTH1

SCD1U16V2KX-3GP
PTH4 PTH2

2
3

SKT-HDMI23-92-GP

HPD_HDMI_CON
D5401
BAW 56-9-GP
HDMI 3D3V_S0
DDC_CLK_PH1 2

DDC_DATA_PH2 1

2015/1/14 mofidy 84.T3904.H11 R5411

CHDMI 150KR2F-L-GP HDMI / VGA CONN
Q5401 B HDMI_HPD_B 2 1
HDMI HDMI1 22.10296.981 / 22.10296.961/22.10296.A21

1
LMBT3904LT1G-GP
E

R5410
[8,56] CPU_DP1_HPD 1 R5420 2 HDMI_HPD_E DY Do Not Stuff
4
3

3D3V_S0 Do Not Stuff

2
R5412
HDMI RN5401 10KR2J-3-GP HDMI
SRN2K2J-1-GP
Q5402
2
1
2

4 3 DDC_CLK_HDMI
[8] CPU_DP1_CTRL_CLK Iris SKL UMA
A A
5 2
HDMI Wistron Corporation
6 1
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2N7002KDW -GP
[8] CPU_DP1_CTRL_DATA
Title
DDC_DATA_HDMI
HDMI
84.2N702.A3F Size Document Number Rev
2nd = 84.2N702.E3F A3 A00
3rd = 75.00601.07C
Iris2 SKL-U
4th = 84.DMN66.03F Date: W ednesday, September 09, 2015 Sheet 57 of 105

5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C
(Blanking) C

B B

A Iris SKL UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
(Reserved)
Size Document Number Rev
A3
Iris2 SKL-U A00
Date: Tuesday, May 26, 2015 Sheet 58 of 105
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C
(Blanking) C

B B

A Iris SKL UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
(Reserved)
Size Document Number Rev
A3
Iris2 SKL-U A00
Date: Tuesday, May 26, 2015 Sheet 59 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = HDD

SATA HDD Connector
5V_HDD_S0
E
5V_S0
R6001
Vinafix.com
[16] HDD_DEVSLP 1 R6002 2 HDD_DEVSLP_R E

Do Not Stuff
80 mils 1 2 Reserved for M15 EE Implementation. HDD1

Do Not Stuff 14
1

1
C6002 C6001 C6008 C6007 12
DY DY [16] SATA_TX_CPU_P0 SCD22U10V2KX-1GP 2 1 C6005 SATA_TX_CON_P0 11
Do Not Stuff

Do Not Stuff

SC10U10V5KX-2GP

SCD1U16V2KX-3GP
[16] SATA_TX_CPU_N0 SCD22U10V2KX-1GP 2 1 C6006 SATA_TX_CON_N0 10
2

2
9
SCD22U10V2KX-1GP 1 2 C6004 SATA_RX_CON_N0 8
[16] SATA_RX_CPU_N0 SCD22U10V2KX-1GP
[16] SATA_RX_CPU_P0 1 2 C6003 SATA_RX_CON_P0 7
6
HDD_DEVSLP_R 5
0929 modify capacitors value 4
5V_HDD_S0 3
2

1
Close to HDD1 Layout Note: 13
Place near HDD1 STAR-CON12-1-GP

U6001
020.K0125.0012
D D
0929 modify P/N
SATA_TX_CON_P0 1 10 SATA_TX_CON_P0
SATA_TX_CON_N0 LINE_1 NC#10 SATA_TX_CON_N0
2 LINE_2 NC#9 9

SATA_RX_CON_N0
3 GND DY GND 8
SATA_RX_CON_N0
4 LINE_3 NC#7 7
SATA_RX_CON_P0 5 6 SATA_RX_CON_P0
LINE_4 NC#6 5V_HDD_S0 1
AFTP5601 Do Not Stuff
Do Not Stuff

Do Not Stuff
Swap based on the swap report.

Main Func = ODD

3D3V_S0

C R6004
SATA Zero Power ODD C
ZPODD
1 2 SATA_ODD_PW RGT R6007

Do Not Stuff 1 2
ODD
ODD Connector 5V_S0 U6002
Do Not Stuff ODD_PW R_5V

2 6
2.5A 100 mil
ODD1 IN#2 OUT#6
3 IN#3 OUT#7 7
22 OUT#8 8
20 C6012 C6009

1
19 ZPODD [20] SATA_ODD_PW RGT 4 EN/EN#
18
SATA_ODD_DA#_C
DY GND 1
17 1 R6006 2 Do Not Stuff SATA_ODD_DA# [16] Do Not Stuff 5 9 Do Not Stuff

2
FLT# GND
16
15 ODD_PW R_5V
14 R6003
Current limit
13 Do Not Stuff ZPODD
12 1 DY 2
Active High
Do Not Stuff Do Not Stuff
ODD /
11
ZPODD
10
typ =>2.5A 2nd = 74.02311.079
B
9
74.02001.079 is OBS B

8
7
SATA_ODD_PRSNT# [16]
ZPODD Will use 74.06288.079
SATA_RX_CON_P1 C6011 1 2 Do Not Stuff ODD / ZPODD
6
5 SATA_RX_CON_N1 C6010 1 2 Do Not Stuff ODD / ZPODD
SATA_RX_CPU_P1 [16]
SATA_RX_CPU_N1 [16]
but 74.06288.079 is also OBS
4
SATA_TX_CON_N1 C6013 1 2 Do Not Stuff
we will use 074.06288.0079.
3
SATA_TX_CON_P1 C6014 1
ODD / ZPODD SATA_TX_CPU_N1 [16]
2 2 Do Not Stuff SATA_TX_CPU_P1 [16]
ODD / ZPODD
1
21

Do Not Stuff
Do Not Stuff

Iris SKL UMA

A
Wistron Corporation A

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

SATA IF_HDD/ODD
Size Document Number Rev
A3
Iris2 SKL-U A00
Date: W ednesday, September 09, 2015 Sheet 60 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = WLAN

3D3V_S0
3D3V_W LAN_S0
USB_CON_PP7 1 R6111 2
Rc
R6117
Vinafix.com Do Not Stuff
USB_CPU_PP7 [16]

1.1A
D 1 2 D

Do Not Stuff
C6101
Do Not Stuff

C6105

C6102
Do Not Stuff

C6106

C6104
SCD1U16V2KX-3GP

C6103
SCD1U16V2KX-3GP
A00 modify 2015/06/05
1

1
Do Not Stuff

SC10U6D3V3MX-GP
DY DY DY
2

2
Note:pin 76 and pin 77 need contact to GND
USB_CON_PN7 1 R6110 2 USB_CPU_PN7 [16]
W LAN1 Do Not Stuff

NP2 NP2 NP1 NP1

3D3V_W LAN_S0
76 76 77 77
74 3_3V GND 75
72 3_3V REFCLKN1 73
70 PEWAKE1#_0/3_3V REFCLKP1 71
68 CLKREQ1#_0/3_3V GND 69
66 PERST1#_0/3_3V PETN1 67
64 RESERVED#64 PETP1 65
62 ALERT_0/3_3 GND 63
60 I2C_CLK_0/3_3 PERN1 61
TP6103 1 Do Not Stuff E51_RX2 58 59
R6114 1 I2C_DATA_0/3_3 PERP1
[15] W IFI_RF_EN 2 Do Not Stuff W LAN_DISABLE#1 56 W_DISABLE#1_0/3_3V GND 57 Do Not Stuff
[20] BLUETOOTH_EN R6113 1 2 Do Not Stuff BLUETOOTH_EN_NGFF 54 55 W LAN_W AKE 1 TP6101
R6116 1 RESERVED/W_DISABLE#2_0/3_3V PEWAKE0#_0/3_3V
C
[17,24,31,40,55,68,76] PLT_RST# 2 Do Not Stuff PLT_RST_NGFF# 52 PERST0#_0/3_3V 53 W LAN_CLKREQ_W LAN# 1 R6112 2 Do Not Stuff CLKREQ_PCIE#1 [18]
C
50
3.3V CLKREQ0#_0/3_3V 51
SUSCLK/32KHZ_0/3_3V GND
48 COEX1_0/1_8V REFCLKN0 49 PEG_CLK1_CPU# [18]
Do Not Stuff TP6102 1 E51_RX1 46 47 PEG_CLK1_CPU [18]
E51_TX1 COEX2_0/1_8V REFCLKP0
44 COEX3_0/1_8V GND 45
R6109 1 DY 2 Do Not Stuff CL_CLK_R 42 43 EMI request
[18] CL_CLK CLINK_CLK PETN0 PCIE_RX_CPU_N5 [16]
R6119 1 DY 2 Do Not Stuff CL_DATA_R 40 41
[18] CL_DATA CLINK_DATA PETP0 PCIE_RX_CPU_P5 [16]
R6108 1 DY 2 Do Not Stuff CL_RST#_R 38 39
[18] CL_RST# CLINK_RESET GND

PEG_CLK1_CPU#

PEG_CLK1_CPU
36 GND PERN0 37 PCIE_TX_CON_N5 [16]
3160 does not support C-Link 34 DP_ML0P PERP0 35 PCIE_TX_CON_P5 [16]
32 DP_ML0N GND 33
30 GND DP_HPD_0/3_3V 31
28 DP_ML1P GND 29
26 DP_ML1N Module Key DP_ML2P 27
24 GND DP_ML2N 25
22 DP_AUXP GND 23
20 DP_AUXN DP_ML3P 21
18 GND DP_ML3N 19
16 LED#2 DP_MLDIR 17

EC6102
Do Not Stuff

EC6103
Do Not Stuff
1

1
3D3V_W LAN_S0
6 LED#1 GND 7
USB_CON_PN7
DY DY
4 5

2
3_3V USB_D- USB_CON_PP7
2 3_3V USB_D+ 3
GND 1
NGFF_KEY_A 75P

SKT-MINI67P-3-GP-U1
B B
62.10043.K51

Support: Intel Dual Band Wireless-AC 3160

Reserved for NGFF Debug Card
Do Not Stuff AFTP5801 1 3D3V_W LAN_S0
Do Not Stuff AFTP5802 1 W LAN_CLKREQ_W LAN#
3D3V_S5 3D3V_W LAN_S0 1 W LAN_DISABLE#1
Do Not Stuff AFTP5803
Rb Do Not Stuff AFTP5804 1 BLUETOOTH_EN_NGFF
Do Not Stuff AFTP5805 1 PLT_RST_NGFF#
1 R6118 2 Do Not Stuff AFTP5806 1 USB_CON_PN7
DY Do Not Stuff Do Not Stuff AFTP5807 1 USB_CON_PP7

[24] HOST_DEBUG_TX 1 R6115 2 E51_TX1

DY Do Not Stuff
Ra

EE Note:
For NFGG Debug Card:
Stuff Ra, Rb; DY Rc.
A Iris SKL UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

NGFF_WLAN CONN
Size Document Number Rev
A3
Iris2 SKL-U A00
Date: W ednesday, September 09, 2015 Sheet 61 of 105
5 4 3 2 1
 A B C D E

Vinafix.com
4 4

3
(Blanking) 3

2 2

Iris SKL UMA

1
Wistron Corporation 1
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A4
Iris2 SKL-U A00
Date: Tuesday, May 26, 2015 Sheet 62 of 105
A B C D E
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

Iris SKL UMA

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
(Reserved)
Size Document Number Rev
A4 A00
Iris2 SKL-U
Date: Tuesday, May 26, 2015 Sheet 63 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = Power BTN

Power button

1
G6401 G6402
PW R1
Do Not Stuff Do Not Stuff
SRN100J-4-GP 6
1 8 3D3V_S5 1 AFTP6103

2
2 7 4
[24] LID_CL_SIO#
[24] KBC_PW RBTN#
3
4
6
5
Vinafix.com LID_CLOSE#_C 3
KBC_PW RBTN#_C 2
LID_CLOSE#_C 1 AFTP6104

Iris2

1
D
RN6401 1 D
3D3V_S5
DY ED6401 5

Do Not Stuff
AFTP6101 1 DY EC6401 Do Not Stuff
ETY-CON4-34-GP

2
Do Not Stuff
C6401 20.K0465.004

1
1 AFTP6102
DY
2nd = 20.K0422.004

2
20140812 DAVID 3RD = 20.K0382.004
For EMI Reserved
LID_CLOSE#_C EC6105 1DY 2 Do Not Stuff

20141222 Alden

Main Func = Battery LED

5V_S5
C C
Low actived from KBC GPIO Q6403
R2
R6405 E R6407
[24] CHG_AMBER_LED# 1 2CHG_AMBER_LED_R# B R1
C AMBER_LED_BAT 1 2 BAT_AMBER
Do Not Stuff
DDTA144VCA-7-F-GP 470R2J-2-GP
Battery LED1(AMBER_LED)

1
DY EC6402 LED1
84.00144.N11

Do Not Stuff
2
1 + Yellow

- 3
White
2 +
5V_S5
Low actived from KBC GPIO Q6404
LED-YW -5-GP
R2
R6404 E 083.1212A.0070
R6406
[24] BATT_W HITE_LED# 1 2BATT_W HITE_LED_R# B R1
C W HITE_LED_BAT 1 2 BAT_W HITE
Do Not Stuff
DDTA144VCA-7-F-GP 330R2J-3-GP
Battery LED2 (WHITE_LED)

1
DY EC6403
84.00144.N11

Do Not Stuff
2
B B

Main Func = HDD LED

Q6105
[16,24] SATA_LED#_R S

D BATT_W HITE_LED_R#
R6402
SATA HDD LED 1 2 [24] SATA_LED# G HWHDLED
SATA LED
LOW actived from PCH GPIO Do Not Stuff 5V_S0 SATA LED 2N7002K-2-GP
84.2N702.J31
3D3V_S0 2ND = 084.27002.0A31
Q6401
[16,24] SATA_LED#_R S DY HDLED1 3rd = 84.07002.I31
R2 R6120
E R6401
3

3D3V_S0 SATA_LED#_B SATA_LED#

D B
SATA LED
R1
C SATA_LED 1 2 SATA_LED_R
1A 2K
1
HWHDLED
2
X01_0813
G SATA LED 10KR2J-3-GP
Do Not Stuff
Do Not Stuff Do Not Stuff
A Do Not Stuff Iris SKL UMA A
1

Q6402 Do Not Stuff 2nd = 83.00110.R70

Do Not Stuff EC6404 DY 3rd = 083.11204.0070
Do Not Stuff

Wistron Corporation
2

Do Not Stuff R1=R2=4.7K 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
2ND = 84.2N702.031 Taipei Hsien 221, Taiwan, R.O.C.

3rd = 84.07002.I31 Title

LED Board&Power Button

Size Document Number Rev
A3
Iris2 SKL-U A00
Date: W ednesday, September 09, 2015 Sheet 64 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = KB Main Func = TPAD

3D3V_S0 3D3V_S5
TP_VDD

Internal Keyboard Connector

2
TP_VDD Discharge Circuit

1
Do Not Stuff R6521
R6520 DY R6522
Do Not Stuff
AFTP6202 KB1 Do Not Stuff
1 DY

1
32 Q6505

1
TP_ON#_GATE

3D3V_TP_S5_R
30 G

2
[20] KB_DET# AFTP6221 KSI7
1 29
AFTP6222 KSI6 C6503 Q6205_Q

Vinafix.com DY
1 28 D
AFTP6230 1 KSI4 27 SCD1U16V2KX-3GP
AFTP6218 1 KSI2 26 1 2 TP_VDD S
R6509
AFTP6214 KSI5
AFTP6227
1
1 KSI1
25
24 1 2 TP_LOCK# Do Not Stuff X01_0821
D AFTP6234 1 KSI3 23 1KR2J-1-GP Do Not Stuff D
[24] KSI[0..7]

S
AFTP6228 1 KSI0 22 R6516 2ND = 84.2N702.031
KSO5 TP_EN# 100KR2J-1-GP
AFTP6215 1 21 [24] TP_EN# 1 2 TP_ON#_GATE G 3rd = 84.07002.I31
AFTP6224 1 KSO4 20
G
4th = 84.2N702.W31
[24] KSO[0..16]
AFTP6213 1 KSO7 19
AFTP6223 1 KSO6 18 Q6504 D
AFTP6231 1 KSO8 17 TP_VDD DMP2130L-7-GP

D
AFTP6208 1 KSO3 16 84.02130.031
AFTP6206 1 KSO1 15 2ND = 84.03413.A31 Precision Touch Pad Connector
AFTP6226 1 KSO2 14
AFTP6207 1 KSO0 13 TP_VDD Pin number Pin name
AFTP6233 1 KSO12 12 3D3V_S0 TP_VDD
R6517

2
1
AFTP6225 1 KSO16 11 8 VDD
AFTP6229 1 KSO15 10 RN6504 1 2 C6504
AFTP6203 1 KSO13 9 SRN10KJ-5-GP DY 7 DAT(I2C)
AFTP6216 1 KSO14 8 2 1
AFTP6219 1 KSO9 7 TPAD1 6 CLK(I2C)
AFTP6220 1 KSO11 6 Support PTP Do Not Stuff SCD1U16V2KX-3GP

3
4
AFTP6232 1 KSO10 5 2NON TP_WAKE
1 10 5 GND
CAP_LED 4 20.K0592.030 8
3 SRN33J-5-GP-U R6513 I2C1_SDA_R 7 4 ATTN
2 2nd = 20.K0565.030 RN6503 1 4 TPCLK_C 4K7R2J-2-GP I2C1_SCL_R 6
PS2 [24] CLK_TP_SIO
[24] DAT_TP_SIO 2 3 TPDATA_C 5 3 GPIO
AFTP6201 1 1 3rd = 20.K0621.030 4
[4,24] INT_TP# TP_LOCK#
31
[24] TP_LOCK#
3 2 DAT(PS2)
R6518 1 DY 2 Do Not Stuff I2C1_SCL_R TPDATA_C 2
I2C [20] I2C0_SCL_TCH_PAD
[20] I2C0_SDA_TCH_PAD R6519 1 DY 2 Do Not Stuff I2C1_SDA_R 1 CLK(PS2)
ACES-CON30-10-GP TPCLK_C 1
20140820 DAIVD 9

EC6501
Do Not Stuff

EC6504
Do Not Stuff

EC6502
Do Not Stuff
1

1
ACES-CON8-40-GP
EC6503 5V_S0
CAP LED Control 5V_S0 Do Not Stuff
DY DY DY DY
Q6502 1 20.K0667.008

2
AFTP6235
LOW actived from KBC GPIOR6508 R2
E
1 2 CAP_LED_R# B R6506 TP_VDD
[24] CAP_LED#_S R1
CAP_LED_Q CAP_LED
C 1 2

1
Do Not Stuff
DDTA144VCA-7-F-GP
1KR2J-1-GP R6512 Need to check if it is Active High or Active Low
Do Not Stuff and check if there is PH on TPAD side.
C C

2
1
RN6502

2
84.00144.N11 SRN2K2J-1-GP TP_VDD

AFTP6243 1 CAP_LED PTP

TP side has pull high
Q6204_G

3
4
2N7002KDW-GP R6514
2 1 INT_TP#
Keyboard Backlight (Reserved) I2C0_SCL_TCH_PAD 1 6 I2C1_SCL_R
20140820 DAIVD 10KR2J-3-GP
84.2N702.A3F 2 5
EE Note: Never change to short pad after MP 2nd = 84.2N702.E3F
Reserve location for Fuse: 069.50001.0051 3rd = 75.00601.07C 3 4 I2C1_SDA_R
(POLYSW 0603/0.5A/6V) 4th = 84.DMN66.03F
5V_S0 Q6503
+5V_KB_BL TP_VDD 1 AFTP6239
TPCLK_C 1 AFTP6238
I2C0_SDA_TCH_PAD TPDATA_C 1 AFTP6236
1KBBL 2 I2C1_SCL_R 1 AFTP6237
R6504 Do Not Stuff I2C1_SDA_R 1 AFTP6240
1

INT_TP# 1 AFTP6241
KBBLC6501 TP_LOCK# 1 AFTP6242
2

Do Not Stuff
KBBL1 SMBUS
5
Do Not Stuff 1 2 R6515 I2C1_SCL_R
R6503
1 [12,13,18,56,99] PCH_SMBCLK
Do Not Stuff 1
DY I2C1_SDA_R
[12,13,18,56,99] PCH_SMBDATA DY 2 R6511
1 KBBL 2 KB_LED_DET_C 2 KBBL
[19] KB_LED_BL_DET_R
3
1

Do Not Stuff 4
1

Need to check with SW.

KB_BL_CTRL#

KBBL 6

EC6505
Do Not Stuff

EC6506
Do Not Stuff
R6507 DY C6502

1
Do Not Stuff Do Not Stuff
2

Do Not Stuff

DY DY
2

Do Not Stuff 1

2
2ND = 20.K0841.004 AFTP6245
D

B B
KB Backlight Power Consumption: 285mA max. Q6501
Do Not Stuff
KBBL
G
[24] BKLGT_PWM
Do Not Stuff
1

DY R6505
Do Not Stuff
+5V_KB_BL 1
KB_LED_DET_C 1 AFTP6248
2

KB_BL_CTRL# 1 AFTP6246
AFTP6247

A A

Iris SKL UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Key Board&Touch Pad

Size Document Number Rev
A2 A00
Iris2 SKL-U
Date: Wednesday, September 09, 2015 Sheet 65 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = IO Connector

I/O Board Connector

connector follow IRIS2

Vinafix.com CN6301
25
D D
1

2
USB2 (USB2.0) [37] USB_CON_PN1
[37] USB_CON_PP1
USB_CON_PN1
USB_CON_PP1
3
4
5
USB_CON_PP2 6
USB3 (USB2.0) [37] USB_CON_PP2
[37] USB_CON_PN2 USB_CON_PN2 7
8
R6601 1 DY 2 Do Not Stuff GND_R1 9
USB20_VCCA 10
11
12
20140801 david 13
14
R6602 1 2 Do Not Stuff GND_R2 15
DY AUD_AGND 16
[29] AUD_PORTA_L_R_B 17
[29] AUD_PORTA_R_R_B 18
[29] SLEEVE_R 19
20
21
Universal Jack [29] RING2_R

[29] JACK_PLUG
22
23
AUD_AGND 24

26
C ACES-CON24-19-GP C

020.K0142.0024
R6305 2rd = 020.K0139.0024
1 DY 2

Do Not Stuff Pitch: 1mm

AUD_AGND
Power: 5 pins
GND: 4 pins
AGND: 2 Pins
USB_CON_PN1 1 AFTP6301 Do Not Stuff
USB_CON_PP1 1 AFTP6302 Do Not Stuff
USB_CON_PN2 1 AFTP6303 Do Not Stuff
USB_CON_PP2 1 AFTP6304 Do Not Stuff
RING2_R 1 AFTP6305 Do Not Stuff
AUD_PORTA_L_R_B 1 AFTP6306 Do Not Stuff
JACK_PLUG 1 AFTP6307 Do Not Stuff
AUD_PORTA_R_R_B 1 AFTP6309 Do Not Stuff
SLEEVE_R 1
B AFTP6310 Do Not Stuff B
USB20_VCCA 1 AFTP6311 Do Not Stuff

AUD_AGND 1 AFTP6313 Do Not Stuff

1 AFTP6314 Do Not Stuff

Wistron Confidential document, Anyone can not

Duplicate, Modify, Forward or any other purpose
application without get Wistron permission
A Iris SKL UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

IO Board Connector
Size Document Number Rev
A3
Iris2 SKL-U A00
Date: W ednesday, September 09, 2015 Sheet 66 of 105
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A Iris SKL UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Iris2 SKL-U A00
Date: Tuesday, May 26, 2015 Sheet 67 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = Debug

Vinafix.com
D D

Debug Connector
Layout Note:
Place near trace separated point 3D3V_S0
DB1
11
LPC_LAD[3..0] RN6501 1
[18,24] LPC_LAD[3..0]
Do Not Stuff
LPC_LAD3 1 8 LPC_LAD3_C LPC_LAD0_C 2
LPC_LAD2 2 7 LPC_LAD2_C LPC_LAD1_C 3
LPC_LAD1 3 LPC 6 LPC_LAD1_C LPC_LAD2_C 4
LPC_LAD0 4 5 LPC_LAD0_C LPC_LAD3_C 5 A00 modify 2015/06/05
LPC_FRAME#_DEBUG 6
LPC
1 2 PLT_RST#_DEBUG 7
[18,24] LPC_LFRAME#
[17,24,31,40,55,61,76] PLT_RST# R6501 LPC
1 2 Do Not Stuff 8
R6502 Do Not Stuff 9
[18] CLK_PCI_LPC
10
12
C C
Do Not Stuff

20.D0075.110: Dummy Pad with solder mask is ZZ.00PAD.Y41

DB1 Optional: New one smaller LPC connector is 20.F1180.010.

B B

Iris SKL UMA

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Dubug connector
Size Document Number Rev
A4
Iris2 SKL-U A00
Date: Wednesday, September 09, 2015 Sheet 68 of 105
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A Iris SKL UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Iris2 SKL-U A00
Date: Tuesday, May 26, 2015 Sheet 69 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = Hall Sensor

Vinafix.com
D D

C C

(Blanking)

B B

Iris SKL UMA

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)
Size Document Number Rev
A4 A00
Iris2 SKL-U
Date: Tuesday, May 26, 2015 Sheet 70 of 105
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A Iris SKL UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size
RESERVED
Document Number Rev
A3 Iris2 SKL-U A00
Date: Tuesday, May 26, 2015 Sheet 71 of 105
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

B B

A Iris SKL UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

USB3.0 PORT
Size Document Number Rev
A3
Iris2 SKL-U A00
Date: Tuesday, May 26, 2015 Sheet 72 of 105
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A Iris SKL UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Iris2 SKL-U A00
Date: Tuesday, May 26, 2015 Sheet 73 of 105
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A Iris SKL UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Iris2 SKL-U A00
Date: Tuesday, May 26, 2015 Sheet 74 of 105
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A Iris SKL UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Iris2 SKL-U A00
Date: Tuesday, May 26, 2015 Sheet 75 of 105
5 4 3 2 1
 5 4 3 2 1

GFX & GPP, 85Ω

GFX & GPP CLK, 85Ω
GPU1A 1 OF 7
Vinafix.com
D D

[16] PEG_TX_GPU_P0 AF30 AH30 PEG_RX_GPU_P0 C7301 1OPS2 Do Not Stuff PEG_RX_CPU_P0 [16]
PCIE_RX0P PCIE_TX0P PEG_RX_GPU_N0 C7302 1OPS2 Do Not Stuff
[16] PEG_TX_GPU_N0 AE31 PCIE_RX0N PCIE_TX0N AG31 PEG_RX_CPU_N0 [16]

[16] PEG_TX_GPU_P1 AE29 AG29 PEG_RX_GPU_P1 C7303 1OPS2 Do Not Stuff PEG_RX_CPU_P1 [16]
PCIE_RX1P PCIE_TX1P PEG_RX_GPU_N1 C7304 1OPS2 Do Not Stuff
[16] PEG_TX_GPU_N1 AD28 PCIE_RX1N PCIE_TX1N AF28 PEG_RX_CPU_N1 [16]

[16] PEG_TX_GPU_P2 AD30 AF27 PEG_RX_GPU_P2 C7305 1OPS2 Do Not Stuff PEG_RX_CPU_P2 [16]
PCIE_RX2P PCIE_TX2P PEG_RX_GPU_N2 C7306 1OPS2 Do Not Stuff
[16] PEG_TX_GPU_N2 AC31 PCIE_RX2N PCIE_TX2N AF26 PEG_RX_CPU_N2 [16]

[16] PEG_TX_GPU_P3 AC29 AD27 PEG_RX_GPU_P3 C7307 1OPS2 Do Not Stuff PEG_RX_CPU_P3 [16]
PCIE_RX3P PCIE_TX3P PEG_RX_GPU_N3 C7308 1OPS2 Do Not Stuff
[16] PEG_TX_GPU_N3 AB28 PCIE_RX3N PCIE_TX3N AD26 PEG_RX_CPU_N3 [16]

AB30 PCIE_RX4P PCIE_TX4P AC25

AA31 PCIE_RX4N PCIE_TX4N AB25

AA29 PCIE_RX5P PCIE_TX5P Y23

Y28 PCIE_RX5N PCIE_TX5N Y24

Y30 PCIE_RX6P PCIE_TX6P AB27

W31 PCIE_RX6N PCIE_TX6N AB26
C C

W29 PCIE_RX7P PCIE_TX7P Y27

V28 PCIE_RX7N PCIE_TX7N Y26

V30 NC#V30 NC#W24 W24

U31 NC#U31 NC#W23 W23

U29 NC#U29 NC#V27 V27

T28 NC#T28 NC#U26 U26

PCI EXPRESS INTERFACE

T30 NC#T30 NC#U24 U24
R31 NC#R31 NC#U23 U23

R29 NC#R29 NC#T26 T26

P28 NC#P28 NC#T27 T27

P30 NC#P30 NC#T24 T24

N31 NC#N31 NC#T23 T23

N29 NC#N29 NC#P27 P27

M28 NC#M28 NC#P26 P26
B B

M30 NC#M30 NC#P24 P24

L31 NC#L31 NC#P23 P23

DGPU_HOLD_RST# L29 NC#L29 NC#M27 M27

K30 NC#K30 NC#N26 N26
3D3V_VGA_S0
H dGPU mode
L IGPU CLOCK
[18] PEG_CLK_CPU AK30 PCIE_REFCLKP
1

H IGPU with BACO R7625

[18] PEG_CLK_CPU# AK32 PCIE_REFCLKN
Do Not Stuff DY CALIBRATION

Y22 PCIE_CALR_TX Do Not Stuff 2 OPS 1 R7622 0D95V_VGA_S0

2

R7623 PCIE_CALR_TX
2 OPS 1 Do Not Stuff
R7601 2 OPS1 Do Not Stuff PW RGOOD_TEST N10 AA22 PCIE_CALR_RX Do Not Stuff 2 OPS 1 R7618
D7601 TEST_PG PCIE_CALR_RX
[20] DGPU_HOLD_RST# 2
Do Not Stuff
DY 3 ATI_RST# R7621 2 OPS1 Do Not Stuff VGA_RST# AL27 PERST#
1

[17,24,31,40,55,61,68] PLT_RST# 1 C7609

Do Not Stuff DY Do Not Stuff
OPS
2

A Iris SKL UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

076_GPU(1/5) PEG
Size Project Name Rev

<Project Name> SA
Date: W ednesday, September 09, 2015 Sheet 76 of 105
5 4 3 2 1
 5 4 3 2 1

GPU1E 5 OF 7 GPU1G 7 OF 7

DP POWER NC/DP POWER

AA27 A3
1.8V and 0.95V for Clock resource AG15 AE11
GND GND NC_DP_VDDR#AG15 NC#AE11
AB24 GND GND A30 AG16 NC_DP_VDDR#AG16 NC#AF11 AF11
AB32
AC24
GND GND Vinafix.com
AA13
AA16
AF16
AG17
NC_DP_VDDR#AF16 NC#AE13 AE13
AF13
GND GND 1D8V_VGA_S0 DPLL_PVDD DPLL_PVDD NC_DP_VDDR#AG17 NC#AF13
AC26 GND GND AB10 R7704 AG18 NC_DP_VDDR#AG18 NC#AG8 AG8
D D
AC27
AD25
GND GND AB15
AB6 1 OPS 2
40mA AG19
AF14
NC_DP_VDDR#AG19 NC#AG10 AG10
GND GND DP_VDDR
AD32 GND GND AC9

1
AE27 AD6 C7713 C7711 C7710
GND GND Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff
AF32 GND GND AD8 DY
AG27 AE7 OPS OPS

2
GND GND
AH32 GND GND AG12 AG20 NC_DP_VDDC#AG20 NC#AF6 AF6
K28 GND GND AH10 AG21 NC_DP_VDDC#AG21 NC#AF7 AF7
K32 AH28 0D95V_VGA_S0 DPLL_VDDC DPLL_VDDC AF22 AF8
GND GND R7705 NC_DP_VDDC#AF22 NC#AF8
L27
M32
GND GND B10
B12 1 OPS 2
32mA AG22
AD14
NC_DP_VDDC#AG22 NC#AF9 AF9
GND GND DP_VDDC
N25 GND GND B14

1
N27 B16 C7715 C7714
GND GND Do Not Stuff Do Not Stuff Do Not Stuff
P25 GND GND B18
P32 B20 OPS OPS AG14 AE1

2
GND GND NC_DP_VSSR#AG14 NC#AE1
R27 GND GND B22 AH14 NC_DP_VSSR#AH14 NC#AE3 AE3
T25 GND GND B24 AM14 NC_DP_VSSR#AM14 NC#AG1 AG1
T32 GND GND B26 AM16 NC_DP_VSSR#AM16 NC#AG6 AG6
U25 GND GND B6 AM18 NC_DP_VSSR#AM18 NC#AH5 AH5
U27 B8 GPU1F 6 OF 7 AF23 AF10
GND GND NC_DP_VSSR#AF23 NC#AF10
C V32 GND GND C1 AG23 NC_DP_VSSR#AG23 NC#AG9 AG9 C
W25 C32 VGA_CORE AM20 AH8
GND GND NC_DP_VSSR#AM20 NC#AH8
W26 GND GND E28 AM22 NC_DP_VSSR#AM22 NC#AM6 AM6
W27 GND GND F10 NC_VARY_BL AB11 AM24 NC_DP_VSSR#AM24 NC#AM8 AM8
Y25 GND GND F12 NC_DIGON AB12 AF19 NC_DP_VSSR#AF19 NC#AG7 AG7
Y32 GND GND F14 AF20 NC_DP_VSSR#AF20 NC#AG11 AG11
GND F16 BALL: AB11, AB12 AE14 DP_VSSR
F18
GND
F2 EXO : NC
GND
GND F20 NC_UPHYAB_TMDPA_TX0N AL15 MESO : VDDC
M6 GND GND F22 NC_UPHYAB_TMDPA_TX0P AK14 AF17 NC_UPHYAB_DP_CALR NC#AE10 AE10
N13 GND GND F24
N16 GND GND F26 NC_UPHYAB_TMDPA_TX1N AH16
N18 GND GND F6 NC_UPHYAB_TMDPA_TX1P AJ15
N21 GND F8 Do Not Stuff
GND GND
P6 GND GND G10 NC_UPHYAB_TMDPA_TX2N AL17 OPS
P9 GND GND G27 NC_UPHYAB_TMDPA_TX2P AK16
R12 GND GND G31
R15 GND GND G8 NC_UPHYAB_TMDPA_TX3N AH18
R17 GND GND H14 NC_UPHYAB_TMDPA_TX3P AJ17
B R20 GND GND H17 B
T13 GND GND H2 NC_TXOUT_L3P AL19
T16 GND GND H20 NC_TXOUT_L3N AK18
T18 GND GND H6
T21 GND GND J27
TMDP
T6 GND GND J31
U15 GND GND K11
U17 GND GND K2 NC_UPHYAB_TMDPB_TX0N AH20
U20 GND GND K22 NC_UPHYAB_TMDPB_TX0P AJ19
U9 GND GND K6
V13 GND NC_UPHYAB_TMDPB_TX1N AL21
V16 GND NC_UPHYAB_TMDPB_TX1P AK20
V18 GND
Y10 GND NC_UPHYAB_TMDPB_TX2N AH22
Y15 GND NC_UPHYAB_TMDPB_TX2P AJ21
Y17 GND
Y20 AL23 Iris SKL UMA
GND VSS_MECH1 1 TP7701 NC_UPHYAB_TMDPB_TX3N
R11 GND VSS_MECH A32 NC_UPHYAB_TMDPB_TX3P AK22
T11 AM1 VSS_MECH2 1 TP7702
GND VSS_MECH
A
AA11
M12
GND VSS_MECH AM32 VSS_MECH3 1 TP7703
NC_TXOUT_U3P AK24
AJ23
Wistron Corporation A
GND NC_TXOUT_U3N 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
N11 GND Taipei Hsien 221, Taiwan, R.O.C.
V11 GND
Title
Do Not Stuff Do Not Stuff 077_GPU (2/5) DIGITALOUT
OPS OPS Size Project Name Rev
<Project Name> SA
Date: Tuesday, May 26, 2015 Sheet 77 of 105
5 4 3 2 1
 5 4 3 2 1

GPU1C 3 OF 7

GDDR5/DDR3 GDDR5/DDR3
Signal GRP Signal [81] DQA0_[31..0] DQA0_0 K27 DQA0_0 MAA0_0 K17 MAA0 [81,82]
DQ DQA0_1 J29 J20
DQA0_1 MAA0_1 MAA1 [81,82]
DQA0_2 H30 H23 ADD
Clocks CLK
Vinafix.com DQA0_3
DQA0_4
H32
G29
DQA0_2
DQA0_3
DQA0_4
MAA0_2
MAA0_3
MAA0_4
G23
G24
MAA2
MAA3
MAA4
[81,82]
[81,82]
[81,82]
DQA0_5 F28 H24
D
Address ADD BANK DQA0_6 F32
DQA0_5 MAA0_5
J19
MAA5 [81,82]
D
DQA0_6 MAA0_6 MAA6 [81,82]
DQA0_7 F30 K19
DQA0_7 MAA0_7 MAA7 [81,82]
DQA0_8 C30 G20
Command RAS_L CAS_L WE_L DQA0_9 F27
DQA0_8 MAA0_8
L17
MAA13 [81,82]
DQA0_9 MAA0_9 MAA15 [81,82]
DQA0_10 A28
DQA0_11 DQA0_10
C28 J14
Control CKE ODT CS_L DQA0_12 E27
DQA0_11 MAA1_0
K14
MAA8 [81,82]
DQA0_12 MAA1_1 MAA9 [81,82]
DQA0_13 G26 J11
DQA0_13 MAA1_2 MAA10 [81,82]
DQA0_14 D26 J13
Data Data CHECK DM DQS DQA0_14 MAA1_3 MAA11 [81,82]
DQA0_15 F25 H11
DQA0_15 MAA1_4 MAA12 [81,82]
DQA0_16 A25 G11
DQA0_16 MAA1_5 MAA_BA2 [81,82]
DQA0_17 C25 J16
DQA0_17 MAA1_6 MAA_BA0 [81,82]
DQA0_18 E25 L15
DQA0_18 MAA1_7 MAA_BA1 [81,82]
DQA0_19 D24 G14
DQA0_19 MAA1_8 MAA14 [81,82]
DQA0_20 E23 L16 VSSRHA 1

MEMORY INTERFACE
DQA0_21 DQA0_20 MAA1_9 TP7801
F23 DQA0_21
DQA0_22 D22 E32
DQA0_22 WCKA0_0 DQMA0 [81]
DQA0_23 F21 E30 DM
DQA0_23 WCKA0#_0 DQMA1 [81]
DQA0_24 E21 A21
DQA0_24 WCKA0_1 DQMA2 [81]
DQA0_25 D20 C21
DQA0_25 WCKA0#_1 DQMA3 [81]
DQA0_26 F19 E13
DQA0_26 WCKA1_0 DQMA4 [82]
DQA0_27 A19 D12
DQA0_27 WCKA1#_0 DQMA5 [82]
DQA0_28
Please MVREF drivers and Caps close to ASIC DQA0_29
D18
F17
DQA0_28 WCKA1_1 E3
F4
DQMA6 [82]
DQA0_29 WCKA1#_1 DQMA7 [82]
DQA0_30 A17
DQA0_31 DQA0_30
[82] DQA1_[31..0] C17 DQA0_31 EDCA0_0 H28 QSAP_0 [81]
DQA1_0 DQS
DDR3/GDDR3 Memory Stuff Option(JET/TOPAZ) DQA1_1
E17
D16
DQA1_0 EDCA0_1 C27
A23
QSAP_1 [81]
DQA1_1 EDCA0_2 QSAP_2 [81]
DQA1_2 F15 E19
DQA1_2 EDCA0_3 QSAP_3 [81]
C DQA1_3 A15 E15 C
DQA1_3 EDCA1_0 QSAP_4 [82]
GDDR5 GDDR3 DDR3 DQA1_4 D14 DQA1_4 EDCA1_1 D10 QSAP_5 [82]
DQA1_5 F13 D6
DQA1_5 EDCA1_2 QSAP_6 [82]
DQA1_6 A13 G5
DQA1_6 EDCA1_3 QSAP_7 [82]
MVDDQ 1.5V 1D35V 1.5V DQA1_7 C13 DQA1_7
DQA1_8 E11 H27
DQA1_8 DDBIA0_0 QSAN_0 [81]
DQA1_9 A11 A27
DQA1_9 DDBIA0_1 QSAN_1 [81]
Ra 40.2R 40.2R 40.2R DQA1_10 C11 DQA1_10 DDBIA0_2 C23 QSAN_2 [81]
DQA1_11 F11 C19
DQA1_11 DDBIA0_3 QSAN_3 [81]
DQA1_12 A9 C15
DQA1_12 DDBIA1_0 QSAN_4 [82]
Rb 100R 100R 100R DQA1_13 C9 DQA1_13 DDBIA1_1 E9 QSAN_5 [82]
DQA1_14 F9 C5
DQA1_14 DDBIA1_2 QSAN_6 [82]
DQA1_15 D8 H4
DQA1_15 DDBIA1_3 QSAN_7 [82]
DQA1_16 E7
DQA1_17 DQA1_16
1D35V_VGA_S0 1D35V_VGA_S0 DQA1_18
A7 DQA1_17 ADBIA0 L18 ODTA0 [81] Ctrl
C7 DQA1_18 ADBIA1 K16 ODTA1 [82]
DQA1_19 F7
DQA1_20 DQA1_19
A5 DQA1_20 CLKA0 H26 CLKA0 [81]
1

DQA1_21 E5 H25 CLK

DQA1_21 CLKA0# CLKA0# [81]
R7817 R7810 DQA1_22
Do Not Stuff
Ra Do Not Stuff DQA1_23
C3 DQA1_22
Ra DQA1_24
E1 DQA1_23 CLKA1 G9 CLKA1 [82]
OPS OPS DQA1_25
G7 DQA1_24 CLKA1# H9 CLKA1# [82]
G6
2

MVREFDA MVREFSA DQA1_26 DQA1_25

G1 DQA1_26 RASA0# G22 RASA0# [81]
DQA1_27 G3 G17 CMD
DQA1_27 RASA1# RASA1# [82]
1

DQA1_28 J6
OPS OPS DQA1_28
2

R7818 R7814 DQA1_29

Rb Do Not Stuff Do Not Stuff Rb Do Not Stuff Do Not Stuff DQA1_30
J1
J3
DQA1_29 CASA0# G19
G16
CASA0# [81]
C7805 C7801 DQA1_30 CASA1# CASA1# [82]
OPS OPS DQA1_31 J5
1

B DQA1_31 B
H22 CSA0#_0 [81]
2

MVREFDA CSA0#_0
MVREFSA
K26 MVREFDA CSA0#_1 J22 Ctrl, CS
J26 MVREFSA
Jet Setting J25
CSA1#_0 G13
K13
CSA1#_0 [82]
R7809 NC#J25 CSA1#_1
1 OPS 2 Do Not Stuff MEM_CALRP0 K25 MEM_CALRP0
CKEA0 K20 CKEA0 [81] Ctrl
Place all these componets very close to GPU (within 25mm) and keep all CKEA1 J17 CKEA1 [82]
components close to each other G25
DRAM_RST_VGA1 WEA0# W EA0# [81]
This basic topology should be used for DRAM_RST for DDR3/GDDR5 L10 DRAM_RST# WEA1# H10 W EA1# [82] CMD
CLKTESTA K8
1D35V_VGA_S0 CLKTESTB CLKTESTA
L7 CLKTESTB
1

1
1

C7822 DY DY C7821 Do Not Stuff

R7802 Do Not Stuff Do Not Stuff
2

Do Not Stuff
OPS
CLKTESTA_C

CLKTESTB_C

DY Do Not Stuff OPS Do Not Stuff

R7804 R7803 Debug only, for
2

1 2 DRAM_RST_R 1 2 DRAM_RST_VGA1
[81,82] DRAM_RST clock observation,
OPS if not needed, DNI
1

C7802 R7819
Do Not Stuff Do Not Stuff R7821 R7820
2

Do Not Stuff Do Not Stuff

OPS OPS DY DY
A Iris SKL UMA A
2

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

078_GPU (3/5) VRAM I/F

Size Project Name Rev
<Project Name> SA
Date: W ednesday, September 09, 2015 Sheet 78 of 105
5 4 3 2 1
 5 4 3 2 1

上上
EXO : DY GPU1B 2 OF 7
3D3V_VGA_S0
MESO : RN7905

1D8V_VGA_S0 3 2 MESO_U1 #3
R7903 1 Do Not Stuff TESTEN MESO_U3
2 DY 4 MESO 1
NC#AF2
AF2
PS0 ~ PS3 Setting AMD suggest Aperture Size = 256MB
PINs for debug NC#AF4
AF4

R7902 2 Do Not Stuff TESTEN Do Not Stuff TP7909 DBG_DATA16 11001

1 OPS 1
DBG_DATA15
N9
DBG_DATA16 NC#AG3
AG3 Cap Value (nF) Bits [5:4] R_pu (Ω) R_pd (Ω) Bits [3:1]
TP7914 1 L9 AG5
RN7904 XO_IN SMB_CLK_VGA_R R7912 SMB_CLK_VGA DBG_DATA14 DBG_DATA15 NC#AG5 680 00 NC 4750 000
3 2 1 DY 2 Do Not Stuff TP7915 1 AE9 DPA 1D8V_VGA_S0
XO_IN2 TP7916 DBG_DATA13 DBG_DATA14
4 OPS 1
SMB_DATA_VGA_R R7914 SMB_DATA_VGA
1
DBG_DATA12
Y11
DBG_DATA13 NC#AH3
AH3 82 01 8450 2000 001
1 DY 2 Do Not Stuff TP7917 1 AE8 AH1
DBG_DATA12 NC#AH1

1
Do Not Stuff AD9
DBG_DATA11
10 10 4530 2000 010 Do Not Stuff
3D3V_VGA_S0 AC10 AK3 R7926
DBG_DATA10 NC#AK3 NC 11 6980 4990 011

Vinafix.com OPS
AD7 AK1
DBG_DATA9 NC#AK1
AC8
DBG_DATA8 DVO 4530 4990 100
AC7 AK5
3240 5620 101

2
DBG_DATA7 NC#AK5

1
3D3V_VGA_S0 AB9 AM3 PS_0
R7942 DBG_DATA6 NC#AM3
AB8 3400 10000 110

1
DBG_DATA5
D DY Do Not Stuff AB7
DBG_DATA4 NC#AK6
AK6
4750 NC 111
D

1
2015/05/6 DVT2 modify [19,24,85] DGPU_PWROK AB4
DBG_DATA3 NC#AM5
AM5 R7927 OPS C7918
R7904 Do Not Stuff
AB2 DPB Note: 0402 1% resistors are required. DY Do Not Stuff

2
DBG_DATA2

4
3
1 DY 2DGPU_PWROK_R Y8 AJ7

2
RN7902 Q7903 DBG_DATA1 NC#AJ7
Y7 AH6

2
DBG_DATA0 NC#AH6
OPS Do Not Stuff Do Not Stuff G DY
AK8
NC#AK8
D CLKREQ_PEG#0 [18] AL7
Do Not Stuff NC#AL7

1
2
[18,24,26] SML1_SMBCLK 6 1 SMB_CLK_VGA_R [26] S
W6
5 2 V6
NC#W6 PS_1[1]=0 => PCIe GEN2 setting
Do Not Stuff NC#V6
OPS NC#V4
V4 PS_1[1]=1 => PCIe GEN3 setting
4 3 AC6 U5
R7943 NC#AC6 NC#U5 Circuit checklist
1 OPS 2 AC5
NC#AC5 Test only,
Q7901
NC#W3
W3
Connect to GND through a 16.2-K resistor.
MESO-LE only support GEN2
Do Not Stuff AA5 V2
AA6
NC#AA5
DPC
NC#V2 The resistor is not needed on production. 1D8V_VGA_S0 11000
[18,24,26] SML1_SMBDATA NC#AA6
SMB_DATA_VGA_R [26] Y4
NC#Y4 R7938
TP7918 W5

1
NC#W5 Do Not Stuff
MESO_U1 U1 AA3 NC#AA3 2 DY 1 Do Not Stuff GEN3
3D3V_VGA_S0 NC#U1 NC#AA3 R7928
W1 Y2
MESO_U3 NC#W1 NC#Y2
U3

GPU_DPRSLP 1
NC#U3
Y6 J8

2
1
NC#Y6 NC#J8
TP7902 1PLL_ANALOG_IN AA1 PS_1
R7921 NC#AA1

1
OPSDo Not Stuff

1
Q7902 PS_2[1] Reserved. AMD Suggests 0 R7929 C7919
[24] GPU_PWR_LEVEL
R7937 1 OPS 2GPU_PWR_LEVEL_R G OPS Do Not Stuff DY Do Not Stuff

2
I2C PS_2[2] Reserved. AMD Suggests 0 GEN2 680nF

2
Do Not Stuff D GPIO_5_AC_BATT

2
1
VGA_CORE R1
SCL PS_2[3] 0 = Disable the external BIOS ROM device.
S DY R7911 R3
Do Not Stuff
SDA 1 = Enable the external BIOS ROM device.
AM26 NC_R 1 TP7922 PS_2[4] Reserved. AMD Suggests 1
Do Not Stuff NC_R
AK26

2
GPU_DPRSLP_R GENERAL PURPOSE I/ONC_AVSSN#AK26
U6
GPIO_0 PS_2[5] Reserved. AMD Suggests 1
U10 AL25
NC_GPIO_1 NC_G
Pre-PWROK METAL VID CODES SMB_DATA_VGA
T10
NC_GPIO_2 NC_AVSSN#AJ25
AJ25
U8
C SMB_CLK_VGA U7
SMBDATA
AH24
11000 C
GPIO_5_AC_BATT SMBCLK NC_B
SVC SVD Output Voltage T9
GPIO_5_AC_BATT NC_AVSSN#AG25
AG25
PS3: Vram setting for DVT1
T8 R7941 1D8V_VGA_S0
[85] TOPAZ_OCP GPIO_6 DAC1
0 0 1.1 T7
NC_GPIO_7 NC_HSYNC
AH26 Do Not Stuff
TP7905 GPIO_8_ROMSO AJ27 NC_VSYNC 2 MESO1
1 P10
GPIO_8_ROMSO NC_VSYNC Bit 5 4 3 2 1

1
0 1 1.0 VGA_CORE BALL: U10,T10,Y9,W10 TP7906 1 GPIO_9_ROMSI P4 Do Not Stuff
GPIO_9_ROMSI
1 GPIO_10_ROMSCK
上上
TP7901 P2 EXO : DY R7930
AMD suggestion 1 0 0.9 EXO : NC GPIO_10_ROMSCK
Samsung 1G
N6
NC_GPIO_11 NC_RSET
AD22
MESO : PS3 1 1 0 0 0 DY
MESO : VDDC N5
NC_GPIO_12
1 1 0.8 N3 AG24

2
NC_GPIO_13 NC_AVDD PS_2
Y9
NC_GPIO_14 NC_AVSSQ
AE22
PS3 1 1 1 0 0 Micron 1G
JET_SVD N1
GPIO_15_PWRCNTL_0

1
TP7903 1 GPIO16_VGA M4 AE23

1
GPIO_16 NC_VDD1DI
TP7923 1 GPIO_17_THERMAL_INT R6 AD23 Samsung 2G R7931 C7920
R7922
W10
GPIO_17_THERMAL_INT NC_VSS1DI PS3 1 1 0 0 1 Do Not Stuff
OPS DY Do Not Stuff
GPIO_19_CTF NC_GPIO_18
2 OPS 1 M2 FutureASIC/SEYMOUR/PARK

2
JET_SVC GPIO_19_CTF
P8 AM12 Hynix 2G 680nF

2
Do Not Stuff GPIO_20_PWRCNTL_1 CEC_1 PS3 1 1 0 1 1
P7
GPIO_21
TP7910 1 GPIO_22_ROMCS# N8
GPIO_22_ROMCS#
TP7919 1 H_VID3 AK10 AK12 MESO_SVD
JET_SVC GPIO_29 NC_SVI2#AK12
[85] VGA_SVC
R7919 1 EXO 2 Do Not Stuff TP7920 1 H_VID4 AM10 AL11 MESO_SVT
R7920 JET_SVD PEG_CLKREQ#_VGA GPIO_30 NC_SVI2#AL11 MESO_SVC
[85] VGA_SVD 1 EXO 2 Do Not Stuff TP7921 1 N7 AJ11
CLKREQ# NC_SVI2#AJ11
BALL: AB13, W9, AC14 TP7907 1 JTAG_TRST#_VGA L6
PWR_VGA_CORE_VDDIO TP7908 1 JTAG_TDI_VGA L5
JTAG_TRST# ## PS_3[3-1] => MEM_ID setting, need decide for AMD
EXO : NC TP7911 1 JTAG_TCK_VGA L3
JTAG_TDI
JTAG_TCK
MESO : VDDC TP7912 1 JTAG_TMS_VGA L1
JTAG_TMS NC_GENLK_CLK
AL13
TP7913 1 JTAG_TDO_VGA K4 AJ13
VGA_CORE TESTEN JTAG_TDO NC_GENLK_VSYNC 1D8V_VGA_S0
K7
TESTEN
AF24
NC#AF24
2

AG13
Board Configure [5:1]

1
R7940 R7924 R7923 NC_SWAPLOCKA Do Not Stuff
AH12
Do Not Stuff Do Not Stuff Do Not Stuff NC_SWAPLOCKB R7932
AB13
NC_GENERICA AGPIO66 AGPIO71 VRAM
DY MESO MESO W8
NC_GENERICB Bit 5 4 3 2 1
W9
1

NC_GENERICC PS_0
W7 AC19 UMA 0 900M Hz 0

2
R7944 MESO_SVD NC_GENERICD PS_0 PS_3
[85] VGA_SVD 1 MESO 2 Do Not Stuff AD10
NC_GENERICE_HPD4 #3 PS0 1 1 0 0 1
[85] VGA_SVT
R7945 1 MESO 2 Do Not Stuff MESO_SVT AJ9 AD19 PS_1 PX 1 1G 1

1
R7946 MESO_SVC NC#AJ9 PS_1
[85] VGA_SVC 1 MESO 2 Do Not Stuff AL9 VRAM

1
DBG_CNTL0 PS_2 R7933
AE17
PS_2 PS1 1 1 0 0 0 Do Not Stuff C7921
B PX_EN
AC14
NC_HPD1 PS_3
DY Do Not Stuff B
TP7904 1 AB16 AE20

2
PX_EN PS_3
2

PS2 1 1 0 0 0

2
R7925 R7934 R7939
Do Not Stuff Do Not Stuff Do Not Stuff AE19
TS_A
MESO MESO DY AC16
NC_DBG_VREFG PS3 1 1 see below table
1

BALL: AC11,AC13
DDC/AUX
EXO : NC
NC_DDC1CLK
AE6 MESO : VDDC
PLL/CLOCK
AE5
NC_DDC1DATA
AD2 VGA_CORE
NC_AUX1P
AD4
SVID PWR Sequencing
NC_AUX1N Pull-High Pull-Low
NC_DDC2CLK
AC11
AC13
Board Configure [2:0] R7932 R7933 Brand Size Part Number SDV Configure
NC_DDC2DATA
JET R7919 R7920 PR8611 PC8607 / PR8612 PC8612 XTL_27M_X1_VGA
0: Enable MLPS, disable GPIO PINSTRAP AM28
XTALIN NC_AUX2P
AD13 0 0 0 NC 4750 Samsung (1G) 128M x 16 x 4pcs SS K4W2G1646Q-BC1A 2Gb 900(1G) gDDR3(L)
XTL_27M_X2_VGA AK28 AD11
1: Disable MLPS, enable GPIO PINSTRAP XTALOUT NC_AUX2N
XO_IN AC22 AD20
3D3V_VGA_S0 XO_IN2 AB22
XO_IN NC#AD20
AC20
0 1 0 4530 2000 Hynix (1G) 128M x 16 x 4pcs SK H5TC2G63FFR-11C 2Gb 1Ghz gDDR3
XO_IN2 NC#AC20
AE16
1 0 0 4530 4990 Micron (1G) 128M x 16 x 4pcs MIC MT41J128M16JT-093G:K 2Gb 1GhzgDDR3
1

NC#AE16
AD16
R7935 NC#AD16
SEYMOUR/FutureASIC
DY Do Not Stuff
GPU_DPLUS NC_DDCVGACLK
AC1
0 0 1 8450 2000 Samsung (2G) 256M x 16 x 8pcs SS K4W4G1646E-BC1A 4Gb 900(1G) Gddr3
[26] GPU_DPLUS T4 AC3
GPU_DMINUS DPLUS THERMAL NC_DDCVGADATA
[26] GPU_DMINUS T2
2

MLPS_EN# DMINUS
XTL_27M_X2_VGA C7903 1 2 Do Not Stuff
OPS 1D8V_VGA_S0 0 1 1 6980 4990 Hynix (2G) 256M x 16 x 8pcs SK H5TC4G63CFR-N0C 4Gb900Mhz gDDR3
1

X7901 R7936
13mA R5
GPIO28_FDO
AD17
TSVDD
OPS Do Not Stuff AC17 1 0 1 3240 5620 Micron (2G) 256M x 16 x 8pcs MC MT41J256M16HA-093G:E 4Gb 900(1G) gDDR3
1

C7904 TSVSS
2 3
2

OPS Do Not Stuff

2

R7901 Capacitor
2

OPS Do Not Stuff Do Not Stuff Resistor

1 4 OPS 680nF: PN/78.68421.5BL
OPS 4.75Kohm: PN/64.47515.6DL
1

A A
82nF: PN/78.82321.2FL
Do Not Stuff 8.45Kohm: PN/64.84515.6DL
10nF: PN/78.10324.L0L
XTL_27M_X1_VGA C7901 1 2 Do Not Stuff
OPS 2Kohm: PN/64.20015.6DL
4.53Kohm: PN/64.45315.6DL
：
Iris SKL UMA
Note 6.98Kohm: PN/64.69815.6DL
C7501 and C7503 values determine CL value of the oscillation circuit. 4.99Kohm: PN/64.49915.6DL Wistron Corporation
If Negative Resistance is too low, that may cause crystal resonator stop oscillation or not easy 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
3.24Kohm: PN/64.32415.6DL Taipei Hsien 221, Taiwan, R.O.C.
to oscillate.
If Drive Level is too high, that may cause crystal resonator abnormal oscillation or damaged 3.4Kohm: PN/64.34015.6DL Title

the main body of quartz. 5.62Kohm: PN/64.56215.6DL 079_GPU (4/5) GPIO/STRAP

Size Project Name Rev
10Kohm: PN/64.10025.6DL <Project Name> SA
Date: Wednesday, September 09, 2015 Sheet 79 of 105
5 4 3 2 1
 5 4 3 2 1

AMD ORB 10U x 1 LF145M 10U x 1

2.2U x 5 1U x 10 GPU1D 4 OF 7 1D8V_VGA_S0 0D95V_VGA_S0

1D35V_VGA_S0 0.1U x 1 0.1U x 1

AM30
0.1A
0.01U x1 Vinafix.com
0.01U x 1 PCIE_PVDD

PCIE
MEM I/O
1A

1
H13 AB23 C8008 C8002 C8016
VDDR1 NC#AB23 Do Not Stuff Do Not Stuff Do Not Stuff
H16 VDDR1 NC#AC23 AC23

1
D C8001 C8003 C8009 C8004 H19 AD24 OPS OPS OPS D

2
Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff VDDR1 NC#AD24
J10 VDDR1 NC#AE24 AE24
2 OPS OPS OPS OPS J23 AE25

2
VDDR1 NC#AE25
J24 VDDR1 NC#AE26 AE26
1D35V_VGA_S0 J9 AF25
VDDR1 NC#AF25
K10 VDDR1 NC#AG26 AG26
K23 AMD ORB 10U x 1 LF145M 10U x 1 0D95V_VGA_S0
VDDR1
Do Not Stuff K24 VDDR1 2.5A 1U x 6 1U x 6
1

1
C8042 C8005 C8006 C8014 K9 L23
Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff C8007 VDDR1 PCIE_VDDC
L11 VDDR1 PCIE_VDDC L24

1
OPS OPS OPS OPS OPS L12 L25 C8010 C8011 C8012 C8013 C8015 C8057
2

2
VDDR1 PCIE_VDDC Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff
L13 VDDR1 PCIE_VDDC L26
L20 M22 OPS OPS OPS OPS OPS OPS

2
VDDR1 PCIE_VDDC
L21 VDDR1 PCIE_VDDC N22
L22 VDDR1 PCIE_VDDC N23
PCIE_VDDC N24
1

1
C8034 C8031 C8032 C8033 R22
Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff PCIE_VDDC
PCIE_VDDC T22
OPS OPS OPS OPS LEVEL VGA_CORE
U22 AMD ORB 10U x 6 LF145M 4.7U x 6
2

2
TRANSLATION PCIE_VDDC
1D8V_VGA_S0
13mA AA20
PCIE_VDDC V22
2.2U x 16 1U x 20
VDD_CT
AA21 VDD_CT

1
C8017 AB20 AA15 C8018 C8019 C8020 C8021 C8022 C8023
Do Not Stuff VDD_CT CORE VDDC Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff
AB21 VDD_CT VDDC N15
OPS N17 OPS OPS OPS OPS OPS OPS

2
VDDC
VDDC R13
I/O
25mA AA17
VDDC R16
R18
3D3V_VGA_S0 VDDR3 VDDC VGA_CORE
C
AA18 VDDR3 VDDC Y21 NC on JET C
AB17 VDDR3 VDDC T12
AB18 T15 AB13 U10 W9 Y9 W10 T10 AC14 AB12 AB11 AC11 AC13
VDDR3 VDDC
VDDC T17

1
C8024 V12 T20 C8025 C8026 C8027 C8028 C8029 C8030
Do Not Stuff NC_VDDR4#V12 VDDC Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff
Y12 NC_VDDR4#Y12 VDDC U13
OPS U12 U16 OPS OPS OPS OPS OPS OPS
2

2
NC_VDDR4#U12 VDDC
VDDC U18
VDDC V21
VDDC V15
V17 VGA_CORE
VDDC
VDDC V20

POWER
Memory phase lock loop power: Dedicated VDDC Y13
VDDC Y16
analogue power in for memory PLLs

1
Y18 C8035 C8036 C8037 C8058 C8059 C8060
1D8V_VGA_S0 MPV18 VDDC Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff
VDDC AA12
M11 OPS OPS OPS OPS OPS OPS

2
L8001 OPS 2 Do Not Stuff VDDC
1 VDDC N12
VDDC U11
1

C8043 C8044 C8045

Do Not Stuff Do Not Stuff Do Not Stuff
OPS OPS OPS PLL
2

VGA_CORE
0D95V_VGA_S0

R21
1.4A
BIF_VDDC

1
MPV18 U21 C8066 C8061 C8062
BIF_VDDC

1
Engine phase loop power: Dedicated analogue C8065 Do Not Stuff Do Not Stuff Do Not Stuff
90mA L8 Do Not Stuff OPS OPS OPS

2
power pin for engine PLL MPLL_PVDD OPS

2
B 1D8V_VGA_S0 SPV18 B
ISOLATED
SPV18
L8002 OPS 2 Do Not Stuff
CORE I/O
5A
1
75mA H7
VDDCI M13
M15
SPLL_PVDD VDDCI
1

C8053 C8054 M16 AMD ORB 10U x 2 LF145M 4.7U x 2

Do Not Stuff Do Not Stuff VDDCI
VDDCI M17
OPS OPS SPV10 M18 1U x 3 1U x 3 VGA_CORE
2

VDDCI
100mA H8
VDDCI M20
M21
0.1U x2 0.1U x 2
SPLL_VDDC VDDCI
VDDCI N20

1
J7 C8046 C8047 C8048 C8049 C8050
SPLL_PVSS Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff
Engine phase loop power: Dedicated digital
OPS OPS OPS OPS OPS

2
power pin for engine PLL
0D95V_VGA_S0 SPV10 Do Not Stuff
OPS VGA_CORE
L8003 1 OPS 2 Do Not Stuff

Do Not Stuff

Do Not Stuff
1

C8055 C8056

C8051

C8052
1

1
Do Not Stuff Do Not Stuff
OPS OPS OPS OPS
2

2
VGA_CORE
A Iris SKL UMA A
1

1
C8040 C8041 C8063 C8064 C8038 C8039
Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Wistron Corporation
OPS OPS OPS OPS OPS OPS 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
2

2
Taipei Hsien 221, Taiwan, R.O.C.

Title

080_GPU (5/5) PWR/GND

Size Project Name Rev
<Project Name> SA
Date: Tuesday, May 26, 2015 Sheet 80 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = dGPU Data Bits 31:0 RANK 0

1D35V_VGA_S0 VRAM1
DQA0_[31..0] [78] 1D35V_VGA_S0 VRAM2
DQA0_14 DQA0_[31..0] [78]
B2 VDD DQ0 E3
D9 F7 DQA0_12 B2 E3 DQA0_24
VDD DQ1 DQA0_15 VDD DQ0 DQA0_28
G7 VDD DQ2 F2 D9 VDD DQ1 F7
K2 F8 DQA0_8 DQ1 G7 F2 DQA0_25
VDD DQ3 DQA0_9 VDD DQ2 DQA0_29
K8 H3 K2 F8
N1
N9
VDD
VDD
VDD
Vinafix.com
DQ4
DQ5
DQ6
H8
G2
DQA0_11
DQA0_13
K8
N1
VDD
VDD
VDD
DQ3
DQ4
DQ5
H3
H8
DQA0_26
DQA0_30
DQ3

R1 H7 DQA0_10 N9 G2 DQA0_27
1D35V_VGA_S0 VDD DQ7 DQA0_2 VDD DQ6 DQA0_31
D R9 VDD DQ8 D7 R1 VDD DQ7 H7 D
C3 DQA0_5 DQ0 1D35V_VGA_S0 R9 D7 DQA0_21
DQ9 DQA0_0 VDD DQ8 DQA0_19
A1 VDDQ DQ10 C8 DQ9 C3
A8 C2 DQA0_4 A1 C8 DQA0_23
VDDQ DQ11 DQA0_3 VDDQ DQ10 DQA0_16 DQ2
C1 VDDQ DQ12 A7 A8 VDDQ DQ11 C2
C9 A2 DQA0_7 C1 A7 DQA0_20
D2
VDDQ DQ13
B8 DQA0_1 C9
VDDQ DQ12
A2 DQA0_17 Place close VRAM2 VDD ball
VDDQ DQ14 DQA0_6 VDDQ DQ13 DQA0_22
E9 VDDQ DQ15 A3 D2 VDDQ DQ14 B8 1D35V_VGA_S0
F1 E9 A3 DQA0_18 0.1uF(X7R)
VDDQ VDDQ DQ15
H2 F3 F1
H9
VDDQ LDQS
G3
QSAP_1 [78] DQ1 H2
VDDQ
F3
K0402 ×4
VDDQ LDQS# QSAN_1 [78] VDDQ LDQS QSAP_3 [78] DQ3
H9 VDDQ LDQS# G3 QSAN_3 [78]

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff
UDQS C7 QSAP_0 [78]
FBA_VREF_0 H1 B7 DQ0 C7
VREFDQ UDQS# QSAN_0 [78] UDQS QSAP_2 [78]

1
R7808 M8 FBA_VREF_0 H1 B7 DQ2 C8154 C8156 C8155 C8157
VREFCA VREFDQ UDQS# QSAN_2 [78]
1 OPS 2 FBA_ZQ0 L8 ZQ ODT K1 ODTA0 [78] R7811 M8 VREFCA OPS OPS OPS OPS
Do Not Stuff 1 OPS 2FBA_ZQ1 L8 K1 ODTA0 [78]

2
Do Not Stuff ZQ ODT
CS# L2 CSA0#_0 [78]
[78,82] MAA0 N3 A0 RESET# T2 DRAM_RST [78,82] CS# L2 CSA0#_0 [78]
[78,82] MAA1 P7 A1 [78,82] MAA0 N3 A0 RESET# T2 DRAM_RST [78,82]
[78,82] MAA2 P3 A2 NC#J1 J1 [78,82] MAA1 P7 A1
[78,82] MAA3 N2 A3 NC#J9 J9 [78,82] MAA2 P3 A2 NC#J1 J1
[78,82] MAA4 P8 A4 NC#L1 L1 [78,82] MAA3 N2 A3 NC#J9 J9
[78,82] MAA5 P2 A5 NC#L9 L9 [78,82] MAA4 P8 A4 NC#L1 L1
[78,82] MAA6 R8 A6 NC#M7 M7 MAA15 [78,82] [78,82] MAA5 P2 A5 NC#L9 L9
[78,82] MAA7 R2 A7 NC#T3 T3 MAA13 [78,82] [78,82] MAA6 R8 A6 NC#M7 M7 MAA15 [78,82]
[78,82] MAA8 T8 A8 NC#T7 T7 MAA14 [78,82] [78,82] MAA7 R2 A7 NC#T3 T3 MAA13 [78,82]
[78,82] MAA9 R3 A9 [78,82] MAA8 T8 A8 NC#T7 T7 MAA14 [78,82]
[78,82] MAA10 L7 A10/AP [78,82] MAA9 R3 A9
C R7 A9 L7 C
[78,82]
[78,82]
MAA11
MAA12 N7
A11 VSS
B3
[78,82]
[78,82]
MAA10
MAA11 R7
A10/AP
A9
Place close VRAM1VDDQ ball
A12/BC# VSS A11 VSS
VSS E1 [78,82] MAA12 N7 A12/BC# VSS B3 1D35V_VGA_S0
Do Not Stuff VSS G8 VSS E1 0.1uF(X7R)
[78,82] MAA_BA0 M2 BA0 VSS J2 Do Not Stuff VSS G8
K0402 ×4
[78,82] MAA_BA1 N8 BA1 VSS J8 [78,82] MAA_BA0 M2 BA0 VSS J2
[78,82] MAA_BA2 M3 BA2 VSS M1 [78,82] MAA_BA1 N8 BA1 VSS J8

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff
VSS M9 [78,82] MAA_BA2 M3 BA2 VSS M1
VSS P1 VSS M9

1
DQ1 C8149 C8150 C8151 C8152
[78] DQMA1 E7 LDM VSS P9
DQ3
OPS VSS P1
DQ0 [78] DQMA0 D3 UDM VSS T1 [78] DQMA3 E7 LDM VSS P9 OPS OPS OPS OPS
OPS T9 [78] DQMA2 D3 T1

2
VSS DQ2 UDM VSS
VSS T9
[78] CLKA0 J7 CK VSSQ B1
[78] CLKA0# K7 CK# VSSQ B9 [78] CLKA0 J7 CK VSSQ B1
VSSQ D1 [78] CLKA0# K7 CK# VSSQ B9
[78] CKEA0 CKEA0 K9 D8 D1
CKE VSSQ CKEA0 VSSQ
VSSQ E2 [78] CKEA0 K9 CKE VSSQ D8
VSSQ E8 VSSQ E2
[78] W EA0# L3 WE# VSSQ F9 VSSQ E8
[78] CASA0# K3 CAS# VSSQ G1 [78] W EA0# L3 WE# VSSQ F9
[78] RASA0# J3 RAS# VSSQ G9 [78] CASA0# K3 CAS# VSSQ G1
[78] RASA0# J3 RAS# VSSQ G9

Check Do Not Stuff R7805 R7810

Do Not Stuff
Single Rank, 40.2 Ohm = 64.40R25.6DL
Dual Rank, 80.6 Ohm = 64.80R65.6DL
B Frame Buffer Patition A-Lower Half B
CLKA0 CLKA0#
1D35V_VGA_S0

1
R7805 R7806
Do Not Stuff Do Not Stuff
1

1.0uF(X7R) 10uF(X5R) Dual/Single Dual/Single

1D35V_VGA_S0 Place close VRAM2VDDQ ball K0603 ×8 M0805 ×2

2
OPS R7807
Do Not Stuff
CLKA0_CLKA0#

1
C8146
2

FBA_VREF_0 OPS OPS OPS OPS OPS OPS OPS OPS OPS OPS Do Not Stuff
Dual/Single

2
1

Do Not Stuff
C8136

Do Not Stuff
C8137

Do Not Stuff
C8144

Do Not Stuff
C8145

Do Not Stuff
C8138

Do Not Stuff
C8142

Do Not Stuff
C8143

Do Not Stuff
C8139
1

1
Do Not Stuff

Do Not Stuff
Do Not Stuff
C8147

OPS OPS R7801

Do Not Stuff
C8140 C8141
2

2
2

1.0uF(X7R) 10uF(X5R)
1D35V_VGA_S0 Place close VRAM1 VDD ball K0603 ×8 M0805 ×2
Iris SKL UMA
A A

OPS OPS OPS OPS OPS OPS OPS OPS OPS OPS Wistron Corporation
Do Not Stuff
C8129

Do Not Stuff
C8130

Do Not Stuff
C8148

Do Not Stuff
C8158

Do Not Stuff
C8132

Do Not Stuff
C8135

Do Not Stuff
C8153

Do Not Stuff
C8131

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

1

1
Do Not Stuff

Do Not Stuff
Taipei Hsien 221, Taiwan, R.O.C.
C8133 C8134
Title
2

2
GPU-VRAM1,2 (1/4)
Size Document Number Rev
A3
Iris2 SKL-U A00
Date: W ednesday, September 09, 2015 Sheet 81 of 105

5 4 3 2 1
 5 4 3 2 1

Main Func = dGPU Data Bits 63:32 RANK 0

1D35V_VGA_S0 VRAM3 1D35V_VGA_S0 VRAM4 Place close VRAM1VDDQ ball
DQA1_[31..0] [78] DQA1_[31..0] [78]
1D35V_VGA_S0
B2 E3 DQA1_22 B2 E3 DQA1_2 0.1uF(X7R)
VDD DQ0 DQA1_17 VDD DQ0 DQA1_7
D9 F7 D9 F7
G7
VDD DQ1
F2 DQA1_23 G7
VDD DQ1
F2 DQA1_3 K0402 ×4
K2
VDD
VDD Vinafix.com
DQ2
DQ3 F8 DQA1_19 DQ6 K2
VDD
VDD
DQ2
DQ3 F8 DQA1_4

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff
K8 H3 DQA1_20 K8 H3 DQA1_1 DQ4
VDD DQ4 DQA1_16 VDD DQ4 DQA1_5
N1 VDD DQ5 H8 N1 VDD DQ5 H8

1
D N9 G2 DQA1_21 N9 G2 DQA1_0 C8226 C8227 C8228 C8229 D
VDD DQ6 DQA1_18 VDD DQ6 DQA1_6
1D35V_VGA_S0
R1 VDD DQ7 H7
DQA1_28 1D35V_VGA_S0
R1 VDD DQ7 H7
DQA1_15
OPS OPS OPS OPS
R9 D7 R9 D7

2
VDD DQ8 DQA1_27 VDD DQ8 DQA1_8
DQ9 C3 DQ9 C3
A1 C8 DQA1_24 DQ7 A1 C8 DQA1_14
VDDQ DQ10 DQA1_30 VDDQ DQ10 DQA1_11 DQ5
A8 VDDQ DQ11 C2 A8 VDDQ DQ11 C2
C1 A7 DQA1_31 C1 A7 DQA1_12
VDDQ DQ12 DQA1_29 VDDQ DQ12 DQA1_10
C9 VDDQ DQ13 A2 C9 VDDQ DQ13 A2
D2 B8 DQA1_25 D2 B8 DQA1_13
VDDQ DQ14 DQA1_26 VDDQ DQ14 DQA1_9
E9 VDDQ DQ15 A3 E9 VDDQ DQ15 A3
F1 VDDQ F1 VDDQ
H2 VDDQ LDQS F3 QSAP_6 [78] H2 VDDQ LDQS F3 QSAP_4 [78]
H9 G3 DQ6 H9 G3 DQ4
VDDQ LDQS# QSAN_6 [78] VDDQ LDQS# QSAN_4 [78]
C7 C7
Place close VRAM1VDDQ ball
UDQS QSAP_7 [78] DQ7 UDQS QSAP_5 [78] DQ5
FBA_VREF_1 H1 B7 FBA_VREF_1 H1 B7
VREFDQ UDQS# QSAN_7 [78] VREFDQ UDQS# QSAN_5 [78] 1D35V_VGA_S0
R8205 M8 R8203 M8 0.1uF(X7R)
FBA_ZQ2 VREFCA FBA_ZQ3 VREFCA
1 OPS 2 L8 K1 ODTA1 [78] 1 OPS 2 L8 K1 ODTA1 [78]
Do Not Stuff ZQ ODT Do Not Stuff ZQ ODT K0402 ×4
CS# L2 CSA1#_0 [78] CS# L2 CSA1#_0 [78]

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff
[78,81] MAA0 N3 A0 RESET# T2 DRAM_RST [78,81] [78,81] MAA0 N3 A0 RESET# T2 DRAM_RST [78,81]
[78,81] MAA1 P7 A1 [78,81] MAA1 P7 A1

1
[78,81] MAA2 P3 J1 [78,81] MAA2 P3 J1 C8222 C8224 C8223 C8225
A2 NC#J1 A2 NC#J1
[78,81] MAA3 N2 A3 NC#J9 J9 [78,81] MAA3 N2 A3 NC#J9 J9 OPS OPS OPS OPS
[78,81] MAA4 P8 L1 [78,81] MAA4 P8 L1

2
A4 NC#L1 A4 NC#L1
[78,81] MAA5 P2 A5 NC#L9 L9 [78,81] MAA5 P2 A5 NC#L9 L9
[78,81] MAA6 R8 A6 NC#M7 M7 MAA15 [78,81] [78,81] MAA6 R8 A6 NC#M7 M7 MAA15 [78,81]
[78,81] MAA7 R2 A7 NC#T3 T3 MAA13 [78,81] [78,81] MAA7 R2 A7 NC#T3 T3 MAA13 [78,81]
[78,81] MAA8 T8 A8 NC#T7 T7 MAA14 [78,81] [78,81] MAA8 T8 A8 NC#T7 T7 MAA14 [78,81]
C R3 R3 C
[78,81] MAA9 A9 [78,81] MAA9 A9
[78,81] MAA10 L7 A10/AP [78,81] MAA10 L7 A10/AP
[78,81] MAA11 R7 A11 VSS A9 [78,81] MAA11 R7 A11 VSS A9
[78,81] MAA12 N7 A12/BC# VSS B3 [78,81] MAA12 N7 A12/BC# VSS B3
VSS E1 VSS E1
Do Not Stuff VSS G8 Do Not Stuff VSS G8
[78,81] MAA_BA0 M2 BA0 VSS J2 [78,81] MAA_BA0 M2 BA0 VSS J2
[78,81] MAA_BA1 N8 BA1 VSS J8 [78,81] MAA_BA1 N8 BA1 VSS J8
[78,81] MAA_BA2 M3 BA2 VSS M1 [78,81] MAA_BA2 M3 BA2 VSS M1
VSS M9 VSS M9
DQ6 VSS P1
DQ4
OPS VSS P1
[78] DQMA6 E7 LDM VSS P9 [78] DQMA4 E7 LDM VSS P9
[78] DQMA7 D3 UDM VSS T1 [78] DQMA5 D3 UDM VSS T1
DQ7 T9 DQ5 T9
VSS VSS
[78] CLKA1 J7 CK OPS VSSQ B1 [78] CLKA1 J7 CK VSSQ B1
[78] CLKA1# K7 CK# VSSQ B9 [78] CLKA1# K7 CK# VSSQ B9
VSSQ D1 VSSQ D1
[78] CKEA1 CKEA1 K9 D8 [78] CKEA1 CKEA1 K9 D8
CKE VSSQ CKE VSSQ
VSSQ E2 VSSQ E2
VSSQ E8 VSSQ E8
[78] W EA1# L3 WE# VSSQ F9 [78] W EA1# L3 WE# VSSQ F9
[78] CASA1# K3 CAS# VSSQ G1 [78] CASA1# K3 CAS# VSSQ G1
[78] RASA1# J3 RAS# VSSQ G9 [78] RASA1# J3 RAS# VSSQ G9

Do Not Stuff Do Not Stuff

B B

Frame Buffer Patition A-Lower Half

R7905 R7910
1D35V_VGA_S0
1.0uF(X7R) 10uF(X5R) Single Rank, 40.2 Ohm
1D35V_VGA_S0 Place close VRAM2VDDQ ball K0603 ×8 M0805 ×2 Dual Rank, 80.6 Ohm
1

CLKA1 CLKA1#
OPS R8204 OPS OPS OPS OPS OPS OPS OPS OPS OPS OPS

1
Do Not Stuff
Do Not Stuff
C8207

Do Not Stuff
C8209

Do Not Stuff
C8216

Do Not Stuff
C8217

Do Not Stuff
C8210

Do Not Stuff
C8212

Do Not Stuff
C8215

Do Not Stuff
C8211
R8201 R8202
2

1
Do Not Stuff

Do Not Stuff
FBA_VREF_1 Do Not Stuff Do Not Stuff
C8213 C8214 Dual/Single Dual/Single
1

2
1
Do Not Stuff
C8230

CLKA1_CLKA1#
OPS OPS R8206

1
Do Not Stuff C8221
2

Do Not Stuff
2

Dual/Single

2
1.0uF(X7R) 10uF(X5R)
1D35V_VGA_S0 Place close VRAM1 VDD ball K0603 ×8 M0805 ×2
Iris SKL UMA
A A

OPS OPS OPS OPS OPS OPS OPS OPS OPS OPS Wistron Corporation
Do Not Stuff
C8202

Do Not Stuff
C8201

Do Not Stuff
C8218

Do Not Stuff
C8220

Do Not Stuff
C8204

Do Not Stuff
C8208

Do Not Stuff
C8219

Do Not Stuff
C8203

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

1

1
Do Not Stuff

Do Not Stuff

Taipei Hsien 221, Taiwan, R.O.C.

C8205 C8206
Title
2

GPU-VRAM3,4 (2/4)
Size Document Number Rev
A3
Iris2 SKL-U A00
Date: W ednesday, September 09, 2015 Sheet 82 of 105

5 4 3 2 1
 5 4 3 2 1

Main Func = dGPU Data Bits 31:0 RANK 1

Note : Dual Rank need add Vinafix.com

D D

C C

B B

A Iris SKL UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU-VRAM5,6 (3/4)
Size Document Number Rev
A3
Iris2 SKL-U A00
Date: Tuesday, May 26, 2015 Sheet 83 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = dGPU Data Bits 63:32 RANK 1

Vinafix.com
D D

C C

B B

Iris SKL UMA

A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU-VRAM7,8 (4/4)
Size Document Number Rev
A3
Iris2 SKL-U A00
Date: Tuesday, May 26, 2015 Sheet 84 of 105

5 4 3 2 1
 5 4 3 2 1

DCBATOUT PWR_DCBATOUT_VGA_CORE2 DCBATOUT PWR_DCBATOUT_VGA_CORE1

AMD MESO 1
PG8501
2 1
PG8511
2

1
OPS Do Not Stuff Do Not Stuff
PR8502
Do Not Stuff Do Not Stuff PG8502 PG8512
PR8501 1 2 1 2
OPS

2
Do Not Stuff Do Not Stuff
PG8503 PG8513
1 2 1 2
Main source: 84.03660.037

PWR_VGA_CORE_UGATE_LX_NB
3D3V_VGA_S0 PR8503 1 2 Do Not Stuff OPS EN/DEM_VGA
PC8502 1 Do Not Stuff PWR_DCBATOUT_VGA_CORE1

Vinafix.com
2 OPS

PWR_VGA_CORE_LGATE_NB
Do Not Stuff Do Not Stuff
PG8504 PG8514
1 2 1 2
PWR_VGA_CORE_VDDIO PC8527 PC8526
1D8V_VGA_S0 PR8546 1 2 Do Not Stuff MESO PU8502 PU8503

1
OPS

1
OPS

2
Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff

Do Not Stuff
D PR8505 1 2 Do Not Stuff ESO PC8528 PC8529 PC8530 D
3D3V_VGA_S0 PG8505 PG8515

Do Not Stuff

Do Not Stuff
PC8503 1 2 Do Not Stuff OPS 2 2 OPS OPS OPS
1 2 1 2

Do Not Stuff

Do Not Stuff
3 3

1
1 4 1 4
Do Not Stuff Do Not Stuff

PU8201_36
10 10

PU8201_39
PG8506 PG8516 OPS_84.03660.037
9 9
1 2 1 2
7
DY 7
8 6 8 6
Do Not Stuff Do Not Stuff
5V_S5 5 5

40

39

38

37

36

35

34

33

32

31
PU8501 Do Not Stuff Do Not Stuff

ISUMP_NB

ISUMN_NB

VSEN_NB

FB_NB

COMP_NB

PGOOD_NB

LGATE_NB

PHASE_NB

UGATE_NB

BOOT_NB
5V_S5

PC8507
PR8507
PR8506 1 OPS 2 PWR_VGA_CORE_NTC_NB 1 30 PWR_VGA_CORE_BOOT2 1 OPS 2PWR_VGA_CORE__BOOT2_1 1 OPS
2 PR8510
Do Not Stuff NTC_NB BOOT2 Do Not Stuff Do Not Stuff TDC=34A

1
PR8508 1 OPS 2 PWR_VGA_CORE_IMON_NB 2 29 PWR_VGA_CORE_UGATE2 Do Not Stuff 1 2 PWR_VGA_CORE_UGATE1
IMON_NB UGATE2
Do Not Stuff
PR8509 1 PWR_VGA_CORE_SVC PWR_VGA_CORE_PHASE2
OPS PC8508 Do Not Stuff OCP<??A
[79] VGA_SVC 2 3 28
SVC PHASE2
OPS Do Not Stuff OPS
[79] TOPAZ_OCP PR8511 1 2 PWR_VGA_CORE_VR_HOT# 4 27 PWR_VGA_CORE_LGATE2 VGA_CORE

2
Do Not Stuff VR_HOT# LGATE2
OPS
PR8512 1 2 PWR_VGA_CORE_SVD 5 26 PL8501 OPS
[79] VGA_SVD SVD VDDP
OPS Do Not Stuff Do Not Stuff PWR_VGA_CORE_PHASE1 1 2
6 25 PWR_VGA_CORE_VDD 1 2
PWR_VGA_CORE_VDDIO VDDIO VDD Do Not Stuff

Do Not Stuff

Do Not Stuff
PC8509 Do Not Stuff PT8506 PT8507

1
PR8513 1 PWR_VGA_CORE_SVT PWR_VGA_CORE_LGATE1 PWR_VGA_CORE_LGATE1
[79] VGA_SVT 2 7
SVT LGATE1
24 Do Not Stuff

1
Do Not Stuff

Do Not Stuff
OPS Do Not Stuff OPS PR8541
DY

2
OPS OPS

PG8507
PR8514 1 2 PWR_VGA_CORE_ENABLE 8 23 PWR_VGA_CORE_PHASE1 Do Not Stuff
ENABLE PHASE1

PG8508
OPS Do Not Stuff

2
PWR_VGA_CORE_PWROK PWR_VGA_CORE_UGATE1
9 Do Not Stuff 22 PC8510

2
PWROK UGATE1 PR8515 PWR_VGA_SNUB1

1
PD8501 PWR_VGA_CORE_IMON 10 21 PWR_VGA_CORE_BOOT1 1 OPS 2PWR_VGA_CORE__BOOT1_1 1 2

1
IMON BOOT1
[20,86] DGPU_PWR_EN K DY AEN/DEM_VGA Do Not Stuff OPS PC8506 DY
1

Do Not Stuff Do Not Stuff

PWR_VGA_CORE_PH1
41

PWR_VGA_CORE_VO1
Do Not Stuff GND 3D3V_VGA_S0

2
1

PGOOD
PR8516

ISUMN
ISUMP

COMP
ISEN2

ISEN1

VSEN
C Do Not Stuff PC8511 C
NTC

RTN
[86] EN/DEM_VGA

1
OPS Do Not Stuff

FB
2

OPS
PE_GPIO1 is for OPS PR8518
11

12

13

14

15

16

17

18

19

20
Do Not Stuff PR8517
turning off PWR IC OPS PWR_VGA_CORE_ISUMP 1 OPS 2

2
PWR_VGA_CORE_PGOOD PR8520 1 Do Not Stuff
PWR_VGA_CORE_NTC

PWR_VGA_CORE_ISEN2

PWR_VGA_CORE_ISEN1

PWR_VGA_CORE_ISUMP

PWR_VGA_CORE_ISUMN

PWR_VGA_CORE_VSEN

PWR_VGA_CORE_RTN
2 DGPU_PWROK [19,24,79]
OPS Do Not Stuff

1
PR8519
PC8512 PWR_VGA_CORE_ISEN1 1 OPS 2
Do Not Stuff Do Not Stuff

2
OPS OPS
PC8513 PWR_VGA_CORE_VSUM- PR8521 1 2 Do Not Stuff
PR8523
PWR_VGA_CORE_FB 2 OPS 1 PWR_VGA_CORE_FB_R 2 OPS1
Do Not Stuff OPS
2

Do Not Stuff PWR_VGA_CORE_ISEN2 PR8522 1 2 Do Not Stuff

PR8524 PR8525
PC8514
Do Not Stuff OPS
PWR_VGA_CORE_COMP PWR_VGA_CORE_VSEN
OPS 2 1 1 OPS 2
PWR_DCBATOUT_VGA_CORE2
Main source: 84.03660.037
1

Do Not Stuff
Do Not Stuff
PR8526
PC8515 PR8527 PC8516
2 OPS1PWR_VGA_CORE_FB2_R1 OPS 2 1 OPS 2 PWR_VGA_CORE_COMP_1 1 OPS 2
PU8504 PU8505 PC8520 PC8532
1

1
OPS

1
OPS

2
Do Not Stuff Do Not Stuff

Do Not Stuff
Do Not Stuff Do Not Stuff Do Not Stuff PC8519 PC8531 PC8521
Do Not Stuff

Do Not Stuff

Do Not Stuff
PR8528 2 2 OPS OPS OPS

Do Not Stuff

Do Not Stuff
Do Not Stuff DY 3 3

1
1

PC8517 PC8518 1 4 1 4
OPS OPS DY 10 10
2
Do Not Stuff
Do Not Stuff

9 9
OPS_84.03660.037
2

7 7
8 6 8 6
5 5
1

OPS
PR8529
Do Not Stuff PR8530 1 2 PR8531 1 2 Do Not Stuff OPS
OPS Do Not Stuff Do Not Stuff Do Not Stuff
1VGA_VSUM-_1
2

PR8532 VGA_VDD_RUN_FB_L 1
1

1
Do Not Stuff

B PC8522 PC8523 OPS TP8501 B

Do Not Stuff

OPS DY PC8501 2 1 Do Not Stuff

Do Not Stuff

OPS
2

PC8524 PWR_VGA_CORE_UGATE2
2

1DY 2
PR8533
Do Not Stuff Do Not Stuff VGA_VDD_RUN_FB_H 1
TP8502
OPS PR8534 1 2 PR8535 2 1 Do Not Stuff OPS VGA_CORE
OPS Do Not Stuff
2

PWR_VGA_CORE_VSUM- 1 OPS2 VGA_CORE

PR8536
Do Not Stuff PL8502 OPS
1

PWR_VGA_CORE_PHASE2 1 2
PC8525
Do Not Stuff Do Not Stuff
2

1
OPS PWR_VGA_CORE_LGATE2
PR8542
Do Not Stuff PT8508
PC8534 PC8535

1
Do Not Stuff
Do Not Stuff PG8509 PG8510

2
Do Not Stuff

Do Not Stuff

Do Not Stuff
DY OPS OPS OPS

Do Not Stuff
2

2
PWR_VGA_SNUB2

1
1
PC8533
PWR_VGA_CORE_PWROK PR8544 1 Do Not Stuff

PWR_VGA_CORE_PH2
2
OPS Do Not Stuff

PWR_VGA_CORE_VO2
DY

2
PWR_VGA_CORE_PGOOD

Do Not Stuff
PR8539
3D3V_S5 2 DY 1 PWR_VGA_CORE_EN_R# PR8537
PWR_VGA_CORE_ISUMP 1 OPS 2
Do Not Stuff
6

PQ8501 PR8538
VGA_CORE PWR_VGA_CORE_ISEN2 1
Do Not Stuff
Do Not Stuff
OPS
2
A DY A
1

PR8545 PWR_VGA_CORE_VSUM- PR8540 1 OPS 2

Do Not Stuff
DY Do Not Stuff
Iris SKL UMA
1

PWR_VGA_CORE_ISEN1 PR8543
EN/DEM_VGA PQ8206_3
1 OPS 2

Do Not Stuff Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A2
A00
Date: Wednesday, September 09, 2015 Sheet 85 of 105

5 4 3 2 1
 5 4 3 2 1

Main Func = dGPU 3D3V_S0 to 3D3V_VGA_S0 Transfer GPU PWR Sequencing dGPU Power Discharge Circuit
3D3V_S5 3D3V_VGA_S0 3D3V_VGAS0
3D3V_S0
PR8601 1 2 Do Not Stuff 3D3V_AUX_S5
0D95V_VGA_S0
DY 25mA
3D3V_VGA_S0
=> 0D95V_VGA_S0/1D8V_VGA_S0 0D95V_VGA_EN#
0D95V_VGA_S0 1D35V_VGA_S0
1 DY 2
1D35V_VGA_S0
S D

1
PQ8609 PR8608 D G S

1
PC8603 PR8606 PR8619 PC8601 Do Not Stuff => 1D35V_VGA_S0 Do Not Stuff

1
Do Not Stuff

Do Not Stuff
Do Not Stuff Do Not Stuff OPS

1
Do Not Stuff

Do Not Stuff
PC8605 PC8604 OPS DY
DY DY

2
1

1
PR8609 PQ8601 PR8607 PR8614
DY OPS
Vinafix.com DY DY

2
3.3V_ALW_1 DY Do Not Stuff => VGA_CORE Do Not Stuff DY Do Not Stuff Do Not Stuff

2
Do Not Stuff Need to fine tune.
2

3D3V_VGA discharge

2
2nd = 84.2N702.E3F
All the ASIC supplies must reach their respective nominal 3rd = 75.00601.07C S G D Need to fine tune. DIS_1D35V_VGA_S0

3.3V_RUN_VGA_1
D D

4
For power down sequence PQ8604 voltages withing 20ms of the start of the ramp-up sequence, 4th = 84.DMN66.03F
Do Not Stuff though a shorter ramp-up duration is preferred. The maximum

D
OPS 0D95V_VGA_EN 0D95V_VGA_S0_DISCHG
slew rate on all rails is 50mV/us.

3
PQ8602
Do Not Stuff
Do Not Stuff
RR8603
1 2 DGPU_PWR_EN_R
It is recommended that the 3.3V rail ramp up first. DY
[20,85] DGPU_PWR_EN
OPS

1
High Active 3D3V_AUX_S5
PR8616
VGA_CORE

S
Do Not Stuff OPS PC8602
Do Not Stuff
It is recommended that the 0.95V rail reach at least 90% of its PWR_VGA_CORE_EN#
2 DY 1

2
normal value no later than 2ms from the start of VDDC ramping VGA_CORE 1D35V_VGA_EN#
Need to fine tune.
up. Do Not Stuff

1
PQ8606 PR8610
Do Not Stuff DY Do Not Stuff
Do Not Stuff DY

2
2nd = 84.2N702.E3F
3rd = 75.00601.07C
4th = 84.DMN66.03F VGA_CORE_DISCHG

1D35V_VGA_S0 [20,85] DGPU_PWR_EN

3D3V_AUX_S5
1D8V_VGA_S0
1.35V +/- 3%. PR8618
PWR_1D8V_VGA_EN#
1D35V_S3 6.6A 1D35V_VGA_S0
2 DY 1
1D8V_VGA_S0
PQ8605 Do Not Stuff
Need to fine tune.

SIRA06DP-T1-GE3, SO-8 8 D S 1

1
7 D S 2
C Id=40A, Qg=22.5 nC 6 D S 3 1D8V_VGA_S0 PQ8610 PR8617 C

1
Rdson=2.5~3.5 mohm 5 D PC8610 Do Not Stuff DY Do Not Stuff
1

OPS Do Not Stuff

PC8609
Do Not Stuff DY
OPS G OPS
4

2
Do Not Stuff Do Not Stuff 1D8V_S5 1D8V_VGA_S0 2nd = 84.2N702.E3F
2

PQ8607
Do Not Stuff 3rd = 75.00601.07C
Do Not Stuff
4th = 84.DMN66.03F 1D8V_VGA_DISCHG
2rd = 84.08057.037 400mA OPS
S
1D35V_ENABLE_RC D

D
3D3V_S5_KBC 1D8V_VGA_EN
R8609

G
DY OPS OPSPC8635

1
1 2 1 2 OPS PR8650 PC8636

Do Not Stuff
Do Not Stuff Do Not Stuff DY PC8634 DY

Do Not Stuff
PR8615 For power on sequence Do Not Stuff

2
1

Do Not Stuff PR8651

1D8V_VGA_EN# 2
3D3V_AUX_S5 1D8V_VGA_EN_R#
OPS PC8608
Do Not Stuff
1 OPS 2
OPS 2015/02/09 modify
2

1D35V_VGA_EN# Do Not Stuff

1 2
PR8603 PQ8608
Do Not Stuff
PR8612 D G S 0D95V_VGA_EN1 OPS 2 1D8V_VGA_EN G OPS 2nd = 84.00102.031
Do Not Stuff

1
Do Not Stuff PC8612 D 3rd = 84.03413.B31
6

OPS Do Not Stuff

PQ8603 DCBATOUT S

2
Do Not Stuff OPS Do Not Stuff
Do Not Stuff
1

2nd = 84.2N702.E3F
3rd = 75.00601.07C S G D OPS PR8613
Do Not Stuff
4th = 84.DMN66.03F
OPS
1

0D95V_VGA_S0_PG 1 2 1D35V_VGA_EN
R8607
Do Not Stuff 1D35V_ENABLE

[DG-07158-001 Rev03]

B SYW232 for 0.95V_S5 PWR_0D95V_PVDD

PG8601
3D3V_S5 B

D8602
2 1
2

1
[85] EN/DEM_VGA PC8621 PC8622 PC8623 Do Not Stuff
DY

Do Not Stuff

Do Not Stuff

Do Not Stuff
3.3V_RUN_VGA_1 PG8602
OPS 3 OPS OPS
2 1

2
1D35V_ENABLE_RC 1
Do Not Stuff
Do Not Stuff
Do Not Stuff PU8601 Design Current =1.35A
3D3V_VGA_S0 5 3
2nd = 83.R2003.W81 NC#5 IN

OPS PWR_0D95V 0D95V_VGA_S0

3rd = 75.00054.A7D 8 1 PWR_0D95V_FB
SGND FB PL8601
0D95V_VGA_S0_PG PG8603
4th = 83.R2003.V81 PG
2
PWR_0D95V_PHASE
4
PGND LX
6 1 OPS 2 1 2
1

For power down sequence 9 7 0D95V_VGA_EN_R

PR8625 PGND EN Do Not Stuff
Do Not Stuff

1
Do Not Stuff OPS PG8604
OPS

1
Do Not Stuff PR8622 1 2
2015/02/09 modify Do Not Stuff Do Not Stuff
R1 OPS PC8624
2

Do Not Stuff
Do Not Stuff

2
PR8621

2
0D95V_VGA_EN 1 OPS 2 Do Not Stuff
PC8625 PC8626

1
PWR_0D95V_FB
1

Do Not Stuff

Do Not Stuff
PC8607
DY Do Not Stuff OPS OPS

2
2

1
PR8623 OPS
D8601
Do Not Stuff
0D95V_VGA_EN_R 2 R2
OPS 3 3.3V_RUN_VGA_1

2
1D8V_VGA_EN 1
3D3V_S5
Close Pin1
A Do Not Stuff A

Do Not Stuff
1

Vo=0.6x(1+R1/R2)
PR8624
OPS Do Not Stuff =0.6x(1+59/100)
2nd = 83.R2003.W81
=0.954
3rd = 75.00054.A7D Iris SKL UMA
2

0D95V_VGA_S0_PG
4th = 83.R2003.V81
For power down sequence 2015/02/09 modify Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

2015/02/09 modify GPU Discrete Power

Size Document Number Rev
A2 Iris2 SKL-U A00
Date: Wednesday, September 09, 2015 Sheet 86 of 105
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A Iris SKL UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Iris2 SKL-U A00
Date: Tuesday, May 26, 2015 Sheet 87 of 105
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A Iris SKL UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Iris2 SKL-U A00
Date: Tuesday, May 26, 2015 Sheet 88 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = UnusedParts

H6
H1 H2 H3 H4 H5 Do Not Stuff HCPU1 HCPU2 HCPU3
Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff
Vinafix.com
D D

1
1

1
Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff
Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff

Do Not Stuff Do Not Stuff

HGPU1 HGPU2 Do Not Stuff SPR2 H7
HGPU3 Do Not Stuff

SPRING-24-GP-U
OPS OPS
OPS

1
1

1
1
Do Not Stuff
Do Not Stuff Do Not Stuff
Do Not Stuff 34.45T31.001

20140806 20140801 david

C 20140815 david C

Main Func = EMICapacitors

Mind the voltage rating of the caps.

AUD_AGND
DCBATOUT 1D35V_VGA_S0

EC9708 EC9709 EC9710 EC9727 EC9725 EC9726 EC9730 EC9728 EC9729 EC9731 EC9739 EC9744 EC9743 EC9745
1

1
EC9701 EC9702 EC9703 EC9704 EC9705 EC9706 EC9707
DY DY DY DY DY DY DY DY DY DY DY DY
SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff
Do Not Stuff

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP
2

2
Do Not Stuff

Do Not Stuff

Do Not Stuff
EC9711 EC9714
1

EC9717 EC9712 EC9713 EC9716 EC9715

B B
DY DY DY DY
SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP
Do Not Stuff

Do Not Stuff

VGA_CORE
Do Not Stuff

Do Not Stuff
2

DCBATOUT

EC9740 EC9741 EC9742 EC9747 EC9748 EC9749 EC9746 EC9750 EC9751 EC9752 EC9753

1
SCD1U25V2KX-GP

SCD1U25V2KX-GP
Do Not Stuff
DY DY DY DY DY DY

SCD1U25V2KX-GP

SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
2

2
Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff
5V_S0

EC9720 EC9719 EC9718 EC9723 EC9721 EC9722 EC9724

1

DY DY DY DY DY DY DY
Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff
Do Not Stuff

Do Not Stuff
2

3D3V_S0 5V_S5

EC9737 EC9735 EC9736 EC9738 EC9734 EC9732 EC9733

1

1
A Iris SKL UMA A
DY DY DY DY DY DY DY
Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff
2

2
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

UNUSED PARTS/EMI Capacitors

Size Document Number Rev
A3
Iris2 SKL-U A00
Date: Tuesday, September 08, 2015 Sheet 89 of 105
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A Iris SKL UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Iris2 SKL-U A00
Date: Tuesday, May 26, 2015 Sheet 90 of 105
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A Iris SKL UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Iris2 SKL-U A00
Date: Tuesday, May 26, 2015 Sheet 91 of 105
5 4 3 2 1
 5 4 3 2 1

SSID = Finger Print

Vinafix.com
D D

C
Reserved C

B B

Iris SKL UMA

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Finger Print (Reserved)
Size Document Number Rev
A4
Iris2 SKL-U A00
Date: Tuesday, May 26, 2015 Sheet 92 of 102
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A Iris SKL UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)
Size Document Number Rev
A3
Iris2 SKL-U A00
Date: Tuesday, May 26, 2015 Sheet 93 of 105
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A Iris SKL UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)
Size Document Number Rev
A3
Iris2 SKL-U A00
Date: Tuesday, May 26, 2015 Sheet 94 of 105
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A Iris SKL UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)
Size Document Number Rev
A3
Iris2 SKL-U A00
Date: Tuesday, May 26, 2015 Sheet 95 of 105
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A Iris SKL UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)
Size Document Number Rev
A3
Iris2 SKL-U A00
Date: Tuesday, May 26, 2015 Sheet 96 of 105
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

Iris SKL UMA

A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

LVDS_Switch
Size Document Number Rev
A3
Iris2 SKL-U A00
Date: Tuesday, May 26, 2015 Sheet 97 of 105

5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

Iris SKL UMA

A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CRT_Switch
Size Document Number Rev
A3
Iris2 SKL-U A00
Date: Tuesday, May 26, 2015 Sheet 98 of 105

5 4 3 2 1
 5 4 3 2 1

Main Func = Debug

CPU XDP
Layout Note:
ROUTE WITH MINIMAL STUB WITH RESPECT TO CFG<0>
1D0V_S5 +V1.00A_XDP
CFG0 1 R9608 2 FIVR_EN_R XDP_PRSNT_PIN1
XDP XDP1
Do Not Stuff NP1
61 XDP
Layout Note: R9927 1 2 Do Not Stuff

Vinafix.com
1 2
ROUTE WITH MINIMAL STUB WITH RESPECT TO CFG<3> 62
3 4 CFG17
[16] XDP_PREQ#

1
R9902 XDP_PRDY# 5 6 CFG16 C9902
[16] XDP_PRDY#
CFG3 XDP_PRSNT_PIN1 Do Not Stuff
1 2
CFG0
7 8
CFG8
DY
D XDPDo Not Stuff 9 10 D

2
CFG1 11 12 CFG9
13 14
CFG2 15 16 CFG10
[17] PM_RSMRST# R9904 1 XDP 2 Do Not Stuff CFG3 17 18 CFG11
19 20
PM_RSMRST_PWRGD_XDP XDP_BPM0 21 22 CFG19
XDP_BPM1 23 24 CFG18
25 26

1
R9926 1 XDP 2 Do Not Stuff BP_PWRGD_RST# CFG4 27 28 CFG12 C9904
[17,24] SIO_PWRBTN# CFG5 CFG13 Do Not Stuff
29 XDP 30 DY

1
C9901 31 32 PLACE THIS NEAR CPU XDP CONNECTOR

2
Do Not Stuff CFG6 CFG14
XDP 1D0V_S5 CFG7
33 34
CFG15 1D0V_S5
35 36

2
37 38 C9905 1 2 Do Not Stuff
PM_RSMRST_PWRGD_XDP 39 40 PEG_CLK_XDP XDP
BP_PWRGD_RST# 41 42 PEG_CLK_XDP#
43 44
SPI0_MOSI_XDP_R (#543016)Routing of this signal to CFG[0] is OPTIONAL. FIVR_EN_R 45 46 TP_PMODE_XDP_RST_R_N XDP
SPI0_MOSI_XDP_R 47 48 XDP_DBRESET_XDP# R9925 1 2 Do Not Stuff
XDP_DBRESET# [17]
49 50

1
C9903 XDP_SMBDAT 51 52 PCH_JTAG_TDO
3D3V_S5 Do Not Stuff XDP_SMBCLK
XDP XDP_TCLK1
53 54 XDP_TRST# [4]
2 55 56
XDP_TDI [4]
57 58 XDP_TMS [4]
[4] XDP_TCLK
59 60 XDP_SPI0_IO2 [18]
63
1

64
R9909 NP2
Do Not Stuff
XDP
Do Not Stuff +V1.00A_XDP
2

R9910 Do Not Stuff

1
[18] SPI0_MOSI_XDP
1 XDP 2
3D3V_S5 R9932
Do Not Stuff XDP Do Not Stuff (#544669 Rev0.52) NC.
EE Note:
Use ZZ.00PAD.Q81 DUMMY PAD for MP. R9933

2
1
1 XDP 2 TP_PMODE_XDP_RST_R_N
C R9929 [6] ITP_PMODE C
R9911 1XDP 2 Do Not Stuff XDP_SMBDAT
[12,13,18,56,65] PCH_SMBDATA
R9912 1XDP XDP_SMBCLK
DY Do Not Stuff Do Not Stuff
[12,13,18,56,65] PCH_SMBCLK 2 Do Not Stuff

2
XDP_SPI0_IO2

1
R9931

R9913 1 PEG_CLK_XDP
DY Do Not Stuff
[18] PCIE_CLK_XDP_P XDP 2 Do Not Stuff
R9923 1 2 Do Not Stuff PEG_CLK_XDP#
[18] PCIE_CLK_XDP_N XDP

2
(#544669)

XDP_TCLK1 R9914 1 DY 2 Do Not Stuff

PCH_JTAG_TCK [4]

XDP_TCLK R9915 1 2 Do Not Stuff

DY XDP_TCK_JTAGX [4]

[4] XDP_TDO_CPU R9919 1XDP 2 Do Not Stuff

PCH_JTAG_TDO [4]

XDP_TDI R9916 1 DY 2 Do Not Stuff PCH_JTAG_TDI [4]

XDP_TMS R9917 1 2 Do Not Stuff

DY PCH_JTAG_TMS [4]

CFG[19:0]
[6] CFG[19:0]
XDP_BPM[3:0]
[4] XDP_BPM[3:0]

B B

XDP_BPM2 1 TP9901 Do Not Stuff

XDP_BPM3 1 TP9902 Do Not Stuff

+VCCIO
1

R9906
Do Not Stuff XDP
2

FIVR_EN_R

A A

Iris SKL UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_XDP;PCH_XDP
Size Document Number Rev
A2
Iris2 SKL-U A00
Date: Wednesday, September 09, 2015 Sheet 99 of 105
5 4 3 2 1
 5 4 3 2 1

CLK Block Diagram

Vinafix.com Intel CPU

D
Haswell/Broadwell ULT D

M_A_DIMA_CLK_DDR0
CK0 SA_CLK0
M_A_DIMA_CLK_DDR#0
CK0# SA_CLK#0
DDR3L DIMM1
M_A_DIMA_CLK_DDR1
CK1 SA_CLK1
M_A_DIMA_CLK_DDR#1
CK1# SA_CLK#1 CLK_PCIE_WLAN_P3
CLKOUT_PCIE_P2 REFCLKP0
WLAN
CLK_PCIE_WLAN_N3
CLKOUT_PCIE_N2 REFCLKN0 NGFF

LAN
CLK_PCIE_LAN_P4
RTL8106E/RTL8111G
CLKOUT_PCIE_P3 REFCLK_P

FBA_CLK0P CLK_PCIE_LAN_N4
C CK CLKOUT_PCIE_N3 REFCLK_N
VRAM1 FBA_CLK0N
VGA C

CK#
N15V-GM-S-A2
LANXIN
GB2-64 (23x23)
‧‧
CKXTAL1
FBA_CLK0P
CLK_PCIE_VGA#
CK FBA_CLK0 PEX_REFCLK# CLKOUT_PCIE_N4
FBA_CLK0N
VRAM2 CK#
FBA_CLK0# X3001
25MHz
CLK_PCIE_VGA
PEX_REFCLK CLKOUT_PCIE_P4
LANXOUT
CKXTAL2
FBA_CLK1P
CK 27MHZ_IN
XTAL_IN
VRAM3 CK#
FBA_CLK1N

X7601

‧‧
27MHz
FBA_CLK1P
CK FBA_CLK1
VRAM4 FBA_CLK1N
FBA_CLK1# XTAL_OUT
27MHZ_OUT Audio
CK#
RN2102
Realtek
HDA_BITCLK HDA_CODEC_BITCLK
HDA_BCLK/I2S0_SCLK BITCLK ALC3223
B SRN33J-5-GP-U B

RTC_X1
RTCX1

X1901
R5815
0R2J-2-GP
SUSCLK_NGFF
SUS_CLK NGFF
32.768KHz

RTC_X2
RTCX2
XTAL24_IN KBC
XTAL24_IN
NPCE285P
X1801
24MHz
SUSCLK/GPIO62

CLKOUT_LPC_1
SUS_CLK_PCH R1710 SUS_CLK
0R2J-2-GP
CLK_PCI_KBC_R R1805
‧ R2441
0R2J-2-GP
CLK_PCI_KBC
SUS_CLK_KBC
GPIO0/EXTCLK/F_SDIO3

LCLK/GPIOF5
0R2J-2-GP
XTAL24_OUT CLKOUT_LPC_0 CLK_PCI_LPC_R R1804 CLK_PCI_LPC
XTAL24_OUT 0R2J-2-GP
LPC

CLKOUT_ITPXDP#
CLKOUT_ITPXDP_P
Test Point
A A

Iris SKL UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CLK Block Diagram
Size Document Number Rev
A2
Iris2 SKL-U A00
Date: Tuesday, May 26, 2015 Sheet 100 of 105
5 4 3 2 1
 5 4 3 2 1

Change notes -
DATE VERSON DATE Page Modify List OWNER

Vinafix.com
D D

C C

B B

Iris SKL UMA

A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Change History
Size Document Number Rev
A3
Iris2 SKL-U A00
Date: Tuesday, May 26, 2015 Sheet 101 of 105

5 4 3 2 1
 5 4 3 2 1

SKL-U/Y Timing Diagram for G3 to S0/M0 [Non Deep Sx Platform]

[#543016 Rev0.9]
(DC mode) Red Words: Controlled by EC GPIO Tulip Skylake POWER UP SEQUENCE DIAGRAM (Deep Sx Platform)
Red: Power Rail
+RTC_VCC t01 >9ms
Orange: Output from KBC
1D0V_S5 5V_S5
RTC_RST# Light Blue: Output from CPU

DCBATOUT
Vin VDD
3D3V_AUX_S5 DC SI7121DN-T1-GE3
BT+ Page43
Battery EN SW +V1.00U_CPU(VCCST)
a Page43 Page43
Sense the power button status Press Power button SLG59M1470VTR
KBC_PWRBTN# Platform to KBC PSL_IN2 V8P10-5300M3-86A d Page40
PSL_OUT#(GPIO71) keep low AC +DC_IN SI7121DN-T1-GE3
3D3V_AUX_KBC a Adapter in S5_ENABLE 3D3V_S5
KBC GPIO34 control power on by 3V_5V_EN Page43
Page43

Vinafix.com
S5_ENABLE
AD+ 3D3V_S5
5V_S5 IN 1D5V_S0
5V_S5 & 3D3V_S5 need meet 0.7V difference Out
V5REF_Sus must be powered up before EN1 EN2
VccSus3_3, or after VccSus3_3 within 3D3V_S5 3D3V_S5
D
0.7 V. Also, V5REF_Sus must power 5V_S5 & 3D3V_S5 need meet 0.7V difference TLV70215DBVR
down after VccSus3_3, or before Charger EN Vin +VCCIO_VR D
VccSus3_3 within 0.7 V. +5VA_PCH_VCC5REFSUS Ta DCBATOUT TPS51225RUKR Lx
BQ24770RUYR VIN
DC/DC Page54
KBC GPIO43 to PCH
4 PM_SLP_S3# RT8068AZQWID
PM_RSMRST#(RSMRST#_RST) t05 >10ms (3.3V/5V) 5V_S5 EN VCCIO_PWRGD
t07 >100ms PCH to KBC GPIO00 ACOK Page44 PGOOD
In case of a non-Deep S4/S5 Platform
timing t42 should be added to t07 PCH_SUSCLK_KBC
PWR_CHG_ACOK
Page45 Page52 5
which will make it 100mS minimum.
b
KBC GPIO20 to PCH 3D3V_AUX_S5 e PM_SLP_S4# S5 1D35V_S3
PM_PWRBTN# 2N7002 3

PM_SLP_S4#
TPS51716RUKR

PM_SLP_S3#
Page45 SWITCH 3V_5V_POK
DDR_VTT_PG_CTRL 0D675V_S0
Page24 S3

1D35V_VTT_PWRGD
PSL_OUT# 3D3V_AUX_KBC PM_SLP_SUS# PGOOD

PM_PWRBTN# g Page51
DC
After Power Button
3 4 4 5
PCH to KBC GPIO44
c SLP_S4# SLP_S3# DDR_PG_CTL

PM_SLP_S4# GPIO71 GPIO05 H_VR_ENABLE

t10 PCH to KBC GPIO01 VR_EN
KBC_PWRBTN#
PM_SLP_S3# >30us PSL_IN2#
GPIO34
S5_ENABLE DPWROK 7
KBC GPIO47 to LAN 1
PM_LAN_ENABLE d
Enable by PM_SLP_S4# The DSW rails must be stable for at least

TBD
1D5V_S3 10 ms before DSW_PWROK is asserted to PCH.
KBC_DPWROK
GPIO66 DSW_PWROK
DDR_VREF_S3(0.75V)
5V_S0 & 3D3V_S0 need meet 0.7V difference f
5V_S0 AC_IN# b PM_PWRBTN# Skylake-U MCP
PSL_IN1# GPIO20 PWRBTN#
V5REF must be powered up before 3D3V_S0 RSMRST_PWRGD#
TBD KBC 2
Vcc3_3, or after Vcc3_3 within 0.7 j ALL_SYS_PWRGD and VR_RDY assert,
3D3V_S5

Delay 10ms
V. Also, V5REF must power down
after Vcc3_3, or before Vcc3_3
within 0.7 V.
+5VS_PCH_VCC5REF Tb MEC1404 delay 10ms; PCH_PWROK assert.
RSMRST#_KBC: Delay 10 ms after receive 8 PCH_PWROK
1D5V_S0 RSMRST_PWRGD# and PM_SLP_SUS#. AND APWROK 4 PM_SLP_S3#

AND
Vcc
RSMRST#_KBC k AND Gate
1D8V_S0 PCH_PWROK PM_SLP_S0# VCCSTG_EN
GPIO36 GPIO93 PCH_PWROK SLP_S0# U74LVC1G08G-AL5 Y

0D75V_S0 6
1D8V_S0 & 1D5V_S3 power ready 7
VR_RDY TBD PM_SUSWARN# 5
GPIO02 SUSWARN# PROCPWRGD
RUNPWROK
ALL_SYS_PWRGD l
6 GPIO26 9 1D0V_S5 5V_S5
1D05V_PCH PM_SUSACK#
GPIO81 SUSACK#
PLTRST# 11 PCI_PLTRST#
VCCP_CPU m AND VIN VDD
It is recommended that SYS_PWROK be asserted after RSMRST#_KBC VCCSTG_EN
both PWROK assertion and processor core VR PWRGD assertion. RSMRST# EN +V1.00DX(VCCSTG)
1D05_VTT_PWRGD VOUT
k
0D85V_S0 SY6288C10CAC
PM_SLP_S4#
GPIO44 Page41
3

Delay 100ms
PM_SLP_S3#
4 GPIO01 H_VCCST_PWRGD ALL_SYS_PWRGD
0D85V_S0 6 Level Shifter
D85V_PWRGD 10 74LVC1G07GW Page17
C SYS_PWROK C
GPIO77 SYS_PWROK
CPU SVID BUS SetVID ACK 50us< t36 <2000us EXT_PWR_GATE#
Page24 1D35VTT_PWRGD
VCC_CORE EXT_PWR_GATE# 5
ALL_SYS_PWRGD assert, SLP_SUS#
g ALL_SYS_PWRGD
VCC_GFXCORE delay 100ms; SYS_PWROK assert. VCCIO_PWRGD
t37
3D3V_S5 5 6
<5ms
g
IMVP_PWRGD
VIN

PM_SLP_SUS# 3D3V_S5_PCH
PCH_CLOCK_OUT SVID Transanctions EN SW

ALL_SYS_PWRGD=D85V_PWRGD t14 >99ms KBC GPIO77 to PCH

SY6288C10CAC
This signal represents the Power
Good for all the non-CORE and PWROK(S0_PWR_GOOD) Page41
non-graphics power rails.
t18
D85V_PWRGD >0us PCH to CPU
DRAMPWROK(VDDPWRGOOD) 2ms<t17 <650ms IMVP8 3D3V_S5
CPU SVID Rails
t19 >1ms
6 ALL_SYS_PWRGD SA/Core/GT/GTx
VR_ON
1D8V_S0
t20 >2ms
5ms<t13 <650ms VR_RDY VR_READY VIN
PCH to CPU PM_SLP_SUS#
UNCOREPWRGOOD(H_CPUPWRGD) 7 VCCPRIM_CORE
EN LX

SYS_PWROK t21+t22 >1ms+60us RT8068AZQWID VCCPRIMCORE_PWROK

PGOOD

1ms< t25 <100ms PCH to all system 1D0V_S5 5V_S5 Page52 h

PLT_RST#
t39 <200us
3D3V_S5 5V_S5
DMI
Vin VDD

+VCCMPHYGTAON_1P0_LS_SIP
EXT_PWR_GATE# EN SW
Vin VCNTL
g PM_SLP_SUS#
SLG59M1470VTR 1D8V_S5
EN Vout
Page17
APL5930KAI 1D8V_S5_PWROK
PGOOD

Page54 h

3V_5V_POK
e 0R 0402
PWR_DCBATOUT_1D0V
VCCPRIMCORE_PWROK RSMRST_PWRGD#
h 0R 0402

1D8V_S5_PWROK
j VIN
h 0R 0402
1D0V_S5
LX
1D0V_S5_PWRGD VCCPRIMCORE_PWROK EN
i
0R 0402
SY8208DQNC
[dGPU] N16x Power-Up/Down Sequence [dGPU] GC6 2.0 Power-Up/Down Sequence h PGOOD

Page53
1D0V_S5_PWRGD

i
B B

[DG-07158-001_v03]

a b c d e f g h i j k l m

1 2 3a 4 4a 4b 5 6 7 8 9 10 11 12

A A

Iris SKL UMA

Wistron Corporation
21F, 88, Sec.1, Hs in Tai Wu Rd., Hs ichih,
Taipei Hs ien 221, Taiwan, R.O.C.

Title

Size Docum ent Num ber

Power Sequence Rev
A0
Iris2 SKL-U A00
Date: Tues day, May 26, 2015 Sheet 102 of 105
5 4 3 2 1
 5 4 3 2 1

DCBATOUT
Adapter TBD VR_EN VR_EN VR_EN 3D3V_VGA_S0
EN EN(S5) PM_SLP_S4# EN
SY8208DQNC TPS51716RUKR NCP81208MNTXG NCP81210MNTWG
EN
NCP81382MNTXG
EN EN
EN(S3) DDR_VTT_PG_CTRL RT8812AGQW
Charger Vinafix.com NCP81382MNTXG NCP81382MNTXG
BQ24770RUYR 1D0V_S5
D D

Battery BT+ 1D35V_S3 0D675V_S0 VCC_CORE +VCCGT

+V_VCCGTUS_VR +VCCSA_VR VGA_CORE

1D35V_VGA_EN

EN
SIRA06DP

1D35V_VGA_S0

S5_ENABLE

EN
TPS51225RUKR

Boost 3D3V_AUX_S5 5V_PWR_2 5V_S5 3D3V_S5

Circuit
USB_PWR_EN# PM_SLP_S3# PM_SLP_S3# 1D05V_VGA_EN PM_SLP_SUS# PM_LAN_ENABLE PM_SLP_S3# VR_EN PM_SLP_SUS#
C EN EN EN C
EN EN EN EN EN
SY6288DAAC x 3 G5016KD1U RT8068AZQWID EN
RT8068AZQWID RT8068AZQWID
APL5930KAI DMP2130L TLV70215DBVR
15V_S5
3D3V_S0
USB20_VCCA 5V_S0
USB20_VCCB 1D8V_S5 3D3V_LAN_S5 1D5V_S0
USB30_VCCC SATA_ODD_PWRGT
1D05V_VGA_S0 +VCCIO_VR VCCPRIM_CORE
EN
SY6288C10CAC
DGPU_PWR_EN

EN
ODD_PWR_5V
RT9724GB G5016KD1U
Power Shape

LCDVDD 3D3V_VGA_S0 Regulator LDO Switch

B B

A A

Iris SKL UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Power Block Diagram
Size Document Number Rev
A2
Iris2 SKL-U A00
Date: Tuesday, May 26, 2015 Sheet 103 of 105
5 4 3 2 1
 A B C D E

PCH SMBus Block Diagram 3D3V_S0

KBC SMBus Block Diagram
‧
3D3V_S5_PCH

‧ TP_VDD

3D3V_S0 SRN10KJ-5-GP
‧
‧Vinafix.com
SRN2K2J-1-GP SMBus Address:0xA0/0xA1

DIMM 1
‧ ‧
SRN10KJ-5-GP

‧ ‧
SMBCLK MEM_SMBCLK PCH_SMBCLK
1
TouchPad Conn. 1

‧
SCL
SMBDATA MEM_SMBDATA PCH_SMBDATA

‧
SDA PS2_DAT0 DAT_TP_SIO DAT_TP_SIO TPDATA

PS2_CLK0 CLK_TP_SIO CLK_TP_SIO TPCLK

2N7002SPT SMBus Address:0xA0/0xA1
3D3V_AUX_KBC
DIMM 2
SCL

SDA
‧
3D3V_S5_PCH

‧
SRN4K7J-8-GP

TPAD Battery Conn.

‧‧ SRN33J-7-GP

‧ ‧
PCH_SMBCLK SMB01_CLK18 SMBCLK1 PBAT_SMBCLK1 CLK_SMB
SCL
SRN2K2J-1-GP PCH_SMBDATA SMB01_DATA18 SMBDA1 PBAT_SMBDAT1 DAT_SMB SMBus address:16
SDA

SMBus Address:0x58/0x59
SML0CLK SML0_CLK

SML0DATA SML0_DATA HPA02224RGRR

PTN3355
PCH_SMBCLK VDDA33_DP SMSC SCL

SDA SMBus address:12

PCH_SMBDATA
TMS (Janus Only) MEC1404
SMBus Address:0xC0H/0x40H
2 2

GPIO73/SCL2

GPIO74/SDA2

PCH 3D3V_S0 SMBus Address:

‧
3D3V_S5_PCH 0x94/0x95/0x96/0x97
SMBus Address:0x98/0x99
‧ Thermal
‧
SRN2K2J-8-GP

THM_SML1_CLK
SCL
3D3V_S0 GPU T8

‧
SRN2K2J-8-GP THM_SML1_DATA
SDL
NCT7718W
‧ ‧ ‧‧ Thermal
‧ ‧ ‧‧
SML1_SMBCLK THM_SML1_CLK
SCL
SML1CLK
SML1_SMBDATA THM_SML1_DATA
SML1DATA SDL
NCT7718W
SMBus Address:0x82/0x83 SMBus Address:0x98/0x99
2N7002SPT
3D3V_VGA_S0

‧ SRN4K7J-8-GP
3D3V_VGA_S0

‧ dGPU
3 3

‧
‧ SMBus Address:0x9E/0x9F
SMB_CLK_VGA I2CS_SCL

SMB_DATA_VGA I2CS_SDA

3D3V_S0 5V_S0

‧ ‧ 0R2J-2-GP
DY

‧
3D3V_S0
SRN2K2J-1-GP
‧ SRN2K2J-1-GP CMP_VOUT1

GPIO166/CMP_VREF1/UART_CLK
CMP_VOUT1

LCD_TST_EN
‧ LCD_TST_EN
‧ H_PROCHOT_EC

‧ ‧ 0R2J-2-GP

‧ ‧‧ ‧
DDPB_CTRLCLK CPU_DP1_CTRL_CLK DDC_CLK_HDMI
LCD_TST
DDPB_CTRLDATA CPU_DP1_CTRL_DATA DDC_DATA_HDMI
HDMI CONN
2N7002DW-1-GP

4 4

Iris SKL UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

SMBUS Block Diagram

Size Document Number Rev
A2 Iris2 SKL-U A00
Date: Tuesday, May 26, 2015 Sheet 104 of 105
A B C D E
 A B C D E

Thermal Block Diagram Audio Block Diagram

Vinafix.com
1 1

3D3V_S5_PCH 3D3V_S0
PAGE28 D+ NCT7718_DXP
PCH MMBT3904-3-GP
SPKR_L+
SPKR_L-

D- NCT7718_DXN
SC2200P50V2KX-2GP SPKR_R-
SPKR_R+ SPEAKER
Thermal Place near CPU
NCT7718
‧ ‧‧ ‧
PWM CORE
SML1DATA/GPIO74
SML1_DATA THM_SML1_DATA SDA
Codec
‧‧ ‧ ‧
2N7002
SML1CLK/GPIO75 SML1_CLK THM_SML1_CLK SCL
MMBT3904-3-GP
ALC3246
T8 AUD_HP1_JACK_L HP MIC
SML1_DATA

AUD_HP1_JACK_R
SML1_CLK

3D3V_S0
T_CRIT# THERM_SYS_SHDN#
2N7002
D
PURE_HW_SHUTDOWN#
EN 3V/5V SLEEVE COMBO
‧
PAGE20 S PCH_PWROK
G RING2
2
Put under CPU(T8 HW shutdown) 2

PAGE27 GPIO74 PAGE86

KBC GPIO73
DMIC_DATA_R R2714
Digital
MEC1404 2N7002
SMB_CLK_VGA_R I2CS_SCL
VGA GPIO0/DMIC_DATA
0R2J-2-GP
R2716
DMIC_DATA
MIC
SMB_DATA_VGA_R I2CS_SDA DMIC_CLK_R DMIC_CLK
GPIO1/DMIC_CLK
0R2J-2-GP

GPIO4
MESO-LE
GPIO94 GPIO56
GB2-64 (23x23)
FAN_TACH1
FAN1_DAC_1

3 3
TACH

FAN
VIN
FAN_VCC1

5V

VIN VSET VOUT

FAN CONTROL
APL5606AKI
PAGE28

4 4
Iris SKL UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size
Thermal/Audio Block Diagram
Document Number Rev
Custom
Iris2 SKL-U A00
Date: Tuesday, May 26, 2015 Sheet 105 of 105
A B C D E