GANDHI RAJAN RAMACHANDRAN

San Jose, CA | +1-213-949-7697 | gandhirr@usc.edu | www.linkedin.com/in/gandhi-rajan

EDUCATION
MS in Electrical Engineering Grad. Date: December 2019
University of Southern California, GPA: 3.72/4
BE in Electrical and Electronics Engineering August 2012 - June 2016
Sri Venkateswara College of Engineering, Anna University

WORK EXPERIENCE
Xilinx Inc – System Engineering Intern (4 months) Present
• Aided in developing prototype version of complex systems using FPGAs.
• Worked with multiple teams to debug software compatibility issues, DRC errors and RTL issues.
• Developed designs based on FPGAs, Microblaze and Processors using Vivado.
Solarillion Foundation - Research Assistant (1.5 years) May 2016 - November 2017
• Won best orientation performer award, among 15 students, for achieving lower average response time of 3.43s in speed
control of a dc motor over a speed range from 300 to 800 rpm.
• Led a Microgrid Power and Smart Energy Research Group and involved in activities like conducting conceptual review,
group discussions and brainstorming sessions.

SKILLS AND INTERESTS

- OS : Linux, Windows.
- Programming : Verilog, VHDL, C, C++, Tcl, Python, Assembly Language, LATEX.
- Tools : Xilinx Vivado, Mentor Graphics ModelSim, QuestaSim, Synopsys Design Compiler, Virtuoso Cadence,
Innovus, PrimeTime, NCSim, MATLAB, Microsoft Office.
- Area of Interest : ASIC/VLSI – Logic and Physical Design, Verification, Validation, Embedded Systems, Computer
Architecture, SoC, Microprocessors (RISC), Microcontrollers, Algorithms Design and Optimization.

PROJECTS
Architectural design of Tomasulo processor
• Designed key components include Copy Free Check pointing (CFC) module, Physical Register File (PRF), Instruction
Fetch Queue (IFQ), 2-stage Dispatch Unit (DU), Issue Unit (IU), Execution Units (EU), Re-Order Buffer (ROB), Return
Address Stack (RAS) and Branch Prediction Buffer (BPB).
• Final testing was done on Xilinx Artix-7 FPGA board with an on-chip logic analyser at run-time speed of 100 MHz.
Implementation of PCI-express protocol in FPGA
• Implemented PCIe physical layer specifically transmit and receive buffers, byte striping logic, elastic buffer (Clock
Domain Crossing Mechanism), 8b10b encoding and decoding to support a 2 lane PCIe link.
• Acquired good understanding of Transaction Layer flow control, Data Link Layer, Physical Layer and LTSSM operation.
Design of AXI Interconnect
• Developed AXI master and slave interfaces to enable a 4-core processor perform transactions with memory units.
• Employed re-order buffers and FIFO and designed x-first, y-next routing logic and arbitration logic at AXI interfaces.
Quad-core processor design with NOC
• Designed a quad core processor system with a Network-on-chip for inter-chip communication.
• Synthesized the netlist using Synopsys design compiler and performed post synthesis simulation.
• Conducted STA and LEC. Finally, place and route was done using Innovus software.
Divider with Cache
• Designed a 16x4 CAM to hold TAGs in form of Dividend and Divisor, 16x16 cache to hold latest result for Quotient and
Remainder, division logic to emulate memory access and LRU algorithm for replacement policy.
MNIST image prediction using hardware acceleration of Bayesian neural networks
• Designed the inference process in software, that mimics hardware, using custom modules like Wallace Gaussian Random
number generator, logarithmic and exponential functions. The proposed model accuracy was 96.14%.
Full Custom design of CPU using Virtuoso Cadence (Schematic and Layout – Clock: 250 MHz & 45nm technology)
• Developed Low level assembler in python which converts assembly code into machine code.
• The machine code was fed into the pipeline and pass through Execution Stage, Memory Stage and Write back stage.
• Memory Stage incorporates 512-bit (32 locations x 16 bits) SRAM arranged in 4 banks of 128-bit together with row
decoder, column decoder, dynamic pre-charge circuit, read and write circuitry and sense amplifiers.
• Optimization Techniques: Incorporated clock gating and power gating techniques to reduce power. Designed fast carry
ahead adder and booth multiplier to reduce delay in the fat execution stage.

RESEARCH PUBLICATIONS:
1) Low-cost wireless intelligent two hand gesture recognition system; (IEEE SysCon)
2) Rural Indian microgrid design optimization — Intelligent battery sizing; (IEEE GHTC)
3) Intelligent system design optimization with dynamic load profile for a stand-alone rural Indian microgrid; (IEEE TPEC)