24/07/17

Introduc)on
•  Computers have become part and parcel of our daily lives.
–  They are everywhere (embedded systems?)
–  Laptops, tablets, mobile phones, intelligent appliances.

Lecture 1: EVOLUTION OF COMPUTER SYSTEM •  It is required to understand how a computer works.

Lecture
Lecture 1: EVOLUTIONOF
1: EVOLUTION OFCOMPUTER
COMPUTER SYSTEM
SYSTEM –  What are there inside a computer?
–  How does it work?
DR.
DR.
KAMALIKA
DR. KAMALIKA
KAMALIKA
DATTA
DATTA
DATTA •  We disJnguish between two terms: Computer Architecture
DEPARTMENT OF
OFCOMPUTER
DEPARTMENT SCIENCE
OF COMPUTER AND
SCIENCE ENGINEERING,
AND
NITNIT
ENGINEERING, NIT MEGHALAYA
MEGHALAYA
DEPARTMENT COMPUTER SCIENCE AND ENGINEERING, MEGHALAYA and Computer Organiza3on.

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Historical Perspec)ve
•  Computer OrganizaJon:
–  Design of the components and funcJonal blocks using which computer •  Constant quest of building automaJc compuJng machines
systems are built.
have driven the development of computers.
–  Analogy: civil engineer’s task during building construcJon (cement,
–  Ini$al efforts: mechanical devices like pulleys, levers and gears.
bricks, iron rods, and other building materials).
–  During World War II: mechanical relays to carry out computaJons.
•  Computer Architecture:
–  Vacuum tubes developed: first electronic computer called ENIAC.
–  How to integrate the components to build a computer system to
–  Semiconductor transistors developed and journey of miniaturizaJon
achieve a desired level of performance.
began.
–  Analogy: architect’s task during the planning of a building (overall •  SSI à MSI à LSI à VLSI à ULSI à …. Billions of transistors per chip
layout, floorplan, etc.).

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Babbage Engine
•  First automaJc compuJng engine
PASCALINE (1642) was designed by Charles Babbage
•  Mechanical calculator invented by in the 19th century, but he could
B. Pascal. not build it.
•  Could add and subtract two numbers •  The first complete Babbage
directly, and mulJply and divide by engine was built in 2002, 153
repeJJon. years aber it was designed.
•  8000 parts.
•  Weighed 5 tons.
•  11 feet in length.

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Harvard Mark 1
ENIAC •  Built at the University of
(Electrical Numerical
Harvard in 1944, with support
Integrator and
from IBM.
Calculator) •  Used mechanical relays
•  Developed at the University (switches) to represent data.
of Pennsylvania.
•  It weighed 35 tons, and
•  Used 18,000 vacuum tubes, required 500 miles of wiring.
weighed 30 tons, and
occupied a 30b x 50b space.

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IBM System/360 Intel Core i7

•  Very popular mainframe •  A modern processor chip, that comes
computer of the 60s and in dual-core, quad-core and 6-core
70s. variants.
•  Introduced many •  64-bit processor that comes with
advanced architectural various microarchitectures like
concepts that appeared Haswell, Nehalem, Sandy Bridge, etc.
in microprocessors
several decades later.

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Genera)on Main Technology Representa)ve Systems

First (1945-54) Vacuum tubes, relays Machine & assembly language Evolu)on of the
ENIAC, IBM-701
Types of Computer
Second (1955-64) Transistors, memories, I/O Batch processing systems, HLL
processors IBM-7090 Systems
Third (1965-74) SSI and MSI integrated circuits MulJprogramming / Time sharing
Microprogramming IBM 360, Intel 8008
Fourth (1975-84) LSI and VLSI integrated circuits MulJprocessors The future?
Intel 8086, 8088 •  Large-scale IoT based
Fibh (1984-90) VLSI, mulJprocessor on-chip Parallel compuJng, Intel 486 systems.
•  Wearable compuJng.
Sixth (1990 onwards) ULSI, scalable architecture, post- Massively parallel processors
•  Intelligent objects.
CMOS technologies PenJum, SUN Ultra workstaJons

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Evolu)on of Inside a laptop

PC form •  MiniaturizaJon in
factors over feature sizes of all parts.
the years •  Hard drive gegng
replaced by flash-based
memory devices.
•  Cooling is a major issue.

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Moore’s Law
•  Refers to an observaJon made by Intel co-founder Gordon Moore in
1965. He noJced that the number of transistors per square inch on
integrated circuits had doubled every year since their invenJon.
•  Moore's law predicts that this trend will conJnue into the
foreseeable future.
•  Although the pace has slowed, the number of transistors per square
inch has since doubled approximately every 18 months. This is used
as the current definiJon of Moore's law.

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Simplified Block Diagram of a •  Inside the Processor

Computer System –  Also called Central Processing Unit (CPU).
•  All instrucJons and data are –  Consists of a Control Unit and an Arithme3c Logic Unit (ALU).
stored in memory. •  All calculaJons happen inside the ALU.
•  An instrucJon and the required •  The Control Unit generates sequence of control signals to carry out all
data are brought into the operaJons.
processor for execuJon. –  The processor fetches an instrucJon from memory for execuJon.
•  Input and Output devices •  An instrucJon specifies the exact operaJon to be carried out.
interface with the outside world. •  It also specifies the data that are to be operated on.
•  Referred to as von-Neumann
•  A program refers to a set of instrucJons that are required to carry out
architecture. some specific task (e.g. sorJng a set of numbers).

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•  What is the role of ALU? •  What is the role of control unit?

–  It contains several registers, some general-purpose and some special- –  Acts as the nerve center that senses the states of various funcJonal units
purpose, for temporary storage of data. and sends control signals to control their states.
–  It contains circuitry to carry out logic operaJons, like AND, OR, NOT, –  To carry out a specific operaJon (say, R1 ß R2 + R3), the control unit
shib, compare, etc. must generate control signals in a specific sequence.
–  It contains circuitry to carry out arithmeJc operaJons like addiJon, •  Enable the outputs of registers R2 and R3.
subtracJon, mulJplicaJon, division, etc. •  Select the addiJon operaJon.
–  During instrucJon execuJon, the data (operands) are brought in and •  Store the output of the adder circuit into register R1.
stored in some registers, the desired operaJon carried out, and the –  When an instrucJon is fetched from memory, the operaJon (called
result stored back in some register or memory. opcode) is decoded by the control unit, and the control signals issued.

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•  Inside the Memory Unit –  Various different types of memory are possible.
–  Two main types of memory subsystems. a)  Random Access Memory (RAM), which is used for the cache and primary
•  Primary or Main memory, which stores the acJve instrucJons and data for memory sub-systems. Read and Write access Jmes are independent of
the program being executed on the processor. the locaJon being accessed.
•  Secondary memory, which is used as a backup and stores all acJve and b)  Read Only Memory (ROM), which is used as part of the primary memory
inacJve programs and data, typically as files. to store some fixed data that cannot be changed.
–  The processor only has direct access to the primary memory. c)  MagneJc Disk, which uses direcJon of magneJzaJon of Jny magneJc
parJcles on a metallic surface to store data. Access Jmes vary depending
–  In reality, the memory system is implemented as a hierarchy of several on the locaJon being accessed, and is used as secondary memory.
levels.
d)  Flash Memory, which is replacing magneJc disks as secondary memory
•  L1 cache, L2 cache, L3 cache, primary memory, secondary memory. devices. They are faster, but smaller in size as compared to disk.
•  ObjecJve is to provide faster memory access at affordable cost.

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Input Unit
•  Used to feed data to the computer system from the external
environment.
–  Data are transferred to the processor/memory aber appropriate
encoding.
•  Common input devices:
–  Keyboard
–  Mouse
–  JoysJck
–  Camera

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Output Unit
•  Used to send the result of some computaJon to the outside
world.
•  Common output devices:
–  LCD/LED screen
–  Printer and Plooer
–  Speaker / Buzzer
–  ProjecJon system

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END OF LECTURE 1

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Introduc)on
•  The basic mechanism through which an instrucJon gets
executed shall be illustrated.
•  May be recalled:
Lecture 1: EVOLUTION OF COMPUTER SYSTEM –  ALU contains a set of registers, some general-purpose and some special-
Lecture 2: BASIC
Lecture OPERATION
1: EVOLUTION OF A COMPUTER
OF COMPUTER SYSTEM purpose.
–  First we briefly explain the funcJons of the special-purpose registers
DR. KAMALIKA DATTA
DR. KAMALIKA DATTA
before we look into some examples.
DR. KAMALIKA DATTA
DEPARTMENT
DEPARTMENTOF
OFCOMPUTER SCIENCEAND
COMPUTER SCIENCE ANDENGINEERING,
ENGINEERING,NITNIT MEGHALAYA
MEGHALAYA
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING, NIT MEGHALAYA

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For Interfacing with the Primary Memory

Address
•  Two special-purpose registers are used: 0 M Address
–  Memory Address Register (MAR): Holds the 1 A
2 R
address of the memory locaJon to be accessed. 3 PRIMARY
–  Memory Data Register (MDR): Holds the data 4 PROCESSOR MEMORY
5 M Data
that is being wrioen into memory, or will D
receive the data being read out from memory. R
•  Memory considered as a linear array of
storage locaJons (bytes or words) each 1023 Control Signals
with unique address. Memory

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•  To read data from memory

For Keeping Track of Program / Instruc)ons
a)  Load the memory address into MAR.
•  Two special-purpose registers are used:
b)  Issue the control signal READ.
–  Program Counter (PC): Holds the memory address of the next
c)  The data read from the memory is stored into MDR. instrucJon to be executed.
•  To write data into memory •  AutomaJcally incremented to point to the next instrucJon when an
instrucJon is being executed.
a)  Load the memory address into MAR.
–  Instruc3on Register (IR): Temporarily holds an instrucJon that has
b)  Load the data to be wrioen into MDR.
been fetched from memory.
c)  Issue the control signal WRITE. •  Need to be decoded to find out the instrucJon type.
•  Also contains informaJon about the locaJon of the data.

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Architecture of the Example Processor Example Instruc)ons

Memory
•  We shall illustrate the process of instrucJon execuJon with the
help of the following two instrucJons:
MAR MDR a)  ADD R1, LOCA
Control
R0 Add the contents of memory locaJon LOCA (i.e. address of the memory
PC
R1 locaJon is LOCA) to the contents of register R1.
Processor R1 ß R1 + Mem[LOCA]
IR .
ALU
.

b)  ADD R1, R2
Rn-1 Add the contents of register R2 to the contents of register R1.
n General Purpose Registers (GPR) R1 ß R1 + R2

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ExecuJon of ADD R1,LOCA •  LOCA (i.e. 5000) is transferred (from IR) to MAR. MAR ß IR[Operand]
•  Assume that the instrucJon is stored in memory locaJon 1000, the iniJal value of R1 •  READ request is issued to memory unit.
is 50, and LOCA is 5000. •  The data is fetched to MDR. MDR ß Mem[MAR]
•  Before the instrucJon is executed, PC contains 1000. •  The content of MDR is added to R1. R1 ß R1 + MDR
•  Content of PC is transferred to MAR. MAR ß PC
The steps being carried out are called micro-operaJons:
•  READ request is issued to memory unit.
MAR ß PC
•  The instrucJon is fetched to MDR. MDR ß Mem[MAR] MDR ß Mem[MAR]
•  Content of MDR is transferred to IR. IR ß MDR IR ß MDR
PC ß PC + 4
•  PC is incremented to point to the next instrucJon. PC ß PC + 4
MAR ß IR[Operand]
•  The instrucJon is decoded by the control unit. MDR ß Mem[MAR]
ADD R1 5000 R1 ß R1 + MDR

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R1 125
50 ExecuJon of ADD R1,R2
1.  PC = 1000
•  Assume that the instrucJon is stored in memory locaJon 1500, the iniJal value of R1
Address Content 2.  MAR = 1000 is 50, and R2 is 200.
1000 ADD R1, LOCA 3.  PC = PC + 4 = 1004 •  Before the instrucJon is executed, PC contains 1500.
1004 … 4.  MDR = ADD R1, LOCA •  Content of PC is transferred to MAR. MAR ß PC
5.  IR = ADD R1, LOCA •  READ request is issued to memory unit. ADD R1, R2
6.  MAR = LOCA = 5000 •  The instrucJon is fetched to MDR. MDR ß Mem[MAR]
5000 75
7.  MDR = 75 •  Content of MDR is transferred to IR. IR ß MDR
LOCA •  PC is incremented to point to the next instrucJon. PC ß PC + 4
8.  R1 = R1 + MDR = 50 + 75 = 125
•  The instrucJon is decoded by the control unit.
•  R2 is added to R1. R1 ß R1 + R2

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R1 250
50 Bus Architecture
R2 200 1.  PC = 1500 •  The different funcJonal modules must be connected in an
2.  MAR = 1500 organized manner to form an operaJonal system.
Address InstrucJon
3.  PC = PC + 4 = 1504
1500 ADD R1, R2 4.  MDR = ADD R1, R2
•  Bus refers to a group of lines that serves as a connecJng path
1504 … 5.  IR = ADD R1, R2 for several devices.
6.  R1 = R1 + R2 = 250 •  The simplest way to connect the funcJonal unit is to use the
single bus architecture.
–  Only one data transfer allowed in one clock cycle.
–  For mulJ-bus architecture, parallelism in data transfer is allowed.

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System-Level Two-Bus Architecture

System-Level Single Bus Architecture
Processor Memory

Output
Input Output Memory Processor Device

Input
Device
I/O Processor

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Internal Processor Bus

Single-Bus Architecture Inside the Processor
PC InstrucJon
Decoding and
. . Control
•  There is a single bus inside the processor. MAR
. signals
Control Unit
–  ALU and the registers are all connected via the single bus. MEMORY
–  This bus is internal to the processor and should not be confused with the external MDR
IR
bus that connects the processor to the memory and I/O devices. 4 Y R0
•  A typical single-bus processor architecture is shown on the next slide.
Select MUX R1
–  Two temporary registers Y and Z are also included. . .
–  Register Y temporarily holds one of the operands of the ALU. FuncJon
.
ALU
–  Register Z temporarily holds the result of the ALU operaJon. select Carry-in Rn-1

–  The mulJplexer selects a constant operand 4 during execuJon of the micro- Z
operaJon: PC ß PC + 4.

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Mul)-Bus Architectures
•  Modern processors have mulJple buses that connect the
registers and other funcJonal units.
–  Allows mulJple data transfer micro-operaJons to be executed in the END OF LECTURE 2
same clock cycle.
–  Results in overall faster instrucJon execuJon.
•  Also advantageous to have mulJple shorter buses rather than
a single long bus.
–  Smaller parasiJc capacitance, and hence smaller delay.

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Overview of Memory OrganizaJon

•  Memory is one of the most important sub-systems of a computer that
determines the overall performance.
•  Conceptual view of memory:
–  Array of storage locaJons, with each storage locaJon having a unique address.
Lecture 1: EVOLUTION OF COMPUTER SYSTEM –  Each storage locaJon can hold a fixed amount of informaJon (mulJple of bits,

LectureLecture 1: EVOLUTION OF COMPUTER SYSTEM which is the basic unit of data storage).
3: MEMORY ADDRESSING AND LANGUAGES •  A memory system with M locaJons and N bits per locaJon, is referred to
DR. as an M x N memory.
DR.KAMALIKA DATTA
KAMALIKA DATTA –  Both M and N are typically some powers of 2.
DEPARTMENT OF COMPUTERDR.SCIENCE
KAMALIKA DATTA
DEPARTMENT OF COMPUTER SCIENCEAND ENGINEERING,
AND ENGINEERING, NITNIT MEGHALAYA
MEGHALAYA
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING, NIT MEGHALAYA –  Example: 1024 x 8, 65536 x 32, etc.

49
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Some Terminologies How is Memory Organized?

•  Bit: A single binary digit (0 or 1). •  Memory is oben byte organized.
–  Every byte of the memory has a unique address.
•  Nibble: CollecJon of 4 bits. •  MulJple bytes of data can be accessed by an instrucJon.
–  Example: Half-word (2 bytes), Word (4 bytes), Long Word (8
•  Byte: CollecJon of 8 bits. bytes).
•  For higher data transfer rate, memory is oben organized
•  Word: Does not have a unique definiJon. such that mulJple bytes can be read or wrioen
–  Varies from one computer to another; typically 32 simultaneously.
–  Necessary to bridge the processor-memory speed gap.
or 64 bits. –  Shall be discussed later in detail.

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How do we Specify Memory Sizes?

Processor-Memory
Performance Gap Unit Bytes In Decimal
•  With technological 8 bits (B) 1 or 20 100
advancements, both Kilobyte (KB) 1024 or 210 103
processor and memory are
becoming faster. Megabyte (MB) 1,048,576 or 220 106
•  However, the speed gap is Gigabyte (GB) 1,073,741,824 or 230 109
steadily increasing Terabyte (TB) 1,099,511,627,776 or 240 1012
•  Special techniques are this Petabyte (PB) 250 1015
needed to bridge this gap.
•  Cache memory Exabyte (EB) 260 1018
•  Memory interleaving Zeoabyte (ZB) 270 1021

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•  If there are n bits in the address,

the maximum number of
Address Contents
storage locaJons can be 2n.
0000 0000 0000 0000 0000 0001
–  For n=8, 256 locaJons. Address
–  For n=16, 64K locaJons. (n bits) 0000 0001 0000 0100 0101 0000
–  For n=20, 1M locaJons. Data MEMORY 0000 0010 1010 1000 0000 0000
(m bits)
–  For n=32, 4G locaJons.
: :
•  Modern-day memory chips can
store several Gigabits of data.
1111 1111
1011 0000 0000 1010
RD WR EN
–  Dynamic RAM (DRAM).
An example: 28 x 16 memory

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Some Examples Byte Ordering ConvenJons

1.  A computer has 64 MB (megabytes) of byte-addressable memory. How
many bits are needed in the memory address? •  Many data items require mulJple bytes Data Type Size (in Bytes)
–  Address Space = 64 MB = 26 X 220 B = 226 B for storage. Character 1
–  If the memory is byte addressable, we need 26 bits of address. •  Different computers use different data Integer 4
ordering convenJons.
2.  A computer has 1 GB of memory. Each word in this computer is 32 bits. Long integer 8
How many bits are needed to address any single word in memory? –  Low-order byte first FloaJng-point 4
–  Address Space = 1 GB = 230 B –  High-order byte first Double-precision 8
–  1 word = 32 bits = 4 B •  Thus a 16-bit number 11001100 10101010 Typical data sizes
–  We have 230 / 4 = 228 words can be stored as either:
–  Thus, we require 28 bits to address each word.
11001100 10101010 or 10101010 11001100

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An Example
•  The two convenJons have been named as:
•  Represent the following 32-bit number in both Liole-Endian and Big-Endian
a)  Liole Endian in memory from address 2000 onwards:
•  The least significant byte is stored at lower address followed by the 01010101 00110011 00001111 11000011
most significant byte. Examples: Intel processors, DEC alpha, etc.
•  Same concept followed for arbitrary mulJ-byte data. Li_le Endian Big Endian
Address Data Address Data
b)  Big Endian 2000 11000011 2000 01010101
•  The most significant byte is stored at lower address followed by the
least significant byte. Examples: IBM’s 370 mainframes, Motorola 2001 00001111 2001 00110011
microprocessors, TCP/IP, etc. 2002 00110011 2002 00001111
•  Same concept followed for arbitrary mulJ-byte data. 2003 01010101 2003 11000011

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Memory Access by InstrucJons An Example

•  The program instrucJons and data are stored in memory. •  Compute S = (A + B) – (C – D)
–  In von-Neumann architecture, they are stored in the same memory.
LOAD R1,A
–  In Harvard architecture, they are stored in different memories.
LOAD R2,B
•  For execuJng the program, two basic operaJons are required.
ADD R3,R1,R2 // R3 = A + B
a)  Load: The contents of a specified memory locaJon is read into a
processor register. LOAD R1, 2000 LOAD R1,C
b)  Store: The contents of a processor register is wrioen into a specified LOAD R2,D
memory locaJon. STORE 2020, R3 SUB R4,R1,R2 // R4 = C – D
SUB R3,R3,R4 // R3 = R3 – R4
STORE S,R3

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Machine, Assembly and High Level Language Assemblers and Compilers

•  Machine Language •  Assembler
–  NaJve to a processor: executed directly by hardware. –  Translates an assembly language program to machine
–  InstrucJons consist of binary code: 1’s and 0’s. language.
•  Assembly Language •  Compiler
–  Low-level symbolic version of machine language.
–  One to one correspondence with machine language.
–  Translate a high-level language programs to assembly/
machine language.
–  Pseudo instrucJons are used that are much more readable and easy to use.
–  The translaJon is done by the compiler directly, or
•  High-Level Language
–  Programming languages like C, C++, Java.
–  The compiler first translates to assembly language and then
–  More readable and closer to human languages.
the assembler converts it to machine code.

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Compiler and Assembler

High-level •  The compiler or assembler may run on the naJve machine for which the
language target code is being generated, or can be run on another machine.
Compiler –  Called cross-assembler or cross-compiler.

Assembly
•  Example 1: An 8085 cross-assembler is running on a desktop PC which
Compiler Alterna)ve 2 generates 8085 machine code.
language

Assembler •  Example 2: An ARM embed-C cross compiler is running on desktop PC

which generates ARM machine code for an embedded development
Machine code board.

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END OF LECTURE 3
Lecture 1: EVOLUTION OF COMPUTER SYSTEM
Lecture
Lecture 1: EVOLUTION
4: SOFTWARE ANDOFARCHITECTURE
COMPUTER SYSTEM
TYPES
DR. KAMALIKA DATTA
DR. KAMALIKA DATTA
DR. KAMALIKA DATTA
DEPARTMENT
DEPARTMENTOF
OFCOMPUTER
COMPUTER SCIENCE ANDENGINEERING,
SCIENCE AND ENGINEERING, NIT
NIT MEGHALAYA
MEGHALAYA
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING, NIT MEGHALAYA

68
67 2 2

IntroducJon Types of Programs

•  A sobware or a program consists of a set of instrucJons •  Broadly we can classify programs/sobware into
required to solve a specific problem. two types:
–  A program to sort a set of numbers.
–  A program to find the roots of a quadraJc equaJon.
a)  ApplicaJon Sobware
•  Which helps the user to solve a parJcular user-level
–  A program to find the inverse of a matrix. problem.
–  The C compiler that translates a C program to machine language. •  May need system sobware for execuJon.
–  The editor program that helps us in creaJng a document.
b) System Sobware
–  The operaJng system that helps us in using the computer system.
•  A collecJon of programs that helps the users to create,
analyze and run their programs.

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(a) Applica3on SoYware (b) System SoYware

•  ApplicaJon sobware helps users solve parJcular problems. •  System sobware is a collecJon of programs, which helps users run other
programs.
•  In most cases, applicaJon sobware resides on the
computer’s hard disk or removable storage media (DVD, USB •  Typical operaJons carried out by system sobware:
drive, etc.). –  Handling user requests
–  Managing applicaJon programs and storing them as files
•  Typical examples: –  File management in secondary storage devices
–  Financial accounJng package –  Running standard applicaJons such as word processor, internet browser, etc.
–  MathemaJcal packages like MATLAB or MATHEMATICA –  Managing I/O units
–  An app to book a cab –  Program translaJon from source form to object form
–  An app to monitor the health of a person –  Linking and running user programs

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OperaJng System
Users & Applica3on SoYware
•  Provides an interface between
•  Some very commonly used system sobware: computer hardware and users.
–  OperaJng system (WINDOWS, LINUX, MAC/OS, •  Two layers: Shell
ANDROID, etc.) a)  Kernel: contains low-level
•  Instance of a program that never terminates. Kernel
rouJnes for resource
•  The program conJnues running unJl either the machine is management.
switched off or the user manually shuts down the machine. b)  Shell: provides an interface for Computer
the users to interact with the Hardware
–  Compilers and assemblers
computer hardware through the
–  Linkers and loaders kernel.
–  Editors and debuggers

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•  The OS is a collecJon of rouJnes that is used to control •  Depending on the intended use of the computer system, the
sharing of various computer resources as they execute goal of the OS may differ.
applicaJon programs. –  Classical mulJ-programming systems
–  Typical resources: Processor, Memory, Files, I/O devices, etc. •  Several user programs loaded in memory.
•  These tasks include: •  Switch to another program when one program gets blocked due to I/O.
•  ObjecJve is to maximize resource uJlizaJon.
–  Assigning memory and disk space to program and data files.
–  Modern Jme-sharing systems
–  Moving data between I/O devices, memory and disk units.
•  Widely used because every user can now afford to have a separate
–  Handling I/O operaJons, with parallel operaJons where possible. terminal.
–  Handling mulJple user programs that are running at the same •  Processor Jme shared among a number of interacJve users.
Jme. •  ObjecJve is to reduce the user response Jme.

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ClassificaJon of Computer
–  Real-Jme systems
•  Several applicaJons are running with specific deadlines.
Architecture
•  Deadlines can be either hard or sob. •  Broadly can be classified into two types:
•  Interrupt-driven operaJon – processor interrupted when a task arrives.
•  Examples: missile control system, industrial manufacturing plant, paJent
a)  Von-Neumann architecture
health monitoring and control system, automoJve control system, etc.
b)  Harvard architecture
–  Mobile (phone) systems
•  Here user responsiveness is the most important. •  How is a computer different from a calculator?
•  SomeJmes a program that makes the system slow or hogs too much
memory may be forcibly stopped. – They have similar circuitry inside (e.g. for doing
arithmeJc).
– In a calculator, user has to interacJvely give the
77 2
sequence of commands. 78 2

– In contrast, a computer works using the stored-

program concept.
– Write a program, store it in memory, and run it in
one go.

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von-Neumann Architecture Harvard Architecture

•  InstrucJons and data are stored in the
same memory module. •  Separate memory for program and data.
–  InstrucJons are stored in program memory Program
•  More flexible and easier to Memory
implement. Program / and data are stored in data memory.
Processor Data •  InstrucJon and data accesses can be done Processor
•  Suitable for most of the general
purpose processors. Memory in parallel. Data
Memory
•  General Disadvantage: •  Some microcontrollers and pipelines with
–  The processor-memory bus acts as separate instrucJon and data caches follow
the booleneck. this concept.
–  All instrucJons and data are moved
•  The processor-memory booleneck remains.
back and forth through the pipe.

79 2 80 2

Emerging Architectures Pipeline in ExecuJng InstrucJons

•  Several architectural concepts have been proposed that deviate significantly •  InstrucJon execuJon is typically divided into 5 stages:
from the von-Neumann or Harvard model. –  InstrucJon Fetch (IF)
•  There is a proposal for in-memory compuJng architecture, where storage –  InstrucJon Decode (ID)
and computaJon can be done in the same funcJonal unit. –  ALU operaJon (EX)
–  Memristors are projected to make this possible in the near future. –  Memory Access (MEM)
–  Memristors can be used in high capacity non-volaJle resisJve memory systems. –  Write Back result to register file (WB)
–  Memristors within the memory can also be controlled to carry out some
•  These five stage can be executed in an overlapped fashion in a pipeline
computaJons.
architecture.
–  Results in significant speedup by overlapping instrucJon execuJon.

81 2 82 2

How can Harvard Architecture

Basic 5-stage Pipelining Diagram
Help?
InstrucJon Pipeline Stage •  In clock cycle 4, instrucJon 4 is trying to fetch
1 IF ID EX MEM WB
2 IF ID EX MEM WB
an instrucJon (IF), while instrucJon 1 may be
3 IF ID EX MEM WB trying to access data (MEM).
4 IF ID EX MEM –  In von-Neumann architecture, one of these two
5 IF ID EX
operaJons will have to wait resulJng in pipeline
Clock
Cycle
1 2 3 4 5 6 7 slowdown.
–  In Harvard architecture, the operaJons can go on
83 2
without any speed penalty as the instrucJon and 84 2

data memories are separate.

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END OF LECTURE 4
Lecture 1: EVOLUTION OF COMPUTER SYSTEM
Lecture 5: INSTRUCTION
Lecture SET
1: EVOLUTION OF ARCHITECTURE
COMPUTER SYSTEM

DR. KAMALIKA
DR.DR.
KAMALIKA DATTA
DATTA
KAMALIKA DATTA
DEPARTMENT
DEPARTMENT OF
OF COMPUTER
COMPUTER
DEPARTMENT SCIENCE
SCIENCE
OF COMPUTER AND
AND
SCIENCE ENGINEERING,
ENGINEERING,
AND NIT
NITNIT
ENGINEERING, MEGHALAYA
MEGHALAYA
MEGHALAYA

86
85 2 2

IntroducJon InstrucJon Set Design Issues

•  Number of explicit operands:
•  InstrucJon Set Architecture (ISA) –  0, 1, 2 or 3.
–  Serves as an interface between sobware and hardware. •  LocaJon of the operands:
–  Typically consists of informaJon regarding the programmer’s view –  Registers, accumulator, memory, accumulator.
of the architecture (i.e. the registers, address and data buses, etc.).
•  SpecificaJon of operand locaJons:
–  Also consists of the instrucJon set.
–  Addressing modes: register, immediate, indirect, relaJve, etc.
•  Many ISA’s are not specific to a parJcular computer •  Sizes of operands supported:
architecture. –  Byte (8-bits), Half-word (16-bits), Word (32-bits), Double (64-bits), etc.
–  They survive across generaJons.
•  Supported operaJons:
–  Classic examples: IBM 360 series, Intel x86 series, etc.
–  ADD, SUB, MUL, AND, OR, CMP, MOVE, JMP, etc.

87 2 88 2

EvoluJon of InstrucJon Sets Example Code Sequence for Z = X + Y

1.  Accumulator based: 1960’s (EDSAC, IBM 1130)
2.  Stack based: 1960-70 (Burroughs 5000) •  Stack machine: Top Of Stack
3.  Memory-Memory based: 1970-80 (IBM 360)
PUSH X
4.  Register-Memory based: 1970-present (Intel x86) PUSH Y
5.  Register-Register based: 1960-present (MIPS, CDC 6600, SPARC) ADD
POP Z
1: 1-address instrucJons: 3: 2- or 3-address instrucJons:
ADD X à ACC = ACC + Mem[X] ADD A,B à Mem[A] = Mem[A] + Mem[B] •  The ADD instrucJon pops
2: 0-address instrucJons:
ADD A,B,C à Mem[A] = Mem[B] + Mem[C] two elements from stack,
adds them, and pushes ALU
ADD à TOS = TOS + NEXT 5: 3-address instrucJons:
4: 2-address instrucJons:
LOAD R1,X à R1 = Mem[X]
ADD R1,R2,R3 à R1 = R2 + R3 back result.

89 2 90 2

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Registers

•  Accumulator based machine: ACC

•  Register-Memory machine:
LOAD X // ACC = Mem[X]
LOAD R2,X // R2 = Mem[X]
ADD Y // ACC = ACC + Mem[Y]
STORE Z // Mem[Z] = ACC ADD R2,Y // R2 = R2 + Mem[Y]
ALU STORE Z,R2 // Mem[Z] = R2
•  All instrucJons assume that ALU
one of the operands (and also •  One of the operands is assumed
the result) is in a special From to be in register and another in
register called accumulator. From
memory
memory. memory

91 2 92 2

About General Purpose Registers

Registers (GPRs)
•  Older architectures had a large number of special purpose registers.
•  Register-Register machine:
–  Program counter, stack pointer, index register, flag register, accumulator, etc.
LOAD R1,X // R1 = Mem[X]
LOAD R2,Y // R2 = Mem[Y]
•  Newer architectures, in contrast, have a large number of GPRs.
ADD R3,R1,R2 // R3 = R1 + R2 •  Why?
STORE Z,R3 // Mem[Z] = R3 –  Easy for the compiler to assign some variables to registers.
•  Also called load-store architecture, ALU –  Registers are much faster than memory.
as only LOAD and STORE –  More compact instrucJon encoding as fewer bits are required to specify
registers.
instrucJons can access memory.
–  Many processors have 32 or more GPR’s.

93 2 94 2

(a) Stack Architecture •  Example: Y = A / B – (A – C * B)

•  Typical instrucJons: PUSH A
PUSH B
PUSH X, POP X DIV
ADD, SUB, MUL, DIV PUSH A
PUSH C
PUSH B
MUL
COMPARISON BETWEEN VARIOUS SUB

ARCHITECTURE TYPES TOS

SUB
POP Y

95 2 96 2

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(a) Stack Architecture •  Example: Y = A / B – (A – C * B)

(a) Stack Architecture •  Example: Y = A / B – (A – C * B)
•  Typical instrucJons: PUSH A •  Typical instrucJons: PUSH A
PUSH B PUSH B
PUSH X, POP X DIV PUSH X, POP X DIV
ADD, SUB, MUL, DIV PUSH A ADD, SUB, MUL, DIV PUSH A
PUSH C PUSH C
PUSH B PUSH B
MUL MUL
TOS
SUB SUB
TOS SUB B SUB
A POP Y A POP Y

97 2 98 2

(a) Stack Architecture •  Example: Y = A / B – (A – C * B)

(a) Stack Architecture •  Example: Y = A / B – (A – C * B)
•  Typical instrucJons: PUSH A •  Typical instrucJons: PUSH A
PUSH B PUSH B
PUSH X, POP X DIV PUSH X, POP X DIV
ADD, SUB, MUL, DIV PUSH A ADD, SUB, MUL, DIV PUSH A
PUSH C TOS PUSH C
PUSH B PUSH B
B
MUL MUL
C
SUB SUB
TOS SUB A SUB
A/B POP Y A/B POP Y

99 2 100 2

(a) Stack Architecture •  Example: Y = A / B – (A – C * B)

(a) Stack Architecture •  Example: Y = A / B – (A – C * B)
•  Typical instrucJons: PUSH A •  Typical instrucJons: PUSH A
PUSH B PUSH B
PUSH X, POP X DIV PUSH X, POP X DIV
ADD, SUB, MUL, DIV PUSH A ADD, SUB, MUL, DIV PUSH A
PUSH C PUSH C
TOS PUSH B PUSH B
MUL TOS MUL
B*C
SUB SUB
A SUB A-B*C SUB
A/B POP Y A/B POP Y

101 2 102 2

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(a) Stack Architecture •  Example: Y = A / B – (A – C * B)

(a) Stack Architecture •  Example: Y = A / B – (A – C * B)
•  Typical instrucJons: PUSH A •  Typical instrucJons: PUSH A
PUSH B PUSH B
PUSH X, POP X DIV PUSH X, POP X DIV
ADD, SUB, MUL, DIV PUSH A ADD, SUB, MUL, DIV PUSH A
PUSH C PUSH C
PUSH B PUSH B
MUL MUL
SUB SUB
TOS
SUB SUB
A/B-(A-B*C) TOS Y = RESULT
POP Y POP Y

103 2 104 2

(b) Accumulator Architecture Example: Y = A / B – (A – C * B) (c) Memory-Memory Architecture Example: Y = A / B – (A – C * B)

LOAD C DIV A,B,D
•  Typical instrucJons: MUL B •  Typical instrucJons (3 operands): MUL E,C,B
STORE D // D = C*B SUB E,A,E
LOAD X, STORE X ADD X,Y,Z
ADD X, SUB X, MUL X, DIV X LOAD A SUB X,Y,Z SUB Y,D,E
SUB D MUL X,Y,Z
STORE D // D = A – C*B MOV D,A
•  Typical instrucJons (2 operands):
LOAD A DIV D,B
MOV X,Y
DIV B MOV E,C
ADD X,Y
SUB D MUL E,B
SUB X,Y
STORE Y SUB A,E
MUL X,Y
SUB D,A

105 2 106 2

(d) Load-Store Architecture Example: Y = A / B – (A – C * B)

LOAD R1,A
Registers: Pros and Cons
•  Typical instrucJons: LOAD R2,B •  The load-store architecture forms the basis of RISC ISA.
LOAD R1,X LOAD R3,C –  We shall explore one such RISC ISA, viz. MIPS.
DIV R4,R1,R2
STORE Y,R2
MUL R5,R3,R2
•  Helps in reducing memory traffic once the memory data
ADD R1,R2,R3
SUB R5,R1,R5
are loaded into the registers.
SUB R1,R2,R3
SUB R4,R4,R5 •  Compiler can generate very efficient code.
STORE Y,R4 •  AddiJonal overhead for save/restore during procedure
or interrupt calls and returns.
–  Many registers to save and restore.

107 2 108 2

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END OF LECTURE 5

109 2

19