=====================ALU===================

Expt No.:1
Batch: B4
Roll No.:404B070

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity alu_4bit is
Port ( a,b : in std_logic_vector(3 downto 0);
m : in std_logic_vector(2 downto 0);
z : out std_logic_vector(3 downto 0);
c : out std_logic );
end alu_4bit;

architecture Behavioral of alu_4bit is

begin
process(a,b,m)
variable t : std_logic_vector(4 downto 0);
begin

if m = "000" then --------add

t := a + b;
z <= t(3 downto 0);
if t(4)= '1' then
c <= '1';
else
c <= '0';
end if;

elsif m = "001" then --------sub

t := a - b;
z <= t(3 downto 0);
if t(4)= '1' then
c <= '1';
else
c <= '0';
end if;

elsif m = "010" then ---------and

z <= a and b;
c <= 'Z';
elsif m = "011" then ---------or
z <= a or b;
c <= 'Z';
elsif m = "100" then ---------xor
z <= a xor b;
c <= 'Z';
elsif m = "101" then ---------nor
 z <= a nor b;
c <= 'Z';
elsif m = "110" then ---------nand
z <= a nand b;
c <= 'Z';
elsif m = "111" then ---------alu pass
z <= a ;
c <= 'Z';
else
z <="ZZZZ" ; -------high impedance
c <= 'Z';
end if;
end process;

end Behavioral;
 =================================USR=============================
Expt No.:2
Batch: B4
Roll No.:404B070

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity universal_sr is
Port ( clk,rst : in std_logic;
s : in std_logic_vector(3 downto 0);
m : in std_logic_vector(1 downto 0);
y : out std_logic_vector(3 downto 0));
end universal_sr;

architecture Behavioral of universal_sr is

signal t : std_logic_vector(3 downto 0);
begin

process(clk,rst)
begin
if rst='1' then
y <= "0000";
elsif clk'event and clk ='1' then

case(m) is
when "00" => --SISO
t(3) <= s(0);
t(2) <= t(3);
t(1) <= t(2);
t(0) <= t(1);
y(0) <= t(0);

when "01" => --SIPO

t(3) <= s(0);
t(2) <= t(3);
t(1) <= t(2);
t(0) <= t(1);
y <= t;

when "10" => --PIPO

t <= s;
y <= t;

when "11" => --PISO

t <= s;
t(2) <= t(3);
t(1) <= t(2);
t(0) <= t(1);
y(3) <= t(0);
 when others => NULL;

end case;
end if;
end process;
end Behavioral;
 ============================LCD=============================
Expt No.:3
Batch: B4
Roll No.:404B070

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity lcd_fsm is
Port ( clk,rst : in std_logic;
data : out std_logic_vector(7 downto 0);
rw,rs,en : out std_logic);
end lcd_fsm;

architecture Behavioral of lcd_fsm is

signal cntr: std_logic_vector(19 downto 0);
type tstate is
(res_state,cwd0_1,cwd1_1,cwd0_2,cwd1_2,cwd0_3,cwd1_3,cwd0_4,cwd1_4,

char0_1,char1_1,char0_2,char1_2,char0_3,char1_3,char0_4,char1_4);
signal pstate,nstate : tstate;

begin
clk_div: process(clk,rst)
begin
if rst = '1' then
cntr <= (others => '0');
elsif clk'event and clk = '1' then
cntr <= cntr + '1';
end if;
end process;

mem_element: process(cntr(19),rst)
begin
if rst = '1' then
pstate <=res_state;
elsif cntr(19)'event and cntr(19) = '1' then
pstate <= nstate;
end if;
end process;

next_st: process(pstate)
begin
case pstate is
when res_state =>
rw <= '0';
rs <= '0';
en <= '0';
nstate <= cwd0_1;
data <= "00111100";
 when cwd0_1 =>
rw <= '0';
rs <= '0';
en <= '1'; ---- enable high
nstate <= cwd1_1;
data <= "00111100"; ----3CH first line first char

when cwd1_1 =>

rw <= '0';
rs <= '0';
en <= '0'; --- enable low
nstate <= cwd0_2;
data <= "00111100";

when cwd0_2 =>

rw <= '0';
rs <= '0';
en <= '1';
nstate <= cwd1_2;
data <= "00001100"; -------0CH display on ,cursor
off

when cwd1_2 =>

rw <= '0';
rs <= '0';
en <= '0';
nstate <= cwd0_3;
data <= "00001100";

when cwd0_3 =>

rw <= '0';
rs <= '0';
en <= '1';
nstate <= cwd1_3;
data <= "00000001"; ---01H clear display screen

when cwd1_3 =>

rw <= '0';
rs <= '0';
en <= '0';
nstate <= cwd0_4;
data <= "00000001";

when cwd0_4 =>

rw <= '0';
rs <= '0';
en <= '1';
nstate <= cwd1_4;
data <= "00000010"; ---02H return home

when cwd1_4 =>

rw <= '0';
rs <= '0';
 en <= '0';
nstate <= char0_1;
data <= "00000010";

when char0_1 =>

rw <= '0';
rs <= '1';
en <= '1';
nstate <= char1_1;
data <= "01010011"; ---S
when char1_1 =>
rw <= '0';
rs <= '1';
en <= '0';
nstate <= cwd0_2;
data <= "01010011";

when char0_2 =>

rw <= '0';
rs <= '1';
en <= '1';
nstate <= char1_2;
data <= "01000011"; ---C
when char1_2 =>
rw <= '0';
rs <= '1';
en <= '0';
nstate <= cwd0_3;
data <= "01000011";

when char0_3 =>

rw <= '0';
rs <= '1';
en <= '1';
nstate <= char1_3;
data <= "01001111"; ---O
when char1_3 =>
rw <= '0';
rs <= '1';
en <= '0';
nstate <= cwd0_4;
data <= "01001111";

when char0_4 =>

rw <= '0';
rs <= '1';
en <= '1';
nstate <= char1_4;
data <= "01000101"; ---E
when char1_4 =>
rw <= '0';
rs <= '1';
en <= '0';
nstate <= res_state;
 data <= "01000101";

end case;
end process;
end Behavioral;
 ============================keypad============================
Expt No.:4
Batch: B4
Roll No.:404B070

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity keypad is
Port ( clk,rst : in std_logic;
row,sw : in std_logic_vector(3 downto 0);
col,seg_ctrl : out std_logic_vector(3 downto 0);
display : out std_logic_vector(6 downto 0));
end keypad;

architecture Behavioral of keypad is

signal temp : std_logic_vector(2 downto 0);

signal clk1 : std_logic;
signal count : std_logic_vector(10 downto 0);

begin
P1: process(clk,rst)
begin
if rst='1' then
count <= (others => '0');
elsif (clk'event and clk='1') then
count <= count+1;
end if;
end process;
clk1 <= count(10);

P2: process(clk1,rst)
begin
if rst='0' then
display <= "0000000";
elsif clk1'event and clk1='1' then
temp <= temp+1;
seg_ctrl <= sw;

case temp is
when "000" => col <="1110";

when "001" =>

if row = "1110" then
display <= "1111001"; --1
elsif row = "1101" then
display <= "0011001"; --4
elsif row = "1011" then
display <= "1111000"; --7
elsif row = "0111" then
 display <= "1000000"; --0
end if;

when "010" => col <="1101";

when "011" =>

if row = "1110" then
display <= "0100100"; --2
elsif row = "1101" then
display <= "0010010"; --5
elsif row = "1011" then
display <= "0000000"; --8
elsif row = "0111" then
display <= "0001110"; --F
end if;

when "100" => col <="1011";

when "101" =>

if row = "1110" then
display <= "0110000"; --3
elsif row = "1101" then
display <= "0000010"; --6
elsif row = "1011" then
display <= "0010000"; --9
elsif row = "0111" then
display <= "0000110"; --E
end if;

when "110" => col <="0111";

when "111" =>

if row = "1110" then
display <= "0001000"; --A
elsif row = "1101" then
display <= "0000011"; --B
elsif row = "1011" then
display <= "1000110"; --C
elsif row = "0111" then
display <= "0100001"; --D
end if;

when others => display <= "0000000";

end case;
end if;
end process;

end Behavioral;