TESTABILITY OF VLSI

MEL ZG531 / ES ZG532

BITS Pilani Venkata Rangam Totakura

Pilani|Dubai|Goa|Hyderabad

1
ASIC / SOC Design FLOW

Design Architecture
Physical Design

RTL
Design/Verification/
Synthesis Timing Analysis

Logic Synthesis
ATPG,BIST,JTAG Pattern
Pattern simulation conversion
DFT Insertion
ATPG
(SCAN,JTAG,BIST)
Tape out

Timing Analysis
What is next?

• Post TAPEOUT?

• The Fabrication of IC

• IC manufacturing process (Video)

Is the manufacturing process ERROR free?

May not be ..

The process of manufacturing is not 100% error free.

There are defects in silicon which contribute towards
the errors introduced in the physical device.
Is the manufacturing process ERROR free?

May not be ..

The process of manufacturing is not 100% error free.

There are defects in silicon which contribute towards
the errors introduced in the physical device.
Defects In Silicon
▪ IC manufacturing process is defect-prone

OPEN Short
Defects In Silicon
▪ IC manufacturing process is defect-prone
Defects : Particles
▪ Caused by impurities
• Shorts for additive material
• Opens for subtractive material
How to find defective parts?
TESTING

❑ Testing is a process of sorting DUTs to

determine their acceptability
PASS

STIMULUS DUT RESPONSE DECISION

FAIL
❑ Quality – Defective Parts Per Million (DPPM)
TESTING & Diagnosis

Functional Test (Logic Verification)

❑ Ascertain the design perform its specified behavior

Manufacturing Test
❑ Exercise the system and analyze the response to
ascertain whether it behaves correctly

Diagnosis
❑ To locate the cause of misbehavior after the
incorrect behavior is detected
Functional Test
• Does the chip simulate correctly?
– Usually done at HDL level
– Verification engineers write test bench for HDL
• Can’t test all cases
• Look for corner cases
• Try to break logic design
• Ex: 64-bit adder
– Test all combinations of corner cases as inputs
• 0, 1, 2, ……., 263-1
Functional vs. Structural ATPG
Carry Circuit
Functional vs. Structural
• Functional ATPG – generate complete set of tests for circuit input-
output combinations
– 129 inputs, 65 outputs:
– 2129 = 680,564,733,841,876,926,926,749,
214,863,536,422,912 patterns
– Using 1 GHz ATE, would take 2.15 x 1022 years
• Structural test:
– No redundant adder hardware, 64 bit slices
– Each with 27 faults (using fault equivalence)
– At most 64 x 27 = 1728 faults (tests)
– Takes 0.000001728 s on 1 GHz ATE
• Designer gives small set of functional tests – augment with
structural tests to boost coverage to 98+ %
Manufacturing Test
• A speck of dust on a wafer is sufficient to kill
chip
• Yield of any chip is < 100%
– Must test chips after manufacturing before
delivery to customers to only ship good parts
• Manufacturing testers are
very expensive
– Minimize time on tester
– Careful selection of
test vectors
Silicon Debug
• Test the first chips back from fabrication
– If you are lucky, they work the first time
– If not…
• Logic bugs vs. electrical failures
– Most chip failures are logic bugs from inadequate simulation
– Some are electrical failures
• Crosstalk
• Dynamic nodes: leakage, charge sharing
– A few are tool or methodology failures (e.g. DRC)
• Fix the bugs and fabricate a corrected chip
Shmoo plots
• How to diagnose failures?
– Hard to access chips
• Pico probes
• Electron beam
• Laser voltage probing
• Built-in self-test
• Shmoo plots
– Vary voltage, frequency
– Look for cause of
electrical failures
Cost of Test escapes
• Testing is one of the most expensive parts of
chips
– Logic verification accounts for > 50% of design
effort for many chips
– Debug time after fabrication has enormous
opportunity cost
– Shipping defective parts can sink a company

• Example: Intel FDIV bug

– Logic error not caught until > 1M units shipped
– Recall cost $450M (!!!)
Cost of Time-to-Market

❑ Delay of product lifetime → Reduces Revenue

❑ Missed opportunities → for short, stagnation time

❑ Moore’s Law → IC gate count double every 18 moths

(4% more gates every month)
 What is DFT ?
✓ It is a technique of adding testability features to IC
design.
✓ Developing and applying manufacturing tests.
✓ The manufacturing tests help to separate defective
components from the healthy ones.

What are DFT Goals?

✓ Quality: A high degree of confidence during testing
✓ Test cost reduction
✓ Time To Volume reduction through test automation

Why so much importance to DFT today?

✓ DFT ranks as one of the top concerns for SoC design
✓ DFT is an integral part of the high level design process
✓ Reduction in feature size leads to new types of manufacturing
faults
 DESIGN FOR TEST

❑ Test merges with design much earlier in the process

❑ Testable circuitry is both Controllable and Observable

❑ Designers must employ special DFT techniques at

specific stages in the development process

❑ Ad Hoc and Structured DFT

Ad Hoc DFT
To enhance a design’s testability without major changes to the
design style

❑ Minimizing redundant logic

❑ Minimizing asynchronous logic

❑ Isolating clocks from the logic

❑ Adding internal control and observation points

However structured DFT techniques yields greater results

Structured DFT
❑ More systematic and automatic approach

❑ Scan Design

❑ BIST (Built-in-Self Test)

– Memory BIST
– Logic BIST

❑ Boundary Scan

Goal is to increase the controllability and observability of a

circuit
System On Chip (SoC)

Clk & GLUE

ANALOG GLUE LOGIC
Rst LOGIC
ROM
RAM ➢ Digital Logic

PLATFORM ➢ Memories
DIGITAL IPs
➢ IOs
DIGITAL
IPs
FLASH
RAM ➢ Analog blocks
ANALOG

PADI
IOSS TCU
SoC with Design For Testability

Clk & ANALOG GLUE

Clk
Rst
&
ANALOG
with GLUE LOGIC
LOGIC ➢ Digital Logic
Rst
with test
wrapper ROM
muxing (scan inserted) RAM
with ROM BIST

➢ Memories
PLATFORM
PLATFORM
(scan inserted)
DIGITAL
DIGITAL IPs
IPs ➢ IOs
(scan inserted)

DIGITAL
DIGITAL
IPs
IPs ➢ Analog blocks
RAM
FLASH (scan inserted)
with RAM BIST
ANALOG
ANALOG
with wrapper

IOSS
PADI TCU JTAG
with test muxing
DFT comes free ?
• Area penalty
• Test Cost
• Performance penalty
TESTABILITY
▪ Controllable : The ability to set a node in a design to a
desired state, ie logic 0 or 1

▪ Observable : The ability to observe a change in logic

value of a node in a design

▪ Testable : If a design is well-controllable and well-

observable it is said to easily testable.

▪ Not possible to add such ‘directly’ controllable &

observable points to every gate in an actual design
TESTABILITY
TESTABILITY (Area/Performance/cost ?)