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555
555
555
UNIVERSITY
TERM PAPER
Section.D6802
Roll No. 12
B.Tech-ECE
3. DATASHEET SPECIFICATIONS
4. GENERAL CONSIDERATIONS
5. EXTERNAL COMPONENTS
9. INDUSTRIAL APPLICATIONS
10. REFRENCES
555 TIMER: AN INTRODUCTION
Many an electronic designs require some sort of timing, for push-
button debouncing, clocking of digital circuits or whatever. One of the
simplest timing circuits, the resistor-capacitor network usually referred
to as an RC circuit has a few serious limitations, particularly when it
comes to temperature stability and the accuracy of capacitors. While
there are many alternative solutions to RC timing there's one that
many hobbyists take to, the 555 timer IC.
Ultra-low power versions of the 555 are also available, such as the
7555 and TLC555.The 7555 requires slightly different wiring using
fewer external components and less power.
555 TIMER: PIN CONNECTIONS
Trigger (Pin 2): This pin is the input to the lower comparator and is
used to set the latch, which in turn causes the output to go high.
Output (Pin 3): Output high is about 1.7V less than supply. Output
high is capable of ISOURCE up to 200mA while output low is capable of
ISINK up to 200mA.
Reset (Pin 4): This is used to reset the latch and return the output to
a low state. The reset is an overriding function. When not used connect
to V+.
Control (Pin 5): Allows access to the 2/3V+ voltage divider point
when the 555 timer is used in voltage control mode. When not used
connect to ground through a 0.01 uF capacitor.
Threshold (Pin 6): This is an input to the upper comparator. See data
sheet for comprehensive explanation.
Discharge (Pin 7): This is the open collector to Q14 in figure 4 below.
See data sheet for comprehensive explanation.
V+ (Pin 8): This connects to VCC and the Philips data-book states the
ICM7555 cmos version operates 3V - 15V DC while the NE555 version
is 3V - 15V DC. Note comments about effective supply filtering and
bypassing this pin below under "General considerations with using a
555 timer"
Pin 2 of the 555 is the trigger input. When the voltage connected to pin
2 is less than 1/3 of the power supply voltage, the output of the lower
comparator forces the logic state of the flip flop to LOW. The output
stage has an inverting action. In other words, when the output of the
flip flop is LOW, the output of the 555 goes HIGH.
Now think about what happens when the power supply is first
connected to the astable circuit. Initially, timing capacitor C is
discharged. The voltage at pin 2 is 0 V and the output of the 555 is
driven HIGH. C starts to charge through resistors R1 and R2. Note that
C is also connected to pin 6, the threshold input of the 555.
When the voltage across C goes past 1/3 of the power supply voltage,
the output of the lower comparator snaps a new level. This doesn't
change the logic state of the flip flop: its output remains LOW.
The inputs to the second comparator are the voltage at pin 6, the
threshold input, and 2/3 VCC from the internal voltage divider.
When the voltage across C goes past 2/3 of the power supply voltage,
the output of the second comparator snaps to a new level, the flip flop
changes state, its output becomes HIGH and the output of the 555
goes from HIGH to LOW.
Inside the 555, the flip flop is connected to an NPN transistor, the
collector of which is connected to pin 7, the discharge pin of the 555.
When the output of the flip flop goes HIGH, the transistor is switched
ON, providing a low resistance path from the discharge pin to 0 V. The
timing capacitor, C, starts to empty through R2 and the voltage across
it decreases.
Note that the capacitor charges through R1 and R2, but discharges
only through R2.
When the voltage across C decreases below 1/3 of the power supply
voltage, the lower comparator snaps to a new level, the flip flop
changes state and the output of the 555 goes HIGH once again.
The graph below shows how the voltage across the timing capacitor,
VC , changes with the output voltage of the 555, Vout:
The initial ouptut pulse is longer than subsequent pulses because C is
completely discharged when the power supply is first connected.
Subsequent HIGH and low times correspond to half-charge/discharge
times, either from 1/3 to 2/3 of the power supply voltage, or from 2/3
to 1/3 of the power supply voltage.
TimeHIGH = 0.69(R1+R2)×C
Remember C charges through both R1 and R2.
TimeLOW = 0.69R2×C
f= = =
THE 555 TIMER – BISTABLE MODE
The simplest circuit you can buid with the help of a 555 timer IC is
bistable 555 timer circuit. Bistable mode is a less common
configuration in 555 timer designs where the circuit has two stable
states but doesn't actually producing any timing signals. A bistable 555
circuit behaves like a flip-flop, effectively providing one bit of memory.
In bistable mode, the 555 timer acts as a basic flip-flop. The trigger
and reset inputs (pins 2 and 4 respectively on a 555) are held high via
pull-up resisters while the threshold input (pin 6) is simply grounded.
Thus configured, pulling the trigger momentarily to ground acts as a
'set' and transitions the output pin (pin 3) to Vcc (high state). Pulling
the reset input to ground acts as a 'reset' and transitions the output
pin to ground (low state). No capacitors are required in a bistable
configuration. Pin 8 (Vcc) is, of course, tied to Vcc while pin 1 (Gnd) is
grounded. Pins 5 and 7 (control and discharge) are left floating.
BISTABLE CIRCUIT
2) LOUDSPEAKERS
A loudspeaker (minimum resistance 64 ) may be connected to
the output of a 555 or 556 astable circuit but a capacitor (about
100µF) must be connected in series. The output is equivalent to a
steady DC of about ½Vs combined with a square wave AC (audio)
signal. The capacitor blocks the DC, but allows the AC to pass as
explained in CAPACITOR COUPLING.
Piezo transducers may be connected directly to the output and
do not require a capacitor in series.
6) SEQUENTIAL TIMING
One feature of the Bistable is that by utilizing both
halves it is possible to obtain sequential timing. By
connecting the output of the first half to the input of
the second half via a 0.001μF coupling capacitor,
sequential timing may be obtained. Delay t1 is
determined by the first half and t2 by the second half
delay.
THANK YOU VERY MUCH
REFRENCES
1. www.doctronics.co.uk/pdf_files/555an.pdf
2. http://www.doctronics.co.uk/555.htm
3. http://www.buzzle.com/articles/555timer-
applications.html
4. http://www.eleinmec.com/article.asp?5
5. http://www.abcofelectronics.com/555timer.htm
6. http://www.epcity.com/shtml/57309.shtml