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Latches, Flip
Latches, Flip
Fundamentals
Tenth Edition
Floyd
Chapter 7
Q Q
S R
NOR Active-HIGH Latch NAND Active-LOW Latch
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Latches
The active-HIGH S-R latch is in a stable (latched) condition
when both inputs are LOW.
0 R 1
0
Assume the latch is initially RESET Q
(Q = 0) and the inputs are at their Latch
inactive level (0). To SET the latch initially
(Q = 1), a momentary HIGH signal RESET
0
1
is applied to the S input while the R Q
0 S
remains LOW.
0 R 01
To RESET the latch (Q = 0), a Q
momentary HIGH signal is Latch
applied to the R input while the S initially
remains LOW. SET
1
0
Q
0 S
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Latches
The active-LOW S-R latch is in a stable (latched) condition
when both inputs are HIGH.
Assume the latch is initially RESET 1 S 1
0
Q
(Q = 0) and the inputs are at their
Latch
inactive level (1). To SET the latch initially
(Q = 1), a momentary LOW signal RESET
is applied to the S input while the R 1
0
1 R Q
remains HIGH.
To RESET the latch a momentary 1 S 01
Q
LOW is applied to the R input
Latch
while S is HIGH. initially
Never apply an active set and 1 SET
0
Q
reset at the same time (invalid). 1R
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Latches
The active-LOW S-R latch is available as the 74LS279A IC.
It features four internal latches with (2)
1S1
two having two S inputs. To SET any (3) (4) 1Q
1S2
of the latches, the S line is pulsed low. (1)
1R
It is available in several packages. (6)
2S (7)
S-R latches are frequently used for 2Q
(5)
2R
switch debounce circuits as shown:
VCC (11)
3S1
(12) (9) 3Q
3S2
(10)
3R
(15)
2 S Q 4S (13)
S 4Q
(14)
4R
R R Position Position
1 1 to 2 2 to 1
74LS279A
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Latches
A gated latch is a variation on the basic latch.
The gated latch has an additional S
Q
input, called enable (EN) that must
be HIGH in order for the latch to
EN
respond to the S and R inputs.
Show the Q output with Q
relation to the input signals. R
Assume Q starts LOW.
Keep in mind that S and R are only active when EN is HIGH.
S
R
EN
Q
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Latches
The D latch is an variation of the S-R latch but combines
the S and R inputs into a single D input as shown:
D D Q
Q
EN EN
Q
Q
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Latches
The truth table for the D latch summarizes its operation. If
EN is LOW, then there is no change in the output and it is
latched.
Inputs Outputs
D EN Q Q Comments
0 1 0 1 RESET
1 1 1 0 SET
X 0 Q0 Q0 No change
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Latches D Q
EN
Determine the Q output for the
Q
D latch, given the inputs shown.
EN
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Flip-flops
A flip-flop differs from a latch in the manner it changes
states. A flip-flop is a clocked device, in which only the
clock edge determines when a new bit is entered.
The active edge can be positive or negative.
D Q D Q
C C
Dynamic Q Q
input
indicator (a) Positive edge-triggered (b) Negative edge-triggered
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Flip-flops
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Flip-flops
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Flip-flops Q
J
CLK
Determine the Q output for the J-K
flip-flop, given the inputs shown. K Q
Notice that the outputs change on the leading edge of the clock.
CLK
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Flip-flops
A D-flip-flop does not have a toggle mode like the J-K flip-
flop, but you can hardwire a toggle mode by connecting Q
back to D as shown. This is useful in some counters as you
will see in Chapter 8.
D Q
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Flip-flops
CLR
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
PRE
Flip-flops J Q
CLK
K Set
PRE Reset
CLR
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Flip-flop Characteristics
Propagation delay time is specified for the rising and
falling outputs. It is measured between the 50% level of the
clock to the 50% level of the output transition.
50% point on triggering edge
tPLH tPHL
The typical propagation delay time for the 74AHC family (CMOS) is
4 ns. Even faster logic is available for specialized applications.
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Flip-flop Characteristics
tPHL tPLH
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Flip-flop Characteristics
Set-up time and hold time are times required before and
after the clock transition that data must be present to be
reliably clocked into the flip-flop.
D
Setup time is the minimum
time for the data to be present CLK
before the clock.
Set-up time, ts
D
Hold time is the minimum time
for the data to remain after the CLK
clock.
Hold time, tH
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Flip-flop Characteristics
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Flip-flop Applications Output
lines
D Q0
Principal flip-flop applications are for C
Q2
Typically, for data storage applications, D
R
Clear
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Flip-flop Applications
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
One-Shots
The one-shot or monostable multivibrator is a device
with only one stable state. When triggered, it goes to
its unstable state for a predetermined length of time,
then returns to its stable state. +V
REXT CEXT
For most one-shots, the length of time Q
CX
in the unstable state (tW) is determined RX/CX
by an external RC circuit. Trigger
Q
Trigger
Q
tW
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
One-Shots
Nonretriggerable one-shots do not respond to any
triggers that occur during the unstable state.
Retriggerable one-shots respond to any trigger, even if
it occurs in the unstable state. If it occurs during the
unstable state, the state is extended by an amount
equal to the pulse width.
Retriggerable one-shot:
Trigger
Retriggers
Q
tW
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
One-Shots
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
The 555 timer
(4) (8)
R1
(7) RESET VCC
DISCH
(6) (3)
The trigger is a THRES OUT
negative-going (2) (5) tW = 1.1R1C1
TRIG CONT
pulse. GND
C1 (1)
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Internal function The 555
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
The 555 timer
Determine the pulse width for the circuit shown.
(4) (8)
R1
10 kW (7) RESET VCC
DISCH
(6) (3)
THRES OUT
(2) (5) tW = 1.1R1C1
TRIG CONT
C1 GND
(1)
2.2 mF
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
The 555 timer
1.44
f =
( R1 + 2 R2 ) C1
(4) (8)
R1
RESET VCC
(7)
DISCH
The frequency and duty cycle R2 (6)
THRES OUT
(3)
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
The 555 timer
Given the components, you can read the frequency from
the chart. Alternatively, you can use the chart to pick
components for a desired frequency.
+VCC
100
10 (4) (8)
R1
RESET VCC
1.0 (7)
DISCH
C1 (mF)
10
1
1M
10
10
kW
0k
MW
kW
W
(6) (3)
W
f (Hz)
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Selected Key Terms
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Selected Key Terms
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved