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Selection of A Topology To Meet The Design Requirements 2.1. Selection of A Suitable Topology
Selection of A Topology To Meet The Design Requirements 2.1. Selection of A Suitable Topology
The objective of this chapter is to choose a PFC topology that would meet the
design specifications for a high input voltage high output power pre-conditioner circuit.
The design specifications of the pre conditioner circuit are given in Table-1.
Efficiency 0.95
Losses <20W
THD <15%
Theoretically, any switching topology can be used to achieve a high power factor
(PF). The boost topology (Fig. 2.1) widely used because of the following advantages [3,
1. The circuit requires the fewest external parts, thus it is the cheapest and cost-effective.
2. The boost inductor located between the bridge and the switch causes the input di/dt to
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be low, thus minimizing the noise generated at the input and therefore, on the
The factors which make a boost converter unsuitable for the work considered in
this thesis are outlined first. The boost topology requires the DC output voltage to be
higher than the maximum expected peak line voltage. For a high input voltage range
(347-480V), using a Boost would require the output voltage to have a magnitude of
750V.This would imply higher losses and higher voltage and current rating devices,
which will not be cost-effective. The higher voltage and current rated components also
lead to higher losses. Also, a boost converter designed for the input range considered in
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this work would be heavily oversized compared to any other converter because the
inductor has to be sized for the highest volt-seconds applied throughout the input-line
range [2]. The boost converter has a large energy storage filter capacitor at the output,
resulting in the inrush current problem which can be eliminated by using additional
The HID lamps require 230V-240V as their open circuit voltage. The lamp driver
used is the half-bridge resonating driver, so the DC voltage bus should be nearly twice
the open-circuit voltage, so that is around 460-480V. Thus the output voltage is set at
490+/-10%.
With the wide input voltage range considered, the topologies to be considered are
those which give the flexibility of the output voltage to be lesser or greater than the input
voltage. DC-DC converters with step-up/step down characteristics are required in all
applications where the input and the output voltage range overlap. In power factor
correction (PFC) applications, the use of step-up/step-down converters such as the buck-
boost, SEPIC or CUK allows one to set the output DC voltage to an arbitrary
intermediate value. For one given DC operating point, it is well known that the buck or
the boost perform conversion with lower component stresses and energy storage
stresses at the expense of more switching components. Neither of these approaches aims
The buck-boost topology, fly back, SEPIC topologies have the step-up/step-down
capabilities. Therefore they all are relevant candidates to meet the input-output
output voltage. Topologies that offer the flexibility of the output voltage without the
inversion of the polarity would be considered a better option. The plain buck-boost, fly
back, Single Ended Primary Inductance Converter (SEPIC) and CUK converters seem the
possible options then. These converters have greatly increased component stresses,
component sizes and reduced efficiency compared to the boost converter [2, 33, 34]. To
reduce the losses caused by these high voltages, a circuit with buck-boost conversion
characteristics, losses comparable to the boost converter and smaller inductor size is
desired.
Thus, the optimum converter however should have low component stresses, low
energy storage requirements and size and efficiency performance comparable to the boost
Taking the above-mentioned issues into consideration, the two topologies that
seem to be ideal for such an application are the Cascaded Buck-Boost topology and the
choosing these topologies is that not much work had been done on them earlier and it
provided an opportunity for an analysis in detail. In this chapter, the basic operation of
these two topologies is explained followed by a loss analysis in the next chapter.
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The cascaded buck-boost topology, shown in Fig. 2.2, will be discussed first. The
basic operation of the buck and boost converters are discussed first followed by the
boost topology. The basic buck and boost mode operations are discussed first.The buck
V 0 < 2⋅ V rms
As seen in Fig. 2.4, the conversion ratio of the buck converter is given by M (D) =D. This
is represented in Eq.2.1.
Vo t on
=
Vi T (2.1)
V0
=D (2.2)
Vi
When the switch is turned ON, the voltage across the inductor is given by
di
VL = L × = Vi − Vo
dt (2.3)
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When the switch is turned OFF, since the current through the inductor L cannot
change instantaneously, the diode provides the freewheeling path for the current to flow
through the load. During this period the voltage across the inductor is given by
dil
Vl = L * = V0 (2.4)
dt
The current through the inductor during the on time is given by Eq. 2.5.
(Vi − V0 )
Il = * D *T (2.5)
L
The discharge portion of the current through the inductor is given by Eq. (2.6).
V0
Il = − * (1 − D) * T (2.6)
L
Equating Eq. (2.5) and Eq. (2.6), the conversion ratio of the buck converter is given in
Eq. (2.7).
Vo t on
=
Vi T (2.7)
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M(D)=D
M(D)
0
D
V 0 > 2⋅ V rms
When the output voltage is greater than the instantaneous line voltage, the circuit
When the switch is closed, the source voltage Vs is applied across the inductor.
The rate of rise of inductor current is dependent on the source voltage and inductance L.
diL
L = Vs (t )
dt (2.8)
The current through the inductor during the on-time is given by Eq. (2.8).
Vs * t on
IL = (2.9)
L
When the switch is open, the voltage across the inductor is:
VL = Vs − Vo (2.10)
V s − V0
IL = * (1 − D) * T (2.11)
L
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The sum of net changes in inductor current expressed by (2.8) and (2.10) should
Vs Vs − Vo
× DT + × (1 − D)T = 0
L L (2.12)
Vs
Vo =
1− D (2.13)
The value of D varies such that 0 < D < 1 and it can be seen from Eq. (2.13) that output
voltage is greater than the source voltage, and hence this circuit is called the boost
converter. The conversion ratio of the boost converter is given in Fig. 2.6.
M(D)=1/1-D
M(D)
0
D
The cascaded buck-boost topology is the buck converter cascaded with the boost
converter. This offers the advantage of the elimination of the inversion of the output
voltage which is seen in the conventional buck-boost converter. In this thesis, both the
switches will be controlled simultaneously. Thus depending on the input voltage, the duty
cycle of the switches will be varied to obtain the desired output voltage. Thus if the input
voltage is higher than the output voltage, the duty cycle is adjusted so that the converter
operates like a buck converter and if the input voltage is lower than the output voltage the
duty cycle is varied so that the converter performs the boost function. The variation of the
duty cycle with the input voltage is given in Table-2 and the calculations are shown in
detail in Appendix A.
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312V 0.606
347V 0.58
480V 0.5
528V 0.476
The equivalent circuit when the position is turned on is given in Fig. 2.8
The voltage across the inductor when the switch is turned on is given by Eq. (2.13).
dil
Vl = L * = Vi (t ) (2.13)
dt
Vi (t )
Il = * D *T (2.14)
L
The equivalent circuit when the switches are in the off position is given in Fig. 2.9
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The voltage across the inductor when the switch is open is given by Eq. (2.15).
dil
Vl = L * = V0 (2.15)
dt
V0
Il = * (1 − D) * T (2.16)
L
V0 D
= (2.17)
Vi 1 − D
The Single-ended Primary Inductor Converter (SEPIC) topology (Fig. 2.10) offers
the flexibility of the output voltage being higher or lower than the input voltage, thus
making itself as one of the candidates for consideration. Because of the coupling between
the inductors in a SEPIC topology, it has an additional advantage of input current ripple
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reduction Compared to the Fly-back converter, the input current in SEPIC converter is
continuous and thus the SEPIC rectifier needs a smaller volume of input filter SEPIC
We assume that the values of current and voltage ripple are small with respect to
inductances L1 and L2 (neglecting the voltage drop across their parasitic resistances).
Therefore, Cp sees a DC potential of Vin at one side, through L1, and ground on
the other side, through L2. The DC voltage across Cp is given in equation Eq. (2.18).
The period of one switching cycle is represented as T. The duty cycle of the switch is
represented by D and the (1-D) is the time during which the switch is turned off. The
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mean voltage across L1 equals to zero during steady-state conditions and so the voltage
seen by L1 during DT (Ton) is exactly compensated by the voltage seen during (1- D) T
where Vd is the forward voltage drop of D1 for a direct current of (IL1 + IL2), and
(V0 + Vd ) D
= =A (2.20)
Vin (1 − D ) i
Where Ai is called the amplification factor, where "i" represents the ideal case for
which parasitic resistances are null. Neglecting Vd with respect to V0 (as a first
approximation), we see that the ratio of V0 to Vin can be greater than or less than 1,
For a SEPIC converter, the peak to peak current ripple in inductors is given in Eq.
v1 (t ) * t on (t )
∆i1 (t ) = (2.21)
L1
v1 (t )* ton (t )
∆i2 (t ) = (2.22)
L2
When the transistor is conducting, the peak current going through the transistor is the
sum of the two inductor currents and is shown in the Eq. (2.23).
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1 1
itrans _ peak = + * ton (t ) * VM sin (ω * t ) (2.23)
L1 L2
The loss analysis of both these topologies is discussed in Chapter 3. Based on the
results of the loss analysis, the topology which is best suited for this application is
selected.