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com Table of Contents

Application Report
Voltage Fed Full Bridge DC-DC and DC-AC Converter for
High-Frequency Inverter Using C2000

Atul Singh and Jabir VS

ABSTRACT
The High-Frequency Inverter is mainly used today in uninterruptible power supply systems, AC motor drives,
induction heating and renewable energy source systems. The simplest form of an inverter is the bridge-type,
where a power bridge is controlled according to the sinusoidal pulse-width modulation (SPWM) principle and the
resulting SPWM wave is filtered to produce the alternating output voltage. In many applications, it is important
for an inverter to be lightweight and of a relatively small size. This can be achieved by using a High-Frequency
Inverter that involves an isolated DC-DC stage (Voltage Fed Push-Pull/Full Bridge) and the DC-AC section,
which provides the AC output. This application report documents the implementation of the Voltage Fed Full
Bridge isolated DC-DC converter followed by the Full-Bridge DC-AC converter using TMS320F28069 ( C2000™)
for High-Frequency Inverters.
Project collateral and source code discussed in this document can be downloaded from this URL: http://
www.ti.com/lit/zip/sprabw0.

Table of Contents
1 Basic Inverter Concept...........................................................................................................................................................2
2 High-Frequency Inverter – Block Diagram........................................................................................................................... 3
3 DC-DC Isolation Stage - High-Frequency Inverter...............................................................................................................4
4 DC-AC Converter.................................................................................................................................................................... 6
5 DC-DC Converter Section (Voltage Fed Full Bridge)........................................................................................................... 7
6 Control Section....................................................................................................................................................................... 9
7 DC-AC Converter Section...................................................................................................................................................... 9
8 Firmware Flowchart.............................................................................................................................................................. 11
9 Waveforms.............................................................................................................................................................................12
10 Conclusion.......................................................................................................................................................................... 13
11 References...........................................................................................................................................................................13
12 Revision History................................................................................................................................................................. 13
A Application Schematic.........................................................................................................................................................14

List of Figures
Figure 1-1. 50 Hz Technology......................................................................................................................................................2
Figure 1-2. Transformerless Inverter Technology........................................................................................................................ 2
Figure 1-3. High-Frequency Inverter Technology........................................................................................................................ 3
Figure 2-1. High-Frequency Inverter – Block Diagram................................................................................................................ 3
Figure 3-1. Push-Pull Topology....................................................................................................................................................4
Figure 3-2. Half Bridge Converter................................................................................................................................................5
Figure 3-3. Full Bridge Converter................................................................................................................................................ 5
Figure 5-1. Functional Block Diagram of UCC27211................................................................................................................... 7
Figure 5-2. Gate Drive Waveforms for the Full Bridge DC-DC Converter................................................................................... 8
Figure 7-1. Functional Block Diagram....................................................................................................................................... 10
Figure 8-1. Firmware Flowchart................................................................................................................................................. 11
Figure 9-1. Output Voltage at No Load...................................................................................................................................... 12
Figure 9-2. Output Voltage and Current (100W Load)...............................................................................................................12
Figure A-1. DC-DC Converter Schematic (Voltage Fed Isolated Full-Bridge)........................................................................... 14
Figure A-2. Control Section Schematic......................................................................................................................................15
Figure A-3. DC-AC Converter Schematic.................................................................................................................................. 16

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Trademarks www.ti.com

Trademarks
C2000™ and Piccolo™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
1 Basic Inverter Concept
There are basically three different inverter technologies:
• Inverter with a 50 Hz transformer
• Inverter without a transformer
• Inverter with a high-frequency (HF) transformer

S1 S3
L1

C1

S2 S4

Figure 1-1. 50 Hz Technology

The applied DC voltage is converted to a 50 Hz AC voltage via a full bridge (S1...S4). This is then transmitted via
a 50 Hz transformer and subsequently fed into the public grid.
• Benefits:
– High degree of reliability due to fewer components
– Safety through galvanic isolation of the DC and AC sides
• Disadvantages:
– Low degree of efficiency resulting from high transformer losses
– Heavy weight and volume (for example, due to 50 Hz transformer)

S1 S3
L1

C1
L2

S2 S4

Figure 1-2. Transformerless Inverter Technology

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www.ti.com High-Frequency Inverter – Block Diagram

The existing DC voltage is converted to a square 50 Hz AC voltage via a full bridge (S1...S4), then smoothed to
a sinusoidal 50 Hz AC voltage via the chokes (L1+L2) and fed into the public grid.
• Benefits:
– Compact and light due to lack of transformer
– Very high degree of efficiency (for example, no transformer losses)
• Disadvantages:
– Additional safety measures (residual current circuit breaker) required. In some countries, a lack of galvanic
isolation between the DC and AC sides is not permitted.
– Complicated lightning protection
– Not compatible with modules that must be earthed
L1

S1 S3 D1 D3 S5 S7
Tr1 L2

C1 C2
L3

D2 D4
S2 S4 S6 S8

Figure 1-3. High-Frequency Inverter Technology

The full bridge (S1...S4) generates a high-frequency square-wave signal with 40 – 50 kHz, which is transmitted
via the HF transformer (Tr1). The bridge rectifiers (D1...D4) convert the square-wave signal back to DC voltage
and store it in the intermediate circuit (L1+C2). A second full bridge (S5...S8) then generates a 50 Hz AC
voltage, which is smoothed to a sinusoidal 50 Hz AC voltage via the chokes (L2+L3) before being fed into the
public grid.
• Benefits:
– Compact and light, as the HF transformer is very small and light
– High degree of efficiency through reduction of transformer losses
– Safety through galvanic isolation between the DC and AC sides
– Suitable for all module technologies, as module earthing (positive and negative) is possible
2 High-Frequency Inverter – Block Diagram

AC Input EMI Filter DPDT Relay Load

AC-DC Isolated TMS320F28069

Power Supply C2000 Series

DC-DC DC-AC
Battery LC Filter
Isolation Stage Converter

Figure 2-1. High-Frequency Inverter – Block Diagram

The present application report documents the implementation of the DC-DC isolation and DC-AC conversion
stage using TMS320F28069. The F2806x Piccolo™ family of microcontrollers provides the power of the C28x
core and the Control Law Accelerator (CLA) coupled with highly integrated control peripherals in low-pin count
devices. This family is code-compatible with previous C28x-based code, as well as providing a high level
of analog integration. An internal voltage regulator allows for single-rail operation. Enhancements have been

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made to the high-resolution pulse width modulator (HRPWM) module to allow for dual-edge control (frequency
modulation).
Analog comparators with internal 10-bit references have been added and can be routed directly to control the
pulse width modulation (PWM) outputs. The analog-to-digital converter (ADC) converts from 0 to 3.3-V fixed full
scale range and supports ratio-metric VREFHI/VREFLO references. The ADC interface has been optimized for
low overhead and latency. The above features make the F2806x Piccolo suitable for handling both the stages of
the High-Frequency Inverter.
The main blocks of the High-Frequency Inverter include:
• DC-DC isolation stage
• DC-AC converter section
3 DC-DC Isolation Stage - High-Frequency Inverter
The selection of the DC-DC isolation stage for the High-Frequency Inverter depends on the kVA requirements of
the inverter. The power supply topologies suitable for the High-Frequency Inverter includes push-pull, half-bridge
and the full-bridge converter as the core operation occurs in both the quadrants, thereby, increasing the power
handling capability to twice of that of the converters operating in single quadrant (forward and flyback converter).
The push-pull and half-bridge require two switches while the full-bridge requires four switches. Generally, the
power capability increases from push-pull to half-bridge to full-bridge.
L
D1
+
VOUT

np ns C R

np ns

VIN D2

Q2 Q1

PUSH PULL

Figure 3-1. Push-Pull Topology

The Push-Pull topology is basically a forward converter with two primaries. The primary switches alternately
power their respective windings. When Q1 is active, current flows through D1. When Q2 is active, current flows
through D2. The secondary is arranged in a center tapped configuration as shown in Figure 3-1. The output filter
sees twice the switching frequency of either Q1 or Q2. The transfer function is similar to the forward converter,
where “D” is the duty cycle of a given primary switch, which accounts for the “2X” term. When neither Q1 nor Q2
are active, the output inductor current splits between the two output diodes.
A transformer reset winding shown on the forward topology is not necessary, the topology is self resetting.

Ns
Vout = Vin ´ D ´ ´2
Np (1)

3.1 Half Bridge Converter

The Half Bridge converter is similar to the Push-Pull converter, but a center tapped primary is not required. The
reversal of the magnetic field is achieved by reversing the direction of the primary winding current flow. In this
case, two capacitors, C1 and C2, are required to form the DC input mid-point. Transistors Q1 and Q2 are turned
ON alternately to avoid a supply short circuit, in which case the duty cycle d must be less than 0.5.

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+VIN
D1 L1
T1
Q1 +VOUT
+
+
C1 +
C3

0V
+

+ Q2
C2

0V D2

Figure 3-2. Half Bridge Converter

For the Half-Bridge converter, the output voltage VOUT equals:

N
Vout = Vin 2 ´ d
N1
(2)

Where, d is the duty cycle of the transistors and 0 < d < 0.5.
N2/N1 is the secondary to primary turns ratio of the transformer.
3.2 Full Bridge Converter
The transformer topology for both the Half Bridge and Full Bridge converter is the same, except that for a given
DC link voltage of the Half Bridge transformer sees half the applied voltage as compared with that of the Full
Bridge transformer. The current flows in opposite directions during alternate half cycles. So flux in the core
swings from negative to positive, utilizing even the negative portion of the hysteresis loop, thereby, reducing the
chances of core saturation. Therefore, the core can be operated at greater Bm value here. The largest power
is transferred when the duty cycle is less than 50%. Diagonal pairs of transistors (Q1-Q4 or Q2-Q3) conduct
alternately, thus, achieving current reversal in the transformer primary.
Output voltage equals:

N
Vout = 2 ´ Vin 2 ´ d
N1
(3)

Where, d is the duty cycle of the transistors and 0 < d < 0.5.
N2/N1 is the secondary to primary turns ratio of the transformer.
+VIN L1
T1 D1
Q1 Q3 +VOUT
+
+
C2

+
C1 0V
+

Q2 Q4
D2

0V

Figure 3-3. Full Bridge Converter

The choice of the DC-DC isolation stage for the High-Frequency Inverter among the three topologies discussed
above depends on the VA requirement. For applications targeting 1KVA and above, the Full Bridge converter is
the ideal choice pertaining to the points below:

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• For a given input voltage, the voltage stress on the transistors is double in case of the push-pull topology than
Half Bridge and Full Bridge configuration.
• The center tapped primary in the case of the push-pull converter limits the operation for a higher VA rating for
the same core size when compared to the Half Bridge and Full Bridge converter.
• To prevent flux walking in the DC-DC stage, the current in both the halves need to be sensed and the duty
cycle needs to be corrected accordingly.
3.2.1 Flux Walking
Faraday’s Law states that the flux through a winding is equal to the integral volt-seconds per turn. This requires
that the voltage across any winding of any magnetic device must average zero over a period of time. The
smallest DC voltage component in an applied AC waveform will slowly but inevitably “walk” the flux into
saturation.
In a low frequency mains transformer, the resistance of the primary winding is usually sufficient to control this
problem. As a small DC voltage component pushes the flux slowly toward saturation, the magnetizing current
becomes asymmetrical. The increasing DC component of the magnetizing current causes an IR drop in the
winding, which eventually cancels the DC voltage component of the drive waveform, hopefully well short of
saturation. In a high frequency switchmode power supply, a push-pull driver will theoretically apply equal and
opposite volt-seconds to the windings during alternate switching periods, thus, “resetting” the core (bringing the
flux and the magnetizing current back to its starting point). But there are usually small volt second asymmetries
in the driving waveform due to inequalities in MOSFET RDSon or switching speeds. The resulting small DC
component causes the flux to “walk”. The high frequency transformer, with relatively few primary turns, has
extremely low DC resistance, and the IR drop from the DC magnetizing current component is usually not
sufficient to cancel the volt-second asymmetry until the core reaches saturation.
The flux walking problem is a serious concern with any Push-Pull topology (bridge, half-bridge or push-pull CT),
when using voltage mode control. One solution is to put a small gap in series with the core. This raises the
magnetizing current so that the IR drop in the circuit resistances is able to offset the DC asymmetry in the drive
waveform. But the increased magnetizing current represents increased energy in the mutual inductance, which
usually ends up in a snubber or clamp, increasing circuit losses. A more elegant solution to the asymmetry
problem is an automatic benefit of using the current mode control (peak or average CMC). As the DC flux
starts to walk in one direction, due to the volt-second drive asymmetry, the peak magnetizing current becomes
progressively asymmetrical in alternate switching periods. However, current mode control senses the current and
turns off the switches at the same peak current level in each switching period, so that ON times are alternately
lengthened and shortened. The initial volt-second asymmetry is thereby corrected, peak magnetizing currents
are approximately equal in both directions, and flux walking is minimized.
However, with the Half Bridge topology this creates a new problem. When current mode control corrects the volt-
second inequality by shortening and lengthening alternate pulse widths, an ampere-second (charge) inequality
is created in alternate switching periods. This is of no consequence in full bridge or push-pull center-tap circuits,
but in the half-bridge, the charge inequality causes the capacitor divider voltage to walk towards the positive
or negative rail. As the capacitor divider voltage moves away from the mid-point, the volt-second unbalance is
made worse, resulting in further pulse width correction by the current mode control. A runaway situation exists,
and the voltage will walk (or run) to one of the rails.
Considering the above points, the Full Bridge converter seems to be the ideal choice for the High-Frequency
Inverter rated above 1kVA.
4 DC-AC Converter
The DC-AC Converter section of the High-Frequency Inverter is an H-Bridge, which converts the high voltage
DC bus (380 V) into sinusoidal AC waveform.
The sinusoidal PWM generation is done using the PWM interrupt handler in TMS320F28069 by entering into an
infinite loop. A look-up table is formed that samples the instantaneous values at specific time intervals based on
the operating frequency of the DC-AC section. The DC-AC section is operated at 20 kHz, based on that the total
number of samples for half cycle is 200. The instantaneous value is then multiplied by the maximum duty cycle
count to get the duty cycle count at the corresponding sample instant. This generates the sinusoidal PWM for
the full bridge section. The DC-AC section consists of high-side and low-side drivers to drive the Mosfets in the
H-Bridge configuration followed by an output L-C- L filter resulting in sinusoidal sine wave.

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5 DC-DC Converter Section (Voltage Fed Full Bridge)

The DC-DC section consists of 120 V boot, 4A peak high frequency high-side and low-side driver UCC27211 for
driving the high-side and low-side FET’s of the Full Bridge converter.
In UCC27211, the high side and low side each have independent inputs, which allow maximum flexibility of input
control signals in the application. The boot diode for the high-side driver bias supply is internal to the chip. The
UCC27210 is the pseudo-CMOS compatible input version and the UCC27211 is the TTL or logic compatible
version. The high-side driver is referenced to the switch node (HS), which is typically the source pin of the
high-side MOSFET and drain pin of the low-side MOSFET. The low-side driver is referenced to VSS, which is
typically ground. The functions contained are the input stages, UVLO protection, level shift, boot diode, and
output driver stages.
Figure 5-1 shows the independent control of the high-side and low-side drivers and the internal bootstrap diode
capable of withstanding the reverse voltage up to 120 V.

2 HB

UVLO
Level 3 HO
Shift

4 HS
HI 5

VDD 1

UVLO
8 LO

LI 6 7 VSS

Figure 5-1. Functional Block Diagram of UCC27211

The VDD supply of the IC is derived from the 12 V battery itself (HF inverter source). The DC-DC stage converts
the 12 V input voltage to a regulated 380 V DC bus, which is the input to the DC-AC section. To avoid battery
inrush current at the start of the PWM, soft start is implemented that controls the rate of di/dt. The PWM’s initially
start with a very low duty and finally duty cycle is adjusted as per the regulation point of the DC bus voltage
(380 V). The operating frequency for the switches in the DC-DC section is 40 kHz, the output filter sees twice the
frequency of the switches M6 or M9 (see Figure A-1).
5.1 Voltage Fed Full Bridge Converter Transformer Calculation
• Total Output Power Po = (Vo + Vrl + Vd) Io
Where, Vo = Output voltage

Vrl = Voltage drop due to winding resistance

Vd= Forward voltage drop of the output diode

Io= Output current

• The Area Product for this configuration is given as:

Po é 2 + (1/ h)ù
Ap = ë û
4.Kw .J.Bm.Fsw

Where, η = Efficiency of the Full Bridge converter

Kw = Window factor

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J = Current Density (A/m2)

Bm = Magnetic flux density

Fsw = Switching frequency

• Primary Number of Turns

Vin (maximum )
Np =
4.Ac.Bm.Fsw
Where, Ac= Core area

Vin (maximum) = Maximum input voltage applied to the Full Bridge converter

• Turns Ratio

n=
(Vo + Vrl + Vd )
2.D max.Vin min
Where, Vin min = Minimum input voltage applied to the Full Bridge converter

Secondary turns Ns = n x Np

• RMS Values of Currents

Isec = Io√Dmax

Ipri = n x Io

Where, Isec = Secondary current

Ipri = Primary current

Using the above calculations, the number of turns can be calculated for the required output power and the rms
values of the primary and secondary currents can also be found out for a given core area.
The calculation was done considering 1kVA requirement with battery input as the input voltage (12 V) in EF32
core and the corresponding numbers of turns were calculated for both primary and secondary.

Figure 5-2. Gate Drive Waveforms for the Full Bridge DC-DC Converter

In order to minimize flux walking, as discussed Section 3.2.1, the peak current in each of the conducting halves
can be sensed using the fully differential isolation amplifier AMC1100.

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The AMC1100 is a precision isolation amplifier with an output separated from the input circuitry by a silicon
dioxide (SiO2) barrier that is highly resistant to magnetic interference. This barrier has been certified to provide
galvanic isolation of up to 4250 V peak, according to UL1577 and IEC60747-5-2. Used in conjunction with
isolated power supplies, this device prevents noise currents on a high common-mode voltage line from entering
the local ground and interfering with or damaging sensitive circuitry.
After sensing the peak current, the duty cycle is corrected for each of the corresponding halves and volt second
asymmetry is thereby corrected, to minimize flux walking.
6 Control Section
The control section consists of TMS320F28069 performing the control operation generating PWM’s for both
DC-DC section and SPWM’s for the DC-AC section using the PWM interrupt handler.
• MCU PWM Outputs
• DC-DC section
– PWM1DH_MCU = High-Side Input Gate Drive 1
– PWM1DL_MCU = Low-Side Input Gate Drive 1
– PWM2DH_MCU = High-Side Input Gate Drive 2
– PWM2DL_MCU = Low-Side Input Gate Drive 2
• DC-AC section:
– PWM1AH_MCU = High-Side Input Gate Drive 1 for UCC27712
– PWM1AL_MCU = Low-Side Input Gate Drive 1 for UCC27712
– PWM2AH_MCU = High-Side Input Gate Drive 2 for UCC27712
– PWM2AL_MCU = Low-Side Input Gate Drive 2 for UCC27712
• The Opto couplers HCPL-0211 provides isolated gate drives for the DC-DC section:
– PWM1DH = High-Side Input Gate Drive for UCC27211 (Driver 1)
– PWM1DL = Low-Side Input Gate Drive for UCC27211 (Driver 1)
– PWM2DH = High-Side Input Gate Drive for UCC27211 (Driver 2)
– PWM2DL = Low-Side Input Gate Drive for UCC27211 (Driver 2)
7 DC-AC Converter Section
The DC-AC converter section consists of high- and low-side driver UCC27712, which is a high-voltage, high-
speed power Mosfet and IGBT driver with independent low side and high side referenced output channels. It has
a floating channel designed for bootstrap operation and fully operational to +600 V. The floating channel can be
used to drive an N-channel power MOSFET or IGBT in the high-side configuration, which operates up to 600 V.
Figure 7-1 shows the functional block diagram of the driver. The bootstrap diode is placed external to the driver
and the device can handle peak currents up to 4A.

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VB

UV
Detect
R Q
Pulse R HO
HV Level Q
Shifter Filter S
VSSCOM
HIN Level
Shift Pulse
Generator
VS

VCC

UV
Detect

LO

VSSCOM
LIN Level Delay
Shift
COM

Figure 7-1. Functional Block Diagram

The AC voltage feedback to the MCU for closed-loop control is given by scaling down the voltage by a resistor
divider network and rectifying it by means of a precision rectifier circuit. The precision rectifier circuit is built with
the high-speed precision difference amplifier INA143 followed by TL082 powered from a dual supply (±12 V).
The rectified and scaled down Sine wave is fed to the MCU for closed-loop control of the output voltage.
The load current sense is done using ACS709, which is a precision linear Hall sensor integrated circuit with
copper conduction path. Applied current flows through the copper conduction path, and the analog output
voltage from the Hall sensor IC linearly tracks the magnetic field generated by the applied current. The voltage
on the overcurrent input (VOC pin) allows to define an overcurrent fault threshold for the device. When the
current flowing through the copper conduction path (between the IP+ and IP– pins) exceeds this threshold, the
open drain overcurrent fault pin transitions to a logic-low state and can be used to shut down the PWM pulses
of the DC-AC section and DC-DC section as well to provide protection against overload and short circuit of the
load.

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www.ti.com Firmware Flowchart

8 Firmware Flowchart

Power on reset

Set the clock to 60 MHz

Initialize GPIO
Initialize ADC

Initialize PWM1 for DC-DC Conversion

Configure the PWM1 Interrupts

Start the PWM switching

with very low duty cycle for
soft start

Is the DC BUS NO Increase the

voltage equal
Duty Cycle
to 380 Volts?

YES

Initialize PWM2 for DC-AC conversion

Configure the PWM2 Interrupts

Generate the Sine

modulated PWM using the
PWM Interrupt Handler

Enter Infinite loop and

operate using the interrupt
handlers

Figure 8-1. Firmware Flowchart

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Waveforms www.ti.com

9 Waveforms

Figure 9-1. Output Voltage at No Load

Figure 9-2. Output Voltage and Current (100W Load)

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www.ti.com Conclusion

10 Conclusion
This application report documents the concept reference design for the DC-DC Stage and the DC-AC Converter
section that can be used in the High-Frequency Inverter using TMS320F28069, which handles the PWM
generation and closed loop control of both the stages.
The reference design was tested for 100W load and can be further tested at higher VA ratings modifying
the power components of the DC-AC Converter Section. The reference design is targeted for High-Frequency
Inverters rated for higher VA used in the industrial segment.
11 References
1. Analysis of a Voltage-fed Full Bridge DC-DC Converter in Fuel Cell Systems by A. Averberg, A. Mertens,
Power Electronics Specialists Conference, 2007. PESC 2007. IEEE.
2. A Current Mode Control Technique with Instantaneous Inductor Current Feedback for UPS Inverter by H.Wu,
D.Lin, D. Zhang, K. Yao, J.Zhang, IEEE transaction, 1999.
3. Power Electronics Converter, Applications and Design by Mohan, T.M. Undeland, and W.P. Robbins.
4. TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064,
TMS320F28063, TMS320F28062 Piccolo Microcontrollers Data Manual (SPRS698)

12 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (January 2018) to Revision D (April 2021) Page
• Updated the numbering format for tables, figures and cross-references throughout the document...................3

Changes from Revision B (June 2015) to Revision C (January 2018) Page

• Updates were made in Section 6........................................................................................................................9
• Updates were made in Section 7........................................................................................................................9
• Update was made in Appendix A......................................................................................................................14

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 14
Application Schematic

Inverter Using C2000

VBAT

2
D16
C73 C74 15V VBAT
4.7uF 100nF

1
A.1 Application Schematic
A Application Schematic

EE32/16/9

2
D16A
U18 C78 15V M6 PHP20NQ20T 9 1011121314
100nF L7 380VDC

1
1 2 PHP20NQ20T M7 1 8
VDD HB R62
5 3 2DH 2 3 4 5 6 7
PWM1DH HI HO 1DH
6 4 4.7E 1DH EE32/16/9 D17 D20
PWM1DL LI HS C1D
DSEP8-12A DSEP8-12A
7 8 R65 T2
VSS LO 14
1DL
J4
UCC27211 4.7E 1 13
1 C80
2 220uF
7 10
9
VBAT VBAT 8
3
4
5
6

2
C81 D22 D21 D23
C82 100nF 15V DSEP8-12A DSEP8-12A
4.7uF

1
C1D C2D C94

2
D22A
U19 4700pF/2kV
15V

Voltage Fed Full Bridge DC-DC and DC-AC Converter for High-Frequency
C83

1
1 2 100nF
VDD HB R68 M9
5 3 M8
PWM2DH HI HO 2DH
6 4 4.7E
PWM2DL LI HS 1DL 2DL
7 8 C2D
PHP20NQ20T PHP20NQ20T
VSS LO R70
2DL
UCC27211
4.7E

5VDC 3.3VDCISO
U21

1 8
VDD1 VDD2
2 7
VINP VOUP ISWADC
R85
25mOhm 3 6
VINN VOUN

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U20 4 5

6
GND1GND2
VBAT
1 AMC1100

TAB
SHDN 4
OUT
R86
2 100k
IN C35
5 10uF
ADJ
3
GND R87
31.926k

TL1963A

Figure A-1. DC-DC Converter Schematic (Voltage Fed Isolated Full-Bridge)

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SPRABW0D – MAY 2014 – REVISED APRIL 2021
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 www.ti.com

12VDC 12VDC
PWM1DH_MCU PWM2DH_MCU
U1 380VDC

6
R1 R2
5VDC ISO 1.5k 1.5k
1 3.3VDCISO

TAB
SHDN 4 C1 R3

8
8
OUT U2 C2 U3 0.1uF 110k
R4 0.1uF
2 100k 2 7 2 7
IN PWM1DH PWM2DH
C3

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5 10uF
ADJ 3 5 3 5 R5
3 SHIELD SHIELD
GND 110k
R32
57.9k
HCPL-0211 HCPL-0211
TL1963A

12VDC R6
PWM2DL_MCU 110k
12VDC
PWM1DL_MCU
R7
1.5k
R8
VBUS
U5 1.5k C6

6
0.1uF

8
12VDC ISO U4 R9

8
1 5VDC ISO U6 3.3k

TAB
SHDN 4 2 7
OUT PWM2DL
2 7
PWM1DL
R10
2 3 5

SPRABW0D – MAY 2014 – REVISED APRIL 2021

100k
IN C9 3 5 C8 SHIELD
5 10uF SHIELD
ADJ 0.1uF
3 HCPL-0211
GND R11 HCPL-0211
31.926k

TL1963A

3.3VDCISO
3.3VDCISO
U8 TMS320F28069U-PFP
2 2 2 2 2 2 2 J1
4 19 ADC-A0 3.3VDCISO R80 3.3VDCISO
C13 C13A C13B C14 C14A C14B C17
VdIO33 ADC-A0 ISWADC 2.2K TMS 1 2 TRSTn
2.2uF 2.2uF 2.2uF 2.2uF 2.2uF 2.2uF 2.2uF 11 18 ADC-A1
1 1 1 1 1 1 1 VdIO33 ADC-A1 TDI 3 4 TDIS
30 17 ADC-A2
49 VdIO33 CMP1A/ADC-A2 VBUS VTREF 5 6
VdIO33 R78 TDO 7 8 R79
63 16 ADC-A4
VdIO33 CMP2A/ADC-A4 IADC 2.2K RTCK 9 10 2.2K
L2 BEAD 74 15 ADC-A5
VdIO33 ADC-A5 TCK 11 12
14 ADC-A6
CMP3A/ADC-A6 VADC EMU0 13 14 EMU1
37
VdFL33
20 22 ADC-B0
VdADC33 ADC-B0 23 ADC-B1 CON14A
2 ADC-B1 24 ADC-B2
C17A 2 CMP1B/ADC-B2
12 Vdd18 25 ADC-B4
2.2uF Vdd18 CMP2B/ADC-B4
1 29 26 ADC-B5
51 Vdd18 ADC-B5 27 ADC-B6
65 Vdd18 CMP3B/ADC-B6
72 Vdd18
2 Vdd18
2 2 2 2 2
C18B
C17B C18 C18A 2.2uF C19 C20 69 GPIO-00
1 GPIO-00 PWM1DH_MCU
2.2uF 2.2uF 2.2uF 2.2uF 2.2uF 68 GPIO-01
1 1 1 1 1 GPIO-01 PWM1DL_MCU
67 GPIO-02
GPIO-02 66 PWM2DH_MCU 3.3VDCISO
3.3VDCISO R12 GPIO-03
GPIO-03 PWM2DL_MCU
R13 9 7 GPIO-04 RS232
71 XRSn GPIO-04 8 PWM1AH_MCU
GPIO-05
VREGENZ GPIO-05 PWM1AL_MCU
46 GPIO-06
2.2K GPIO-06 PWM2AH_MCU
C21 45 GPIO-07
2.2K GPIO-07 PWM2AL_MCU

Copyright © 2021 Texas Instruments Incorporated

100nF 36 43
10 TEST GPIO-08 39
54 TRSTn GPIO-09 60
SW1 58 TCK GPIO-10 59 C10 C11 C12
57 TMS GPIO-11 35 100nF 100nF 100nF

Figure A-2. Control Section Schematic

GPIO-12
TDI GPIO-12
2
6
16

56 75
TDO GPIO-13 76 TP1
48 GPIO-14 70 TEST POINT
V-
V+

SW DPST 47 X1 GPIO-15 J2
VCC

X2 44 GPIO-16 RXD 12
1

GPIO-16 TXD 11 ROUT1 14 UART1TXD_232 UART1TXD_232 1

42 GPIO-17 DIN1 DOUT1
TCK GPIO-17 41 GPIO-18 7 UART1RXD_232 2
GPIO-18 9 DOUT2 13 UART1RXD_232 3
TDI 3 52 GPIO-19 ROUT2 RIN1
TDO 13 DGND GPIO-19 5 10 8
DGND GPIO-20 C15 DIN2 RIN2 C16
TMS 28 6
TRSTn 38 DGND GPIO-21 78 1 4 CON3
DGND GPIO-22 3 C1+ C2+ 5
50 1 C1- C2-
64 DGND GPIO-23 77 100nF
GND

DGND GPIO-24 100nF

R14 73 31
2.2K DGND GPIO-25 62
15

LED1 LED2 LED3 LED4 GPIO-26 61

GPIO-27 40 RXD
21 GPIO-28 34 TXD MAX3232CPW
R14A ADCGND GPIO-29 33 U7
2.2K GPIO-30 32 LED1
D27 D28 D29 D30 3.3VDCISO GPIO-31 79 LED2
53 GPIO-32 80 LED3
LED LED LED LED GPIO-39 GPIO-33 55 LED4
GPIO-34

R74 R75 R76 R77

330E 330E 330E 330E

Voltage Fed Full Bridge DC-DC and DC-AC Converter for High-Frequency
Inverter Using C2000
15
Application Schematic
 16
380VDC U9
R15 R16 R17 12VDC ISO
12VDC ISO VP VP+ 1 8
Ref NC
100k 100k 100k
VN- 2 7 12VDC ISO

2
M1 FCPF400N60 R18 -IN V+
C24 D2 330E C25 C26
100nF 15V FCPF400N60 M2 VP+ 3 6 0.1uF 0.1uF
+IN OUT U10A

1
8
Application Schematic

PWM1AH PWM2AH R21 R22 R23

D5 VN VN- 4 5 3 D6

2
V- Sense +
1
100k 100k 100k
U11 D2A R24 2 -
MURS160

Inverter Using C2000

C27 15V 330E INA143/SO D1N4148
1 8 4.7uF

1
4

VCC VB R25 TL082

2 7 -12VDC ISO C28
D PWM1AH_MCU HIN HO PWM1AH
VP 0.1uF C29
4.7E
3 6 -12VDC ISO 0.1uF
PWM1AL_MCU LIN VS A1D
R26
4 5
COM LO PWM1AL
L3 C30
4.7E
AC TRANS 5uF 12VDC ISO
UCC27712
VADC
VN U10B
8

12VDC ISO U12 5VDC ISO 5 + D7

A1D 7
A2D 6

2
-
1 24 R27 D1N4148
C31 D8 IP1+ NC4
4

100nF 15V 2 23 R28 TL082

IP2+ NC3 1k

1
4.7k
3 22 FAULT_EN
D9 IP+FAULT_EN R29 -12VDC ISO

2
4 21
U13 D8A IP4+ VOC R31
MURS160 1k
C32 15V FCPF400N60 5 20
1 8 4.7uF M4 IP5+ VCC R33

1
VCC VB 1k
R34 M3 6 19
2 7 IP6+ FAULT
PWM2AH_MCU HIN HO PWM2AH 330k
7 18 C33 C34
4.7E PWM2AL IP1- VIOUT IADC
3 6 10nF 0.1uF
PWM2AL_MCU LIN VS A2D PWM1AL 8 17
R35 FCPF400N60
4 5 IP2- FILTER
COM LO PWM2AL
9 16
4.7E IP3- VZCR C37
UCC27712 10 15 C38 10nF
IP4- GND
1nF
11 14
IP5- NC1
12 13
IP6- NC2

ACS709

C39

R36
4700pF/2kV 1

MBRD1045 1uH -12VDC ISO

VBAT T3 1 D12 L4 12VDC ISO

Voltage Fed Full Bridge DC-DC and DC-AC Converter for High-Frequency
VBAT 5 6 4
3

C40 C41 2 7 -12VDC ISOF -12VDC ISOC

3 8 1 C42 C43
4.7uF 4.7uF 4 4 10uF 10uF C44 C45
C46 9 3 50V 50V 10uF 10uF
R37 1 10 35V
R38 0.1uF D13
3
2
1

0E 20k 1/2W 100V EE25137 MBRD1045

C47 L5 1uH -12VDC ISOF

10uF 10uF J3
R39 0.1uF 10uF 10uF C50 C51 CON3
D14 C48 C49
C52 402k BAS16
U14

470pF 1 10
C53 RC VDD
2 9
SS VBP R40 Q1

Copyright © 2021 Texas Instruments Incorporated

0.22uF 3 8 C54
DIS/EN GDRD Si448EY 1000pF 12VDC ISO
20E
4 R41
COMP 7
5 ISNS
FB 2k
6 R42 R43

PMPD
GND

Figure A-3. DC-AC Converter Schematic

10E 10k
R44 U15 LM5088 2
1

11
C55 C56 2 2
TPS40210DGQ 0.18 1W R45 EN 2 15 C57 M5 C58
EN BOOT
VIN

1uF 100pF C59 C60 C61 1.43k 100nF 1uF

1uF 100nF CSD185Q351A 1
1 100nF
1 14
10 HG
RES L6
C63 R47 R48 C62 13
SW
4

R46 39nF 16
33pF VCC D15 1 10uH 25mOhm
2k 3.01k 49.9E
C64 R49 12
R50 CS 3
221k MBRB2060CT

4
1
R51 19.6k 220nF 4 2 2
U16 RAMP
3.01k
R53 TCMT1109 11 R52 C65 C66
CSG
24mOhm 22uF 1uF

3
2 R54 C67 5 1 1
1k RT 9
OUT -12VDC ISOC
0E
C68 C69
470pF R55 8
1

3300pF 200pF 3 FB
5.11k
AGND
COMP
EP

3 SS
C70
6
7
17

U17 R56 1uF R57

2

TL431AIDBZ 10.2k 14.7k

C71 R58

2nF 17.4k
C72
R59
82pF 1.65k

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SPRABW0D – MAY 2014 – REVISED APRIL 2021
www.ti.com
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