KYLE JUNZEL P.

BAÑARIA BSCompE-4

1. Explain how the ISA can affect the HSA.

The architecture and instruction set of a processor determine how many cycles are needed to
perform a given instruction. Some instruction sets are more energy-efficient than others.
Heterogeneous architectures have already been introduced.

The ISA defines the characteristics of a computer's instruction set. The HSA serves as the
subsystems and their connections to each other.

An instruction set can be built into a processor or an interpreter, and it can be emulated in
software. The hardware design of an ISA is more energy-efficient than that of an emulated
software version.

A distinction between computer design and architecture could be made by having hardware
attributes that align with the instruction set and memory addressing techniques. The defining line
between the two is muddled as ISA and HSA each can be used to replace portions of the other.

ISA specifies what the processor is capable of doing and the ISA, how it gets accomplished. So
the instruction set architecture is basically the interface between your hardware and the software.
The only way that you can interact with the hardware is the instruction set of the processor.

2. Explain the instruction based on its addressing modes, data addressing, and the movement of data in

the instruction.

MOV AH, 01H

MOV key, AL

Int 21h

-The operation accepts a character from the keyboard buffer. If none is present, waits for keyboard
entry. It returns the character in AL.

Problem:

1. MIPS = [F+(F(.5))]/2 The value of MIPS is directly proportional to the value of F(frequency +
fifty percent)over 2(CPIave). MIPS = F(1+(1(.5)))/2 = F(1.5)/2 = F(.75)

2.

Generate (R5) = A OR B :
MOV R2, B //R2 = B

MOV R1, A //R1 = A

ADD R1, R2 //R1 = R1 + R2

//R1 = A + B

MOV R5, R1 //R5 = A + B

R5 <- (R1) OR (R2)

3.

ADD U, X, Y

Once-address format:

MOV R1, Y // R1 = Y

MOV R2, X // R2 = X

ADD R2, R1 // R2 = X + Y

MOV U, R2 // U = X + Y

Zero-address format:

SUB V, X, Y

One-address format:

MOV R1, Y // R1 = Y

MOV R2, X // R2 = X

SUB R2, R1 // R2 = X – Y

MOV V, R2 // V = X - Y
4.

A. ADD1 R4, R2, R1

ADD R2, R1 // R2 = $00008124; R1 = $00000100

// R2 = R2 + R1

// R2 = $00008224

ADD R4, R2 //R4 = $00000000 ; R2 = $00008224

// R4 = R4 + R2

// R4 = $00008224

B. ADD1 R5, R3, #$80FE

ADD R3, #$80FE // R3 = $1234FF78 + #$80FE

// R3 = $004E1005

ADD R5, R3 // R5 = R5 + R3

// R5 = R5 + R3

// R5 = $004E1005

C. STORE (R1) +, R, R3 ;store value of the register to a memory location

MOV R, R3 // R3 = $1234FF78 ;R = R3

// R = $1234FF78

ADD R1, R // R1 = $00000100 ; R = $1234FF78

// R1 = R1 +R