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Interfacing
Interfacing
Interfacing
It has 8 input lines identified as DI1 to DI8 and 8 output lines identified as DO1
to DO8. When it is used to communicate or transfer data from input devices,
input lines are used while output lines are used for data transfer to output
devices.
Two selecting lines DS1 and DS2 are used to identify what device will be
interfaced along with a control signal MD.
Two control groups, labeled group A control and group B control define how
the three I/O ports operate. There are several different operating modes for
the 8255 and these modes must be defined by the CPU writing programming
or control words to the device 8255.
The line group of port C consists of two 4 bit ports. One of the 4 bit group is
associated with group A control and the other 4 bit group with group B
control device signals. The upper 4 bits of port C are associated with group A
control while the lower 4 bits are associated with group B control.
The final logic blocks are read/write control logic and data bus buffer. These
blocks provide the electrical interface between the 8085 and the 8255.
The data bus buffer buffers the data I/O lines to/from the 8085 data bus. The
read/write control logic routes the data to and from the correct internal
registers with the right timing. The internal path being enabled depends on
the type of operation performed by the 8085. The type of operation can be I/O
read or I/O write.
The 8259 PIC controls the CPU's interrupt mechanism, by accepting several
interrupt requests and feeding them to the processor in order. For instance,
when a keyboard registers a key-hit, it sends a pulse along it's interrupt line
(IRQ 1) to the PIC chip, which then translates the IRQ into a system interrupt,
and sends a message to interrupt the CPU from whatever it is doing. Part of
the kernel's job is to either handle these IRQs and perform the necessary
procedures (poll the keyboard for the scan code) or alert a user space
program to the interrupt (send a message to the keyboard driver).
Without a PIC, you would have to poll or continuously monitor all the devices
in the system to see if they want to do anything (signal an event), but with a
PIC, your system can run along nicely until such time that a device wants to
signal an event, which means you don't waste time going to the devices, you
let the devices come to you when they are ready.
Microprocessors/6th/EcE/Dipankar Mishra April 1, 2011
8259 Features
Block Diagram
Features
Keyboard section:
• The two operating modes of keyboard section are 2- 2-key lockout and N-
key rollover.
• In the 2-
2-key lockout mode, if two keys are pressed simultaneously, only
the first key is recognized.
• In the N-
N-key rollover mode simultaneous keys are recognized and their
codes are stored in FIFO.
• The keyboard section also have an 8 x 8 FIFO (First In First Out) RAM.
• The FIFO can store eight key codes in the scan keyboard mode. The
status of the shift key and control key are also stored along with key
code. The 8279 generate an interrupt signal when there is an entry in
FIFO. The format of key code entry in FIFO for scan keyboard mode is,
Display section:
Scan section:
• The scan section has a scan counter and four scan lines, SL0 to SL3.
• In decoded scan mode, the output of scan lines will be similar to a 2-
2-to-
to-
4 decoder.
• In encoded scan mode, the output
output of scan lines will be binary count,
and so an external decoder should be used to convert the binary count
to decoded output.
Microprocessors/6th/EcE/Dipankar Mishra April 1, 2011
• The CPU interface section takes care of data transfer between 8279
and the processor.
• This section has eight bidirectional data lines DB0 to DB7 for data
transfer between 8279 and CPU.
• It requires two internal address A =0 for selecting data buffer and A = 1
for selecting control register of8279.
• The control signals WR (low), RD (low), CS (low)
(low) and A0 are used for
read/write to 8279.
• It has an interrupt request line IRQ, for interrupt driven data transfer
with processor.
• The 8279 require an internal clock frequency of 100 kHz. This can be
obtained by dividing the input clock by an internal prescaler.
prescaler.
• The RESET signal sets the 8279 in 16-
16-character display with two -key
lockout keyboard modes.
Features
Control Word Register : This register is accessed when lines A0 and A1 are at
logic 1. It is used to write a command word which specifies the counter to be
used (binary or BCD), its mode, and either a read or write operation.
Counters : These three functional blocks are identical in operation. Each
counter consists of a single, 16 bit, pre-settable, down counter. The counter
can operate in either binary or BCD and its input, gate and output are
configured by the selection of modes stored in the control word register. The
counters are fully independent.
8254 programming
Microprocessors/6th/EcE/Dipankar Mishra April 1, 2011