CIRCUIT SIMULATION LAB

LAB REPORT

EXPERIMENT:7

SUBMITTED TO: Prof. Manodipan Sahoo

SUBMITTED BY : SANDEEP KUMAR (20MT0348)

Subject code: ECC 566

DEPARTMENT OF ELECTRONICS ENGINEERING INDIAN INSTITUTE

OF TECHNOLOGY

(INDIAN SCHOOL OF MINES),

DHANBAD DHANBAD-826004

JHARKHAND
 Experiment – 7
Objective :
To finddesign and simulate various Current Mirror Topologies and plot Ids v/s Vdc curve and
output resistance v/s frequency characteristics for different topologies.

Theory :

Current Mirrors :
Current Mirrors are current copying circuits which are used to bias the typical circuits like
differential amplifiers and acts as current source for many other circuits as well.

So the basic property expected from a current mirror are same as from a current source i.e.
high output resistance and others are accurate current copying and low voltage headroom.

From now on we will refer to Current Mirror as CM .

So we will observe these three properties for all 5 topologies under consideration namely :

 Simple CM
 Cascode CM
 Improved Wilson CM
 Modified Cascode CM
 Regulated CM

Each of these topologies has their characteristics which make them suitable for one application
an unsuitable for other.

Let’s Arrange these topologies in order corresponding to the high op resistances, voltage
headroom, and current precision.

Output Resistances
Simple CM Cascode CM Modified Cascode Improved WilsonRegulated CM

Current Copying Precision

Simple CM Improved Wilson CM Modified Cascode CM Regulated CM Cascode CM

Voltage Headroom
Higher  Lesser

Cascode CM Modified Cascode CM  Improved Wilson Regulated CM  Simple CM

SIMULATIONS RESULTS:
Simple current mirror

 Schematic as shown in fig 1

Fig:1
  Ids v/s Vdc as shown in fig:2

Fig:2

Cascode Current mirror

Schematic as shown in figure:3
 Fig:3

 Ids v/s Vdc as shown in figure:4

Fig:4
Improved Wilson Current mirror
 Schematic as shown in fig:5

Fig:5
  Ids v/s Vdc as shown in fig:6

Fig:6

ModifiedCascode current mirror

 Schematic as shown in figure:7
 Fig:7

 Ids v/s Vdc as shown in figure:8

Regulated Current mirror
 Schematic AS shown in figure:9

Fig:9
 Ids v/s Vdc as shown in figure:10

Fig:10