Lab 3: NIOS-II and SDRAM

LAB 3: NIOS-II and SDRAM

I. OBJECTIVE
The objective of this lab is to:
 Understand SDRAM and memory management, as well as use SDRAM for
supporting in creating a custom project.
 The board features 64MB of SDRAM with a single 64MB (32Mx16) SDRAM chip.
The chip consists of 16-bit data line, control line, and address line connected to the
FPGA. This chip uses the 3.3V LVCMOS signaling standard. Connections between
the FPGA and SDRAM are shown, and the pin assignment is listed.

Figure 1: Connection Diagram of SRAM 16bit data.

 First, we use QSYS tool to create a simple project which using SDRAM to store
data and instruction. In Figure 2, a diagram of a simple project using SDRAM is
introduced. For further application, we need to add PIO IP (which is introduced in
previous lab) to control leds and buttons. A diagram of this project is shown in
Figure 3.
 Second, we use Eclipse Software to program some mini projects: read and write
data from SDRAM, or control LEDS based on data in SDRAM, ….

Reference:
Chapter 3 - Using the DE10-Standard Board (DE10-Standard User Manual.pdf)
Chapter 4 - DE10-Standard System Builder (DE10-Standard User Manual.pdf)

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Ho Chi Minh City University of Technology, Vietnam
 Lab 3: NIOS-II and SDRAM

Figure 2: Diagram of a simple project using NIOS II connect SDRAM.

Figure 3: Diagram of a project using SDRAM and PIO IP.

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Ho Chi Minh City University of Technology, Vietnam
 Lab 3: NIOS-II and SDRAM

II. SDRAM INTERFACE

- The SDRAM chip on the DE0-Standard board has the capacity of 64 Mbytes. It is organized
as 213 columns x 210 rows x 16 bits x 4 banks. For this information, we need to config IP
Controller SDRAM as Figure 3.

Figure 3: Config SDRAM Controller IP.

- The signals needed to communicate with this chip are shown in Figure 4. All of the signals,
except the clock, can be provided by the SDRAM Controller that can be generated by using
the Qsys tool. Note that some signals are active low, which is denoted by the suffix N.

Figure 4: The SDRAM signals.

- The SDRAM chip requires careful timing control. The clock skew depends on physical
characteristics of the DE0-Standard. For proper operation of the SDRAM chip, it is
necessary that its clock signal, DRAM_CLK, leads the NIOS-II system clock, CLOCK_50,
by 3 nanoseconds. This can be accomplished by using a phase-locked loop (PLL) circuit

Electronics Department
Ho Chi Minh City University of Technology, Vietnam
 Lab 3: NIOS-II and SDRAM

which can be manually created using the IP System and SDRAM Clocks for DE-Series
Boards – which is shown in Figure 5.

Figure 5: IP System and SDRAM Clocks for DE-Series Boards.

Electronics Department
Ho Chi Minh City University of Technology, Vietnam
 Lab 3: NIOS-II and SDRAM

III. PROCEDURE
I. Design flow

Figure 6: Design flow of building a project from the beginning to the end

- The students must read carefully “Chapter 4 - DE10-Standard System Builder

(DE10-Standard User Manual.pdf)” to understand about DE10-Standard System
Builder tool and the multiple parts of this tool.
- The design flow of building a Quartus II project for DE10-Standard under the DE10-
Standard System Builder is illustrated in Figure 6.

Electronics Department
Ho Chi Minh City University of Technology, Vietnam
 Lab 3: NIOS-II and SDRAM

II. CREATING PROJECT

Step 1: Open System Builder and choose peripheral as previous lab (only choose
what we need) and do not choose HPS.

Step 2: Open project using Quartus 18.1, and choose icon to open Platform
Designer. At tab IP Catalog, search IP and add to our system.

Electronics Department
Ho Chi Minh City University of Technology, Vietnam
 Lab 3: NIOS-II and SDRAM

Step 3: Search, config and add NIOS II, JTAG UART, SystemID and PIO which are
the same as previous lab.

Electronics Department
Ho Chi Minh City University of Technology, Vietnam
 Lab 3: NIOS-II and SDRAM

Step 4: Search, config and add SDRAM controller.

Electronics Department
Ho Chi Minh City University of Technology, Vietnam
 Lab 3: NIOS-II and SDRAM

Step 5: As discuss in last part, we need to add PLL to create two clocks which deviate
from each other by 3 nanoseconds. Add System and SDRAM Clocks for DE-series
Board.

After this step, we have six IP in qsys windows (5 IPs in picture and 1 IP SystemID-is
not shown picture).

Step 5: In this step, we assign pins’ name for out and in pins which is connected to
peripherals’ pin. In next picture, we see that we need to assign 5 pins:
- Clock Input, Clock Reset, Clock Output: in System and SDRAM Clocks IP.
- Conduit in SDRAM Controller IP.
- Conduit in PIO Controller IP.

Electronics Department
Ho Chi Minh City University of Technology, Vietnam
 Lab 3: NIOS-II and SDRAM

Besides, we might to rename PIO IP and SDRAM Controller IP to SDRAM and LEDR.
This name helps us check registers and code easier when coding in Eclipse.

Step 6: Connect IP as next picture.

Electronics Department
Ho Chi Minh City University of Technology, Vietnam
 Lab 3: NIOS-II and SDRAM

After that, choose Assign Base Address as picture below.

Step 7: Open NIOS-II IP again and change Reset Vector Memory and Exception
Vector Memory to SDRAM.s1. This leads NIOS-II read data and instruction from
SDRAM.

Electronics Department
Ho Chi Minh City University of Technology, Vietnam
 Lab 3: NIOS-II and SDRAM

Step 8: Change System ID in SytemID IP to address of it. This leads eclipse tool can
confirm ID of system when running.

Step 9: Save qsys system and make sure no errors, then generate HDL.

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Ho Chi Minh City University of Technology, Vietnam
 Lab 3: NIOS-II and SDRAM

From here, do as previous lab (Lab 2 – Step 7 to Step 13).

III. Homework
In this program, we create an array A containing ten elements of type integer 16 (each element
has random value). After that, create another array B containing arranged elements of array
A. Print to console the position of each elements of arrays A and B.

Electronics Department
Ho Chi Minh City University of Technology, Vietnam