EEE4028 VLSI Design L T P J C

3 0 2 0 4

Pre-requisite EEE3002 Syllabus version

Anti-requisite v. 2.0

Course Objectives:

1. To provide an understanding of the digital VLSI concepts, circuit design, principles.

2. To provide introduction to architecture and design concepts underlying modern complex
VLSI.
3. To provide students with the background needed to design, develop, and test digital circuits
using VHSIC Hardware Description Language (VHDL) and Verilog HDL.
4. To provide the students to design the digital circuits using transistors for complex systems.

Expected Course Outcome:

On the completion of this course the student will be able to:

1. Analyze and identify the methodologies for fabricating the ICs.

2. Synthesize and design arithmetic circuits using HDL.
3. Design logic circuits using CMOS and its equivalent layout for fabrication.
4. Reduce the delay and power dissipation in logic circuits by analyzing the characteristics of
CMOS.
5. Identify the exact transistor configurations for better performance in logic circuits.
6. Design memory devices using transistors.
7. Identify and design arithmetic circuits for various applications.
8. Design and Conduct experiments, as well as analyze and interpret data

Student Learning Outcomes (SLO): 2,5,9

Module:1 Overview of VLSI Design Methodology 4 Hours

The VLSI design process, Architectural design, logical design, Physical design, layout styles, Full
custom, Semi custom approaches.

Module:2 Introduction to Verilog HDL 6 Hours

Introduction Verilog HDL, Gate level, data flow, behavioralmodeling, Data types and Operators,
Blocking and non-blocking assignment statements. Test benches.
Module:3 Introduction to MOS Devices 6 Hours

Introduction to MOS Transistor Theory: nMOS, pMOS Enhancement Transistor, MOSFET as a

Switch, Threshold voltage, MOS Device Design Equations, Body effect, Second order effects. MOS
Transistor Circuit Model. Stick Diagram, Layout Design Rules.

Module:4 Circuit Characterization And Performance 6 Hours

Estimation

DC Characteristics of CMOS Inverter, Switching Characteristics of CMOS Inverter, Transistor

Sizing Analytical Delay model- Rise Time, Fall Time. Gate Delays, RC Delay Models, Logical
Effort. Power Dissipation: Static- Dynamic-Short Circuit Power Dissipation

Module:5 Combinational logic Circuits 6 Hours

Introduction, Static CMOS Design- Complex Logic Gates, Ratioed Logic, Pass-Transistor Logic,
Transmission gate Logic, Dynamic CMOS Logic Design: Dynamic Logic Design Considerations.
Speed and Power Dissipation of Dynamic logic, Signal integrity issues, Cascading Dynamic gates.

Module:6 Sequential Logic Circuits 6 Hours

Static and Dynamic Latches and Registers, Timing issues, pipelining

Module:7 Designing arithmetic circuits 9 Hours

Adders-Ripple carry, Carry-Look ahead, Multiplier using Array based-Ripple carry adder, Carry-
Save adder, Multiplier using Tree based-Wallace Tree, Dadda Tree, Booth Multiplier, Squarer.

Modeling of arithmetic circuits using HDL:

Pipelined Multiplier and Accumulator, FIR filter design. Verilog Coding for arithmetic circuits.

Module:8 Contemporary issues: 2 Hours

Total Lecture hours: 45 Hours

List of Challenging Experiments (Indicative) SLO:2,5,9

1. Four bit adder using different approaches for delay and Area reduction 3 Hours

2. Four Bit Wallace tree multiplier 3 Hours

3. Four bit dada tree multiplier 3 Hours

4. Four bit squarer design 3 Hours

5. Multiplier and Accumulator design 3 Hours

6. FIR filter design 3 Hours

7. CMOS switch level implementation of Complex Boolean functions 3 Hours

8. CMOS switch level implementation of adder and subtractor 3 Hours

9. Implementation of Boolean function using various transistors 3 Hours

10. Positive and negative edge triggered register design 3 Hours

Total Laboratory Hours 30 hours

Text Book(s)

1. Jan Rabaey, AnanthaChandrakasan, B.Nikolic, “Digital Integrated circuits: A design

perspective”. Second Edition, Prentice Hall of India, 2013.

2. Neil H.E.Weste, David Money Harris, “CMOS VLSI DESIGN: a circuits and systems
perspective”, Fourth edition, Pearson 2015.

Reference Books

1. Samir Palnitkar, “Verilog HDL”, Prentice Hall, 2010.

2. Sung-Ma Kong, Yusuf Leblebici and Chulwoo Kim, "CMOS digital integrated circuits:
analysis and design", 4th edition, McGraw-Hill Education, 2015.

Mode of Evaluation: CAT I & II – 30%, DA I & II – 20%, Quiz – 10%, FAT – 40%

Mode of assessment:

Recommended by Board of Studies 30/11/2015

Approved by Academic Council 39th AC Date 17/12/2015