ALU CODE-

-- Company:

-- Engineer:

--

-- Create Date: 03/11/2019 07:46:33 PM

-- Design Name:

-- Module Name: alu - Behavioral

-- Project Name:

-- Target Devices:

-- Tool Versions:

-- Description:

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-- Dependencies:

--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity ALU is

Port ( D1 : in STD_LOGIC_VECTOR (31 downto 0);

D2 : in STD_LOGIC_VECTOR (31 downto 0);

S_E : in STD_LOGIC_VECTOR (31 downto 0);

ALUS : in STD_LOGIC;

Zero : out STD_LOGIC;

ALU_R : out STD_LOGIC_VECTOR (31 downto 0);

ALUC : in std_logic_vector(2 downto 0));

end ALU;

architecture Behavioral of ALU is

SIGNAL A_in, B_in : STD_LOGIC_VECTOR (31 DOWNTO 0);

SIGNAL ALU_out : STD_LOGIC_VECTOR (31 DOWNTO 0);

begin

A_in <= D1;

B_in <= D2 when ALUS = '0' else

 S_E;

Zero<= '1' when (ALU_out = X"00000000") else '0';

process(ALUC, A_in, B_in)

begin

case ALUC is

when "000" => ALU_out <= A_in AND B_in;

when "001" => ALU_out<= A_in OR B_in;

when "010" => ALU_out<= A_in + B_in;

when "110" => ALU_out <= A_in - B_in;

when "100" => ALU_out<= A_in Nor B_in;

when others => ALU_out<= X"00000000";

end case;

end process;
TEST BENCH-

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-- Company:

-- Engineer:

--

-- Create Date: 03/11/2019 07:48:25 PM

-- Design Name:

-- Module Name: alu_tb - Behavioral

-- Project Name:

-- Target Devices:

-- Tool Versions:

-- Description:

--

-- Dependencies:

--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

----------------------------------------------------------------------------------

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--USE ieee.numeric_std.ALL;

ENTITY ALU_TB IS

END ALU_TB;

ARCHITECTURE behavior OF ALU_TB IS

COMPONENT ALU IS

PORT(

D1 : IN std_logic_vector(31 downto 0);

D2 : IN std_logic_vector(31 downto 0);

S_E : IN std_logic_vector(31 downto 0);

ALUS : IN std_logic;

Zero : OUT std_logic;

ALU_R : OUT std_logic_vector(31 downto 0);

ALUC : IN std_logic_vector(2 downto 0));

END COMPONENT;

--Inputs

signal D1 : std_logic_vector(31 downto 0) := (others => '0');

signal D2 : std_logic_vector(31 downto 0) := (others => '0');

signal S_E : std_logic_vector(31 downto 0) := (others => '0');

signal ALUS : std_logic := '0';

signal ALUC : std_logic_vector(2 downto 0) := (others => '0');

--Outputs
 signal Zero : std_logic;

signal ALU_R : std_logic_vector(31 downto 0);

-- No clocks detected in port list. Replace <clock> below with

-- appropriate port name

BEGIN

-- Instantiate the Unit Under Test (UUT)

L1: ALU PORT MAP (

D1 => D1,

D2 => D2,

S_E => S_E,

ALUS => ALUS,

Zero => Zero,

ALU_R=> ALU_R,

ALUC => ALUC );

-- Stimulus process

stim_proc: process

begin

-- hold reset state for 100 ns.

D1 <= X"00000001";

D2 <= X"00000002";

S_E <= X"00000003";

 ALUS <= '0'; --Select D2 as input b

ALUC <= "010"; --Addition

wait for 100 ns;

ALUS <= '1'; --Select S_E as input b

wait for 10 ns;

ALUSr<= '0';

D1 <= X"00000003";

D2 <= X"00000007";

ALUC <= "000"; -- Boolean AND operation

wait for 10 ns;

D1 <= X"00000003";

D2 <= X"0000000A";

ALUC <= "001"; -- Boolean OR operation

wait for 10 ns;

D1 <= X"0000000A";

D2 <= X"00000003";

ALUC <= "110"; -- Subtraction

wait for 10 ns;

D1 <= X"0000000A";

D2 <= X"00000003";

ALUC <= "100"; -- nor operation

wait for 10 ns;

 D1 <= X"0000000A";

D2 <= X"0000000A";

ALUC <= "110"; -- Subtraction same input

wait for 10 ns;

wait;

end process;

end behavior;