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  • NM - B681 M/B Schematics Document: Amd R17M-P1-50/R18M-M2-60 Amd Fp5 Raven Ridge Soc With Ddriv

    Uploaded by

    Mike Otte
    521 views53 pages
    1. The document contains schematics for an AMD R17M-P1-50 and R18M-M2-60 SoC with DDR4 memory and various I/O including HDMI, USB, SATA, and PCIe ports. 2. Key components include an AMD FP5 APU, DDR4 memory on two channels up to 8GB total, HDMI and eDP ports, USB 3.0 and 2.0 ports, SATA HDD and ODD ports, and an Intel camera. 3. The schematics provide details on the pinouts and specifications for the various components and connections in the system.

    Original Description:

    Lenovo_Ideapad_330-15AR_LCFC_330ARR_NM-B681_Rev_1.0_2

    Original Title

    Lenovo_Ideapad_330-15AR_LCFC_330ARR_NM-B681_Rev_1.0_2

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    © © All Rights Reserved

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    1. The document contains schematics for an AMD R17M-P1-50 and R18M-M2-60 SoC with DDR4 memory and various I/O including HDMI, USB, SATA, and PCIe ports. 2. Key components include an AMD FP5 APU, DDR4 memory on two channels up to 8GB total, HDMI and eDP ports, USB 3.0 and 2.0 ports, SATA HDD and ODD ports, and an Intel camera. 3. The schematics provide details on the pinouts and specifications for the various components and connections in the system.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pdf or txt
    521 views53 pages

    NM - B681 M/B Schematics Document: Amd R17M-P1-50/R18M-M2-60 Amd Fp5 Raven Ridge Soc With Ddriv

    Uploaded by

    Mike Otte
    1. The document contains schematics for an AMD R17M-P1-50 and R18M-M2-60 SoC with DDR4 memory and various I/O including HDMI, USB, SATA, and PCIe ports. 2. Key components include an AMD FP5 APU, DDR4 memory on two channels up to 8GB total, HDMI and eDP ports, USB 3.0 and 2.0 ports, SATA HDD and ODD ports, and an Intel camera. 3. The schematics provide details on the pinouts and specifications for the various components and connections in the system.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pdf or txt
    of 53

    A B C D E

    LCFC
    1 1

    NM_B681 M/B Schematics Document


    2
    AMD FP5 Raven Ridge SoC with DDRIV 2

    Vinafix.com
    AMD R17M-P1-50/R18M-M2-60

    2017-09-6
    REV:1.0
    3 3

    4 4

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/15 Deciphered Date 2013/08/15 Cover Page
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 330ARR
    Date: Friday, March 23, 2018 Sheet 1 of 52
    A B C D E
    5 4 3 2 1

    D D
    PRT06 NEC_UMA@ PRT06 NEC_R17@ PRT06 NEC_R18@

    0_0402_5% 540_0402NEW_30% 0_0402_5%


    SD02800008J SL20000220J SD02800008J

    PRT07 NEC_UMA@ PRT07 NEC_R17@ PRT07 NEC_R18@

    C C
    0_0402_5% 540_0402NEW_30% 540_0402NEW_30%
    SD02800008J SL20000220J SL20000220J

    Vinafix.com
    PRT08 NEC_UMA@ PRT08 NEC_R17@ PRT08 NEC_R18@

    0_0402_5% 540_0402NEW_30% 540_0402NEW_30%


    SD02800008J SL20000220J SL20000220J

    B B
    PR609 R18@

    R18 LL=1mohm,PR609=18.7K
    R17 LL=0.6mohm,PR609=31.6K
    18.7K_0402_1%
    SD03418728J

    A A

    Title
    <Title>

    Size Document Number Rev


    A <Doc> 1.0

    Date: Friday, March 23, 2018 Sheet 1 of 1


    5 4 3 2 1
    A B C D E

    Memory BUS (DDR4)


    AMD: R17M-P1-50 Channel A DDR4-SO-DIMM X1
    R18M-M2-60 PCI-Express
    Package: S4a 8x Gen3 1.2V DDR4 2400MT/s
    PEG 0~7 UP TO 8G x 1
    1
    VRAM 256*16 1

    GDDR5*2 2G Memory BUS (DDR4)


    Channel B DDR4 DRAM DOWN
    1.2V DDR4 2400MT/s 4pcs x16
    HDMI x4 Lane Port1
    HDMI Conn.
    USB Left
    USB 3.0 1x
    eDP Conn
    eDP x2 Lane port0 USB 2.0 1x USB 2.0 Port4
    Int. Camera USB 3.0 Port4
    USB 2.0 Port1

    Int. DMIC Conn.


    AMD FP5 APU USB Left
    USB 3.0 1x
    USB 2.0 1x USB 2.0 Port2
    2 Raven Ridge TDP 15W USB 3.0 Port2 2

    SATA HDD SATA Gen3

    Vinafix.com
    SATA Port0
    USB 3.0 1x USB Repeater USB 3.0 1x CC logic&Mux USB 3.0 2x
    Parade PS8713
    Realtek RTS5449
    SATA ODD SATA Gen1 USB 3.0 Port3 Type C Conn
    USB 2.0 1x USB 2.0 Port3
    SATA Port1
    BGA-1140P
    NGFF Card 35mm*25mm LAN Realtek
    WLAN&BT PCIe 1x
    PCIe 1x
    Key E PCIe Port1 RTL8111GUL RJ45 Conn.
    USB2.0 1x PCIe Port2
    USB 2.0 Port

    fingerprint USB 2.0 1x


    USB 2.0 Port USB 2.0 1x USB HUB USB2.0(480M) 1x
    reserve GL850G
    USB 2.0 1x
    3
    Touch Screen USB 2.0 Port5 SPI BUS SPI ROM 3
    USB2.0 1x
    USB 2.0 Port 8MB
    HD Audio

    USB 2.0 Port0


    SPK Conn.

    Codec&Card reader LPC TPM


    Realtek_RTS5199 SD/MMC Conn.
    reserve

    EC
    IT8586E-FX_LQFP128
    HP&Mic Combo Conn.
    Sub-board for 15&17

    ODD BOARD
    4

    Touch Pad Int.KBD Thermal Sensor Thermistor 4

    NCT7718W
    reserve
    Security Classification LC Future Center Secret Data Title
    Issued Date 2013/08/15 Deciphered Date 2013/08/15 Block Diagram
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 330ARR
    Date: Friday, March 23, 2018 Sheet 2 of 52
    A B C D E
    A B C D E

    Voltage Rails ( O --> Means ON , X --> Means OFF )


    SIGNAL
    +5VS STATE SLP_S3# SLP_S5# +VALW +V +VS Clock
    +3VS
    S0 (Full ON) HIGH HIGH ON ON ON ON
    +1.8VS
    power +0.9VS S1 (Power On Suspend) HIGH HIGH ON ON ON LOW
    plane B+
    1 (+20VSB) +5VALW +1.2V +0.6VS 1
    S3 (Suspend to RAM) LOW HIGH ON ON OFF OFF
    +3VL +3VALW +2.5VS
    (+3VALW_APU)
    +5VLP +VDDC_VDD S4 (Suspend to Disk) LOW LOW ON OFF OFF OFF
    +1.8VALW
    +VDDCR_SOC
    +0.9VALW S5 (Soft OFF) LOW LOW ON OFF OFF OFF
    +VDDC
    BOM Structure Table
    +VDDCI
    State BOM Structure BTO Item
    +3VGS
    Port List @ Not stuff
    +1.8VGS
    ME@ Connector
    +1.35VGS HSIO Port Device
    EMC@ EMC Part
    0 WLAN
    EMC_NS@ EMC reserve Part
    1 LAN
    RF@ RF Part
    I2C Control Table 2 N/A
    RF_PXNS@
    S0 O O O O GPP 3 N/A
    RF GPU reserve part
    UMA@ UMA SKU ID part
    SOURCE Device
    4 N/A
    PX@ Discrete GPU SKU part
    S3
    O O O X 5 N/A
    R17M-P1@ R17M-P1-50 SKU part
    2
    6 HDD
    R18M-M2@ R18M-M2-60 SKU part
    2

    TP_I2C0_SCL APU Touch Pad 7 ODD

    Vinafix.com
    S5 S4/AC
    O O X X TPM@ TPM part
    TP_I2C0_SDA +3VALW +3VS 0 KBL@ Keyboard backlight part
    1 HDT@ HDT Debug part
    S5 S4/ Battery only
    O X X X 2 REDRV@ Redriver part
    APU I2C address 3
    GFX GPU USB_HUB@ USB HUB part
    Device Address 4
    S5 S4/AC & Battery
    don't exist X X X X Elan：SA469 D- 22 HA 69x104x1. 0 ? 5
    Synaptics：T M- P3255- 008 69x104x 1. 0 ? 6
    7
    SMBUS Control Table 0 N/A
    1 Type C
    SOURCE GPU BATT IT8586 SODIMM WLAN Thermal APU Charger PMIC
    USB3.0 2 LEFT USB (3.0) lower
    Sensor 3 LEFT USB (3.0) upper
    4 N/A
    3 3
    EC_SMB_CK1 0 Card Reader
    EC_SMB_DA1
    IT8586
    +3VL X V X X X X V X 1 Type C
    USB2.0
    2 LEFT USB (3.0) lower
    EC_SMB_CK2 3 LEFT USB (3.0) upper
    EC_SMB_DA2
    IT8586
    +3VL X X X X V X X V 4 USB HUB(Camera,FP,Touch)
    +3VS
    5 BT
    EC_SMB_CK3
    EC_SMB_DA3
    IT8586
    +3VS V X X X X V X X
    +3VS_VGA

    APU_SCLK0
    APU_SDATA0
    APU
    +3VS X X X V V X X X
    S2G@ SAMSUNG 2G

    EC SM Bus1 address EC SM Bus2 address EC SM Bus3 address VRAM M2G@ MICRON 2G

    Device Device Device


    H2G@ HYNIX 2G
    Address Address Address
    4
    Battery ? PMIC 0X34 GPU 0x41(default)
    HDMI@ HDMI Logo 4

    Charger 0001 0010 b Thermal Sensor 1001_100xb(reserve) APU SB-TSI releate to F3x1E4[SbiAddr] or
    Address Select Pins setting

    APU SM Bus address Security Classification LC Future Center Secret Data Title

    Device Address
    Issued Date 2013/08/15 Deciphered Date 2013/08/15 Notes List
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    DDR4 SO-DIMM ? AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 1.0
    WLAN RSVD
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 330ARR
    Date: Friday, March 23, 2018 Sheet 3 of 52
    A B C D E
    5 4 3 2 1

    UC2B
    PCIE

    PCIE_CRX_GTX_P0 P8 N1 PCIE_CTX_GRX_P0 0.22U_0201_6.3V6-K 1 2 PX@ CC5 PCIE_CTX_C_GRX_P0


    17 PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0 P_GFX_RXP0 P_GFX_TXP0 PCIE_CTX_GRX_N0 0.22U_0201_6.3V6-K 1 PCIE_CTX_C_GRX_N0 PCIE_CTX_C_GRX_P0 17
    P9 N3 2 PX@ CC6
    17 PCIE_CRX_GTX_N0 P_GFX_RXN0 P_GFX_TXN0 PCIE_CTX_C_GRX_N0 17
    D PCIE_CRX_GTX_P1 PCIE_CTX_GRX_P1 0.22U_0201_6.3V6-K 1 PCIE_CTX_C_GRX_P1 D
    N6 M2 2 PX@ CC7
    17 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1 P_GFX_RXP1 P_GFX_TXP1 PCIE_CTX_GRX_N1 0.22U_0201_6.3V6-K 1 PCIE_CTX_C_GRX_N1 PCIE_CTX_C_GRX_P1 17
    N7 M4 2 PX@ CC8
    17 PCIE_CRX_GTX_N1 P_GFX_RXN1 P_GFX_TXN1 PCIE_CTX_C_GRX_N1 17
    PCIE_CRX_GTX_P2 M8 L2 PCIE_CTX_GRX_P2 0.22U_0201_6.3V6-K 1 2 PX@ CC9 PCIE_CTX_C_GRX_P2
    17 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2 P_GFX_RXP2 P_GFX_TXP2 PCIE_CTX_GRX_N2 0.22U_0201_6.3V6-K 1 PCIE_CTX_C_GRX_N2 PCIE_CTX_C_GRX_P2 17
    M9 L4 2 PX@ CC10
    17 PCIE_CRX_GTX_N2 P_GFX_RXN2 P_GFX_TXN2 PCIE_CTX_C_GRX_N2 17
    PCIE_CRX_GTX_P3 L6 L1 PCIE_CTX_GRX_P3 0.22U_0201_6.3V6-K 1 2 PX@ PCIE_CTX_C_GRX_P3
    17 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3 L7 P_GFX_RXP3 P_GFX_TXP3 L3 PCIE_CTX_GRX_N3 0.22U_0201_6.3V6-K 1 2 PX@
    CC11
    PCIE_CTX_C_GRX_N3 PCIE_CTX_C_GRX_P3 17 GPU
    GPU 17 PCIE_CRX_GTX_N3 P_GFX_RXN3 P_GFX_TXN3
    CC12
    PCIE_CTX_C_GRX_N3 17
    PCIE_CRX_GTX_P4 K11 K2 PCIE_CTX_GRX_P4 0.22U_0201_6.3V6-K 1 2 R5R7@ CC18 PCIE_CTX_C_GRX_P4
    17 PCIE_CRX_GTX_P4 PCIE_CRX_GTX_N4 P_GFX_RXP4 P_GFX_TXP4 PCIE_CTX_GRX_N4 0.22U_0201_6.3V6-K 1 PCIE_CTX_C_GRX_N4 PCIE_CTX_C_GRX_P4 17
    J11 K4 2 R5R7@ CC30
    17 PCIE_CRX_GTX_N4 P_GFX_RXN4 P_GFX_TXN4 PCIE_CTX_C_GRX_N4 17
    PCIE_CRX_GTX_P5 H6 J2 PCIE_CTX_GRX_P5 0.22U_0201_6.3V6-K 1 2 R5R7@ CC31 PCIE_CTX_C_GRX_P5
    17 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_N5 P_GFX_RXP5 P_GFX_TXP5 PCIE_CTX_GRX_N5 0.22U_0201_6.3V6-K 1 PCIE_CTX_C_GRX_N5 PCIE_CTX_C_GRX_P5 17
    H7 J4 2 R5R7@ CC33
    17 PCIE_CRX_GTX_N5 P_GFX_RXN5 P_GFX_TXN5 PCIE_CTX_C_GRX_N5 17
    PCIE_CRX_GTX_P6 G6 H1 PCIE_CTX_GRX_P6 0.22U_0201_6.3V6-K 1 2 R5R7@ CC32 PCIE_CTX_C_GRX_P6
    17 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_N6 P_GFX_RXP6 P_GFX_TXP6 PCIE_CTX_GRX_N6 0.22U_0201_6.3V6-K 1 PCIE_CTX_C_GRX_N6 PCIE_CTX_C_GRX_P6 17
    F7 H3 2 R5R7@ CC34
    17 PCIE_CRX_GTX_N6 P_GFX_RXN6 P_GFX_TXN6 PCIE_CTX_C_GRX_N6 17
    PCIE_CRX_GTX_P7 G8 H2 PCIE_CTX_GRX_P7 0.22U_0201_6.3V6-K 1 2 R5R7@ CC35 PCIE_CTX_C_GRX_P7
    17 PCIE_CRX_GTX_P7 PCIE_CRX_GTX_N7 P_GFX_RXP7 P_GFX_TXP7 PCIE_CTX_GRX_N7 0.22U_0201_6.3V6-K 1 PCIE_CTX_C_GRX_N7 PCIE_CTX_C_GRX_P7 17
    C F8 H4 2 R5R7@ CC36 C

    Vinafix.com
    17 PCIE_CRX_GTX_N7 P_GFX_RXN7 P_GFX_TXN7 PCIE_CTX_C_GRX_N7 17

    PCIE_PRX_DTX_P1 N10 N2 PCIE_PTX_DRX_P1 0.1U_0201_6.3V6-K 1 2 PCIE_PTX_C_DRX_P1


    WLAN 35 PCIE_PRX_DTX_P1 PCIE_PRX_DTX_N1 N9 P_GPP_RXP0 P_GPP_TXP0 P3 PCIE_PTX_DRX_N1 0.1U_0201_6.3V6-K 1 2
    CC1
    CC2 PCIE_PTX_C_DRX_N1 PCIE_PTX_C_DRX_P1 35 WLAN
    35 PCIE_PRX_DTX_N1 P_GPP_RXN0 P_GPP_TXN0 PCIE_PTX_C_DRX_N1 35
    PCIE_PRX_DTX_P2 L10 P4 PCIE_PTX_DRX_P2 0.1U_0201_6.3V6-K 1 2 PCIE_PTX_C_DRX_P2
    LAN 32 PCIE_PRX_DTX_P2 PCIE_PRX_DTX_N2 L9 P_GPP_RXP1 P_GPP_TXP1 P2 PCIE_PTX_DRX_N2 0.1U_0201_6.3V6-K 1 2
    CC3
    CC4 PCIE_PTX_C_DRX_N2 PCIE_PTX_C_DRX_P2 32 LAN
    32 PCIE_PRX_DTX_N2 P_GPP_RXN1 P_GPP_TXN1 PCIE_PTX_C_DRX_N2 32
    L12 R3
    M11 P_GPP_RXP2 P_GPP_TXP2 R1
    P_GPP_RXN2 P_GPP_TXN2
    P12 T4
    P11 P_GPP_RXP3 P_GPP_TXP3 T2
    P_GPP_RXN3 P_GPP_TXN3

    V6 W2
    V7 P_GPP_RXP4 P_GPP_TXP4 W4
    B P_GPP_RXN4 P_GPP_TXN4 B
    T8 W3
    T9 P_GPP_RXP5 P_GPP_TXP5 V2
    P_GPP_RXN5 P_GPP_TXN5
    SATA_PRX_DTX_P0 R6 V1 SATA_PTX_DRX_P0
    38 SATA_PRX_DTX_P0 SATA_PRX_DTX_N0 P_GPP_RXP6/SATA_RXP0 P_GPP_TXP6/SATA_TXP0 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 38
    R7 V3
    HDD 38 SATA_PRX_DTX_N0 P_GPP_RXN6/SATA_RXN0 P_GPP_TXN6/SATA_TXN0 SATA_PTX_DRX_N0 38 HDD
    SATA_PRX_DTX_P1 R9 U2 SATA_PTX_DRX_P1
    38 SATA_PRX_DTX_P1 SATA_PRX_DTX_N1 P_GPP_RXP7/SATA_RXP1 P_GPP_TXP7/SATA_TXP1 SATA_PTX_DRX_N1 SATA_PTX_DRX_P1 38
    R10 U4
    ODD 38 SATA_PRX_DTX_N1 P_GPP_RXN7/SATA_RXN1 P_GPP_TXN7/SATA_TXN1 SATA_PTX_DRX_N1 38 ODD
    FP5 REV 0.90
    PART 2 OF 13
    @ AMD-RAVEN-FP5_BGA1140

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP5 (PCIE SATA I/F)
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Custom
    330ARR 1.0

    Date: Friday, March 23, 2018 Sheet 4 of 52


    5 4 3 2 1
    5 4 3 2 1

    DDRB_DQS[0..7]
    15 DDRB_DQS[0..7]
    DDRB_DQS#[0..7]
    DDRA_DQS[0..7] 15 DDRB_DQS#[0..7]
    14 DDRA_DQS[0..7]
    DDRA_DQS#[0..7]
    14 DDRA_DQS#[0..7]
    UC2I DQ bit swapping is allowed in a byte lane.
    MEMORY B

    15 DDRB_MA[13..0] DDRB_MA0 AG30


    DDRB_MA1 MB_ADD0/MBB_CS0 DDRB_DQ0 DDRB_DQ[63..0] 15
    AC32 B21
    UC2A DDRB_MA2 AC30 MB_ADD1/RSVD MB_DATA0/MBA_DATA8 D21 DDRB_DQ1
    MEMORY A
    DDRB_MA3 AB29 MB_ADD2/RSVD MB_DATA1/MBA_DATA9 B23 DDRB_DQ2
    DDRB_MA4 AB31 MB_ADD3/RSVD MB_DATA2/MBA_DATA13 D23 DDRB_DQ3
    14 DDRA_MA[13..0] DDRA_MA0 DDRB_MA5 MB_ADD4/RSVD MB_DATA3/MBA_DATA12 DDRB_DQ4
    AF25 AA30 A20
    D
    DDRA_MA1
    DDRA_MA2
    AE23 MA_ADD0/MAB_CS0
    MA_ADD1/RSVD MA_DATA0/MAA_DATA8
    J21 DDRA_DQ0
    DDRA_DQ1
    DDRA_DQ[63..0] 14 DDRB_MA6
    DDRB_MA7
    AA29 MB_ADD5/RSVD
    MB_ADD6/RSVD
    MB_DATA4/MBA_DATA11
    MB_DATA5/MBA_DATA10
    C20 DDRB_DQ5
    DDRB_DQ6
    APU SO-DIMM DRAM D

    AD27 H21 Y30 A22 DA0 DQ2 UD1.0


    DDRA_MA3 AE21 MA_ADD2/RSVD MA_DATA1/MAA_DATA9 F23 DDRA_DQ2 DDRB_MA8 AA31 MB_ADD7/MBA_CA3 MB_DATA6/MBA_DATA15 C22 DDRB_DQ7
    DDRA_MA4 AC24 MA_ADD3/RSVD MA_DATA2/MAA_DATA13 H23 DDRA_DQ3 DDRB_MA9 W29 MB_ADD8/MBA_CA4 MB_DATA7/MBA_DATA14
    DDRA_MA5 MA_ADD4/RSVD MA_DATA3/MAA_DATA12 DDRA_DQ4 DDRB_MA10 MB_ADD9/MBA_CKE1 DDRB_DQ8
    DA1 DQ7 UD1.3
    AC26 G20 AH29 D24
    DDRA_MA6 AD21 MA_ADD5/RSVD MA_DATA4/MAA_DATA11 F20 DDRA_DQ5 DDRB_MA11 Y32 MB_ADD10/MBB_CKE0 MB_DATA8/MBA_DATA0 A25 DDRB_DQ9
    DA2 DQ6 UD1.4
    DDRA_MA7
    DDRA_MA8
    AC27 MA_ADD6/RSVD
    MA_ADD7/MAA_CA3
    MA_DATA5/MAA_DATA10
    MA_DATA6/MAA_DATA15
    J22 DDRA_DQ6
    DDRA_DQ7
    APU SO-DIMM DRAM DDRB_MA12
    DDRB_MA13
    W31 MB_ADD11/MBA_CA5
    MB_ADD12/MBA_CA2
    MB_DATA9/MBA_DATA1
    MB_DATA10/MBA_DATA5
    D27 DDRB_DQ10
    DDRB_DQ11
    AD22 J23 DA32 DQ39 UD3.1 AL30 C27 DA3 DQ0 UD1.5
    DDRA_MA9 AC21 MA_ADD8/MAA_CA4 MA_DATA7/MAA_DATA14 DDRB_MA14_WE# AK30 MB_ADD13_BANK2/RSVD MB_DATA11/MBA_DATA4 C23 DDRB_DQ12
    DDRA_MA10 MA_ADD9/MAA_CKE1 DDRA_DQ8 15 DDRB_MA14_WE# DDRB_MA15_CAS# MB_WE_L_ADD14/MBB_CA2 MB_DATA12/MBA_DATA7 DDRB_DQ13
    AF22 G25 DA33 DQ36 UD3.6 AK32 B24 DA4 DQ1 UD1.2
    DDRA_MA11 MA_ADD10/MAB_CKE0 MA_DATA8/MAA_DATA0 DDRA_DQ9 15 DDRB_MA15_CAS# DDRB_MA16_RAS# MB_CAS_L_ADD15/MBB_CA4 MB_DATA13/MBA_DATA6 DDRB_DQ14
    AA24 F26 AJ30 C26
    DDRA_MA12 MA_ADD11/MAA_CA5 MA_DATA9/MAA_DATA1 DDRA_DQ10 15 DDRB_MA16_RAS# MB_RAS_L_ADD16/MBB_CA3 MB_DATA14/MBA_DATA2 DDRB_DQ15
    AC23 L24 DA34 DQ35 UD3.2 B27 DA5 DQ5 UD1.7
    DDRA_MA13 AJ25 MA_ADD12/MAA_CA2 MA_DATA10/MAA_DATA5 L26 DDRA_DQ11 MB_DATA15/MBA_DATA3
    DDRA_MA14_WE# AG27 MA_ADD13_BANK2/RSVD MA_DATA11/MAA_DATA4 L23 DDRA_DQ12 DDRB_BA0 AH31 C30 DDRB_DQ16
    14 DDRA_MA14_WE# DDRA_MA15_CAS# MA_WE_L_ADD14/MAB_CA2 MA_DATA12/MAA_DATA7 DDRA_DQ13
    DA35 DQ34 UD3.7 15 DDRB_BA0 DDRB_BA1 MB_BANK0/MBB_CS1 MB_DATA16/MBA_DATA19 DDRB_DQ17
    DA6 DQ4 UD1.1
    AG23 F25 AG32 E29
    14 DDRA_MA15_CAS# DDRA_MA16_RAS# MA_CAS_L_ADD15/MAB_CA4 MA_DATA13/MAA_DATA6 DDRA_DQ14 15 DDRB_BA1 MB_BANK1/MBB_CA0 MB_DATA17/MBA_DATA18 DDRB_DQ18
    AG26 K25 DA36 DQ37 UD3.5 H29 DA7 DQ3 UD1.6
    14 DDRA_MA16_RAS# MA_RAS_L_ADD16/MAB_CA3 MA_DATA14/MAA_DATA2 DDRA_DQ15 DDRB_BG0 MB_DATA18/MBA_DATA22 DDRB_DQ19
    K27 V31 H31
    MA_DATA15/MAA_DATA3 15 DDRB_BG0 DDRB_BG1 MB_BG0/MBA_CS1 MB_DATA19/MBA_DATA23 DDRB_DQ20
    DA37 DQ32 UD3.3 TC213 @ 1 V29 A28 DA8 DQ12 UD1.11
    DDRA_BA0 AF21 M25 DDRA_DQ16 MB_BG1/MBA_CKE0 MB_DATA20/MBA_DATA20 D28 DDRB_DQ21
    14 DDRA_BA0 DDRA_BA1 MA_BANK0/MAB_CS1 MA_DATA16/MAA_DATA17 DDRA_DQ17 DDRB_ACT# MB_DATA21/MBA_DATA21 DDRB_DQ22
    AF27 M27 DA38 DQ38 UD3.4 V30 F31 DA9 DQ13 UD1.9
    14 DDRA_BA1 MA_BANK1/MAB_CA0 MA_DATA17/MAA_DATA16 DDRA_DQ18 15 DDRB_ACT# MB_ACT_L/MBA_CS0 MB_DATA22/MBA_DATA17 DDRB_DQ23
    P27 G30
    DDRA_BG0 MA_DATA18/MAA_DATA23 DDRA_DQ19 15 DDRB_DM[7..0] DDRB_DM0 MB_DATA23/MBA_DATA16
    AA21 R24 DA39 DQ33 UD3.0 C21 DA10 DQ11 UD1.12
    14 DDRA_BG0 DDRA_BG1 MA_BG0/MAA_CS1 MA_DATA19/MAA_DATA20 DDRA_DQ20 DDRB_DM1 MB_DM0/MBA_DM1 DDRB_DQ24
    AA27 L27 C25 J29
    14 DDRA_BG1 MA_BG1/MAA_CKE0 MA_DATA20/MAA_DATA19 DDRA_DQ21 DDRB_DM2 MB_DM1/MBA_DM0 MB_DATA24/MBA_DATA30 DDRB_DQ25
    M24 DA40 DQ45 UD3.15 E32 J31 DA11 DQ10 UD1.14
    DDRA_ACT# AA22 MA_DATA21/MAA_DATA18 P24 DDRA_DQ22 DDRB_DM3 K30 MB_DM2/MBA_DM2 MB_DATA25/MBA_DATA31 L29 DDRB_DQ26
    14 DDRA_ACT# MA_ACT_L/MAA_CS0 MA_DATA22/MAA_DATA21 DDRA_DQ23 DDRB_DM4 MB_DM3/MBA_DM3 MB_DATA26/MBA_DATA26 DDRB_DQ27
    P25 DA41 DQ44 UD3.9 AP30 L31 DA12 DQ9 UD1.13
    14 DDRA_DM[7..0] DDRA_DM0 MA_DATA23/MAA_DATA22 DDRB_DM5 MB_DM4/MBB_DM2 MB_DATA27/MBA_DATA27 DDRB_DQ28
    F21 AW31 H30
    DDRA_DM1 G27 MA_DM0/MAA_DM1 M22 DDRA_DQ24 DDRB_DM6 BB26 MB_DM5/MBB_DM3 MB_DATA28/MBA_DATA28 H32 DDRB_DQ29
    DDRA_DM2 MA_DM1/MAA_DM0 MA_DATA24/MAA_DATA30 DDRA_DQ25
    DA42 DQ47 UD3.14 DDRB_DM7 MB_DM6/MBB_DM1 MB_DATA29/MBA_DATA29 DDRB_DQ30
    DA13 DQ8 UD1.15
    N24 N21 BD22 L30
    DDRA_DM3 N23 MA_DM2/MAA_DM2 MA_DATA25/MAA_DATA31 T22 DDRA_DQ26 N32 MB_DM7/MBB_DM0 MB_DATA30/MBA_DATA25 L32 DDRB_DQ31
    DDRA_DM4 MA_DM3/MAA_DM3 MA_DATA26/MAA_DATA26 DDRA_DQ27
    DA43 DQ46 UD3.8 RSVD_21 MB_DATA31/MBA_DATA24 DA14 DQ15 UD1.8
    AL24 V21
    DDRA_DM5 AN27 MA_DM4/MAB_DM2 MA_DATA27/MAA_DATA27 L21 DDRA_DQ28 DDRB_DQS0 D22 AP29 DDRB_DQ32
    DDRA_DM6 MA_DM5/MAB_DM3 MA_DATA28/MAA_DATA28 DDRA_DQ29
    DA44 DQ40 UD3.13 DDRB_DQS#0 MB_DQS_H0/MBA_DQS_H1 MB_DATA32/MBB_DATA16 DDRB_DQ33
    DA15 DQ14 UD1.10
    AW25 M20 B22 AP32
    DDRA_DM7 AT21 MA_DM6/MAB_DM1 MA_DATA29/MAA_DATA29 R23 DDRA_DQ30 DDRB_DQS1 D25 MB_DQS_L0/MBA_DQS_L1 MB_DATA33/MBB_DATA17 AT29 DDRB_DQ34
    C MA_DM7/MAB_DM0 MA_DATA30/MAA_DATA24 DDRA_DQ31
    DA45 DQ41 UD3.11 DDRB_DQS#1 MB_DQS_H1/MBA_DQS_H0 MB_DATA34/MBB_DATA21 DDRB_DQ35
    DA16 DQ20 UD2.7 C
    T27 T21 B25 AU32
    RSVD_36 MA_DATA31/MAA_DATA25 DDRB_DQS2 F29 MB_DQS_L1/MBA_DQS_L0 MB_DATA35/MBB_DATA20 AN30 DDRB_DQ36
    DA46 DQ43 UD3.12 DA17 DQ16 UD2.3

    Vinafix.com
    DDRA_DQS0 F22 AL27 DDRA_DQ32 DDRB_DQS#2 F30 MB_DQS_H2/MBA_DQS_H2 MB_DATA36/MBB_DATA19 AP31 DDRB_DQ37
    DDRA_DQS#0 G22 MA_DQS_H0/MAA_DQS_H1 MA_DATA32/MAB_DATA16 AL25 DDRA_DQ33 DDRB_DQS3 K31 MB_DQS_L2/MBA_DQS_L2 MB_DATA37/MBB_DATA18 AR30 DDRB_DQ38
    DDRA_DQS1 MA_DQS_L0/MAA_DQS_L1 MA_DATA33/MAB_DATA17 DDRA_DQ34
    DA47 DQ42 UD3.10 DDRB_DQS#3 MB_DQS_H3/MBA_DQS_H3 MB_DATA38/MBB_DATA23 DDRB_DQ39
    DA18 DQ19 UD2.4
    H27 AP26 K29 AT31
    DDRA_DQS#1 H26 MA_DQS_H1/MAA_DQS_H0 MA_DATA34/MAB_DATA22 AR27 DDRA_DQ35 DDRB_DQS4 AR29 MB_DQS_L3/MBA_DQS_L3 MB_DATA39/MBB_DATA22
    DDRA_DQS2 MA_DQS_L1/MAA_DQS_L0 MA_DATA35/MAB_DATA20 DDRA_DQ36
    DA48 DQ55 UD4.0 DDRB_DQS#4 MB_DQS_H4/MBB_DQS_H2 DDRB_DQ40
    DA19 DQ18 UD2.1
    N27 AK26 AR31 AU29
    DDRA_DQS#2 N26 MA_DQS_H2/MAA_DQS_H2 MA_DATA36/MAB_DATA19 AK24 DDRA_DQ37 DDRB_DQS5 AW30 MB_DQS_L4/MBB_DQS_L2 MB_DATA40/MBB_DATA24 AV30 DDRB_DQ41
    DDRA_DQS3 MA_DQS_L2/MAA_DQS_L2 MA_DATA37/MAB_DATA18 DDRA_DQ38
    DA49 DQ49 UD4.3 DDRB_DQS#5 MB_DQS_H5/MBB_DQS_H3 MB_DATA41/MBB_DATA25 DDRB_DQ42
    DA20 DQ17 UD2.0
    R21 AM24 AW29 BB30
    DDRA_DQS#3 P21 MA_DQS_H3/MAA_DQS_H3 MA_DATA38/MAB_DATA23 AP27 DDRA_DQ39 DDRB_DQS6 BC25 MB_DQS_L5/MBB_DQS_L3 MB_DATA42/MBB_DATA29 BA28 DDRB_DQ43
    DDRA_DQS4 MA_DQS_L3/MAA_DQS_L3 MA_DATA39/MAB_DATA21
    DA50 DQ54 UD4.2 DDRB_DQS#6 MB_DQS_H6/MBB_DQS_H1 MB_DATA43/MBB_DATA28 DDRB_DQ44
    DA21 DQ21 UD2.2
    AM26 BA25 AU30
    DDRA_DQS#4 AM27 MA_DQS_H4/MAB_DQS_H2 AM23 DDRA_DQ40 DDRB_DQS7 BC22 MB_DQS_L6/MBB_DQS_L1 MB_DATA44/MBB_DATA31 AU31 DDRB_DQ45
    DDRA_DQS5 MA_DQS_L4/MAB_DQS_L2 MA_DATA40/MAB_DATA30 DDRA_DQ41
    DA51 DQ48 UD4.7 DDRB_DQS#7 MB_DQS_H7/MBB_DQS_H0 MB_DATA45/MBB_DATA30 DDRB_DQ46
    DA22 DQ22 UD2.6
    AN24 AM21 BA22 AY32
    DDRA_DQS#5 AN25 MA_DQS_H5/MAB_DQS_H3 MA_DATA41/MAB_DATA31 AR25 DDRA_DQ42 N31 MB_DQS_L7/MBB_DQS_L0 MB_DATA46/MBB_DATA26 AY29 DDRB_DQ47
    DDRA_DQS6 MA_DQS_L5/MAB_DQS_L3 MA_DATA42/MAB_DATA26 DDRA_DQ43
    DA52 DQ53 UD4.5 RSVD_20 MB_DATA47/MBB_DATA27
    DA23 DQ23 UD2.5
    AU23 AU27 N29
    DDRA_DQS#6 AT23 MA_DQS_H6/MAB_DQS_H1 MA_DATA43/MAB_DATA27 AL22 DDRA_DQ44 RSVD_18 BA27 DDRB_DQ48
    DDRA_DQS7 MA_DQS_L6/MAB_DQS_L1 MA_DATA44/MAB_DATA28 DDRA_DQ45
    DA53 DQ52 UD4.1 DDRB_CLK0 MB_DATA48/MBB_DATA11 DDRB_DQ49
    DA24 DQ24 UD2.9
    AV20 AL21 AC31 BC27
    DDRA_DQS#7 MA_DQS_H7/MAB_DQS_H0 MA_DATA45/MAB_DATA29 DDRA_DQ46 15 DDRB_CLK0 DDRB_CLK0# MB_CLK_H0/MBA_CKT MB_DATA49/MBB_DATA10 DDRB_DQ50
    AW20 AP24 DA54 DQ50 UD4.6 AD30 BA24 DA25 DQ28 UD2.11
    MA_DQS_L7/MAB_DQS_L0 MA_DATA46/MAB_DATA24 DDRA_DQ47 15 DDRB_CLK0# MB_CLK_L0/MBA_CKC MB_DATA50/MBB_DATA14 DDRB_DQ51
    V24 AP23 AD29 BC24
    V23 RSVD_41 MA_DATA47/MAB_DATA25 AD31 MB_CLK_H1/MBB_CKT MB_DATA51/MBB_DATA15 BD28 DDRB_DQ52
    RSVD_40 DDRA_DQ48
    DA55 DQ51 UD4.4 MB_CLK_L1/MBB_CKC MB_DATA52/MBB_DATA12 DDRB_DQ53
    DA26 DQ30 UD2.12
    AW26 AE30 BB27
    DDRA_CLK0 AD25 MA_DATA48/MAB_DATA11 AV25 DDRA_DQ49 AE32 RSVD_89 MB_DATA53/MBB_DATA13 BB25 DDRB_DQ54
    14 DDRA_CLK0 DDRA_CLK0# MA_CLK_H0/MAA_CKT MA_DATA49/MAB_DATA10 DDRA_DQ50
    DA56 DQ61 UD4.14 RSVD_90 MB_DATA54/MBB_DATA9 DDRB_DQ55
    DA27 DQ26 UD2.8
    AD24 AV22 AF29 BD25
    14 DDRA_CLK0# DDRA_CLK1 MA_CLK_L0/MAA_CKC MA_DATA50/MAB_DATA15 DDRA_DQ51 RSVD_91 MB_DATA55/MBB_DATA8
    AE26 AW22 DA57 DQ56 UD4.10 AF31 DA28 DQ25 UD2.13
    14 DDRA_CLK1 DDRA_CLK1# MA_CLK_H1/MAB_CKT MA_DATA51/MAB_DATA14 DDRA_DQ52 RSVD_92 DDRB_DQ56
    AE27 AU26 BC23
    14 DDRA_CLK1# MA_CLK_L1/MAB_CKC MA_DATA52/MAB_DATA12 DDRA_DQ53 DDRB_CS0# MB_DATA56/MBB_DATA6 DDRB_DQ57
    AV27 DA58 DQ63 UD4.11 AJ31 BB22 DA29 DQ29 UD2.15
    MA_DATA53/MAB_DATA13 DDRA_DQ54 15 DDRB_CS0# MB_CS_L0/MBB_CKE1 MB_DATA57/MBB_DATA7 DDRB_DQ58
    AW23 AM31 BC21
    MA_DATA54/MAB_DATA9 AT22 DDRA_DQ55 AJ29 MB_CS_L1/RSVD MB_DATA58/MBB_DATA2 BD20 DDRB_DQ59
    MA_DATA55/MAB_DATA8
    DA59 DQ58 UD4.12 RSVD_95 MB_DATA59/MBB_DATA3 DDRB_DQ60
    DA30 DQ27 UD2.14
    AM29 BB23
    AW21 DDRA_DQ56 RSVD_97 MB_DATA60/MBB_DATA4 BA23 DDRB_DQ61
    DDRA_CS0# MA_DATA56/MAB_DATA5 DDRA_DQ57
    DA60 DQ60 UD4.13 MB_DATA61/MBB_DATA5 DDRB_DQ62
    DA31 DQ31 UD2.10
    AG21 AU21 BB21
    14 DDRA_CS0# DDRA_CS1# MA_CS_L0/MAB_CKE1 MA_DATA57/MAB_DATA6 DDRA_DQ58 MB_DATA62/MBB_DATA1 DDRB_DQ63
    AJ27 AP21 DA61 DQ57 UD4.9 BA21
    14 DDRA_CS1# MA_CS_L1/RSVD MA_DATA58/MAB_DATA2 DDRA_DQ59 DDRB_CKE0 MB_DATA63/MBB_DATA0
    AN20 U29
    MA_DATA59/MAB_DATA3 DDRA_DQ60 15 DDRB_CKE0 MB_CKE0/MBA_CA0
    AR22 DA62 DQ59 UD4.15 T30 M31
    B
    MA_DATA60/MAB_DATA7 AN22 DDRA_DQ61 V32 MB_CKE1/MBA_CA1 RSVD_17 N30 B
    MA_DATA61/MAB_DATA4 AT20 DDRA_DQ62 U31 RSVD_93 RSVD_19 P31
    MA_DATA62/MAB_DATA1 DDRA_DQ63
    DA63 DQ62 UD4.8 RSVD_94 RSVD_26
    AR20 R32
    DDRA_CKE0 Y23 MA_DATA63/MAB_DATA0 DDRB_ODT0 AL31 RSVD_29 M30
    14 DDRA_CKE0 DDRA_CKE1 MA_CKE0/MAA_CA0 15 DDRB_ODT0 MB_ODT0/MBB_CA5 RSVD_16
    Y26 T24 AM32 M29
    14 DDRA_CKE1 MA_CKE1/MAA_CA1 RSVD_34 MB_ODT1/RSVD RSVD_15
    T25 AL29 P30
    RSVD_35 W25 AM30 RSVD_96 RSVD_25 P29
    RSVD_51 W27 RSVD_98 RSVD_24
    DDRA_ODT0 AG24 RSVD_52 R26 DDRB_ALERT# W30
    14 DDRA_ODT0 DDRA_ODT1 MA_ODT0/MAB_CA5 RSVD_27 15 DDRB_ALERT# MB_ALERT_L/MB_TEST DDRB_PAR
    AJ22 R27 AG31
    14 DDRA_ODT1 MA_ODT1/RSVD RSVD_28 MEM_MB_EVENT#AG29 MB_PAROUT/MBB_CA1 DDRB_PAR 15
    V27
    RSVD_43 V26 RC240 1 @ 2 0_0402_5% MEM_MB_RST#_R T31 MB_EVENT_L
    RSVD_42 15 MEM_MB_RST# MB_RESET_L
    FP5 REV 0.90
    DDRA_ALERT# AA25 PART 9 OF 13
    14 DDRA_ALERT# MA_ALERT_L/MA_TEST DDRA_PAR
    AF24 @ AMD-RAVEN-FP5_BGA1140
    MEM_MA_EVENT# AE24 MA_PAROUT/MAB_CA1 DDRA_PAR 14
    14 MEM_MA_EVENT# MEM_MA_RST#_R Y24 MA_EVENT_L
    RC283 1 @ 2 0_0402_5%
    14 MEM_MA_RST# MA_RESET_L
    FP5 REV 0.90 +1.2V
    PART 1 OF 13

    Memory down
    @ AMD-RAVEN-FP5_BGA1140

    RC9 1 DRAM@ 2 1K_0402_5% MEM_MB_EVENT#

    +1.2V
    SO-DIMM
    RC284 1 2 1K_0402_5% MEM_MA_EVENT#

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP5 (MEM)
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Custom
    330ARR 1.0

    Date: Friday, March 23, 2018 Sheet 5 of 52


    5 4 3 2 1
    5 4 3 2 1

    +3VS_APU
    RPC18 +1.8VS +1.8VS
    UC2C APU_DDC_CLK 1 4
    APU_DDC_DATA 2 3
    DISPLAY/SVI2/JTAG/T EST
    APU_EDP_TX0+ DP_ENBKL

    2
    C8 G15
    26 APU_EDP_TX0+ APU_EDP_TX0- A8 DP0_TXP0 DP_BLON F15 DP_ENVDD RC2 RC3101
    +1.8VS 26 APU_EDP_TX0- DP0_TXN0 DP_DIGON L14 DP_EDP_PWM 2.2K_0404_4P2R_5%
    APU_EDP_TX1+ DP_VARY_BL APU_EDP_HPD 39.2_0402_1% 1K_0402_5%
    D8 RC35 1 2 100K_0402_5%
    eDP 26 APU_EDP_TX1+ APU_EDP_TX1- B8 DP0_TXP1 D9 APU_EDP_AUX
    @

    APU_TEST31
    26 APU_EDP_TX1- DP0_TXN1 DP0_AUXP APU_EDP_AUX# APU_EDP_AUX 26 APU_TEST31 DP_STEREOSYNC

    1
    1

    B9
    RC18 B6 DP0_AUXN C10 APU_EDP_HPD APU_EDP_AUX# 26 eDP M_TEST CONNECTION TBD
    DP0_TXP2 DP0_HPD APU_EDP_HPD 26

    2
    300_0402_5% C7
    DP0_TXN2 G11 APU_DDC_CLK RC3131 RC3102
    D
    C6 DP1_AUXP F11 APU_DDC_DATA APU_DDC_CLK 27 D
    APU_RST# DP0_TXP3 DP1_AUXN APU_HDMI_HPD APU_DDC_DATA 27 HDMI 39.2_0402_1% 1K_0402_5%
    2

    D6 G13 @ @
    DP0_TXN3 DP1_HPD APU_HDMI_HPD 27
    APU_HDMI_TX2+

    1
    PLACE CC16 CAPS CLOSE TO APU,CRB reserve 27pf E6 J12
    27 APU_HDMI_TX2+ APU_HDMI_TX2- D5 DP1_TXP0 DP2_AUXP H12
    1 27 APU_HDMI_TX2- DP1_TXN0 DP2_AUXN K13
    CC16 APU_HDMI_TX1+ E1 DP2_HPD
    56P_0201_50V8-J 27 APU_HDMI_TX1+ APU_HDMI_TX1- C1 DP1_TXP1 J10
    2 27 APU_HDMI_TX1- DP1_TXN1 DP3_AUXP H10
    @
    APU_HDMI_TX0+ F3 DP3_AUXN K8
    HDMI 27 APU_HDMI_TX0+ APU_HDMI_TX0- E4 DP1_TXP2 DP3_HPD
    27 APU_HDMI_TX0- DP1_TXN2 K15 DP_STEREOSYNC
    APU_HDMI_CLK+ F4 DP_STEREOSYNC
    +1.8VS 27 APU_HDMI_CLK+ APU_HDMI_CLK- F2 DP1_TXP3 F14 1 @
    27 APU_HDMI_CLK- DP1_TXN3 RSVD_4 F12 1 @
    TC34 To EDP panel +3VS_APU
    TC33
    RSVD_3
    1

    F10 1 @ TC32
    RSVD_2

    1
    PU FOR INTERNAL
    RC19
    300_0402_5% PD FOR CUSTOMER +3VALW_APU RC70
    4.7K_0402_5%
    2

    2
    APU_PWROK

    2
    RC71
    10K_0402_5%
    PCH_EDP_PWM 26
    PLACE CC17 CAPS CLOSE TO APU,CRB reserve 27pf
    1 AP14 TEST4 1 @ TC204 +1.8VS
    TEST4

    1
    AN14 TEST5 1 @ TC205
    TEST5

    3
    CC17 D
    56P_0201_50V8-J F13 1 @ TC206 5 QC8B
    2 TEST6 RPC47 G
    @ DMN5L06DWK-7 2N SOT363-6
    G18 APU_TEST14 4 5
    TEST14 H19 APU_TEST15
    APU_TEST15
    3 6 S
    TEST15 APU_TEST16

    4
    6
    F18 2 7 D
    C TEST16 F19 APU_TEST17
    APU_TEST17
    1 8 DP_EDP_PWM 2 QC8A C
    TEST17 G
    APU_TEST311 @ DMN5L06DWK-7 2N SOT363-6

    Vinafix.com
    +3VS_APU W24 TC24 10K_0804_8P4R_5%
    TEST31/RSVD

    1
    S
    @

    1
    RC11
    RPC8 AR11 1 @ TC23 100K_0402_5%
    1 4 APU_SIC TEST41
    2 3 APU_SID APU_TDI AU2 AJ21 TEST470 1 @ TC22
    APU_TDO TDI TEST470

    2
    AU4 AK21 TEST471 1 @ TC21 RC2051 @ 2 0_0402_5%
    1K_0404_4P2R_5% APU_TCK AU1 TDO TEST471
    APU_TMS AU3 TCK
    APU_TRST# AV3 TMS
    RPC51 APU_DBREQ# AW3 TRST_L +3VS_APU
    1 4 APU_PROCHOT#_R DBREQ_L +0.9VS
    2 3 ALERT#
    APU_RST# AW4 V4 SMU_ZVDDP RC3 1 2 196_0402_1%
    APU_PWROK RESET_L SMU_ZVDD

    1
    1K_0404_4P2R_5% AW2 +3VALW_APU
    52 APU_PWROK PWROK +3VALW_APU RC74
    RC3129 1 @ 2 0_0402_5% APU_SIC H14 AW11 CORETYPE RC3113 2 @ 1 1K_0402_5% 4.7K_0402_5%
    +3VS_APU 18,39 EC_SMB_CK3 2 0_0402_5% APU_SID SIC CORETYPE
    18,39 EC_SMB_DA3 RC3130 1 @ J14 @
    SID

    2
    ALERT# J15
    APU_THERMTRIP# AP16 ALERT_L APU_VDDP_RUN_FB_H

    2
    AN11 1 @ TC35 RC73
    39 APU_THERMTRIP# 1 2 0_0402_5% APU_PROCHOT#_R L19 THERMTRIP_L VDDP_SENSE J19 VDDCR_SOC_VCC_SENSE PCH_ENVDD 26
    RC31 @ 10K_0402_5%
    2 1K_0402_1% APU_THERMTRIP# 39,49 H_PROCHOT# PROCHOT_L VDDCR_SOC_SENSE VDDCR_VCC_SENSE VDDCR_SOC_VCC_SENSE 52
    RC22 1 K18 @
    VDDCR_SENSE VDDCR_VCC_SENSE 52
    2 0_0402_5% APU_SVC_RA

    3
    RC213 1 @ F16 D
    52 APU_SVC 1 2 0_0402_5% APU_SVD_RA H16 SVC0 J18 VDDCR_VSS_SENSE 5
    RC215 @ QC9B
    52 APU_SVD 1 2 0_0402_5% APU_SVT_RA J16 SVD0 VSS_SENSE_A AM11 VSS_SENSEB 1 @ VDDCR_VSS_SENSE 52 G
    RC279 @ FP5 REV 0.90 TC40 DMN5L06DWK-7 2N SOT363-6
    52 APU_SVT SVT0 PART 3 OF 13
    VSS_SENSE_B
    @
    @ @ AMD-RAVEN-FP5_BGA1140 S
    APU_THERMTRIP# APU_SVC APU_SVD APU_SVT VDDCR_SOC_VCC_SENSE

    4
    6
    CC1393 1 2 0.1U_0201_6.3V6-K 1 @ TC52 D
    VDDCR_VCC_SENSE 1 @ TC207 DP_ENVDD 2 QC9A
    @ VDDCR_VSS_SENSE 1 @ TC208 G
    APU_PROCHOT#_R 1 1 1 DMN5L06DWK-7 2N SOT363-6
    B CC1394 1 2 0.1U_0201_6.3V6-K CC1281 CC1283 CC214 @
    B

    1
    1000P_0201_50V7-K 1000P_0201_50V7-K 1000P_0201_50V7-K S

    1
    RC13
    2 2 2 100K_0402_5%
    @ @ @
    @

    2
    RC206 1 @ 2 0_0402_5%
    With HDT+ Header LCD Power IC can change for PCH_ENVDD for cost down

    +1.8VALW +1.8VALW +3VS_APU


    +1.8VALW +1.8VALW
    +1.8VALW JHDT1 @ RPC5
    APU_TCK

    2
    1 2 8 1
    1 2 7 2 RC77
    APU_TMS 1

    1
    3 4 6 3 +3VALW_APU 2.2K_0402_5%
    3 4
    2

    5 4 CC25 RC32 RC36


    RC7 5 6 APU_TDI 0.1U_0201_6.3V6-K 300_0402_5% 300_0402_5% @
    5 6

    1
    2

    2
    1K_0402_5% 1K_0804_8P4R_5% HDT@ HDT@ HDT@
    7 8 APU_TDO RC75
    7 8 PCH_ENBKL 26

    2
    UC6 10K_0402_5%
    APU_TRST# 2 33_0402_5% APU_TRST#_R APU_PWROK_BUF APU_PWROK APU_PWROK_BUF
    1

    RC76 1 HDT@ 9 10 3 4 @
    9 10 2A 2Y
    APU_RST#_BUF

    3
    2 11 12 2 5 D
    11 12 GND VCC 5 QC10B
    CC84 13 14 APU_DBRDY APU_RST# 1 6 APU_RST#_BUF G
    13 14 APU_DBRDY 12 1A 1Y DMN5L06DWK-7 2N SOT363-6
    0.01U_0201_10V6K
    1 15 16 RC273 1 HDT@ 2 33_0402_5% APU_DBREQ# HDT@ SN74LVC2G07YZPR_WCSP6 S @
    15 16

    4
    6
    D
    APU_PLLTEST0 DP_ENBKL
    8
    7
    6
    5

    17 18 APU_PLLTEST0 12 2 QC10A
    RPC17 17 18 G
    APU_PLLTEST1 DMN5L06DWK-7 2N SOT363-6
    10K_0804_8P4R_5% 19 20 APU_PLLTEST1 12
    19 20

    1
    S @
    HDT@

    1
    A RC14 A
    1
    2
    3
    4

    100K_0402_5%
    SAMTE_ASP-136446-07-B APU_DBREQ# APU_TDI @

    2
    2 2 RC207 1 @ 2 0_0402_5%

    CC213 CC212
    0.01U_0201_10V6K 0.01U_0201_10V6K
    1 HDT@ 1 @
    Security Classification LC Future Center Secret Data Title
    Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP5 (DP/JTAG/SIV2/MISC)
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Custom
    330ARR 1.0

    Date: Friday, March 23, 2018 Sheet 6 of 52


    5 4 3 2 1
    5 4 3 2 1

    +1.8VALW

    +3VALW_APU
    RC243 2 @ 1 0_0402_5% 1

    1
    PCIE_WAKE#_RA RC88 1

    1
    RC3198 CC8783 RC3199 @ 2 0_0402_5%
    10K_0402_5% 10U_0402_6.3V6M 10K_0402_5%
    2 @ DC4
    DC1 SYS_RESET# 1 2 SYS_PWRGD_R AGPIO5 RC92 2 @ 1 0_0402_5% PCIE_WAKE# 32,35,39

    2
    1 2 RSMRST#_R
    39 EC_RSMRST#

    2
    RB751V-40_SOD323-2
    RB751V-40_SOD323-2 @ RC3065 1 @ 2 0_0402_5% SYS_PWRGD_R @ 2 1 DC3
    1 39 EC_SYS_PWRGD 1
    CC1316 1
    0.1U_0201_6.3V6-K CC38 SDM10U45LP-7_DFN1006-2-2
    CC1314 0.1U_0201_6.3V6-K @
    2 0.1U_0201_6.3V6-K 2
    2
    D D

    RC3202 1 2 33_0402_5% PCIE_RST0#_R


    17,32,35 PLT_RST# 1

    1
    RC3201 CC1389
    100K_0402_5% 100P_0201_25V8J
    @
    2
    2

    RPC55
    UC2D EGPIO149 1 8
    ACPI/AUDIO/I2C/GPIO/MISC EGPIO150 2 7
    EGPIO151 3 6
    AW12 EGPIO152 4 5
    EGPIO41/SFI_S5_EGPIO41 AU12
    PCIE_RST0#_R BD5 AGPIO39/SFI_S5_AGPIO39 10K_0804_8P4R_5%
    PCIE_RST1#_R BB6 PCIE_RST0_L/EGPIO26 AR13 EGPIO151
    RSMRST#_R AT16 PCIE_RST1_L/EGPIO27 I2C0_SCL/SFI0_I2C_SCL/EGPIO151 AT13 EGPIO152
    RSMRST_L I2C0_SDA/SFI0_I2C_SDA/EGPIO152
    PBTN_OUT# RC191 1 @ 2 0_0402_5% PWRBTN#_R AR15 AN8 EGPIO149
    39 PBTN_OUT# SYS_PWRGD_R AV6 PWR_BTN_L/AGPIO0 I2C1_SCL/SFI1_I2C_SCL/EGPIO149 AN9 EGPIO150
    SYS_RESET# AP10 PWR_GOOD I2C1_SDA/SFI1_I2C_SDA/EGPIO150
    13 SYS_RESET# PCIE_WAKE#_RA SYS_RESET_L/AGPIO1 I2C2_SCL_APU
    AV11 BC20 RC501 1 @ 2 0_0402_5%
    WAKE_L/AGPIO2 I2C2_SCL/EGPIO113/SCL0 I2C2_SDA_APU APU_SMB_CLK 14,35
    BA20 1 2 0_0402_5%
    PM_SLP_S3# RC193 1 @ 2 0_0402_5% PM_SLP_S3#_R AV13 I2C2_SDA/EGPIO114/SDA0
    RC500 @
    APU_SMB_DATA 14,35 SO-DIMM,Mini Card
    39 PM_SLP_S3# PM_SLP_S5# RC194 1 2 0_0402_5% PM_SLP_S5#_R AT14 SLP_S3_L AM9 TP_I2C0_SCL_R
    @
    13,39 PM_SLP_S5# SLP_S5_L I2C3_SCL/AGPIO19/SCL1 TP_I2C0_SDA_R TP_I2C0_SCL_R 13,40
    AM10
    AR8 I2C3_SDA/AGPIO20/SDA1 TP_I2C0_SDA_R 13,40 Touch Pad
    S0A3_GPIO/AGPIO10 L16 PSA_I2C_SCL
    AC_PRESENT AT10 PSA_I2C_SCL M16 PSA_I2C_SDA
    39 AC_PRESENT AC_PRES/AGPIO23 PSA_I2C_SDA CRB connect to EC and PMIC
    +3VALW_APU RC100 1 2 10K_0402_5% BATLOW# AN6 +1.8VS
    LLB_L/AGPIO12
    AT15 BOARD_ID2
    C AGPIO3 C
    Board ID Description Stuff R AW8 AW10 PSA_I2C_SCL RC3126 2 @ 1 4.7K_0402_5%
    EGPIO42 AGPIO4/SATAE_IFDET PSA_I2C_SDA RC3127 2 @ 1 4.7K_0402_5%
    AP9 AGPIO5
    AGPIO5/DEVSLP0
    0 R17 RC1616 AGPIO6/DEVSLP1
    AU10
    USBDEBUG 28

    Vinafix.com
    Board_ID0 SATA_ACT_L/AGPIO130
    AV15 +3VS_APU

    1 R18 RC3234 AU7 BOARD_ID6 RPC21


    AGPIO9 AU6 PXS_PWREN_R1 RC3240 2 PX@ 1 0_0402_5% I2C2_SCL_APU 3 2
    AGPIO40 BOARD_ID3 PXS_PWREN 8,50,51 I2C2_SDA_APU
    AW13 4 1
    AGPIO69
    0 Discrete GPU RC1614 AGPIO86
    AW15
    EC_SMI# 39
    Board_ID1 HDA_BITCLK AR2 2.2K_0404_4P2R_5%
    RC201 1 @ 2 0_0402_5% HDA_SDIN0_R AP7 AZ_BITCLK/TDM_BCLK_MIC
    36 HDA_SDIN0 HDA_SDIN1 AZ_SDIN0/CODEC_GPI INTRUDER_ALERT
    1 UMA RC1613 TC42 @ 1 AP1
    AZ_SDIN1/SW_DATA1B/TDM_BCLK_PLAYBACK INTRUDER_ALERT
    AU14 RC3100 2 @ 1 20M_0402_5% VCCRTC
    TC210 @ 1 HDA_SDIN2 AP4 AU16 EC_SMI# RC3081 1 2 2.2K_0402_5%
    HDA_RST# AZ_SDIN2/SW_DATA2/TDM_DATA_PLAYBACK SPKR/AGPIO91 PCH_BEEP 36 PCH_TP_INT#
    AP3 AV8 BLINK RC3213 1 2 10K_0402_5%
    HDA_SYNC AZ_RST_L/SW_DATA1A/SW_DATA3/TDM_DATA_MIC BLINK/AGPIO11
    0 NONEC RC1612 HDA_SDOUT
    AR4
    AZ_SYNC/TDM_FRM_MIC PCH_TP_INT#
    Board_ID2 AR3 AW16
    AZ_SDOUT/TDM_FRM_PLAYBACK GENINT1_L/AGPIO89 BD15 PCH_TP_INT# 40
    GENINT2_L/AGPIO90
    1 NEC RC1611 AT2
    SW_MCLK/TDM_BCLK_BT
    +3VALW_APU
    AT4
    AR6 SW_DATA0/TDM_DOUT_BT AR18
    BOARD_ID0 AP6 AGPIO7/FCH_ACP_I2S_SDIN_BT FANIN0/AGPIO84 AT18
    00 Hynix 8Gb RC1610 RC1607 AGPIO8/FCH_ACP_I2S_LRCLK_BT FANOUT0/AGPIO85 PXS_PWREN TP_I2C0_SCL_R
    RPC56
    FP5 REV 0.90 3 2
    PART 4 OF 13 TP_I2C0_SDA_R 4 1

    2
    01 Micron 8Gb RC1610 RC1608 @ AMD-RAVEN-FP5_BGA1140
    Board_ID RC3244 2.2K_0404_4P2R_5%
    [3,4] 1K_0402_5%
    10 DIMM_ONLY RC1609 RC1607 PX@ +3VALW_APU
    RPC15

    1
    PBTN_OUT# 1 8
    11 Samsung 8Gb RC1609 RC1608 PCIE_WAKE#_RA 2 7
    AC_PRESENT

    1
    D 3 6
    2 QC11 4 5
    14,27,41 SUSP
    0 NON-TS RC123 G 2N7002KW_SOT323-3
    Board_ID5 PX@ 10K_0804_8P4R_5%
    S

    3
    B 1 TS RC1606 Blink RC3119 1 @ 2 10K_0402_5% B
    RPC4 PM_SLP_S3# RC203 1 @ 2 2.2K_0402_5%
    PM_SLP_S5# RC208 1 @ 2 2.2K_0402_5%
    0 Reserved RC3224 1 8 HDA_RST# PXS_PWREN_R1 RC3241 1 PX@ 2 10K_0402_5%
    36 HDA_RST_AUDIO# HDA_SYNC
    Board_ID6 36 HDA_SYNC_AUDIO
    2 7
    HDA_BITCLK
    3 6
    36 HDA_BITCLK_AUDIO HDA_SDOUT
    1 Reserved RC3225 36 HDA_SDOUT_AUDIO
    4 5

    33_0804_8P4R_5%
    PCH_TP_INT# RC248 1 @ 2 10K_0402_5%
    RSMRST#_R

    2
    RC87 1 2 100K_0402_5%

    1K_0402_5%

    1K_0402_5%

    1K_0402_5%
    +1.8VS +1.8VALW +3VALW_APU SYS_PWRGD_R RC89 1 2 100K_0402_5%

    RC260

    RC261

    RC262
    PCIE_RST1#_R RC3227 1 2 10K_0402_5%
    PXS_PWREN_R1 RC3242 1 @ 2 10K_0402_5%

    1
    @ @ @
    1

    RC3234 RC3231 RC1615 +3VS_APU +3VALW_APU


    2K_0402_5% 2K_0402_5% 2K_0402_5%
    @ R18@ @
    2

    RC1613 RC1611 RC1609 RC1608 RC1606 RC3225


    2K_0402_5% 10K_0402_5% 2K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
    UMA@ NEC@ @ @ TS@ @
    2

    BOARD_ID0
    BOARD_ID1
    9 BOARD_ID1 BOARD_ID2
    BOARD_ID3
    BOARD_ID4
    9 BOARD_ID4 BOARD_ID5
    A 9 BOARD_ID5 A
    BOARD_ID6
    2

    RC1616 RC1614 RC1612 RC1610 RC1607 RC123 RC3224


    10K_0402_5% 10K_0402_5% 2K_0402_5% 10K_0402_5% 10K_0402_5% 2K_0402_5% 10K_0402_5%
    R17@ PX@ NONEC@ @ @ NOTS@ @
    1

    Security Classification LC Future Center Secret Data Title

    Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP5 AZ/I2C/ACPI/GPIO


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Custom
    330ARR 1.0

    Date: Friday, March 23, 2018 Sheet 7 of 52


    5 4 3 2 1
    5 4 3 2 1

    LPCCLK0 PCH_SPI_CLK

    LPC_RST#_R

    2
    RC46 1 2 33_0402_5%
    13,34,39 APU_LPC_RST#
    RC282
    1 0_0201_5% RC139
    CC1318 EMC_NS@ 10_0402_5%
    150P_0402_50V8-J EMC_NS@

    1
    2
    1 1
    CC219 CC26
    22P_0201_25V8 10P_0201_25V8G
    EMC_NS@ EMC_NS@
    2 2

    UC2E EMC EMC


    D D
    CLK/LPC/EMMC/SD/SPI/eSPI/UART

    AV18
    WLAN_CLKREQ# AN19 CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92
    35 WLAN_CLKREQ# LAN_CLKREQ# CLK_REQ1_L/AGPIO115
    AP19
    +3VS_APU 32 LAN_CLKREQ# PCH_BT_OFF# CLK_REQ2_L/AGPIO116
    AT19
    35 PCH_BT_OFF# PCH_WLAN_OFF# AU19 CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131
    1 2 PCH_WLAN_OFF# 35 PCH_WLAN_OFF# PXS_PWREN_R CLK_REQ4_L/OSCIN/EGPIO132
    RC3161 10K_0402_5% 0_0402_5% 2 @ 1 RC109 AW18
    1 2 LAN_CLKREQ# 7,50,51 PXS_PWREN GPU_CLKREQ# AW19 CLK_REQ5_L/EGPIO120 2 13.3_0402_1%
    RC3162 10K_0402_5% LPCCLK0 RC126
    WLAN_CLKREQ# 18 GPU_CLKREQ# CLK_REQ6_L/EGPIO121 CLK_PCI_EC 13,39
    RC3163 1 2 10K_0402_5% RC125 2 TPM@ 122_0402_5% TPM_CLK 34
    RC3164 1 2 10K_0402_5% PCH_BT_OFF# BD13 EGPIO70
    RC3217 1 UMA@ 2 10K_0402_5% GPU_CLKREQ# EGPIO70/SD_CLK BB14 LPCPD#
    LPC_PD_L/SD_CMD/AGPIO21 LPCPD# 13
    AK1 BB12 LAD0 RC3208 1 2 10_0402_5%
    AK3 GPP_CLK0P LAD0/SD_DATA0/EGPIO104 BC11 1 2 LPC_AD0 13,34,39
    LAD1 RC3209 10_0402_5%
    GPP_CLK0N LAD1/SD_DATA1/EGPIO105 LPC_AD1 13,34,39 +3VS_APU
    BB15 LAD2 RC3210 1 2 10_0402_5% LPC_AD2 13,34,39
    CLK_PCIE_WLAN RC119 1 @ 2 0_0402_5% CLK_PCIE_WLAN_R AM2 LAD2/SD_DATA2/EGPIO106 BC15 LAD3 RC3211 1 2 10_0402_5%
    35 CLK_PCIE_WLAN CLK_PCIE_WLAN# RC120 GPP_CLK1P LAD3/SD_DATA3/EGPIO107 LPC_AD3 13,34,39
    PCIE CLK1 WLAN 1 @ 2 0_0402_5% CLK_PCIE_WLAN#_R AM4 BA15 LPCCLK0
    35 CLK_PCIE_WLAN# GPP_CLK1N LPCCLK0/EGPIO74 BC13 LPC_FRAME# 1 2 10K_0402_5%
    RC152 @
    CLK_PCIE_LAN 1 2 0_0402_5% CLK_PCIE_LAN_R AM1 LPC_CLKRUN_L/AGPIO88 BB13 LPC_CLKRUN# 13,34
    RC121 @ EGPIO75
    32 CLK_PCIE_LAN CLK_PCIE_LAN# GPP_CLK2P LPCCLK1/EGPIO75
    PCIE CLK2 LAN RC122 1 @ 2 0_0402_5% CLK_PCIE_LAN#_R AM3 BC12 SERIRQ 13,34,39 KBRST# RC3063 1 2 10K_0402_5%
    32 CLK_PCIE_LAN# GPP_CLK2N SERIRQ/AGPIO87 BA12
    LFRAME_L/EGPIO109 LPC_FRAME# 13,34,39 PXS_RST#_R
    AL2 RC3226 1 @ 2 10K_0402_5%
    +3VS_APU AL4 GPP_CLK3P BD11 LPC_RST#_R
    GPP_CLK3N LPC_RST_L/SD_WP_L/AGPIO32 BA11 PXS_PWREN_R RC3228 1 @ 2 10K_0402_5%
    AN2 AGPIO68/SD_CD BA13
    GPP_CLK4P LPC_PME_L/SD_PWR_CTRL/AGPIO22 EC_SCI# 39 DGPU_PWROK
    AN4 RC3229 1 @ 2 1K_0402_5%
    RC10 2 @ 1 150_0402_1% XGBECLK0 GPP_CLK4N
    RC6 2 @ 1 150_0402_1% XGBECLK1 AN3
    AP2 GPP_CLK5P BC8
    GPP_CLK5N SPI_ROM_REQ/EGPIO67 BB8 +3VALW_APU
    CLK_PCIE_GPU RC117 1 @ 2 0_0402_5% CLK_PCIE_GPU_R AJ2 SPI_ROM_GNT/AGPIO76
    GPU_CLKREQ# 17 CLK_PCIE_GPU CLK_PCIE_GPU# GPP_CLK6P
    RC3223 1 PX@ 2 2K_0402_5% RC118 1 @ 2 0_0402_5% CLK_PCIE_GPU#_R AJ4 BB11 KBRST# KBRST# 39
    EC_SCI# RC3091 1 @ 2 10K_0402_5%
    17 CLK_PCIE_GPU# GPP_CLK6N ESPI_RESET_L/KBRST_L/AGPIO129 BC6 RC3141 1 @ 2 0_0402_5% LDRQ0# LDRQ0# 13
    TC41 @ 1 48M_OSC AJ3 ESPI_ALERT_L/LDRQ0_L/EGPIO108
    X48M_OSC BB7 SPI_CLK RC3083 1 2 10_0402_5% PCH_SPI_CLK
    SPI_CLK/ESPI_CLK PCH_SPI_CLK 13
    C BA9 SPI_D1 RC3084 1 @ 2 0_0402_5% PCH_SPI_D1
    C
    X48M_X1 BB3 SPI_DI/ESPI_DAT1 BB10 SPI_D0 RC3085 1 @ 2 0_0402_5% PCH_SPI_D0 +1.8VS
    X48M_X1 SPI_DO/ESPI_DAT0 BA10 SPI_D2 RC3087 1 @ 2 0_0402_5% PCH_SPI_D2
    SPI_WP_L/ESPI_DAT2 BC10 SPI_D3 RC3088 1 @ 2 0_0402_5% PCH_SPI_D3
    SPI_HOLD_L/ESPI_DAT3 BC9 SPI_CS0# RC3089 1 @ 2 0_0402_5% PCH_SPI_CS0#
    X48M_X2 SPI_CS1_L/EGPIO118

    1 RC3136 2

    1 RC3212 2

    1 RC3138 2

    1 RC3139 2

    1 RC3140 2
    Vinafix.com
    BA5 BA8 AGPIO30

    1K_0402_1%

    1K_0402_1%

    1K_0402_1%

    1K_0402_1%

    1K_0402_1%
    X48M_X2 SPI_CS2_L/ESPI_CS_L/AGPIO30 BA6
    SPI_CS3_L/AGPIO31 BD8
    SPI_TPM_CS_L/AGPIO29
    XGBECLK0 AF8
    XGBECLK1 AF9 RSVD_76 BA16 APU_UART0_RXD
    RSVD_77 UART0_RXD/EGPIO136 APU_UART0_TXD @ @ @ @ @
    BB18
    UART0_TXD/EGPIO138 BC17 APU_UART0_RTS#
    UART0_RTS_L/UART2_RXD/EGPIO137 BA18 APU_UART0_CTS#
    AW14 UART0_CTS_L/UART2_TXD/EGPIO135 BD18 APU_UART0_INTR
    35 SUSCLK RTCCLK UART0_INTR/AGPIO139

    X32K_X1 AY1 BC18


    X32K_X1 EGPIO141/UART1_RXD BA17 DGPU_PWROK
    EGPIO143/UART1_TXD DGPU_PWROK 17
    BC16
    EGPIO142/UART1_RTS_L/UART3_RXD BB19 PXS_RST#_R RC3220 1 @ 2 0_0402_5%
    X32K_X2 EGPIO140/UART1_CTS_L/UART3_TXD PXS_RST# 17
    RC45 AY4 BB16
    1 2 X32K_X2 AGPIO144/UART1_INTR
    20M_0402_5%
    YC3 FP5 REV 0.90
    1 2 PART 5 OF 13
    @ AMD-RAVEN-FP5_BGA1140
    32.768KHZ_12.5PF_202740-PG14

    1 1

    48MHz/10pF Crystal X48M_X1


    CC21
    10P_0402_50V8J
    CC22
    12P_0402_50V8-J PX@
    2 2 PXS_RST# 0.01U_0201_10V6K 1 2 CC1259
    X48M_X2
    PXS_RST#_R 10K_0402_5% 1 PX@ 2 RC3222

    B RC3204 1 2 1M_0402_5% EGPIO70 10K_0402_5% 1 @ 2 RC3157 B


    Kevin H: change YC2 PN change to SJ10000MQ00,manual modify PN to SJ10000MQ00
    AGPIO30 10K_0402_5% 1 2 RC3158
    YC1
    EGPIO75 10K_0402_5% 1 2 RC3160
    1 4
    OSC1 NC2 DGPU_PWROK 10K_0402_5% 2 UMA@ 1 RC1558
    2 3
    NC1 OSC2
    1 1
    48MHZ_10PF_7V48000017
    CC1390 CC1391 +1.8V_SPI +1.8VALW
    8P_0402_50V8-B 8P_0402_50V8-B UC3
    2 2 PCH_SPI_CS0# 1 8 +1.8V_SPI 0.085 A
    RC435 1 @ 2 0_0402_5%
    PCH_SPI_D1 2 /CS VCC 7 PCH_SPI_D3
    PCH_SPI_D2 3 DO(IO1) /HOLDor/RESET(IO3) 6 PCH_SPI_CLK
    /WP(IO2) CLK PCH_SPI_D0 1
    4 5
    GND DI(IO0) CC220
    0.1U_0201_6.3V6-K
    W25Q64FWSSIQ_SO8 2

    8MB(64Mb)
    +1.8V_SPI

    RC3235 1 2 10K_0402_5% PCH_SPI_CS0#


    RC3236 1 2 10K_0402_5% PCH_SPI_D1
    RC3237 1 @ 2 10K_0402_5% PCH_SPI_D2
    RC3238 1 @ 2 10K_0402_5% PCH_SPI_D3

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP5 CLK/LPC/SD/EMMC/UART


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Custom
    330ARR 1.0

    Date: Friday, March 23, 2018 Sheet 8 of 52


    5 4 3 2 1
    5 4 3 2 1

    UC2J
    USB

    AD2 AE7 USB20_P4


    USBC0_A2/USB_0_TXP0/DP3_TXP2 USB_0_DP0 USB20_N4 USB20_P4 36
    AD4 AE6 Card Reader
    USBC0_A3/USB_0_TXN0/DP3_TXN2 USB_0_DM0 USB20_N4 36
    AC2 AG10 USB20_P7
    USBC0_B11/USB_0_RXP0/DP3_TXP3 USB_0_DP1 USB20_N7 USB20_P7 29
    AC4 AG9 Type C
    USBC0_B10/USB_0_RXN0/DP3_TXN3 USB_0_DM1 USB20_N7 29
    D USB20_P6 D
    AF4 AF12
    USBC0_B2/DP3_TXP1 USB_0_DP2 USB20_N6 USB20_P6 28
    AF2 AF11 LEFT USB (3.0) lower
    USBC0_B3/DP3_TXN1 USB_0_DM2 USB20_N6 28
    AE3 AE10 USB20_P5
    USBC0_A11/DP3_TXP0 USB_0_DP3 USB20_N5 USB20_P5 28
    AE1 AE9 LEFT USB (3.0) upper
    USBC0_A10/DP3_TXN0 USB_0_DM3 USB20_N5 28
    USB30_TX_P3 AG3 AJ12 USB20_P5_HUB
    29 USB30_TX_P3 USB30_TX_N3 USB_0_TXP1 USB_1_DP0 USB20_N5_HUB USB20_P5_HUB 31
    AG1 AJ11 USB HUB(Camera,FP,Touch Screen)
    29 USB30_TX_N3 USB_0_TXN1 USB_1_DM0 USB20_N5_HUB 31
    Type C
    USB30_RX_P3 AJ9 AD9 USB20_P0
    29 USB30_RX_P3 USB30_RX_N3 USB_0_RXP1 USB_1_DP1 USB20_N0 USB20_P0 35
    AJ8 AD8 BT
    29 USB30_RX_N3 USB_0_RXN1 USB_1_DM1 USB20_N0 35
    USB30_TX_P2 AG4 +1.8VALW
    28 USB30_TX_P2 USB30_TX_N2 USB_0_TXP2
    AG2
    28 USB30_TX_N2 USB_0_TXN2
    LEFT USB (3.0) lower
    USB30_RX_P2 AG7
    28 USB30_RX_P2 USB30_RX_N2 USB_0_RXP2 USBC_I2C_SCL USBC_I2C_SCL
    AG6 AM6 RC270 1 2 4.7K_0402_5%
    28 USB30_RX_N2 USB_0_RXN2 USBC_I2C_SCL USBC_I2C_SDA RC3232 1 2 4.7K_0402_5%
    USB30_TX_P1 AA2 AM7 USBC_I2C_SDA
    28 USB30_TX_P1 USB30_TX_N1 USBC1_A2/USB_0_TXP3/DP2_TXP2 USBC_I2C_SDA
    AA4
    28 USB30_TX_N1 USBC1_A3/USB_0_TXN3/DP2_TXN2
    LEFT USB (3.0) upper
    USB30_RX_P1 Y1
    28 USB30_RX_P1 USB30_RX_N1 USBC1_B11/USB_0_RXP3/DP2_TXP3
    Y3
    28 USB30_RX_N1 USBC1_B10/USB_0_RXN3/DP2_TXN3
    AC1
    AC3 USBC1_B2/DP2_TXP1
    USBC1_B3/DP2_TXN1 AK10 BOARD_ID1
    USB_OC0_L/AGPIO16 USB_OC3# BOARD_ID1 7 TYPE_C_OCP#
    AB2 AK9 RC3239 1 @ 2 0_0402_5%
    USBC1_A11/DP2_TXP0 USB_OC1_L/AGPIO17 USB_OC2# USB_OC1# TYPE_C_OCP# 29
    AB4 AL9 RC3233 1 @ 2 0_0402_5%
    USBC1_A10/DP2_TXN0 USB_OC2_L/AGPIO18 AL8 USB_OC1#
    C C
    USB_OC3_L/AGPIO24 BOARD_ID5 USB_OC1# 28
    AH4 AW7
    USB_1_TXP0 AGPIO14/USB_OC4_L BOARD_ID4 BOARD_ID5 7
    AH2 AT12
    USB_1_TXN0 AGPIO13/USB_OC5_L BOARD_ID4 7

    Vinafix.com
    AK7
    AK6 USB_1_RXP0
    USB_1_RXN0
    FP5 REV 0.90
    PART 10 OF 13 +3VALW _APU
    @ AMD-RAVEN-FP5_BGA1140

    USB_OC3# RC3218 1 2 10K_0402_5%


    USB_OC1# RC3219 1 2 10K_0402_5%

    UC2L
    RSVD
    T11 AA9
    RSVD_32 RSVD_62 AA8
    AC7 RSVD_61 AC6
    RSVD_66 RSVD_65
    B B
    Y9
    Y10 RSVD_55 AD11
    RSVD_56 RSVD_72
    W11 AC9
    W12 RSVD_47 RSVD_67 AA11
    RSVD_48 RSVD_63
    V9 T12
    V10 RSVD_38 RSVD_33 AD12
    RSVD_39 RSVD_73
    Y6
    RSVD_53 Y7
    RSVD_54
    AA12 W8
    AC10 RSVD_64 RSVD_45 W9
    RSVD_68 RSVD_46

    FP5 REV 0.90


    PART 12 OF 13
    @ AMD-RAVEN-FP5_BGA1140

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP5 USB/WIFI
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 330ARR
    Date: Friday, March 23, 2018 Sheet 9 of 52
    5 4 3 2 1
    5 4 3 2 1

    D D

    UC2M
    CAMERAS
    C C
    A18 B15
    C18 CAM0_CSI2_CLOCKP CAM0_CLK
    CAM0_CSI2_CLOCKN D15
    A15 CAM0_I2C_SCL C14
    C15 CAM0_CSI2_DATAP0 CAM0_I2C_SDA
    CAM0_CSI2_DATAN0 B13

    Vinafix.com
    B16 CAM0_SHUTDOWN
    C16 CAM0_CSI2_DATAP1
    CAM0_CSI2_DATAN1
    C19
    B18 CAM0_CSI2_DATAP2
    CAM0_CSI2_DATAN2
    B17
    D17 CAM0_CSI2_DATAP3
    CAM0_CSI2_DATAN3
    D12 B10
    B12 CAM1_CSI2_CLOCKP CAM1_CLK
    CAM1_CSI2_CLOCKN A11
    C13 CAM1_I2C_SCL C11
    A13 CAM1_CSI2_DATAP0 CAM1_I2C_SDA
    CAM1_CSI2_DATAN0 D11
    B11 CAM1_SHUTDOWN
    C12 CAM1_CSI2_DATAP1 D13
    CAM1_CSI2_DATAN1 CAM_PRIV_LED D10
    J13 CAM_IR_ILLU
    FP5 REV 0.90
    RSVD_6 PART 13 OF 13
    @ AMD-RAVEN-FP5_BGA1140

    B B

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP5 CAM


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    C
    330ARR 1.0

    Date: Friday, March 23, 2018 Sheet 10 of 52


    5 4 3 2 1
    5 4 3 2 1

    +VDDC_VDD
    +VDDCR_SOC
    UC2F
    10A M15
    POWER
    G7 35A
    M18 VDDCR_SOC_1 VDDCR_1 G10
    M19 VDDCR_SOC_2 VDDCR_2 G12
    N16 VDDCR_SOC_3 VDDCR_3 G14
    D D
    N18 VDDCR_SOC_4 VDDCR_4 H8
    N20 VDDCR_SOC_5 VDDCR_5 H11
    P17 VDDCR_SOC_6 VDDCR_6 H15
    P19 VDDCR_SOC_7 VDDCR_7 K7
    R18 VDDCR_SOC_8 VDDCR_8 K12
    R20 VDDCR_SOC_9 VDDCR_9 K14
    T19 VDDCR_SOC_10 VDDCR_10 L8
    U18 VDDCR_SOC_11 VDDCR_11 M7
    U20 VDDCR_SOC_12 VDDCR_12 M10
    V19 VDDCR_SOC_13 VDDCR_13 N14
    W18 VDDCR_SOC_14 VDDCR_14 P7
    W20 VDDCR_SOC_15 VDDCR_15 P10
    +1.2V Y19 VDDCR_SOC_16 VDDCR_16 P13
    VDDCR_SOC_17 VDDCR_17 P15
    6A T32 VDDCR_18 R8
    V28 VDDIO_MEM_S3_1 VDDCR_19 R14
    W28 VDDIO_MEM_S3_2 VDDCR_20 R16
    W32 VDDIO_MEM_S3_3 VDDCR_21 T7
    Y22 VDDIO_MEM_S3_4 VDDCR_22 T10
    Y25 VDDIO_MEM_S3_5 VDDCR_23 T13
    +3VS_APU Y28 VDDIO_MEM_S3_6 VDDCR_24 T15
    +VDDC_VDD +3VS AA20 VDDIO_MEM_S3_7 VDDCR_25 T17
    AA23 VDDIO_MEM_S3_8 VDDCR_26 U14

    22U_0603_6.3V6-M
    180P_0402_50V8-J

    AA26 VDDIO_MEM_S3_9 VDDCR_27 U16

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    RC3112 1 @ 2 0_0402_5% AA28 VDDIO_MEM_S3_10 VDDCR_28 V13
    1 1 1 VDDIO_MEM_S3_11 VDDCR_29

    1
    AA32 V15
    CC1382

    CC1375

    CC1337

    CC1338
    AC20 VDDIO_MEM_S3_12 VDDCR_30 V17
    AC22 VDDIO_MEM_S3_13 VDDCR_31 W7
    VDDIO_MEM_S3_14 VDDCR_32

    2
    2 2 2 AC25 W10
    AC28 VDDIO_MEM_S3_15 VDDCR_33 W14
    +1.8VS BO BU AD23 VDDIO_MEM_S3_16 VDDCR_34 W16
    AD26 VDDIO_MEM_S3_17 VDDCR_35 Y8

    22U_0603_6.3V6-M

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    CD@
    AD28 VDDIO_MEM_S3_18 VDDCR_36 Y13
    1 1 VDDIO_MEM_S3_19 VDDCR_37
    AD32 Y15

    CC1336

    CC1335
    VDDIO_MEM_S3_20 VDDCR_38

    1
    AE20 Y17

    CC1376
    AE22 VDDIO_MEM_S3_21 VDDCR_39 AA7
    +VDDCR_SOC 2 2 AE25 VDDIO_MEM_S3_22 VDDCR_40 AA10
    VDDIO_MEM_S3_23 VDDCR_41

    2
    +1.8VS +1.8VALW AE28 AA14
    BO BU AF23 VDDIO_MEM_S3_24 VDDCR_42 AA16
    CD@ AF26 VDDIO_MEM_S3_25 VDDCR_43 AA18
    1 1 VDDIO_MEM_S3_26 VDDCR_44
    C +1.8VALW AF28 AB13 C
    VDDIO_MEM_S3_27 VDDCR_45

    2
    AF32 AB15

    22U_0603_6.3V6-M

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    CC1372 CC1383
    10U_0402_6.3V6M RC3154 RC3118 AG20 VDDIO_MEM_S3_28 VDDCR_46 AB17
    10U_0402_6.3V6M 1 1 VDDIO_MEM_S3_29 VDDCR_47
    2 2 AG22 AB19

    CC1333

    CC1334
    0_0402_5% 0_0402_5% VDDIO_MEM_S3_30 VDDCR_48

    1
    AG25 AC14

    CC1377
    @ @ +VDD_AUD_ALW AG28 VDDIO_MEM_S3_31 VDDCR_49 AC16
    VDDIO_MEM_S3_32 VDDCR_50

    1
    2 2 AJ20 AC18

    22U_0603_6.3V6-M
    Vinafix.com
    VDDIO_MEM_S3_33 VDDCR_51

    2
    AJ23 AD7

    1U_0402_6.3V6K
    BO BU AJ26 VDDIO_MEM_S3_34 VDDCR_52 AD10
    1 VDDIO_MEM_S3_35 VDDCR_53

    1
    AJ28 AD13

    CC1385

    CC1339
    CD@
    +3VALW_APU AJ32 VDDIO_MEM_S3_36 VDDCR_54 AD15
    AK28 VDDIO_MEM_S3_37 VDDCR_55 AD17

    22U_0603_6.3V6-M

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    VDDIO_MEM_S3_38 VDDCR_56

    2
    2 AL28 AD19
    1 1 VDDIO_MEM_S3_39 VDDCR_57
    +1.2V AL32 AE8

    CC1331

    CC1332
    VDDIO_MEM_S3_40 VDDCR_58

    1
    AE14
    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    0.2A

    CC1378
    BO BU
    AP12 VDDCR_59 AE16
    180P_0402_50V8-J
    1U_0402_6.3V6K

    1U_0402_6.3V6K

    2 2 VDDIO_AUDIO VDDCR_60 AE18


    1 1 1 0.25A VDDCR_61

    2
    1

    AL18 AF7
    CC1257

    CC1341

    CC1342

    CC1343

    CC1344

    CC1345

    CC1346

    CC1347

    CC1348

    CC1373

    CC1374

    CC1384

    BO BU AM17 VDD_33_1 VDDCR_62 AF10


    VDD_33_2 VDDCR_63 AF13
    CD@
    2A VDDCR_64
    2

    2 2 2 +0.9VALW AL20 AF15


    AM19 VDD_18_1 VDDCR_65 AF17

    22U_0603_6.3V6-M

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    VDD_18_2 VDDCR_66 AF19
    CD@ CD@ CD@ 1 1 1 0.5A AL19 VDDCR_67 AG14

    CC1328

    CC1329

    CC1330
    VDD_18_S5_1 VDDCR_68

    1
    All BU(on bottom side under SOC) AM18 AG16

    CC1379
    CD@
    VDD_18_S5_2 VDDCR_69 AG18
    2 2 2 0.25A AL17 VDDCR_70 AH13
    VDD_33_S5_1 VDDCR_71

    2
    AM16 AH15
    VDD_33_S5_2 VDDCR_72 AH17
    BO
    CD@
    BU CD@
    1A AL14 VDDCR_73 AH19
    +1.2V AL15 VDDP_S5_1 VDDCR_74 AJ7
    +0.9VS AM14 VDDP_S5_2 VDDCR_75 AJ10

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    VDDP_S5_3 VDDCR_76 AJ14
    4A

    180P_0402_50V8-J
    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    AL13 VDDCR_77 AJ16
    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    1 1 1 1 1 1 1 1 1 VDDP_1 VDDCR_78

    1
    AM12 AJ18
    180P_0402_50V8-J

    180P_0402_50V8-J

    CC1380

    CC1319

    CC1320

    CC1321

    CC1322

    CC1323

    CC1324

    CC1325

    CC1326

    CC1327
    VDDP_2 VDDCR_79

    1
    AM13 AK13

    CC1381
    1 1 1 1 1 1 VDDP_3 VDDCR_80
    AN12 AK15
    CC168

    CC169

    CC170

    CC172

    CC179

    CC176

    VDDP_4 VDDCR_81

    2
    2 2 2 2 2 2 2 2 2 AN13 AK17
    VDDP_5 VDDCR_82

    2
    AK19
    2 2 2 2 2 2 AT11 VDDCR_83
    BO(Bottom side outside SOC) BU VDDBT_RTC_G
    B B
    FP5 REV 0.90
    @ CD@ +RTCBATT +RTCBATT_APU
    DECOUPLING BETWEEN PROCESSOR AND DIMMs
    @
    1 2 0.1A @
    PART 6 OF 13
    AMD-RAVEN-FP5_BGA1140
    RC3128 1K_0402_5%

    0.22U_0201_6.3V6-K
    ACROSS VDDIO AND VSS SPLIT

    1U_0402_6.3V6K
    1 1

    CC1340

    CC192
    2 2

    BU

    UC5
    VCCRTC
    RC231 1 2 10K_0402_5% 1
    Vin
    3 +RTCBATT
    Vout
    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1
    1 2 1
    GND

    1
    CC37

    CC194
    RC8
    470_0603_5%
    AP2138N-1.5TRG1_SOT23-3 @
    2 2 JCMOS1
    @

    12
    D QC7
    2 EC_RTCRST#_ON
    G EC_RTCRST#_ON 39

    1
    S 2N7002KW_SOT323-3 RC15

    3
    @ 100K_0402_5%
    @

    2
    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP5 POWER
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Custom
    330ARR 1.0

    Date: Friday, March 23, 2018 Sheet 11 of 52


    5 4 3 2 1
    5 4 3 2 1

    D D

    UC2G UC2H UC2K


    GND GND GND/RSVD
    N12 K32 V8 AG8 AR5 BD16
    A3 VSS_316 VSS_62 L5 V11 VSS_124 VSS_186 AG11 AR7 VSS_248 VSS_310 BD19
    A5 VSS_1 VSS_63 L13 V12 VSS_125 VSS_187 AG12 AR12 VSS_249 VSS_311 BD21
    A7 VSS_2 VSS_64 L15 V14 VSS_126 VSS_188 AG13 AR14 VSS_250 VSS_312 BD23
    A10 VSS_3 VSS_65 L18 V16 VSS_127 VSS_189 AG15 AR16 VSS_251 VSS_313 BD26
    A12 VSS_4 VSS_66 L20 V18 VSS_128 VSS_190 AG17 AR19 VSS_252 VSS_314 BD30
    A14 VSS_5 VSS_67 L25 V20 VSS_129 VSS_191 AG19 AR21 VSS_253 VSS_315
    A16 VSS_6 VSS_68 L28 V22 VSS_130 VSS_192 AH14 AR26 VSS_254
    A19 VSS_7 VSS_69 M1 V25 VSS_131 VSS_193 AH16 AR28 VSS_255
    A21 VSS_8 VSS_70 M5 W1 VSS_132 VSS_194 AH18 AR32 VSS_256
    A23 VSS_9 VSS_71 M12 W5 VSS_133 VSS_195 AH20 AU5 VSS_257
    A26 VSS_10 VSS_72 M21 W13 VSS_134 VSS_196 AJ1 AU8 VSS_258
    A30 VSS_11 VSS_73 M23 W15 VSS_135 VSS_197 AJ5 AU11 VSS_259
    C3 VSS_12 VSS_74 M26 W17 VSS_136 VSS_198 AJ13 AU13 VSS_260
    C32 VSS_13 VSS_75 M28 W19 VSS_137 VSS_199 AJ15 AU15 VSS_261
    D16 VSS_14 VSS_76 M32 W23 VSS_138 VSS_200 AJ17 AU18 VSS_262
    D18 VSS_15 VSS_77 N4 W26 VSS_139 VSS_201 AJ19 AU20 VSS_263
    D20 VSS_16 VSS_78 N5 Y5 VSS_140 VSS_202 AK5 AU22 VSS_264
    E7 VSS_17 VSS_79 N8 Y11 VSS_141 VSS_203 AK8 AU25 VSS_265 B20
    E8 VSS_18 VSS_80 N11 Y12 VSS_142 VSS_204 AK11 AU28 VSS_266 RSVD_1 G3
    E10 VSS_19 VSS_81 N13 Y14 VSS_143 VSS_205 AK12 AV1 VSS_267 RSVD_5 J20
    E11 VSS_20 VSS_82 N15 Y16 VSS_144 VSS_206 AK14 AV5 VSS_268 RSVD_7 K3
    E12 VSS_21 VSS_83 N17 Y18 VSS_145 VSS_207 AK16 AV7 VSS_269 RSVD_8 K6
    E13 VSS_22 VSS_84 N19 Y20 VSS_146 VSS_208 AK18 AV10 VSS_270 RSVD_9 K20
    E14 VSS_23 VSS_85 N22 AA1 VSS_147 VSS_209 AK20 AV12 VSS_271 RSVD_10 M3
    E15 VSS_24 VSS_86 N25 AA5 VSS_148 VSS_210 AK22 AV14 VSS_272 RSVD_11 M6
    E16 VSS_25 VSS_87 N28 AA13 VSS_149 VSS_211 AK25 AV16 VSS_273 RSVD_12 M13
    C C
    E18 VSS_26 VSS_88 P1 AA15 VSS_150 VSS_212 AL1 AV19 VSS_274 RSVD_13 P6
    E19 VSS_27 VSS_89 P5 AA17 VSS_151 VSS_213 AL5 AV21 VSS_275 RSVD_22 P22
    E20 VSS_28 VSS_90 P14 AA19 VSS_152 VSS_214 AL7 AV23 VSS_276 RSVD_23 T3
    E21 VSS_29 VSS_91 P16 AB14 VSS_153 VSS_215 AL10 AV26 VSS_277 RSVD_30 T6
    E22 VSS_30 VSS_92 P18 AB16 VSS_154 VSS_216 AL12 AV28 VSS_278 RSVD_31 T29
    E23 VSS_31 VSS_93 P20 AB18 VSS_155 VSS_217 AL16 AV32 VSS_279 RSVD_37 W6

    Vinafix.com
    E25 VSS_32 VSS_94 P23 AB20 VSS_156 VSS_218 AL23 AW5 VSS_280 RSVD_44 W21
    E26 VSS_33 VSS_95 P26 AC5 VSS_157 VSS_219 AL26 AW28 VSS_281 RSVD_49 W22
    E27 VSS_34 VSS_96 P28 AC8 VSS_158 VSS_220 AM5 AY6 VSS_282 RSVD_50 Y21
    F5 VSS_35 VSS_97 P32 AC11 VSS_159 VSS_221 AM8 AY7 VSS_283 RSVD_57 Y27
    F28 VSS_36 VSS_98 R5 AC12 VSS_160 VSS_222 AM15 AY8 VSS_284 RSVD_58 AA3
    G1 VSS_37 VSS_99 R11 AC13 VSS_161 VSS_223 AM20 AY10 VSS_285 RSVD_59 AA6
    G5 VSS_38 VSS_100 R12 AC15 VSS_162 VSS_224 AM22 AY11 VSS_286 RSVD_60 AC29
    G16 VSS_39 VSS_101 R13 AC17 VSS_163 VSS_225 AM25 AY12 VSS_287 RSVD_69 AD3
    G19 VSS_40 VSS_102 R15 AC19 VSS_164 VSS_226 AM28 AY13 VSS_288 RSVD_70 AD6
    G21 VSS_41 VSS_103 R17 AD1 VSS_165 VSS_227 AN1 AY14 VSS_289 RSVD_71 AF3
    G23 VSS_42 VSS_104 R19 AD5 VSS_166 VSS_228 AN5 AY15 VSS_290 RSVD_74 AF6
    G26 VSS_43 VSS_105 R22 AD14 VSS_167 VSS_229 AN7 AY16 VSS_291 RSVD_75 AF30
    G28 VSS_44 VSS_106 R25 AD16 VSS_168 VSS_230 AN10 AY18 VSS_292 RSVD_78 AJ6
    G32 VSS_45 VSS_107 R28 AD18 VSS_169 VSS_231 AN15 AY19 VSS_293 RSVD_79 AJ24
    H5 VSS_46 VSS_108 R30 AD20 VSS_170 VSS_232 AN18 AY20 VSS_294 RSVD_80 AK23
    H13 VSS_47 VSS_109 T1 AE5 VSS_171 VSS_233 AN21 AY21 VSS_295 RSVD_81 AK27
    H18 VSS_48 VSS_110 T5 AE11 VSS_172 VSS_234 AN23 AY22 VSS_296 RSVD_82 AL3
    H20 VSS_49 VSS_111 T14 AE12 VSS_173 VSS_235 AN26 AY23 VSS_297 RSVD_83 AN29
    H22 VSS_50 VSS_112 T16 AE13 VSS_174 VSS_236 AN28 AY25 VSS_298 RSVD_87 AN31
    H25 VSS_51 VSS_113 T18 AE15 VSS_175 VSS_237 AN32 AY26 VSS_299 RSVD_88
    H28 VSS_52 VSS_114 T20 AE17 VSS_176 VSS_238 AP5 AY27 VSS_300 +5VALW
    K1 VSS_53 VSS_115 T23 AE19 VSS_177 VSS_239 AP8 BB1 VSS_301
    K5 VSS_54 VSS_116 T26 AF1 VSS_178 VSS_240 AP13 BB20 VSS_302
    K16 VSS_55 VSS_117 T28 AF5 VSS_179 VSS_241 AP15 BB32 VSS_303 M14 RC3103
    UNNAMED_15_FP5_I216_RSVD14
    1 @ 2 0_0402_5% APU_PLLTEST0
    K19 VSS_56 VSS_118 U13 AF14 VSS_180 VSS_242 AP18 BD3 VSS_304 RSVD_14 AL6 1 2 APU_PLLTEST0 6
    RC3104 @ 0_0402_5%
    UNNAMED_15_FP5_I216_RSVD84

    K21 VSS_57 VSS_119 U15 AF16 VSS_181 VSS_243 AP20 BD7 VSS_305 RSVD_84 AL11 RC3105
    UNNAMED_15_FP5_I216_RSVD85
    1 @ 2 0_0402_5% APU_PLLTEST1
    VSS_58 VSS_120 VSS_182 VSS_244 VSS_306 RSVD_85 APU_PLLTEST1 6
    K22 U17 AF18 AP25 BD10 AN16 RC3106 1 @ 2 0_0402_5% APU_DBRDY
    UNNAMED_15_FP5_I216_RSVD86

    K26 VSS_59 VSS_121 U19 AF20 VSS_183 VSS_245 AP28 BD12 VSS_307 RSVD_86 APU_DBRDY 6
    K28 VSS_60 VSS_122 V5 AG5 VSS_184 VSS_246 AR1 BD14 VSS_308
    VSS_61 VSS_123 VSS_185 VSS_247 VSS_309
    FP5 REV 0.90 FP5 REV 0.90 FP5 REV 0.90
    PART 7 OF 13 PART 8 OF 13 PART 11 OF 13
    B B
    @ AMD-RAVEN-FP5_BGA1140 @ AMD-RAVEN-FP5_BGA1140 @ AMD-RAVEN-FP5_BGA1140

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP5 GND


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    C
    330ARR 1.0

    Date: Friday, March 23, 2018 Sheet 12 of 52


    5 4 3 2 1
    5 4 3 2 1

    +1.8VS +1.8VALW +3VALW_APU

    1
    RC3134 RC3133 RC156
    10K_0402_5% 10K_0402_5% 10K_0402_5%
    @

    2
    D D
    PCH_SPI_CLK
    8 PCH_SPI_CLK 7 SYS_RESET#

    1
    RC159 RC163
    2K_0402_5% 2K_0402_5%
    @ @

    2
    STRAP PINS SYS_RESET#
    1:USE 48MHZ CRYSTAL CLOCK AND
    GENERATE BOTH INTERNAL AND EXTERNAL CLOCKS(DEFAULT)
    PCH_SPI_CLK 0:USE 100MHZ PCIE CLOCK AS REFERENCE CLOCK AND
    GENERATE INTERNAL CLOCKS ONLY
    C C

    1:NORMAL RESET MODE(DEFAULT)


    SYS_RESET# 0:SHORT RESET MODE

    Vinafix.com
    15P_0402_50V8J

    CC1387 2 1 1
    RC3147
    UNNAMED_16_CAP_I116_B
    LPC ROM EMULATOR HEADER

    2 33_0402_5%
    +3VALW_APU
    2

    RC3146
    +3VS_APU
    2

    RC3145
    PIN4 should be removed as a Key

    @ @ 0_0402_5% 0_0402_5%
    DAISY CHAIN ROUTING FOR LPC SIGNALS
    LPC@ LPC@
    1

    B B
    CLK_PCI_EC
    8,39 CLK_PCI_EC LPC_FRAME# J601
    1 2
    8,34,39 LPC_FRAME# APU_LPC_RST# RC3144 1 LPC@ 2 0_0402_5% 3 4
    8,34,39 APU_LPC_RST# LPC_RST#_H 5 6 RC3142 1 @ 2 0_0402_5% PM_SLP_S5#
    UNNAMED_16_CON20_I130_P6

    LPC_AD3 LPC_AD2 PM_SLP_S5# 7,39


    7 8
    8,34,39 LPC_AD3 LPCRUNPWR 9 10 LPC_AD1 LPC_AD2 8,34,39
    LPC_AD0 LPC_AD1 8,34,39
    11 12
    8,34,39 LPC_AD0 I2C2_SCL_LPC I2C2_SDA_LPC RC3153 1 LPC@
    RC3152 1 LPC@ 2 0_0402_5% 13 14 2 0_0402_5%
    7,40 TP_I2C0_SCL_R TP_I2C0_SDA_R 7,40
    15 16 SERIRQ
    LPC_CLKRUN# SERIRQ 8,34,39
    17 18
    19 20 LPC_CLKRUN# 8,34
    LPCPD# LDRQ0#
    8 LPCPD# LDRQ0# 8
    2 2 HEADER_2X10
    @
    CD345 CD347
    0.1U_0402_10V7K 0.1U_0402_10V7K
    LPC@ 1 1 LPC@

    RC3152 RC3153 should be put on APU side to reduce stub when MP

    +3VS_APU

    RC3214 1 LPC@ 2 10K_0402_5% LPCPD#

    RC3215 1 @ 2 10K_0402_5% LPC_CLKRUN#

    RC3216 1 LPC@ 2 100K_0402_5% APU_LPC_RST#


    A A
    CC1392 1 @ 2 150P_0402_50V8-J

    Security Classification LC Future Center Secret Data Title

    Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP5 Straps


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    C
    330ARR 1.0

    Date: Friday, March 23, 2018 Sheet 13 of 52


    5 4 3 2 1
    5 4 3 2 1

    DDRA_DQ[0..63]
    DDRA_DQ[0..63] 5
    DDRA_DQS[0..7]
    DDRA_DQS[0..7] 5
    DDRA_DQS#[0..7]
    DDRA_DQS#[0..7] 5
    DDRA_MA[0..13]
    +1.2V +1.2V DDRA_MA[0..13] 5
    DDRA_DM[0..7]
    DDRA_DM[0..7] 5
    JDDR1A JDDR1B
    Swap Table
    1 2 DDRA_MA3 131 132 DDRA_MA2
    DDRA_DQ1 3 VSS_1 VSS_2 4 DDRA_DQ4 DDRA_MA1 133 A3 A2 134 MEM_MA_EVENT#
    DQ5 DQ4 A1 EVENT_n MEM_MA_EVENT# 5 Pin Name Net Name
    5 6 135 136
    DDRA_DQ6 7 VSS_3 VSS_4 8 DDRA_DQ5 DDRA_CLK0 137 VDD_9 VDD_10 138 DDRA_CLK1
    DQ1 DQ0 5 DDRA_CLK0 DDRA_CLK0# CK0_t CK1_t DDRA_CLK1# DDRA_CLK1 5 DQ0 DDRA_DQ6
    9 10 139 140 DQ1 DDRA_DQ5
    D
    DDRA_DQS#0 VSS_5 VSS_6 DDRA_DM0 5 DDRA_CLK0# CK0_c CK1_c DDRA_CLK1# 5 D
    11 12 141 142
    DDRA_DQS0 13 DQS0_C DM0_n/DBIO_n/NC 14 143 VDD_11 VDD_12 144 DDRA_MA0 DQ2 DDRA_DQ2
    DQS0_t VSS_7 DDRA_DQ0 5 DDRA_PAR Parity A0 DQ3 DDRA_DQ3
    15 16
    DDRA_DQ7 17 VSS_8 DQ6 18 DQ4 DDRA_DQ4
    19 DQ7 VSS_9 20 DDRA_DQ2 DDRA_BA1 145 146 DDRA_MA10 DQ5 DDRA_DQ0
    DDRA_DQ3 VSS_10 DQ2 5 DDRA_BA1 BA1 A10/AP
    21 22 147 148 DQ6 DDRA_DQ1
    23 DQ3 VSS_11 24 DDRA_DQ12 DDRA_CS0# 149 VDD_13 VDD_14 150 DDRA_BA0
    DDRA_DQ8 25 VSS_12 DQ12 26 5 DDRA_CS0# DDRA_MA14_WE# 151 CS0_n BA0 152 DDRA_MA16_RAS# DDRA_BA0 5 DQ7 DDRA_DQ7
    27 DQ13 VSS_13 28 DDRA_DQ13 5 DDRA_MA14_WE#
    153 WE_n/A14 RAS_n/A16 154 DDRA_MA16_RAS# 5 DQS#0 DDRA_DQS#0
    DDRA_DQ9 29 VSS_14 DQ8 30 DDRA_ODT0 155 VDD_15 VDD_16 156 DDRA_MA15_CAS# DQS0 DDRA_DQS0
    31 DQ9 VSS_15 32 DDRA_DQS#1 5 DDRA_ODT0 DDRA_CS1# 157 ODT0 CAS_n/A15 158 DDRA_MA13 DDRA_MA15_CAS# 5
    DDRA_DM1 VSS_16 DQS1_c DDRA_DQS1 5 DDRA_CS1# CS1_n A13
    33 34 159 160 DQ8 DDRA_DQ13
    35 DM1_n/DBl1_n/NC DQS1_t 36 DDRA_ODT1 161 VDD_17 VDD_18 162 +VREF_CA
    DDRA_DQ14 VSS_17 VSS_18 DDRA_DQ10 5 DDRA_ODT1 ODT1 C0/CS2_n/NC DQ9 DDRA_DQ9
    37 38 163 164
    39 DQ15 DQ14 40 165 VDD_19 VREFCA 166 DDRA0_SA2 DQ10 DDRA_DQ14
    DDRA_DQ11 41 VSS_19 VSS_20 42 DDRA_DQ15 167 C1/CS3_n/NC SA2 168 DQ11 DDRA_DQ10
    43 DQ10 DQ11 44 DDRA_DQ33 169 VSS_53 VSS_54 170 DDRA_DQ37 DQ12 DDRA_DQ12
    DDRA_DQ17 45 VSS_21 VSS_22 46 DDRA_DQ16 171 DQ37 DQ36 172 DQ13 DDRA_DQ8
    47 DQ21 DQ20 48 DDRA_DQ32 173 VSS_55 VSS_56 174 DDRA_DQ36
    DDRA_DQ21 VSS_23 VSS_24 DDRA_DQ20 DQ33 DQ32 DQ14 DDRA_DQ15
    49 50 175 176
    51 DQ17 DQ16 52 DDRA_DQS#4 177 VSS_57 VSS_58 178 DDRA_DM4 DQ15 DDRA_DQ11
    DDRA_DQS#2 53 VSS_25 VSS_26 54 DDRA_DM2 DDRA_DQS4 179 DQS4_c DM4_n/DBl4_n/NC 180 DQS#1 DDRA_DQS#1
    DDRA_DQS2 55 DQS2_c DM2_n/DBl2_n/NC 56 181 DQS4_t VSS_59 182 DDRA_DQ39 DQS1 DDRA_DQS1
    57 DQS2_t VSS_27 58 DDRA_DQ18 DDRA_DQ35 183 VSS_60 DQ39 184
    DDRA_DQ22 59 VSS_28 DQ22 60 185 DQ38 VSS_61 186 DDRA_DQ38
    DQ23 VSS_29 DDRA_DQ23 DDRA_DQ34 VSS_62 DQ35
    DQ16 DDRA_DQ20
    61 62 187 188 DQ17 DDRA_DQ21
    DDRA_DQ19 63 VSS_30 DQ18 64 189 DQ34 VSS_63 190 DDRA_DQ45
    65 DQ19 VSS_31 66 DDRA_DQ24 DDRA_DQ40 191 VSS_64 DQ45 192 DQ18 DDRA_DQ22
    DDRA_DQ25 67 VSS_32 DQ28 68 193 DQ44 VSS_65 194 DDRA_DQ44 DQ19 DDRA_DQ19
    69 DQ29 VSS_33 70 DDRA_DQ28 DDRA_DQ41 195 VSS_66 DQ41 196 DQ20 DDRA_DQ16
    DDRA_DQ29 71 VSS_34 DQ24 72 197 DQ40 VSS_67 198 DDRA_DQS#5 DQ21 DDRA_DQ17
    73 DQ25 VSS_35 74 DDRA_DQS#3 DDRA_DM5 199 VSS_68 DQS5_c 200 DDRA_DQS5
    DDRA_DM3 VSS_36 DQS3_c DDRA_DQS3 DM5_n/DBl5_n/NC DQS5_t DQ22 DDRA_DQ23
    75 76 201 202
    77 DM3_n/DBl3_n/NC DQS3_t 78 DDRA_DQ46 203 VSS_69 VSS_70 204 DDRA_DQ42 DQ23 DDRA_DQ18
    DDRA_DQ30 79 VSS_37 VSS_38 80 DDRA_DQ26 205 DQ46 DQ47 206 DQS#2 DDRA_DQS#2
    81 DQ30 DQ31 82 DDRA_DQ47 207 VSS_71 VSS_72 208 DDRA_DQ43 DQS2 DDRA_DQS2
    DDRA_DQ31 83 VSS_39 VSS_40 84 DDRA_DQ27 209 DQ42 DQ43 210
    C DQ26 DQ27 VSS_73 VSS_74 C
    85 86 DDRA_DQ52 211 212 DDRA_DQ53
    VSS_41 VSS_42 DQ52 DQ53
    DQ24 DDRA_DQ28
    87 88 213 214 DQ25 DDRA_DQ29
    89 CB5/NC CB4/NC 90 DDRA_DQ49 215 VSS_75 VSS_76 216 DDRA_DQ48
    +1.2V +1.2V 91 VSS_43 VSS_44 92 +1.2V 217 DQ49 DQ48 218 DQ26 DDRA_DQ31
    93 CB1/NC CB0/NC 94 DDRA_DQS#6 219 VSS_77 VSS_78 220 DDRA_DM6 DQ27 DDRA_DQ27

    Vinafix.com
    RD273 1 @ 2 240_0402_1% 95 VSS_45 VSS_46 96 DDRA_DQS6 221 DQS6_c DM6_n/DBl6_n/NC 222 DQ28 DDRA_DQ24
    RD274 1 @ 2 240_0402_1% 97 DQS8_c DM8_n/DBI8_n/NC 98 223 DQS6_t VSS_79 224 DDRA_DQ54 DQ29 DDRA_DQ25
    99 DQS8_t VSS_47 100 DDRA_DQ50 225 VSS_80 DQ54 226
    VSS_48 CB6/NC DQ55 VSS_81 DDRA_DQ51
    DQ30 DDRA_DQ30
    101 102 227 228
    103 CB2/NC VSS_49 104 for MEM_MB_RST# overshoot issue DDRA_DQ55 229 VSS_82 DQ50 230
    DQ31 DDRA_DQ26
    105 VSS_50 CB7/NC 106 231 DQ51 VSS_83 232 DDRA_DQ56 DQS#3 DDRA_DQS#3
    107 CB3/NC VSS_51 108 MEM_MA_RST# DDRA_DQ60 233 VSS_84 DQ60 234 DQS3 DDRA_DQS3
    DDRA_CKE0 109 VSS_52 RESET_n 110 DDRA_CKE1 MEM_MA_RST# 5 235 DQ61 VSS_85 236 DDRA_DQ61
    5 DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 5 DDRA_DQ57 VSS_86 DQ57
    111 112 237 238 DQ32 DDRA_DQ33

    0.1U_0201_6.3V6-K
    DDRA_BG1 113 VDD_1 VDD_2 114 DDRA_ACT# 239 DQ56 VSS_87 240 DDRA_DQS#7
    5 DDRA_BG1 DDRA_BG0 BG1 ACT_n DDRA_ALERT# DDRA_ACT# 5 1 DDRA_DM7 VSS_88 DQS7_c DDRA_DQS7 DQ33 DDRA_DQ37
    115 116 241 242
    5 DDRA_BG0
    117 BG0 ALERT_n 118
    DDRA_ALERT# 5
    243 DM7_n/DBl7_n/NC DQS7_t 244 DQ34 DDRA_DQ34
    DDRA_MA12 119 VDD_3 VDD_4 120 DDRA_MA11 DDRA_DQ63 245 VSS_89 VSS_90 246 DDRA_DQ58 DQ35 DDRA_DQ38
    CD120
    DDRA_MA9 121 A12 A11 122 DDRA_MA7 2 247 DQ62 DQ63 248 DQ36 DDRA_DQ32
    123 A9 A7 124 @ DDRA_DQ62 249 VSS_91 VSS_92 250 DDRA_DQ59 DQ37 DDRA_DQ36
    DDRA_MA8 125 VDD_5 VDD_6 126 DDRA_MA5 251 DQ58 DQ59 252
    DDRA_MA6 A8 A5 DDRA_MA4 +VDDSPD APU_SMB_CLK VSS_93 VSS_94 APU_SMB_DATA
    DQ38 DDRA_DQ35
    127 128 253 254
    129 A6 A4 130 7,35 APU_SMB_CLK 255 SCL SDA 256 DDRA0_SA0 APU_SMB_DATA 7,35 DQ39 DDRA_DQ39
    VDD_7 VDD_8 257 VDDSPD SA0 258 DQS#4 DDRA_DQS#4
    +2.5V VPP_1 Vtt DDRA0_SA1 +0.6VS DQS4 DDRA_DQS4
    1 1 259 260
    CD28 CD29 VPP_2 SA1
    1
    ARGOS_D4AS0-26001-1P60 1U_0402_6.3V6K 0.1U_0201_6.3V6-K CD121 261 262 DQ40 DDRA_DQ44
    22P_0402_50V8-J GND_1 GND_2
    ME@ 2 2 DQ41 DDRA_DQ40
    RF RF_NS@ ARGOS_D4AS0-26001-1P60
    2 DQ42 DDRA_DQ47
    ME@ DQ43 DDRA_DQ43
    DQ44 DDRA_DQ41
    DQ45 DDRA_DQ45
    +3VS +VDDSPD
    DQ46 DDRA_DQ46
    1 2 0_0402_5%
    DQ47 DDRA_DQ42
    RD271 @
    +2.5VS DQS#5 DDRA_DQS#5
    B B
    +1.2V DQS5 DDRA_DQS5
    +1.2V RD272 1 @ 2 0_0402_5%
    +2.5V +2.5VS DQ48 DDRA_DQ48
    1

    DQ49 DDRA_DQ49
    1

    RD10 3 1

    D
    RD258 +VREF_CA QD1
    DQ50 DDRA_DQ55
    1K_0402_1%
    1K_0402_1% LP2301ALT1G_SOT23-3 DQ51 DDRA_DQ50
    DQ52 DDRA_DQ52
    15mil Layout Note: Place near JDDR1

    G
    2

    2
    @
    @
    DQ53 DDRA_DQ53
    2

    DQ54 DDRA_DQ54
    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    DDRA_ALERT#
    2

    1000P_0201_50V7-K

    27,41 SUSP DQ55 DDRA_DQ51


    RD11 1 1 1
    1K_0402_1% +0.6VS +1.2V DQS#6 DDRA_DQS#6
    DQS6 DDRA_DQS6
    follow CRB 1pcs 4.7uf + 1pcs 0.1uf follow CRB 6pcs 0.1uf
    CD262

    CD116

    CD117
    1

    2 2 2 DQ56 DDRA_DQ60

    180P_0402_50V8-J
    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    27P 25V J NPO 0201

    0.1U_0201_6.3V6-K

    27P 25V J NPO 0201

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K
    DQ57 DDRA_DQ56
    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    4.7U_0402_6.3V6M

    1 1 1 1 1 1 1 1 1 1 1 1 1 DQ58 DDRA_DQ63
    1 1 1 1 CD16 CD17 CD18 CD20 CD21 CD22 CD23 CD58 CD59 CD60 CD61 CD62 CC211
    CD249 CD251 CD250 CD248 @ EMC@ @ EMC@ @ @ DQ59 DDRA_DQ59
    @ @ DQ60 DDRA_DQ61
    2 2 2 2 2 2 2 2 2 2 2 2 2 DQ61 DDRA_DQ57
    2 2 2 2
    DQ62 DDRA_DQ58
    DQ63 DDRA_DQ62
    +3VS +3VS +3VS DQS#7 DDRA_DQS#7
    DQS7 DDRA_DQS7
    1

    RD26 RD269 RD270 +2.5V +1.2V

    10K_0402_5% 10K_0402_5% 10K_0402_5% follow CRB 1pcs 1uf + 2pcs 0.1uf + 1pcs 180pf
    @ @ @
    2

    DDRA0_SA0 DDRA0_SA1 DDRA0_SA2


    10U_0603_6.3V6M

    10U_0603_6.3V6M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    1U_0402_6.3V6K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    180P_0402_50V8-J

    1 1 1 1 1 1 1 1 1
    1

    1 1 1 1 CD261 CD63 CD66 CD67 CD19 CD260 CD12 CD348 CD349


    A RD268 RD28 RD29 CD122 CD123 CD124 CC206 @ @ 22P_0402_50V8-J 22P_0402_50V8-J 22P_0402_50V8-J 22P_0402_50V8-J 22P_0402_50V8-J A
    0_0402_5% 0_0402_5% 0_0402_5% RF@ RF@ RF@ RF_NS@ RF_NS@
    2 2 2 2 2 2 2 2 2
    @ @ @ 2 2 2 2
    RF
    2

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/15 Deciphered Date 2013/08/15 DDRIV SO-DIMM A
    SPD Address = A2H THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Custom
    330ARR 1.0

    Date: Friday, March 23, 2018 Sheet 14 of 52


    5 4 3 2 1
    5 4 3 2 1

    DDRB_DQ[0..63]
    DDRB_DQ[0..63] 5
    DDRB_DQS[0..7]
    DDRB_DQS[0..7] 5
    DDRB_DQS#[0..7]
    UD1 UD2 DDRB_DQS#[0..7] 5
    DDRB_MA[0..13]
    DDRB_MA0 DDRB_DQ3 DDRB_MA0 DDRB_DQ19 DDRB_MA[0..13] 5
    P3 G2 P3 G2 DDRB_DM[0..7]
    DDRB_MA1 P7 A0 DQ0 F7 DDRB_DQ7 DDRB_MA1 P7 A0 DQ0 F7 DDRB_DQ23
    DDRB_MA2 A1 DQ1 DDRB_DQ2 DDRB_MA2 A1 DQ1 DDRB_DQ22 DDRB_DM[0..7] 5
    R3 H3 R3 H3
    DDRB_MA3 N7 A2 DQ2 H7 DDRB_DQ0 DDRB_MA3 N7 A2 DQ2 H7 DDRB_DQ17
    DDRB_MA4 N3 A3 DQ3 H2 DDRB_DQ6 DDRB_MA4 N3 A3 DQ3 H2 DDRB_DQ18
    DDRB_MA5 P8 A4 DQ4 H8 DDRB_DQ5 DDRB_MA5 P8 A4 DQ4 H8 DDRB_DQ21
    DDRB_MA6 P2 A5 DQ5 J3 DDRB_DQ1 DDRB_MA6 P2 A5 DQ5 J3 DDRB_DQ20
    DDRB_MA7
    DDRB_MA8
    R8
    R2
    A6
    A7
    DQ6
    DQ7
    J7
    A3
    DDRB_DQ4
    DDRB_DQ11
    DDRB_MA7
    DDRB_MA8
    R8
    R2
    A6
    A7
    DQ6
    DQ7
    J7
    A3
    DDRB_DQ16
    DDRB_DQ27 CD163 change from K to J +1.2V
    DDRB_MA9 R7 A8 DQ8 B8 DDRB_DQ8 DDRB_MA9 R7 A8 DQ8 B8 DDRB_DQ29
    DDRB_MA10 M3 A9 DQ9 C3 DDRB_DQ15 DDRB_MA10 M3 A9 DQ9 C3 DDRB_DQ31
    DRAM@
    DDRB_MA11 T2 A10/AP DQ10 C7 DDRB_DQ9 DDRB_MA11 T2 A10/AP DQ10 C7 DDRB_DQ25 DDRB_CLK0# 1 DRAM@ 2 1 2
    RD122 39_0402_5% CD163 0.1U_0402_10V7K
    DDRB_MA12 M7 A11 DQ11 C2 DDRB_DQ10 DDRB_MA12 M7 A11 DQ11 C2 DDRB_DQ26 DDRB_CLK0 1 DRAM@ 2
    RD123 39_0402_5%
    DDRB_MA13 T8 A12/BC_N DQ12 C8 DDRB_DQ13 DDRB_MA13 T8 A12/BC_N DQ12 C8 DDRB_DQ28
    D D
    A13 DQ13 D3 DDRB_DQ14 A13 DQ13 D3 DDRB_DQ30

    5 DDRB_MA14_W E#
    DDRB_MA14_W E#
    DDRB_MA15_CAS#
    L2
    M8 WE_N/A14
    DQ14
    DQ15
    D7 DDRB_DQ12 DDRB_MA14_W E#
    DDRB_MA15_CAS#
    L2
    M8 WE_N/A14
    DQ14
    DQ15
    D7 DDRB_DQ24
    2/22: change to K back for materil stock risk, and this change +0.6VS

    has conf i r mt o A MD
    5 DDRB_MA15_CAS# DDRB_MA16_RAS# CAS_N/A15 +1.2V DDRB_MA16_RAS# CAS_N/A15 +1.2V
    L8 L8
    5 DDRB_MA16_RAS# RAS_N/A16 RAS_N/A16
    D1 D1
    DDRB_CLK0# K8 VDD1 J1 DDRB_CLK0# K8 VDD1 J1 DDRB_MA0 1 2
    5 DDRB_CLK0# RD148 DRAM@ 39_0402_5%
    DDRB_CLK0 K7 CK_C VDD2 L1 DDRB_CLK0 K7 CK_C VDD2 L1 DDRB_MA1 1 2
    5 DDRB_CLK0 RD149 DRAM@ 39_0402_5%
    CK_T VDD3 R1 CK_T VDD3 R1 DDRB_MA2 1 2
    RD124 DRAM@ 39_0402_5%
    DDRB_CKE0 K2 VDD4 B3 DDRB_CKE0 K2 VDD4 B3 DDRB_MA3 1 2
    5 DDRB_CKE0 RD125 DRAM@ 39_0402_5%
    CKE VDD5 G7 CKE VDD5 G7 DDRB_MA4 RD126 1 DRAM@ 2 39_0402_5%
    DDRB_DQS#0 F3 VDD6 B9 DDRB_DQS#2 F3 VDD6 B9 DDRB_MA5 1 2
    RD127 DRAM@ 39_0402_5%
    DDRB_DQS0 G3 LDQS_C VDD7 J9 DDRB_DQS2 G3 LDQS_C VDD7 J9 DDRB_MA6 1 2
    RD128 DRAM@ 39_0402_5%
    DDRB_DQS#1 A7 LDQS_T VDD8 L9 DDRB_DQS#3 A7 LDQS_T VDD8 L9 DDRB_MA7 1 2
    RD129 DRAM@ 39_0402_5%
    DDRB_DQS1 B7 UDQS_C VDD9 T9 DDRB_DQS3 B7 UDQS_C VDD9 T9 DDRB_MA8 1 2
    RD130 DRAM@ 39_0402_5%
    UDQS_T VDD10 UDQS_T VDD10 DDRB_MA9 RD131 1 DRAM@ 2 39_0402_5%
    DDRB_DM1 E2 A1 DDRB_DM3 E2 A1 DDRB_MA10 1 2
    RD132 DRAM@ 39_0402_5%
    DDRB_DM0 E7 NF/UDM_N/UDBI_N VDDQ1 C1 DDRB_DM2 E7 NF/UDM_N/UDBI_N VDDQ1 C1 DDRB_MA11 1 2
    RD133 DRAM@ 39_0402_5%
    NF/LDM_N/LDBI_N VDDQ2 G1 NF/LDM_N/LDBI_N VDDQ2 G1 DDRB_MA12 1 2
    RD134 DRAM@ 39_0402_5%
    DDRB_BA0 N2 VDDQ3 F2 DDRB_BA0 N2 VDDQ3 F2 DDRB_MA13 1 2
    5 DDRB_BA0 RD135 DRAM@ 39_0402_5%
    DDRB_BA1 BA0 VDDQ4 DDRB_BA1 BA0 VDDQ4
    RF 5 DDRB_BA1 N8
    BA1 VDDQ5
    J2 N8
    BA1 VDDQ5
    J2
    DDRB_MA14_W E#
    F8 F8 RD138 1 DRAM@ 2 39_0402_5%
    DDRB_ACT# L3 VDDQ6 J8 DDRB_ACT# L3 VDDQ6 J8 DDRB_MA15_CAS# 1 DRAM@ 2
    5 DDRB_ACT# RD139 39_0402_5%
    DDRB_CS0# L7 ACT_N VDDQ7 A9 DDRB_CS0# L7 ACT_N VDDQ7 A9 DDRB_MA16_RAS# 1 DRAM@ 2
    RD140 39_0402_5%
    5 DDRB_CS0# DDRB_ALERT# CS_N VDDQ8 DDRB_ALERT# CS_N VDDQ8
    P9 D9 P9 D9
    5 DDRB_ALERT# ALERT_N VDDQ9 +2.5V ALERT_N VDDQ9 +2.5V DDRB_ACT#
    G9 G9 RD144 1 DRAM@ 2 39_0402_5%
    5 DDRB_BG0
    DDRB_BG0 M2 VDDQ10 DDRB_BG0 M2 VDDQ10
    DDRB_ODT0
    Swap Table
    BG0 B1 BG0 B1 RD147 1 DRAM@ 2 39_0402_5%
    DDRB_ODT0 K3 VPP1 R9 DDRB_ODT0 K3 VPP1 R9 DDRB_CS0# 1 DRAM@ 2
    RD145 39_0402_5% Pin Name Net Name
    5 DDRB_ODT0 ODT VPP2 +VREF_CA ODT VPP2 +VREF_CA DDRB_CKE0
    RD141 1 DRAM@ 2 39_0402_5%
    DDRB_PAR T3 M1 DDRB_PAR T3 M1
    5 DDRB_PAR PAR VREFCA PAR VREFCA
    DQ0 DDRB_DQ3

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K
    1 1 1 1 DQ1 DDRB_DQ6
    10K_0402_5%1 DRAM@ 2 RD251 TEN1 N9 E1 10K_0402_5% 1 DRAM@ 2 RD253 TEN2 N9 E1 DQ2 DDRB_DQ2

    CD202

    CD203

    CD232

    CD233
    TEN VSS1 TEN VSS1

    1000P_0201_50V7-K

    1000P_0201_50V7-K
    K1 K1

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K
    MEM_MB_RST# VSS2 1 1 MEM_MB_RST# VSS2 1 1 DDRB_BA0 DQ3 DDRB_DQ0
    P1 N1 P1 N1 RD142 1 DRAM@ 2 39_0402_5%

    CD189

    CD188

    CD230

    CD231
    5 MEM_MB_RST# RESET_N VSS3 2 2 RESET_N VSS3 DDRB_BA1 DQ4 DDRB_DQ7
    T1 DRAM@ DRAM@ T1 DRAM@2 2 RD143 1 DRAM@ 2 39_0402_5%
    F1 VSS4 B2 F1 VSS4 B2 DQ5 DDRB_DQ5
    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K
    DRAM@
    H1 VSSQ1 VSS5 G8 DRAM@ 2 DRAM@2 H1 VSSQ1 VSS5 G8 2 2 DQ6 DDRB_DQ4
    1 VSSQ2 VSS6 1 VSSQ2 VSS6
    A2 E9 A2 E9 DRAM@ DRAM@ DQ7 DDRB_DQ1
    CD132

    CD160
    D2 VSSQ3 VSS7 K9 D2 VSSQ3 VSS7 K9 DDRB_BG0 1 DRAM@ 2
    RD146 39_0402_5% DQS#0 DDRB_DQS#0
    E3 VSSQ4 VSS8 M9 E3 VSSQ4 VSS8 M9 DDRB_PAR RD275 1 DRAM@ 2 39_0402_5%
    2 VSSQ5 VSS9 2 VSSQ5 VSS9 DQS0 DDRB_DQS0
    @ A8 @ A8
    D8 VSSQ6 T7 D8 VSSQ6 T7 UD1
    E8 VSSQ7 NC E8 VSSQ7 NC
    VSSQ8 VSSQ8 +1.2V
    DQ8 DDRB_DQ9
    C9 C9 DQ9 DDRB_DQ11
    C
    H9 VSSQ9 H9 VSSQ9 C
    VSSQ10 VSSQ10 DQ10 DDRB_DQ12
    F9 F9 DDRB_ALERT#
    RD86 1 DRAM@ 2 1K_0402_1%
    DQ11 DDRB_DQ8

    Vinafix.com
    ZQ ZQ +1.2V DQ12 DDRB_DQ15
    DQ13 DDRB_DQ13
    1

    1
    RD116 RD117 DQ14 DDRB_DQ14
    MT40A512M16HA083EA_FBGA96 MT40A512M16HA083EA_FBGA96 DQ15 DDRB_DQ10
    Layout Note: Place near DRAM
    240_0402_1% 240_0402_1%
    @ DRAM@ @ DQS#1 DDRB_DQS#1
    DQS1 DDRB_DQS1
    2

    2
    DRAM@
    CD266 1 CD267 1 CD268 1 CD269 1 CD270 1 CD271 1 CD272 1 CD273 1 CD274 1 CD275 1 CD276 1 CD277 1 3A@1.5V UD1

    47P_0201_25V8-J

    27P 25V J NPO 0201

    27P 25V J NPO 0201

    27P 25V J NPO 0201

    27P 25V J NPO 0201

    27P 25V J NPO 0201

    27P 25V J NPO 0201

    47P_0201_25V8-J

    27P 25V J NPO 0201

    47P_0201_25V8-J

    47P_0201_25V8-J

    27P 25V J NPO 0201


    +1.2V

    EMC_NS@

    EMC@

    EMC@

    EMC@

    EMC@

    EMC@

    EMC@

    EMC_NS@

    EMC@

    EMC_NS@

    EMC_NS@

    EMC@
    DQ16 DDRB_DQ7
    2 2 2 2 2 2 2 2 2 2 2 2
    DQ17 DDRB_DQ3
    follow SCL 20pcs 0.22uf DQ18 DDRB_DQ4
    DQ19 DDRB_DQ0
    DQ20 DDRB_DQ6

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K
    1 1 1 1 1 1 1 1 1 1
    DQ21 DDRB_DQ5
    CD154 CD155 CD142 CD127 CD141 CD152 CD150 CD158 CD143 CD137 DQ22 DDRB_DQ2
    DQ23 DDRB_DQ1
    2 2 2 2 2 2 2 2 2 2
    DQS#2 DDRB_DQS#2
    DQS2 DDRB_DQS2
    UD3
    UD4
    UD2
    DDRB_MA0 DDRB_DQ39 DQ24 DDRB_DQ15
    P3 G2 DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DQ25 DDRB_DQ11
    DDRB_MA1 P7 A0 DQ0 F7 DDRB_DQ35 DDRB_MA0 P3 G2 DDRB_DQ59
    DDRB_MA2 A1 DQ1 DDRB_DQ34 DDRB_MA1 A0 DQ0 DDRB_DQ57 3A@1.5V DQ26 DDRB_DQ12
    R3 H3 P7 F7
    DDRB_MA3 N7 A2 DQ2 H7 DDRB_DQ37 DDRB_MA2 R3 A1 DQ1 H3 DDRB_DQ58 DQ27 DDRB_DQ8
    DDRB_MA4 N3 A3 DQ3 H2 DDRB_DQ38 DDRB_MA3 N7 A2 DQ2 H7 DDRB_DQ61 +1.2V DQ28 DDRB_DQ13
    DDRB_MA5 P8 A4 DQ4 H8 DDRB_DQ36 DDRB_MA4 N3 A3 DQ3 H2 DDRB_DQ63 DQ29 DDRB_DQ9
    DDRB_MA6 P2 A5 DQ5 J3 DDRB_DQ32 DDRB_MA5 P8 A4 DQ4 H8 DDRB_DQ56 DQ30 DDRB_DQ14
    DDRB_MA7 A6 DQ6 DDRB_DQ33 DDRB_MA6 A5 DQ5 DDRB_DQ62
    DDRB_MA8
    R8 J7
    DDRB_DQ47 DDRB_MA7
    P2 J3
    DDRB_DQ60
    DQ31 DDRB_DQ10
    R2 A7 DQ7 A3 R8 A6 DQ6 J7
    DDRB_MA9 A8 DQ8 DDRB_DQ40 DDRB_MA8 A7 DQ7 DDRB_DQ50 DQS#3 DDRB_DQS#3
    R7 B8 R2 A3

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K
    DDRB_MA10 A9 DQ9 DDRB_DQ46 DDRB_MA9 A8 DQ8 DDRB_DQ52 DQS3 DDRB_DQS3
    M3 C3 R7 B8
    DDRB_MA11
    DDRB_MA12
    T2 A10/AP DQ10 C7 DDRB_DQ44
    DDRB_DQ42
    DDRB_MA10
    DDRB_MA11
    M3 A9 DQ9 C3 DDRB_DQ55
    DDRB_DQ48
    CD174
    1
    CD173
    1
    CD169
    1
    CD165
    1
    CD167
    1
    CD172
    1
    CD171
    1
    CD175
    1
    CD168
    1
    CD166
    1 UD2
    M7 A11 DQ11 C2 T2 A10/AP DQ10 C7
    DDRB_MA13 A12/BC_N DQ12 DDRB_DQ45 DDRB_MA12 A11 DQ11 DDRB_DQ54 DQ32 DDRB_DQ6
    T8 C8 M7 C2 DQ33 DDRB_DQ7
    A13 DQ13 D3 DDRB_DQ43 DDRB_MA13 T8 A12/BC_N DQ12 C8 DDRB_DQ49 2 2 2 2 2 2 2 2 2 2
    DDRB_MA14_W E# L2 DQ14 D7 DDRB_DQ41 A13 DQ13 D3 DDRB_DQ51 DQ34 DDRB_DQ2
    DDRB_MA15_CAS# M8 WE_N/A14 DQ15 DDRB_MA14_W E# L2 DQ14 D7 DDRB_DQ53 DQ35 DDRB_DQ1
    DDRB_MA16_RAS# L8 CAS_N/A15 +1.2V DDRB_MA15_CAS# M8 WE_N/A14 DQ15 DQ36 DDRB_DQ5
    RAS_N/A16 D1 DDRB_MA16_RAS# L8 CAS_N/A15 +1.2V DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DQ37 DDRB_DQ3
    DDRB_CLK0# K8 VDD1 J1 RAS_N/A16 D1 DQ38 DDRB_DQ4
    B B
    DDRB_CLK0 CK_C VDD2 DDRB_CLK0# VDD1 +1.2V
    K7 L1
    DDRB_CLK0
    K8 J1 DQ39 DDRB_DQ0
    CK_T VDD3 R1 K7 CK_C VDD2 L1 +1.2V
    DDRB_CKE0 VDD4 CK_T VDD3
    DQS#4 DDRB_DQS#4
    K2 B3 R1 DQS4 DDRB_DQS4
    CKE VDD5 G7 DDRB_CKE0 K2 VDD4 B3
    DDRB_DQS#4
    DDRB_DQS4
    F3 VDD6 B9
    DDRB_DQS#7
    CKE VDD5 G7 UD3
    G3 LDQS_C VDD7 J9 F3 VDD6 B9

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K
    DDRB_DQS#5 LDQS_T VDD8 DDRB_DQS7 LDQS_C VDD7
    DQ40 DDRB_DQ9
    A7 L9 G3 J9 1 1 1 1 DQ41 DDRB_DQ15
    DDRB_DQS5 B7 UDQS_C VDD9 T9 DDRB_DQS#6 A7 LDQS_T VDD8 L9 CD215 CD218 CD212 CD211 1 1 DQ42 DDRB_DQ12
    UDQS_T VDD10 DDRB_DQS6 B7 UDQS_C VDD9 T9 @ @ @ @ CD133 CD153
    DDRB_DM5 E2 A1 UDQS_T VDD10 22P_0402_50V8-J 22P_0402_50V8-J
    DQ43 DDRB_DQ14
    DDRB_DM4 E7 NF/UDM_N/UDBI_N VDDQ1 C1 DDRB_DM6 E2 A1 2 2 2 2 RF_NS@ RF_NS@ DQ44 DDRB_DQ11
    NF/LDM_N/LDBI_N VDDQ2 G1 DDRB_DM7 E7 NF/UDM_N/UDBI_N VDDQ1 C1 2 2 DQ45 DDRB_DQ13
    DDRB_BA0 N2 VDDQ3 F2 NF/LDM_N/LDBI_N VDDQ2 G1 DQ46 DDRB_DQ10
    DDRB_BA1 BA0 VDDQ4 DDRB_BA0 VDDQ3
    N8 J2
    DDRB_BA1
    N2 F2 DQ47 DDRB_DQ8
    BA1 VDDQ5 F8 N8 BA0 VDDQ4 J2
    DDRB_ACT# VDDQ6 BA1 VDDQ5
    DQS#5 DDRB_DQS#5
    L3 J8 F8 DQS5 DDRB_DQS5
    DDRB_CS0# L7 ACT_N VDDQ7 A9 DDRB_ACT# L3 VDDQ6 J8
    DDRB_ALERT# P9 CS_N VDDQ8 D9 DDRB_CS0#
    DDRB_ALERT#
    L7 ACT_N VDDQ7 A9 UD3
    ALERT_N VDDQ9 G9 +2.5V P9 CS_N VDDQ8 D9 +0.6VS
    DDRB_BG0 VDDQ10 ALERT_N VDDQ9 +2.5V
    DQ48 DDRB_DQ11
    M2 G9 DQ49 DDRB_DQ13
    BG0 DDRB_BG0 VDDQ10
    DDRB_ODT0 K3 VPP1
    B1
    R9
    M2
    BG0 B1 follow SCL 10pcs 0.22uf DQ50 DDRB_DQ8
    ODT VPP2 +VREF_CA DDRB_ODT0 K3 VPP1 R9 DQ51 DDRB_DQ14
    DDRB_PAR T3 M1 ODT VPP2 +VREF_CA DQ52 DDRB_DQ9

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K
    PAR VREFCA DDRB_PAR DQ53 DDRB_DQ15
    1U_0402_6.3V6K

    T3 M1
    0.1U_0201_6.3V6-K

    1 1 PAR VREFCA 1 1 1 1 1 1 1 1 1 1
    DQ54 DDRB_DQ12

    1U_0402_6.3V6K
    0.1U_0201_6.3V6-K
    10K_0402_5%1 DRAM@ 2 RD255 TEN3 N9 E1 1 1 CD146 CD148 CD139 CD138 CD201 CD245 CD246 CD244 CD243 CD242
    CD236

    CD237

    TEN VSS1
    1000P_0201_50V7-K

    K1 10K_0402_5%1 DRAM@ 2 RD257 N9 E1 DQ55 DDRB_DQ10


    0.1U_0201_6.3V6-K

    1 1 TEN4

    CD240

    CD241
    MEM_MB_RST# VSS2 TEN VSS1

    1000P_0201_50V7-K
    P1 N1 K1

    0.1U_0201_6.3V6-K
    1 1 DQS#6 DDRB_DQS#7
    CD234

    CD235

    RESET_N VSS3 T1 2 2 MEM_MB_RST# P1 VSS2 N1 2 2 2 2 2 2 2 2 2 2


    DQS6 DDRB_DQS7

    CD238

    CD239
    F1 VSS4 B2 DRAM@ RESET_N VSS3 T1 2 DRAM@ 2
    0.1U_0201_6.3V6-K

    VSSQ1 VSS5 2 2 DRAM@ VSS4 DRAM@ UD4


    0.1U_0201_6.3V6-K

    1 H1 G8 F1 B2
    A2 VSSQ2 VSS6 E9 H1 VSSQ1 VSS5 G8 2 2
    1 DQ56 DDRB_DQ5
    CD161

    D2 VSSQ3 VSS7 K9 DRAM@ DRAM@ A2 VSSQ2 VSS6 E9 DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DQ57 DDRB_DQ1
    CD162

    E3 VSSQ4 VSS8 M9 D2 VSSQ3 VSS7 K9


    @ 2 A8 VSSQ5 VSS9 E3 VSSQ4 VSS8 M9
    DQ58 DDRB_DQ2
    D8 VSSQ6 T7 @ 2 A8 VSSQ5 VSS9 +0.6VS +0.6VS DQ59 DDRB_DQ0
    E8 VSSQ7 NC D8 VSSQ6 T7 +2.5V DQ60 DDRB_DQ7
    C9 VSSQ8 E8 VSSQ7 NC DQ61 DDRB_DQ3
    H9 VSSQ9 C9 VSSQ8 DQ62 DDRB_DQ6
    VSSQ10 H9 VSSQ9 DQ63 DDRB_DQ4
    VSSQ10

    180P_0402_50V8-J
    F9

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K
    ZQ 1 1 DQS#7 DDRB_DQS#6
    F9 1 1 1 1 CD265 DQS7 DDRB_DQS6

    CC205
    ZQ
    1

    CD259 CD252 CD263 CD264 22P_0402_50V8-J


    UD4
    1

    RD118 @ @ 22P_0402_50V8-J 22P_0402_50V8-J RF_NS@


    A MT40A512M16HA083EA_FBGA96
    240_0402_1% RD119 RF_NS@ RF_NS@ 2 2 A
    @ MT40A512M16HA083EA_FBGA96 2 2 2 2
    240_0402_1%
    DRAM@ @
    2

    DRAM@ DRAM@
    2

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/15 Deciphered Date 2013/08/15 DDRVI MD
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 330ARR
    Date : Friday, March 23, 2018 Sheet 15 of 52
    5 4 3 2 1
    5 4 3 2 1

    D D

    Power-Up/Down Sequence VRAM ID config


    "Topaz" has the following requirements with regards to power-supply sequencing to
    avoid damaging the ASIC: BOARD_CONFIG[2:0] VRAM ID
    GPU Memory Type Stuff R
    DBGDATA_[5..3] PS_3[3:1]
    All the ASIC supplies must reach their respective nominal voltages within 20 ms
    of the start of the ramp-up sequence, though a shorter ramp-up duration is Samsung
    preferred. The maximum slew rate on all rails is 50 mV/μ s. K4G80325FB-HC28 6.0Gbps@1.35V
    000 NA RV1307 RV1304 RV1298
    It is recommended that the 3.3-V rail ramp up first. 8Gb GDDR5
    The 3.3-V, 1.8-V, and 0.95-V rails must reach their ready state at least 10 μ s Hynix
    before VDDC, VDDCI, and VMEMIO start to ramp up. R17M-P1-50 256M x 32 001 NA RV1307 RV1304 RV1297
    H5GC8H24MJR-R0C 6.0Gbps@1.35V
    The power rails that are shared with other components on the system should be (UV3/UV4)
    gated for the dGPU so that when the dGPU is powered down (for example
    AMD PowerXpress idle state), all the power rails are removed from the dGPU. Micron
    010 NA RV1307 RV1303 RV1298
    The gate circuits must meet the slew rate requirement (such as ≤ 50 mV/μ s). MT51J256M32HF-70:A 6.0Gbps@1.35V
    For power down, reversing the ramp-up sequence is recommended.
    Samsung
    NA 000 RV1415(NC) RV1418(4.75K)
    K4G80325FB-HC28 6.0Gbps@1.35V
    C C
    8Gb GDDR5

    256M x 32 Hynix
    NA 001 RV1415(8.45K) RV1418(2K)

    Vinafix.com
    R18M-M2-60 H5GC8H24MJR-R0C 6.0Gbps@1.35V
    (UV3/UV4)
    Micron
    NA 010 RV1415(4.53K) RV1418(2K)
    MT51J256M32HF-70:A 6.0Gbps@1.35V

    0 ~ 20ms

    VDDR3(+3VGS)
    0 ~ 20ms

    VDD_CT(+1.8VGS)

    PCIE_VDDC(+0.95VGS)
    10us min.

    B VDDR1(+1.35VGS) B

    VDDC/VDDCI(+VGA_CORE) 100ms min.

    100us min.
    PERSTb(GPU_RST#)

    REFCLK(CLK_PCIE_VGA)

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2016/08/16 Deciphered Date 2017/08/15 VGA Notes List
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 330ARR
    Date: Friday, March 23, 2018 Sheet 16 of 52
    5 4 3 2 1
    5 4 3 2 1

    4 PCIE_CTX_C_GRX_P[0..7] PCIE_CRX_GTX_P[0..7] 4

    4 PCIE_CTX_C_GRX_N[0..7] PCIE_CRX_GTX_N[0..7] 4

    D D

    UV1B
    symbol2
    PCIE_CTX_C_GRX_P0 AT41 AV35 PCIE_CRX_C_GTX_P0 PX@ CV1 1 2 0.22U_0201_6.3V6-K PCIE_CRX_GTX_P0
    PCIE_CTX_C_GRX_N0 AT40 PCIE_RX0P PCIE_TX0P AU35 PCIE_CRX_C_GTX_N0 PX@ CV2 1 2 0.22U_0201_6.3V6-K PCIE_CRX_GTX_N0
    PCIE_RX0N PCIE_TX0N
    PCIE_CTX_C_GRX_P1 AR41 AU38 PCIE_CRX_C_GTX_P1 PX@ CV3 1 2 0.22U_0201_6.3V6-K PCIE_CRX_GTX_P1
    PCIE_CTX_C_GRX_N1 AR40 PCIE_RX1P PCIE_TX1P AU39 PCIE_CRX_C_GTX_N1 PX@ CV4 1 2 0.22U_0201_6.3V6-K PCIE_CRX_GTX_N1
    PCIE_RX1N PCIE_TX1N
    PCIE_CTX_C_GRX_P2 AP41 AR37 PCIE_CRX_C_GTX_P2 PX@ CV5 1 2 0.22U_0201_6.3V6-K PCIE_CRX_GTX_P2
    PCIE_CTX_C_GRX_N2 AP40 PCIE_RX2P PCIE_TX2P AR38 PCIE_CRX_C_GTX_N2 PX@ CV6 1 2 0.22U_0201_6.3V6-K PCIE_CRX_GTX_N2
    PCIE_RX2N PCIE_TX2N
    PCIE_CTX_C_GRX_P3 AM41 AN37 PCIE_CRX_C_GTX_P3 PX@ CV7 1 2 0.22U_0201_6.3V6-K PCIE_CRX_GTX_P3
    PCIE_CTX_C_GRX_N3 AM40 PCIE_RX3P PCIE_TX3P AN38 PCIE_CRX_C_GTX_N3 PX@ CV8 1 2 0.22U_0201_6.3V6-K PCIE_CRX_GTX_N3
    PCIE_RX3N PCIE_TX3N
    PCIE_CTX_C_GRX_P4 AL41 AL37 PCIE_CRX_C_GTX_P4 R5R7@CV141 1 2 0.22U_0201_6.3V6-K PCIE_CRX_GTX_P4
    PCIE_CTX_C_GRX_N4 AL40 PCIE_RX4P PCIE_TX4P AL38 PCIE_CRX_C_GTX_N4 R5R7@CV138 1 2 0.22U_0201_6.3V6-K PCIE_CRX_GTX_N4
    PCIE_RX4N PCIE_TX4N
    PCIE_CTX_C_GRX_P5 AK41 AJ37 PCIE_CRX_C_GTX_P5 R5R7@CV143 1 2 0.22U_0201_6.3V6-K PCIE_CRX_GTX_P5
    PCIE_CTX_C_GRX_N5 AK40 PCIE_RX5P PCIE_TX5P AJ38 PCIE_CRX_C_GTX_N5 R5R7@CV136 1 2 0.22U_0201_6.3V6-K PCIE_CRX_GTX_N5
    PCIE_RX5N PCIE_TX5N
    PCIE_CTX_C_GRX_P6 AJ41 AG37 PCIE_CRX_C_GTX_P6 R5R7@CV140 1 2 0.22U_0201_6.3V6-K PCIE_CRX_GTX_P6
    PCIE_CTX_C_GRX_N6 AJ40 PCIE_RX6P PCIE_TX6P AG38 PCIE_CRX_C_GTX_N6 R5R7@CV142 1 2 0.22U_0201_6.3V6-K PCIE_CRX_GTX_N6
    C PCIE_RX6N PCIE_TX6N C
    PCIE_CTX_C_GRX_P7 AH41 AE37 PCIE_CRX_C_GTX_P7 R5R7@CV137 1 2 0.22U_0201_6.3V6-K PCIE_CRX_GTX_P7
    PCIE_RX7P PCIE_TX7P

    Vinafix.com
    PCIE_CTX_C_GRX_N7 AH40 AE38 PCIE_CRX_C_GTX_N7 R5R7@CV139 1 2 0.22U_0201_6.3V6-K PCIE_CRX_GTX_N7
    PCIE_RX7N PCIE_TX7N

    CLK_PCIE_GPU AV33 AV41 GPU_RST#


    8 CLK_PCIE_GPU CLK_PCIE_GPU# PCIE_REFCLKP PERSTB GPU_RST# 18
    AU33
    8 CLK_PCIE_GPU# PCIE_REFCLKN AC41 PX_EN RV1226 1 @ 2 1K_0402_5%
    PX_EN
    PX_EN: On/off regulator control signal for BACO mode, internal pull down.
    High(3.3V)--switches the regulators off. (enter BACO mode)
    Low(0V)--switches the regulators on. (Default)
    Can be left unconnected if not used.
    +3VALW +3V_GATE
    AU41 PCIE_ZVSS RV1228 1 PX@ 2 200_0402_1%
    +3VGS RV1430 1 @ 2 0_0402_5% PCIE_ZVSS
    REV 0.91

    RV1429 1 @ 2 0_0402_5% 216-0905018-C3_FCBGA769


    @

    RV1236 1 @ 2 0_0402_5%

    B +3V_GATE B

    1
    CV122
    0.1U_0201_6.3V6-K
    @
    2
    5

    UV5 DV6
    GPU_RST# 2
    VCC

    PXS_RST# 1 1 VGA_PWROK
    8 PXS_RST# IN1 GPU_RST# VR_VGA_PWRGD VGA_PWROK 51
    4 3
    PLT_RST# 2 OUT 51 VR_VGA_PWRGD
    GND

    7,32,35 PLT_RST# IN2 LBAT54AWT1G_SOT323-3


    1

    PX@
    MC74VHC1G08DFT2G_SC70-5 RV1227
    3

    PX@ 100K_0402_5%
    PX@
    VR_VGA_PWRGD RV1404 1 @ 2 0_0402_5%
    DGPU_PWROK 8
    2

    Need confirm if can NC UV5/RV1227


    A and stuff RV1236--Brooks 0708 A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2016/08/16 Deciphered Date 2017/08/15 R17M-P1-50_PCIE
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    B
    330ARR 1.0

    Date: Friday, March 23, 2018 Sheet 17 of 52


    5 4 3 2 1
    5 4 3 2 1

    RECOMMENDED SETTINGS
    CONFIGURATION STRAPS R17M-P1-50 0 = PULL-DOWN TO GND
    1 = PULL-UP TO POWER
    Any external circuit using these pins must not conflict with the logic level X = DESIGN DEPENDENT
    +3VGS +3VGS required by the strap after power up until PCIe reset gets de-asserted. NA = NOT APPLICABLE
    UV1E
    Reserve for R18M-M2-60
    Recommended
    RV1251 1 @ 2 0_0402_5% +VDD_33 AM31 symbol5 W40 GPU_GPIO0 RV1424 1 R18@ 2 0_0402_5% GPU_VR_HOT# RV1247 1 @ 2 5.1K_0402_5% GPU_GPIO0 RV1248 1 @ 2 5.1K_0402_5% Strap Name Pin Name Description GPU Default
    VDD_33 GPIO_0 AA40 Settings
    GPIO_1 AA35 GPU_GPIO2 RV1281 1 @ 2 5.1K_0402_5% GPU_GPIO2 RV1282 1 @ 2 5.1K_0402_5% Controls the transmitter full/half swing mode.
    1 GPIO_2
    CV11 RB751V-40_SOD323-2 TX_HALF_SWING GPIO_0 0: The transmitter fullswing is enabled. 0 0 0
    1U_0402_6.3V6K DV1 2 1 PX@ 1: The transmitter halfswing is enabled. (Internal pulldown)
    GPU_GPIO5 VGA_AC_DET 39 GPU_GPIO5
    PX@ AA34 RV1246 1 PX@ 2 10K_0402_5% PCIe Gen3 capability. RECOMMENDED SETTINGS
    2 GPIO_5_REG_HOT_AC_BATT
    GPIO_6_TACH
    U35 GPU_GPIO6 RV1257 1 R17@ 2 0_0402_5%
    GPU_VR_HOT# 39,51
    RV1405 1 R17@ 2 10K_0402_5% GPU_GPIO6 BIF_GEN3_EN_A GPIO_2 1: PCIe Gen3 is supported.
    0: PCIe Gen3 is not supported.
    1 1 X CONFIGURATION STRAPS R18M-M2-60 0= DO NOT INSTALL RESISTOR
    1 = INSTALL 10K RESISTOR
    (Internal pull-up)
    AP25 GPU_GPIO8 RV1261 1 @ 2 33_0402_5% GPU_ROMSO RV1252 1 @ 2 5.1K_0402_5% GPU_GPIO8 RV1253 1 @ 2 5.1K_0402_5% 0: The CLKREQB power management
    ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE X = DESIGN DEPENDANT
    GPIO_8_ROMSO AM25 GPU_GPIO9 RV1264 1 @ 2 33_0402_5% GPU_ROMSI RV1254 1 @ 2 5.1K_0402_5% GPU_GPIO9 RV1255 1 @ 2 5.1K_0402_5% BIF_CLK_PM_EN GPIO_8 capability is disabled. 0 0 1 GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET NA = NOT APPLICABLE
    GPIO_9_ROMSI AM27 GPU_GPIO10 RV1265 1 @ 2 33_0402_5% GPU_ROMSCK _ROMSO 1: The CLKREQB power management (Internal pulldown)
    GPIO_10_ROMSCK W41 GPU_GPIO11 RV1270 1 @ 2 5.1K_0402_5% GPU_GPIO11 RV1271 1 @ 2 5.1K_0402_5% capability is enabled.
    GPIO_11 Y40 GPU_GPIO12 RV1272 1 @ 2 5.1K_0402_5% GPU_GPIO12 RV1273 1 @ 2 5.1K_0402_5%
    D
    GPIO_12 GPU_GPIO13 GPU_GPIO13 MLPS Bit Strap Name Description RECOMMENDED D
    Y41 RV1274 1 @ 2 5.1K_0402_5% RV1275 1 R17@ 2 5.1K_0402_5% Reserved GPIO_9 Reserved 0 0 Must default to 0 for SETTINGS
    GPIO_13 AU21 GPU_EDP_HPD GPU_EDP_HPD RV1312 1 R17@ 2 10K_0201_5% _ROMSI (Internal pulldown) production. PS_0[1] ROM_CONFIG[0] Define the ROM type when STRAP_BIOS_ROM_EN = 1,
    GPIO_14_HPD2 AA41 GPU_GPIO15 RV1287 1 @ 2 5.1K_0402_5% GPU_GPIO15 RV1288 1 @ 2 5.1K_0402_5% If BIOS_ROM_EN = 1, defines the ROM type. PS_0[2] ROM_CONFIG[1] Define the primary memory-aperture size when STRAP_BIOS_ROM_EN = 0.
    GPIO_15 U34 ROM_CONFIG GPIO_13 If BIOS_ROM_EN = 0, defines the primary 101 X PS_0[3] ROM_CONFIG[2] X
    GPIO_16_8P_DETECT R37 [2:0] GPIO_12 memory aperture size. 001 = 256MB (Internal pull-up 001 = 256MB
    GPIO_17_THERMAL_INT AV25 GPU_GPIO18 GPU_GPIO18 RV1316 1 R17@ 2 10K_0201_5% GPIO_11 /pull-down)
    GPIO_18_HPD3 R38 GPU_GPIO19 GPU_GPIO19 RV1419 1 PX@ 2 10K_0402_5% PS_0[4] N/A Reserved for internal use only. Must be 1 at reset. 1
    GPIO_19_CTF AB40 GPU_GPIO20 RV1283 1 R17@ 2 5.1K_0402_5% GPU_GPIO20 RV1284 1 @ 2 5.1K_0402_5% Reserved GPIO_15 Reserved 0 0 Must default to 0 for
    AC35 GPIO_20 AB41 GPU_GPIO21 1 TV57 PAD @ (Internal pulldown) production.
    AC34 SCL GPIO_21 AP27 GPU_GPIO22 RV1277 1 @ 2 33_0402_5% GPU_ROMCS# RV1258 1 @ 2 5.1K_0402_5% GPU_GPIO22 RV1259 1 R17@ 2 5.1K_0402_5% PCI Express transmitter de-emphasis enable PS_0[5] N/A Reserved 1
    SDA GPIO_22_ROMCSB W37 GPU_GPIO29 RV1279 1 R17@ 2 5.1K_0402_5% GPU_GPIO29 RV1280 1 @ 2 5.1K_0402_5% TX_DEEMPH_EN GPIO_20 0: Tx de-emphasis disabled. 1 0 1
    EC_SMB_CK3 RV1334 1 @ 2 0_0402_5% GPU_SMB_CLK AW40 GPIO_29 W38 1: Tx de-emphasis enabled. (Internal pulldown) 1 = PCIe GEN3 is supported.
    EC_SMB_DA3 RV1336 1 @ 2 0_0402_5% GPU_SMB_DATA AW41 SMBCLK GPIO_30 BA38 GENERICA 1 TV59 PAD @ Enable external BIOS ROM device. PS_1[1] STRAP_BIF_GEN3_EN_A 0 = PCIe GEN3 is not supported. 1= GEN3 is supported X
    SMBDAT GENERICA AV29 PS_1 BIOS_ROM_EN GPIO_22 0: Disable external BIOS ROM device. 0 1 X
    GENERICB AU31 PS_2 _ROMCSB 1: Enable external BIOS ROM device. (Internal pull-up) 0 = The CLKREQB power management capability is disabled
    GENERICC AV31 PS_3 0: VGA Controller capacity enabled. PS_1[2] STRAP_BIF_CLK_PM_EN 1 = The CLKREQB power management capability is enabled 0
    GENERICD AU25 GENERICE_HPD4 GENERICE_HPD4 RV1317 1 R17@ 2 10K_0201_5% BIF_VGA_DIS GPIO_29 1: The device will not be recognized as the 1 0 X
    RV1421 1 @ 2 0_0402_5% GPU_SVC_R AU17 GENERICE_HPD4 AV23 GENERICF_HPD5 GENERICF_HPD5 RV1318 1 R17@ 2 10K_0201_5% system's VGA controller(for headless designs) (Internal pulldown) PS_1[3] N/A Reserved for internal use only. Must be 0 at reset. 0
    51 GPU_SVC GPU_SVD_R GPIO_SVC GENERICF_HPD5 PS_0
    RV1422 1 @ 2 0_0402_5% AV17 AM29
    51 GPU_SVD GPU_SVT_R GPIO_SVD GENERICG
    RV1423 1 @ 2 0_0402_5% AR17 Special Usage [1] HS YNC Special usage 00 0 X STRAP_TX_CFG_DRV_ 0 = The transmitter half-swing is enabled
    51 GPU_SVT GPIO_SVT GPU_HDMI_HPD GPU_HDMI_HPD RV1309 1 R17@ Special Usage [0] VS YNC (Internal pulldown) FULL_SWING 1 = The transmitter full-swing is enabled
    AV21 2 10K_0201_5% PS_1[4] 1
    AN34 HPD1 +3VGS Determine the maximum number of digital
    AP31 DDCVGACLK display audio endpoints that will be
    DDCVGADATA Need confirm the BOM Structure --Brooks0727 AUD_PORT
    _CONN[2:0]
    DBGDATA_2
    DBGDATA_1 presented to the OS and user.
    0 = Tx deemphasis disabled.
    1 = Tx deemphasis enabled.
    PS_1[5] STRAP_TX_DEEMPH_EN 1= Enable X
    111: No usable endpoints

    2
    DBGDATA_0

    G
    QV2 110: One usable endpoint 0 X PS_2[1] N/A Reserved. 0
    +1.8VGS @ 101: Two usable endpoints (Internal pulldown)
    111
    100: Three usable endpoints
    011: Four usable endpoints PS_2[2] N/A Reserved. 0
    R17@ AV40 GPU_CLKREQ#_R 3 1 RV1302 1 @ 2 10K_0402_5% GPU_CLKREQ#_R RV1313 1 @ 2 10K_0402_5%
    TEST_PG CLKREQB GPU_WAKE# 1 GPU_CLKREQ# 8 010: Five usable endpoints
    RV1300 1 2 1K_0402_5% AY13 AU40

    D
    001: Six usable endpoints 0 = Disable the external BIOS ROM device.
    RV1301 1 2 1K_0402_5% TEST_PG_BACO BA13 TEST_PG WAKEB 2N7002KW_SOT323-3 PS_2[3] STRAP_BIOS_ROM_EN 1 = Enable the external BIOS ROM device. 0= Disable X
    000: All endpoints are usable
    TEST_PG_BACO TV60 PAD @
    R17@ RV20 1 @ 2 0_0402_5% Provides an option to specify certain
    1

    AC40 1 TV67 PAD @ BOARD_CONFIG DBGDATA_5 board-level specifics to the VBIOS or driver. 0 X PS_2[4] N/A Reserved 1
    DIGON [2:0] DBGDATA_4 (Internal pulldown)
    RV1410 HSYNC/VSYNC: If use dGPU for display output, this 2 DBGDATA_3
    000 = Samsung 8Gb
    10K_0402_5% AC37 1 TV68 PAD @ 001 = Hynix 8Gb PS_2[5] N/A Reserved 1
    R18@ K41 BL_ENABLE AC38 1 TV69 PAD @ pins need pull up to VDD_33 --Brooks 0718 010 = Micron 8Gb
    R34 RSVD#K41 BL_PWM_DIM Provide a strap option to change the SMBUS Board configuration related strapping, such as for memory ID
    RSVD#R34 GPU_HSYNC GPU_HSYNC
    2

    C W34 RV1266 1 @ 2 5.1K_0402_5% RV1267 1 @ 2 5.1K_0402_5% SMBUS_ADDR DBGDATA_7 slave address of the GPU. PS_3[1] BOARD_CONFIG[0] 000 = Samsung 8Gb X C
    HSYNC W35 GPU_VSYNC RV1268 1 @ 2 5.1K_0402_5% GPU_VSYNC RV1269 1 @ 2 5.1K_0402_5% [1:0] DBGDATA_6 00: 0x40 0 X PS_3[2] BOARD_CONFIG[1] 001 = Hynix 8Gb
    VSYNC 01: 0x41 01 (Internal pulldown) (Strap the address to PS_3[3] BOARD_CONFIG[2] 010 = Micron 8Gb

    Vinafix.com
    10: 0x42 0x41 if no conflict)
    Reserve for 11: 0x43
    AG34 Need confirm the BOM Structure --Brooks0726 PS_3[4] N/A Reserved 1
    R18M-M2-60 SWAPLOCKA AE34 Note: To change the straps from the default values, use pull-up or pull-down resistors of
    SWAPLOCKB AR29 PS_3[5] N/A Reserved 1
    GENLK_CLK 5.1Kohm (5%) on the PCB
    AP29
    GENLK_VSYNC

    REV 0.91
    216-0905018-C3_FCBGA769
    @

    For R18M-M2-60
    +3VGS +3VGS UV1K +1.8VGS +1.8VGS
    symbol11 SVC SVD Output Voltage +1.8VGS +1.8VGS
    +1.8VGS RV1428 UV1J L40 DBGDATA_0 RV1285 1 R17@ 2 5.1K_0402_5% DBGDATA_0 RV1286 1 @ 2 5.1K_0402_5%
    0_0402_5% symbol10 DBGDATA_0 L41 DBGDATA_1 0 0 1.1 V
    DBGDATA_1 DBGDATA_2 DBGDATA_1

    1
    1 @ 2 AM13 N35 M40 RV1289 1 R17@ 2 5.1K_0402_5% RV1290 1 @ 2 5.1K_0402_5%
    TSVDD DPLUS DBGDATA_2 DBGDATA_3
    1

    M41 0 1 1.0 V RV1325 RV1324 RV1411 RV1412


    RV1321 RV1335 DBGDATA_3 N40 DBGDATA_4 RV1293 1 R17@ 2 5.1K_0402_5% DBGDATA_2 RV1294 1 @ 2 5.1K_0402_5% 10K_0402_5% 10K_0402_5% 8.45K_0402_1% 8.45K_0402_1%
    1 DBGDATA_4 DBGDATA_5
    2

    CV18 J8 47K_0402_5% 47K_0402_5% N41 1 0 0.9 V PX@ @ R18@ R18@


    G

    1U_0402_6.3V6K TEMPIN0 N34 PX@ PX@ DBGDATA_5 P40 DBGDATA_6 RV1297 1 @ 2 5.1K_0402_5% DBGDATA_3 RV1298 1 @ 2 5.1K_0402_5%
    DMINUS DBGDATA_6 DBGDATA_7 GPU_SVC PS_0 PS_1

    2
    PX@ P41 1 1 0.8 V
    2 DBGDATA_7 DBGDATA_8 DBGDATA_4 GPU_SVD
    2

    J7 R40 1 TV24 PAD @ RV1303 1 @ 2 5.1K_0402_5% RV1304 1 @ 2 5.1K_0402_5%


    TEMPINRETURN GPU_SMB_CLK DBGDATA_8 DBGDATA_9

    1
    QV1A 1 6 PX@ R41 1 TV25 PAD @ 1 1
    S

    EC_SMB_CK3 6,39
    U38 GPU_GPIO28_FDO DBGDATA_9 T40 DBGDATA_10 1 RV1306 1 2 5.1K_0402_5% DBGDATA_5 RV1307 1 2 5.1K_0402_5%
    D

    TV26 PAD @ @ @ RV1413 CV124 RV1414 CV125


    GPIO_28_FDO DBGDATA_10 DBGDATA_11

    1
    N38 2N7002KDWH_SOT363-6 T41 1 TV27 PAD @ 2K_0402_1% .01U_0402_16V7-K 2K_0402_1% .01U_0402_16V7-K
    TS_A DBGDATA_11 DBGDATA_12 DBGDATA_6
    1

    U40 1 TV28 PAD @ RV1310 1 R17@ 2 5.1K_0402_5% RV1311 1 @ 2 5.1K_0402_5% RV1329 RV1331 R18@ @ R18@ @
    G

    REV 0.91 RV1343 DBGDATA_12 U41 DBGDATA_13 1 TV29 PAD @ 10K_0402_5% 10K_0402_5% 2 2
    DBGDATA_13 DBGDATA_14 DBGDATA_7

    2
    216-0905018-C3_FCBGA769 10K_0402_5% V40 1 TV30 PAD @ RV1314 1 @ 2 5.1K_0402_5% RV1315 1 @ 2 5.1K_0402_5% @ PX@
    @ R18@ DBGDATA_14 V41 DBGDATA_15 1 TV31 PAD @
    GPU_SMB_DATA DBGDATA_15

    2
    QV1B 4 3 PX@
    S

    EC_SMB_DA3 6,39
    2

    Reserve for R18M-M2-60 Need confirm if can NC for REV 0.91


    to enable MLPS 2N7002KDWH_SOT363-6 216-0905018-C3_FCBGA769
    CNL-U GT0 --Brooks0710 @ +1.8VGS +1.8VGS

    1
    B B
    RV1416 RV1415
    +3VGS 10K_0402_5% 8.45K_0402_1%
    +1.8VGS @ @
    UV10 R17@
    VDD_CLKGEN PS_2 PS_3

    2
    +1.8VGS 6 1 LV1 1 2
    UV1A VSS VDD

    0.1U_0201_6.3V6-K
    BLM15PD121SN1D_2P
    SSON#_CLKGEN XTALIN_CLKGEN RV1425 1 R17@ 2 XTALIN
    1

    1
    5 2

    R17@
    BP_0 symbol1 GPU_JTAG_TDO SSCLK2/REFCLK_D/OE1/FSEL/SSEL/SSON#/PD#XIN/CLKIN 1 1
    RV1229 1 PX@ 2 10K_0402_5% AA38 AF41 1 TV48 PAD @ RV1233 RV1238 UV1F 0_0201_5% 1 1 RV1417 CV126 RV1418 CV127
    RV1230 1 PX@ 2 10K_0402_5% BP_1 AA37 BP_0 JTAG_TDO AD40 GPU_JTAG_TDI 1 TV49 PAD @ 5.11K_0402_1% 10K_0402_5% symbol6 BA39 GPU_XTALIN RV1337 1 R17@ 2 CLK_100M_CLKGEN 4 3 XTALOUT_CLKGENRV1426 1 R17@ 2 XTALOUT CV17 4.75K_0402_1% .01U_0402_16V7-K 2K_0402_1% .01U_0402_16V7-K
    BP_1 JTAG_TDI AD41 GPU_JTAG_TMS 1 TV50 PAD @ @ PX@ XTALIN 0_0402_5% SSCLK1/REFCLK/FSEL/SSEL/SSON#/OE2 XOUT 0_0201_5% 10U_0603_6.3V6M R18@ @ @ @
    JTAG_TMS AE41 GPU_JTAG_TCK 1 TV51 PAD @ SI51214-A1FAGMR_TDFN6_1P2X1P4 R17@ 2 2

    CV16
    JTAG_TCK
    2

    2 2

    2
    R17@
    RV1234 1 @ 2 0_0402_5% TEST6 B2 AE40 TESTEN
    TEST6 TESTEN AF40 GPU_JTAG_TRST#
    JTAG_TRSTB
    1

    REV 0.91
    216-0905018-C3_FCBGA769 RV1235 RV1239 +1.8VGS
    Reserve +3VGS
    @ 1K_0402_5% 10K_0402_5% AY39 GPU_XTALOUT GPU_XTALIN 1 2 XTALIN CV20 1 2 PX@
    PX@ @ XTALOUT CV123 1 2 @
    RV1341 12P_0201_25V8-J
    2

    1
    0_0402_5% 0.1U_0201_6.3V6-K
    R18@ RV1338
    PLLCHARZ_L

    27MHZ_10PF_7V27000050
    AV15 1 TV42 PAD @ 5.1K_0402_5%
    PLLCHARZ_L PLLCHARZ_H

    8
    AU15 1 TV43 PAD @ R17@ UV7 @
    PLLCHARZ_H YV1 +3VGS +3VGS

    VCC
    GND1
    OSC1

    2
    PX@

    1
    SSON#_CLKGEN GPU_ROMCS# GPU_ROMSI

    1
    Reserve REV 0.91 AY38 ANALOGIO RV1344 1 @ 2 16.2K_0402_1% RV1340 1 5
    ANALOGIO 1M_0402_5% RV1409 /CS DI(IO0) RV1407
    RV1380 1 2

    GND2
    @ 216-0905018-C3_FCBGA769 @ 1K_0402_5% 1K_0402_5%

    OSC2
    WRST# 39 GPU_ROMSO GPU_ROMSCK
    0_0402_5% @ @ 2 6 @
    DO(IO1) CLK

    2
    SSON# Clock SS RV1339
    GPU_ROMWP# GPU_ROMHOLD#

    3
    RV1342 5.1K_0402_5% 3 7
    0_0402_5% 1 SS Off @ /WP(IO2) /HOLD(IO3)
    1

    C QV7 R18@
    GPU_RST#

    2
    DV5 1 2 @ RV1381 1 @ 2 2 MMBT3904WH_SOT323-3 0 SS On
    17 GPU_RST# GPU_XTALOUT 1 2 CV19 1 2 PX@
    0.1U_0201_6.3V6-K

    A 2.2K_0402_5% B @ XTALOUT A

    GND
    @

    SDM10U45LP-7_DFN1006-2-2 E
    3
    1

    1 12P_0201_25V8-J
    RV1384 W25Q80DVSSIG_SO8
    GPU_GPIO19 RV1385 1

    4
    @ 2 100K_0402_5%
    47K_0402_5% @
    2
    CV120
    2

    Security Classification LC Future Center Secret Data Title

    Issued Date 2016/08/16 Deciphered Date 2017/08/15 R17M-P1-50_VRAM I/F


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 330ARR
    Date: Friday, March 23, 2018 Sheet 18 of 52
    5 4 3 2 1
    5 4 3 2 1

    UV1G UV1H UV1O


    symbol7 symbol8 symbol15
    D AY32 AY22 AY18 D
    TX2P_DPB0P TX2P_DPD0P TX2P_DPE0P
    BA32 BA22 BA18
    TX2M_DPB0N TX2M_DPD0N TX2M_DPE0N
    AY31 AY21 AY16
    TX1P_DPB1P TX1P_DPD1P TX1P_DPE1P
    BA31 BA21 BA16
    TX1M_DPB1N TX1M_DPD1N TX1M_DPE1N
    AY30 AY20 AY15
    TX0P_DPB2P TX0P_DPD2P TX0P_DPE2P
    BA30 BA20 BA15
    TX0M_DPB2N TX0M_DPD2N TX0M_DPE2N
    AY28 AY19 AY14
    TXCBP_DPB3P TXCDP_DPD3P TXCEP_DPE3P
    BA28 BA19 BA14
    TXCBM_DPB3N TXCDM_DPD3N TXCEM_DPE3N
    AY11
    AUX1P
    BA11
    AUX1N

    AM21 AY10 AU27 1 TV65 PAD @


    C DDCAUX3P DDC1CLK DDCAUX5P C

    AP21 1 TV64 PAD @ BA10 AV27 1 TV66 PAD @


    DDCAUX3N DDC1DATA DDCAUX5N

    Vinafix.com
    REV 0.91
    216-0905018-C3_FCBGA769
    @

    AY36 AY27
    TX5P_DPA0P TX5P_DPC0P
    BA36 BA27
    TX5M_DPA0N TX5M_DPC0N
    AY35 AY26
    TX4P_DPA1P TX4P_DPC1P
    BA35 BA26
    TX4M_DPA1N TX4M_DPC1N
    AY34 AY25
    TX3P_DPA2P TX3P_DPC2P
    B BA34 BA25 B
    TX3M_DPA2N TX3M_DPC2N
    AY33 AY24
    TXCAP_DPA3P TXCCP_DPC3P
    BA33 BA24
    TXCAM_DPA3N TXCCM_DPC3N
    AP19 1 TV63 PAD @
    AUX2P
    AM19
    BA12 AUX2N
    AUX_ZVSS RV1420 1 @ 2
    51K_0402_5%
    1

    RV1345 AR23 AV19 1 TV62 PAD @


    150_0402_1% DDCAUX4P DDC2CLK
    PX@ REV 0.91 AP23 AU19 1 TV61 PAD @
    DDCAUX4N REV 0.91 DDC2DATA
    2

    216-0905018-C3_FCBGA769 216-0905018-C3_FCBGA769
    @ @

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2016/08/16 Deciphered Date 2017/08/15 R17M-P1-50_GPIO
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    B
    330ARR 1.0

    Date: Friday, March 23, 2018 Sheet 19 of 52


    5 4 3 2 1
    5 4 3 2 1

    +VDDC (1U_0402_6.3V) *7 (1U_0402_6.3V) *4 +VDDCI


    (22U_0603_6.3V) *8 UV1I (22U_0603_6.3V) *2
    N13 L13

    PX_CD@

    PX_CD@

    PX_CD@
    symbol9
    N15 VDDC#0 VDDCI#0 L17

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    N21 VDDC#1 VDDCI#1 L21
    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@
    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    N23 VDDC#2 VDDCI#2 L25
    1 1 1 1 1 1 1 1 VDDC#3 VDDCI#3 1 1 1 1 1 1 1
    CV503 N29 L29 CV502
    33P_0402_50V8J N31 VDDC#4 VDDCI#4 N11 33P_0402_50V8J
    RF_PXNS@ R13 VDDC#5 VDDCI#5 U11 RF_PXNS@
    2 2 2 2 2 2 2 2 R15 VDDC#6 VDDCI#6 AA11 2 2 2 2 2 2 2
    CV21

    CV22

    CV23

    CV24

    CV25

    CV30

    CV31

    CV26

    CV35

    CV27

    CV28

    CV36

    CV29
    R21 VDDC#7 VDDCI#7 AE11
    RF VDDC#8 VDDCI#8
    R23 RF
    R29 VDDC#9
    R31 VDDC#10
    U13 VDDC#11
    U15 VDDC#12
    D U21 VDDC#13 D
    U23 VDDC#14
    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    U29 VDDC#15
    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@
    U31 VDDC#16
    1 1 1 1 1 1 1 1 VDDC#17
    W13
    W15 VDDC#18
    W21 VDDC#19
    2 2 2 2 2 2 2 2 W23 VDDC#20
    CV47

    CV48

    CV49

    CV50

    CV51

    CV52

    CV53

    CV54
    W29 VDDC#21
    W31 VDDC#22
    AA13 VDDC#23
    AA15 VDDC#24
    AA21 VDDC#25
    AA23 VDDC#26
    AA29 VDDC#27
    AA31 VDDC#28
    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    AC13 VDDC#29
    PX@

    PX@

    PX@

    PX@
    @

    @
    AC15 VDDC#30
    1 1 1 1 1 1 1 1 VDDC#31
    AC21
    AC23 VDDC#32
    AC29 VDDC#33
    2 2 2 2 2 2 2 2 AC31 VDDC#34
    CV128

    CV129

    CV130

    CV131

    CV132

    CV133

    CV134

    CV135
    AE13 VDDC#35
    AE15 VDDC#36
    AE21 VDDC#37
    VDDC#38
    Reserve 8pcs 22U_0603 capacitors AE23
    AE29 VDDC#39
    for PWR requirement --Brooks 0717 AE31 VDDC#40
    AG13 VDDC#41
    AG15 VDDC#42
    AG21 VDDC#43
    AG23 VDDC#44
    AG29 VDDC#45
    AG31 VDDC#46
    AJ13 VDDC#47
    AJ15 VDDC#48
    AJ17 VDDC#49
    AJ19 VDDC#50
    AJ21 VDDC#51
    AJ23 VDDC#52
    AJ25 VDDC#53
    AJ27 VDDC#54
    C AJ29 VDDC#55 C
    AJ31 VDDC#56
    AL13 VDDC#57
    AL15 VDDC#58
    AL17 VDDC#59
    AL19 VDDC#60
    AL21 VDDC#61
    AL23 VDDC#62
    AL25 VDDC#63 C3 GPU_VMEMIO_SENSE
    VDDC#64 FB_VMEMIO GPU_VDDCI_SENSE GPU_VMEMIO_SENSE 50
    AL27 AV13
    VDDC#65 FB_VDDCI GPU_VDDC_SENSE GPU_VDDCI_SENSE 51
    AL29 AR13

    Vinafix.com
    VDDC#66 FB_VDDC GPU_VSSC_SENSE GPU_VDDC_SENSE 51
    AL31 AU13
    VDDC#67 FB_VSS GPU_VSSC_SENSE 51
    REV 0.91
    216-0905018-C3_FCBGA769
    @

    +1.8VGS_GPU +1.8VGS
    +1.35VGS (1U_0402_6.3V) *10 UV1N
    (22U_0603_6.3V) *2 symbol14 (1U_0402_6.3V) *3
    K11 AM15 RV1427 1 @ 2 0_0805_5%
    PX_CD@

    PX_CD@

    PX_CD@

    PX_CD@
    K13 VMEMIO#0 VDD_18#0 AP15

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    K19 VMEMIO#1 VDD_18#1 AR15
    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@
    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    K23 VMEMIO#2 VDD_18#2


    1 1 1 1 1 1 1 1 1 1 VMEMIO#3 1 1 1 1
    K27 CV504
    K31 VMEMIO#4 0.1U_0201_6.3V6-K
    L10 VMEMIO#5 @

    CV60

    CV61

    CV62
    2 2 2 2 2 2 2 2 2 2 N10 VMEMIO#6 2 2 2 2
    CV57

    CV55

    CV58

    CV59

    CV56

    CV63

    CV64

    CV65

    CV66

    CV67

    W10 VMEMIO#7
    AC10 VMEMIO#8 For EMC +VDD_08
    AG10 VMEMIO#9
    VMEMIO#10
    (1U_0402_6.3V) *7
    AC32
    VDD_08#0 AG32
    VDD_08#1 AG35

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@
    10U_0402_6.3V6M

    10U_0402_6.3V6M

    1U_0201_6.3V6-M

    1U_0201_6.3V6-M

    1U_0201_6.3V6-M
    1U_0402_6.3V6K

    1U_0402_6.3V6K
    VDD_08#2 AJ32
    VDD_08#3 1 1 1 1 1 1 1 1
    AJ34 CV33
    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    VDD_08#4 AL34
    PX@

    PX@

    0.1U_0201_6.3V6-K
    VDD_08#5 @
    1 1 1
    W32 2 2 2 2 2 2 2 2
    CV501 For EMC
    CV68

    CV69

    CV70

    CV71

    CV72

    CV73

    CV74
    33P_0402_50V8J VDD_08
    RF_PXNS@
    2 2 2 AM23
    CV75

    CV76

    VSS#227 AM17
    VSS#228
    B
    RF REV 0.91
    B

    216-0905018-C3_FCBGA769 Change CV72~CV74 to 0201 size for


    @
    layout space limitation --Brooks 0719

    +3VALW TO +3VGS MOS. AO3402 VGS +1.8VALW TO +1.8VGS


    +3VGS /10mA MAX is 12V +1.8VGS /1.0A Rdson<65mohm
    Backup is AO3420

    Discharge

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2016/08/16 Deciphered Date 2017/08/15 R17M-P1-50_DIGITAL OUT


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Custom
    330ARR 1.0

    Date: Friday, March 23, 2018 Sheet 20 of 52

    5 4 3 2 1
    5 4 3 2 1

    UV1L UV1M
    symbol12 symbol13
    A2 J39 AA5 AN40
    A5 VSS#0 VSS#58 J40 AA10 VSS#115 VSS#171 AN41
    A9 VSS#1 VSS#59 J41 AA17 VSS#116 VSS#172 AP13
    D A13 VSS#2 VSS#60 K21 AA19 VSS#117 VSS#173 AP17 D
    A17 VSS#3 VSS#61 K25 AA25 VSS#118 VSS#174 AR3
    A21 VSS#4 VSS#62 K29 AA27 VSS#119 VSS#175 AR7
    A25 VSS#5 VSS#63 K40 AA32 VSS#120 VSS#176 AR11
    A29 VSS#6 VSS#64 L3 AA39 VSS#121 VSS#177 AR19
    A33 VSS#7 VSS#65 L7 AC3 VSS#122 VSS#178 AR21
    A37 VSS#8 VSS#66 L11 AC7 VSS#123 VSS#179 AR25
    A40 VSS#9 VSS#67 L15 AC11 VSS#124 VSS#180 AR27
    B1 VSS#10 VSS#68 L19 AC17 VSS#125 VSS#181 AR31
    B40 VSS#11 VSS#69 L23 AC19 VSS#126 VSS#182 AR35
    B41 VSS#12 VSS#70 L27 AC25 VSS#127 VSS#183 AR39
    C5 VSS#13 VSS#71 L31 AC27 VSS#128 VSS#184 AU1
    C7 VSS#14 VSS#72 L35 AC39 VSS#129 VSS#185 AU3
    C9 VSS#15 VSS#73 L39 AE1 VSS#130 VSS#186 AU9
    C11 VSS#16 VSS#74 N1 AE3 VSS#131 VSS#187 AU23
    C13 VSS#17 VSS#75 N3 AE5 VSS#132 VSS#188 AU29
    C15 VSS#18 VSS#76 N5 AE10 VSS#133 VSS#189 AW3
    C17 VSS#19 VSS#77 N17 AE17 VSS#134 VSS#190 AW5
    C19 VSS#20 VSS#78 N19 AE19 VSS#135 VSS#191 AW7
    C21 VSS#21 VSS#79 N25 AE25 VSS#136 VSS#192 AW9
    C23 VSS#22 VSS#80 N27 AE27 VSS#137 VSS#193 AW11
    C25 VSS#23 VSS#81 N32 AE32 VSS#138 VSS#194 AW13
    C C27 VSS#24 VSS#82 N37 AE35 VSS#139 VSS#195 AW15 C
    C29 VSS#25 VSS#83 N39 AE39 VSS#140 VSS#196 AW17
    C31 VSS#26 VSS#84 R3 AG3 VSS#141 VSS#197 AW19

    Vinafix.com
    C33 VSS#27 VSS#85 R7 AG7 VSS#142 VSS#198 AW21
    C35 VSS#28 VSS#86 R11 AG11 VSS#143 VSS#199 AW23
    C37 VSS#29 VSS#87 R17 AG17 VSS#144 VSS#200 AW25
    C39 VSS#30 VSS#88 R19 AG19 VSS#145 VSS#201 AW27
    E1 VSS#31 VSS#89 R25 AG25 VSS#146 VSS#202 AW29
    E3 VSS#32 VSS#90 R27 AG27 VSS#147 VSS#203 AW31
    E4 VSS#33 VSS#91 R32 AG39 VSS#148 VSS#204 AW33
    E9 VSS#34 VSS#92 R35 AG40 VSS#149 VSS#205 AW35
    E13 VSS#35 VSS#93 R39 AG41 VSS#150 VSS#206 AW37
    E17 VSS#36 VSS#94 U1 AJ1 VSS#151 VSS#207 AW39
    E21 VSS#37 VSS#95 U3 AJ3 VSS#152 VSS#208 AY1
    E25 VSS#38 VSS#96 U5 AJ5 VSS#153 VSS#209 AY2
    E29 VSS#39 VSS#97 U17 AJ10 VSS#154 VSS#210 AY9
    E39 VSS#40 VSS#98 U19 AJ11 VSS#155 VSS#211 AY12
    E41 VSS#41 VSS#99 U25 AJ35 VSS#156 VSS#212 AY17
    G3 VSS#42 VSS#100 U27 AJ39 VSS#157 VSS#213 AY23
    G7 VSS#43 VSS#101 U32 AL3 VSS#158 VSS#214 AY29
    G11 VSS#44 VSS#102 U37 AL7 VSS#159 VSS#215 AY37
    G15 VSS#45 VSS#103 U39 AL10 VSS#160 VSS#216 AY40
    B G19 VSS#46 VSS#104 W3 AL11 VSS#161 VSS#217 AY41 B
    G23 VSS#47 VSS#105 W7 AL32 VSS#162 VSS#218 BA2
    G27 VSS#48 VSS#106 W11 AL35 VSS#163 VSS#219 BA5
    G31 VSS#49 VSS#107 W17 AL39 VSS#164 VSS#220 BA9
    G35 VSS#50 VSS#108 W19 AN1 VSS#165 VSS#221 BA17
    G39 VSS#51 VSS#109 W25 AN3 VSS#166 VSS#222 BA23
    J1 VSS#52 VSS#110 W27 AN7 VSS#167 VSS#223 BA29
    J3 VSS#53 VSS#111 W39 AN35 VSS#168 VSS#224 BA37
    J5 VSS#54 VSS#112 AA1 AN39 VSS#169 VSS#225 BA40
    J34 VSS#55 VSS#113 AA3 VSS#170 VSS#226
    J37 VSS#56 VSS#114
    VSS#57 REV 0.91
    REV 0.91 216-0905018-C3_FCBGA769
    216-0905018-C3_FCBGA769 @
    @

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2016/08/16 Deciphered Date 2017/08/15 R17M-P1-50_PWR
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 330ARR
    Date: Friday, March 23, 2018 Sheet 21 of 52
    5 4 3 2 1
    5 4 3 2 1

    UV1C UV1D
    symbol3 symbol4
    DQA0_[0..31] DQA0_0 L34 B27 DQA1_0 C2 AH1
    23 DQA0_[0..31] DQA0_1 DQA0_0 DQA1_0 DQA1_1 DQB0_0 DQB1_0
    L37 A27 C1 AH2
    DQA0_2 L38 DQA0_1 DQA1_1 B26 DQA1_2 D2 DQB0_1 DQB1_1 AJ2
    DQA1_[0..31] DQA0_3 J35 DQA0_2 DQA1_2 A26 DQA1_3 D1 DQB0_2 DQB1_2 AK1
    23 DQA1_[0..31] DQA0_4 DQA0_3 DQA1_3 DQA1_4 DQB0_3 DQB1_3
    G37 A24 F1 AL2
    DQA0_5 E38 DQA0_4 DQA1_4 B23 DQA1_5 G2 DQB0_4 DQB1_4 AM1
    DQA0_6 E35 DQA0_5 DQA1_5 A23 DQA1_6 G1 DQB0_5 DQB1_5 AM2
    DQA0_7 D35 DQA0_6 DQA1_6 B22 DQA1_7 H2 DQB0_6 DQB1_6 AN2
    D DQA0_8 H41 DQA0_7 DQA1_7 B20 DQA1_8 K2 DQB0_7 DQB1_7 AR1 D
    DQA0_9 H40 DQA0_8 DQA1_8 A20 DQA1_9 K1 DQB0_8 DQB1_8 AR2
    DQA0_10 G41 DQA0_9 DQA1_9 B19 DQA1_10 L2 DQB0_9 DQB1_9 AT1
    MAA0_[0..8] DQA0_11 G40 DQA0_10 DQA1_10 A19 DQA1_11 L1 DQB0_10 DQB1_10 AT2
    23 MAA0_[0..8] DQA0_12 DQA0_11 DQA1_11 DQA1_12 DQB0_11 DQB1_11
    E40 B17 N2 AV2
    DQA0_13 D41 DQA0_12 DQA1_12 A16 DQA1_13 P2 DQB0_12 DQB1_12 AW 1
    MAA1_[0..8] DQA0_14 D40 DQA0_13 DQA1_13 B16 DQA1_14 P1 DQB0_13 DQB1_13 AW 2
    23 MAA1_[0..8] DQA0_15 DQA0_14 DQA1_14 DQA1_15 DQB0_14 DQB1_14
    C41 A15 R2 AY3
    DQA0_16 C40 DQA0_15 DQA1_15 B15 DQA1_16 R1 DQB0_15 DQB1_15 BA3
    DQA0_17 B39 DQA0_16 DQA1_16 A14 DQA1_17 T2 DQB0_16 DQB1_16 AY4
    DQA0_18 A39 DQA0_17 DQA1_17 B14 DQA1_18 T1 DQB0_17 DQB1_17 BA4
    DQA0_19 B38 DQA0_18 DQA1_18 B13 DQA1_19 U2 DQB0_18 DQB1_18 AY5
    DQA0_20 B36 DQA0_19 DQA1_19 A11 DQA1_20 W1 DQB0_19 DQB1_19 BA7
    DQA0_21 A36 DQA0_20 DQA1_20 B11 DQA1_21 W2 DQB0_20 DQB1_20 AY7
    DQA0_22 B35 DQA0_21 DQA1_21 A10 DQA1_22 Y1 DQB0_21 DQB1_21 AY8
    DQA0_23 A35 DQA0_22 DQA1_22 B10 DQA1_23 Y2 DQB0_22 DQB1_22 BA8
    DQA0_24 B33 DQA0_23 DQA1_23 B8 DQA1_24 AB2 DQB0_23 DQB1_23 AR4
    DQA0_25 B32 DQA0_24 DQA1_24 A7 DQA1_25 AC1 DQB0_24 DQB1_24 AR5
    DQA0_26 A32 DQA0_25 DQA1_25 B7 DQA1_26 AC2 DQB0_25 DQB1_25 AU4
    DQA0_27 B31 DQA0_26 DQA1_26 A6 DQA1_27 AD1 DQB0_26 DQB1_26 AU7
    DQA0_28 A30 DQA0_27 DQA1_27 A4 DQA1_28 AF1 DQB0_27 DQB1_27 AN8
    DQA0_29 B29 DQA0_28 DQA1_28 B4 DQA1_29 AF2 DQB0_28 DQB1_28 AV11
    DQA0_30 B28 DQA0_29 DQA1_29 A3 DQA1_30 AG1 DQB0_29 DQB1_29 AU11
    DQA0_31 A28 DQA0_30 DQA1_30 B3 DQA1_31 AG2 DQB0_30 DQB1_30 AP11
    DQA0_31 DQA1_31 DQB0_31 DQB1_31

    MAA0_0 G25 E15 MAA1_0 R5 AE7


    MAA0_1 H25 MAA0_0 MAA1_0 H15 MAA1_1 R8 MAB0_0 MAB1_0 AE8
    MAA0_2 E27 MAA0_1 MAA1_1 G13 MAA1_2 N7 MAB0_1 MAB1_1 AG5
    MAA0_3 D27 MAA0_2 MAA1_2 D13 MAA1_3 N4 MAB0_2 MAB1_2 AG4
    C C
    MAA0_4 D29 MAA0_3 MAA1_3 H11 MAA1_4 L8 MAB0_3 MAB1_3 AJ4
    MAA0_5 H27 MAA0_4 MAA1_4 H13 MAA1_5 N8 MAB0_4 MAB1_4 AG8
    MAA0_6 H23 MAA0_5 MAA1_5 H17 MAA1_6 U8 MAB0_5 MAB1_5 AC8
    MAA0_7 E23 MAA0_6 MAA1_6 G17 MAA1_7 U7 MAB0_6 MAB1_6 AC5
    MAA0_7 MAA1_7 MAB0_7 MAB1_7

    Vinafix.com
    MAA0_8 D25 D15 MAA1_8 R4 AE4
    H29 MAA0_8 MAA1_8 E11 L5 MAB0_8 MAB1_8 AJ8
    MAA0_9 MAA1_9 MAB0_9 MAB1_9

    WCKA0_0 D33 A22 WCKA1_0 H1 AP1


    23 WCKA0_0 WCKA0#_0 E33 W CKA0_0 W CKA1_0 WCKA1#_0 WCKA1_0 23 W CKB0_0 W CKB1_0
    B21 J2 AP2
    23 WCKA0#_0 W CKA0B_0 W CKA1B_0 WCKA1#_0 23 W CKB0B_0 W CKB1B_0

    WCKA0_1 A34 A8 WCKA1_1 AB1 AN4


    23 WCKA0_1 WCKA0#_1 B34 W CKA0_1 W CKA1_1 WCKA1#_1 WCKA1_1 23 W CKB0_1 W CKB1_1
    B9 AA2 AN5
    23 WCKA0#_1 W CKA0B_1 W CKA1B_1 WCKA1#_1 23 W CKB0B_1 W CKB1B_1

    EDCA0_0 G38 B24 EDCA1_0 F2 AL1


    23 EDCA0_0 EDCA0_1 EDCA0_0 EDCA1_0 EDCA1_1 EDCA1_0 23 EDCB0_0 EDCB1_0
    F41 A18 M2 AU2
    23 EDCA0_1 EDCA0_2 EDCA0_1 EDCA1_1 EDCA1_2 EDCA1_1 23 EDCB0_1 EDCB1_1
    B37 B12 V1 BA6
    23 EDCA0_2 EDCA0_3 EDCA0_2 EDCA1_2 EDCA1_3 EDCA1_2 23 EDCB0_2 EDCB1_2
    A31 B6 AD2 AV7
    23 EDCA0_3 EDCA0_3 EDCA1_3 EDCA1_3 23 EDCB0_3 EDCB1_3

    DDBIA0_0 J38 B25 DDBIA1_0 E2 AK2


    23 DDBIA0_0 DDBIA0_1 DDBIA0_0 DDBIA1_0 DDBIA1_1 DDBIA1_0 23 DDBIB0_0 DDBIB1_0
    F40 B18 M1 AV1
    23 DDBIA0_1 DDBIA0_2 DDBIA0_1 DDBIA1_1 DDBIA1_2 DDBIA1_1 23 DDBIB0_1 DDBIB1_1
    A38 A12 V2 AY6
    23 DDBIA0_2 DDBIA0_3 DDBIA0_2 DDBIA1_2 DDBIA1_3 DDBIA1_2 23 DDBIB0_2 DDBIB1_2
    B30 B5 AE2 AV9
    23 DDBIA0_3 DDBIA0_3 DDBIA1_3 DDBIA1_3 23 DDBIB0_3 DDBIB1_3

    ADBIA0 H21 H19 ADBIA1 W8 AA8


    B 23 ADBIA0 ADBIA0 ADBIA1 ADBIA1 23 ADBIB0 ADBIB1 B

    CSA0#_0 H31 E7 CSA1#_0 G5 AL8


    23 CSA0#_0 CSA0B_0 CSA1B_0 CSA1#_0 23 CSB0B_0 CSB1B_0

    CASA0# D23 D17 CASA1# U4 AC4


    23 CASA0# CASA0B CASA1B CASA1# 23 CASB0B CASB1B
    RASA0# D21 D19 RASA1# W4 AA4 Reserve for R18M-M2-60
    23 RASA0# RASA0B RASA1B RASA1# 23 RASB0B RASB1B
    WEA0# G29 D11 WEA1# L4 AJ7
    23 WEA0# W EA0B W EA1B WEA1# 23 W EB0B W EB1B
    +1.35VGS +1.35VGS

    CKEA0 G21 E19 CKEA1 W5 AA7


    23 CKEA0 CKEA0 CKEA1 CKEA1 23 CKEB0 CKEB1

    1
    CLKA0 E31 D7 CLKA1 RV1240 G4 AL5 RV1387
    23 CLKA0 CLKA0 CLKA1 CLKA1 23 CLKB0 CLKB1
    CLKA0# D31 D9 CLKA1# 40.2_0402_1% J4 AL4 40.2_0402_1%
    23 CLKA0# CLKA0B CLKA1B CLKA1# 23 CLKB0B CLKB1B
    2 PX@ R18@

    2
    RV1241 1 PX@ 2 MEM_CALRA K15 K17 MVREFDA R10 U10 MVREFDB
    120_0402_1% MEM_CALRA MVREFDA MEM_CALRB MVREFDB
    1

    1
    1 1
    CV9 RV1244 CV121 RV1386
    RV1242 1 PX@ 2 DRAM_RST_R RV12431 PX@ 2 DRAM_RST_A L32 1U_0402_6.3V6K 100_0402_1% AM11 1U_0402_6.3V6K 100_0402_1%
    23 DRAM_RST DRAM_RSTA DRAM_RSTB
    49.9_0402_1% 10_0402_1% REV 0.91 PX@ PX@ REV 0.91 R18@ R18@
    2 2
    1

    1 216-0905018-C3_FCBGA769 216-0905018-C3_FCBGA769
    2

    2
    CV10 RV1245 @ @
    120P_0402_50V8-J 4.99K_0402_1%
    PX@ PX@
    A 2 A
    2

    Security Classification LC Future Center Secret Data Title

    Issued Date 2016/08/16 Deciphered Date 2017/08/15 R17M-P1-50_VSS


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 330ARR
    Date: Friday, March 23, 2018 Sheet 22 of 52
    5 4 3 2 1
    5 4 3 2 1

    DQA0_[0..31] DQA1_[0..31]
    22 DQA0_[0..31] 22 DQA1_[0..31]

    MF=0 No Mirror MF=1 Mirror


    MAA0_[0..8] MAA1_[0..8]
    22 MAA0_[0..8] 22 MAA1_[0..8]

    +1.35VGS
    UV3 UV4

    MF=0 MF=1 MF=1 MF=0 RV1346 1 PX@ 2 60.4_0201_1% CLKA0 MF=0 MF=1 MF=1 MF=0
    RV1347 1 PX@ 2 60.4_0201_1% CLKA0#
    A4 DQA0_1 A4 DQA1_11
    EDCA0_0 C2 DQ24 DQ0 A2 DQA0_2 RV1349 1 PX@ 2 60.4_0201_1% CLKA1 EDCA1_1 C2 DQ24 DQ0 A2 DQA1_15
    22 EDCA0_0 EDCA0_1 EDC0 EDC3 DQ25 DQ1 DQA0_7 22 EDCA1_1 EDCA1_0 EDC0 EDC3 DQ25 DQ1 DQA1_10
    C13 B4 RV1348 1 PX@ 2 60.4_0201_1% CLKA1# C13 B4
    22 EDCA0_1 EDCA0_2 R13 EDC1 EDC2 DQ26 DQ2 B2 DQA0_5 22 EDCA1_0 EDCA1_2 R13 EDC1 EDC2 DQ26 DQ2 B2 DQA1_14
    22 EDCA0_2 EDCA0_3 R2 EDC2 EDC1 DQ27 DQ3 E4 DQA0_6 22 EDCA1_2 EDCA1_3 R2 EDC2 EDC1 DQ27 DQ3 E4 DQA1_9
    D 22 EDCA0_3 EDC3 EDC0 DQ28 DQ4 E2 DQA0_4 Byte 0 22 EDCA1_3 EDC3 EDC0 DQ28 DQ4 E2 DQA1_13 Byte 1 D
    DQ29 DQ5 F4 DQA0_3 DQ29 DQ5 F4 DQA1_8
    DDBIA0_0 D2 DQ30 DQ6 F2 DQA0_0 DDBIA1_1 D2 DQ30 DQ6 F2 DQA1_12
    22 DDBIA0_0 DDBIA0_1 D13 DBI0# DBI3# DQ31 DQ7 A11 DQA0_8 22 DDBIA1_1 DDBIA1_0 D13 DBI0# DBI3# DQ31 DQ7 A11 DQA1_1
    22 DDBIA0_1 DDBIA0_2 P13 DBI1# DBI2# DQ16 DQ8 A13 DQA0_9 22 DDBIA1_0 DDBIA1_2 P13 DBI1# DBI2# DQ16 DQ8 A13 DQA1_0
    22 DDBIA0_2 DDBIA0_3 DBI2# DBI1# DQ17 DQ9 DQA0_10 22 DDBIA1_2 DDBIA1_3 DBI2# DBI1# DQ17 DQ9 DQA1_2
    +1.35VGS P2 B11 +1.35VGS P2 B11
    22 DDBIA0_3 DBI3# DBI0# DQ18 DQ10 DQA0_11 22 DDBIA1_3 DBI3# DBI0# DQ18 DQ10 DQA1_3
    B13 B13
    J12 DQ19 DQ11 E11 DQA0_14 J12 DQ19 DQ11 E11 DQA1_4
    22 CLKA0
    CLKA0
    CLKA0# J11 CK DQ20 DQ12 E13 DQA0_12 Byte 1 22 CLKA1
    CLKA1
    CLKA1# J11 CK DQ20 DQ12 E13 DQA1_7 Byte 0
    22 CLKA0# CK# DQ21 DQ13 DQA0_15 22 CLKA1# CK# DQ21 DQ13 DQA1_5
    1

    1
    CKEA0 J3 F11 CKEA1 J3 F11
    22 CKEA0 CKE# DQ22 DQ14 DQA0_13 22 CKEA1 CKE# DQ22 DQ14 DQA1_6
    RV1350 F13 RV1351 F13
    2.37K_0402_1% DQ23 DQ15 U11 DQA0_22 2.37K_0402_1% DQ23 DQ15 U11 DQA1_22
    @ MAA0_2 H11 DQ8 DQ16 U13 DQA0_20 @ MAA1_4 H11 DQ8 DQ16 U13 DQA1_20
    MAA0_5 K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 DQA0_23 MAA1_3 K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 DQA1_23
    BA1/A5 BA3/A3 DQ10 DQ18 BA1/A5 BA3/A3 DQ10 DQ18
    2

    MAA0_4 DQA0_21

    2
    K11 T13 MAA1_2 K11 T13 DQA1_21
    VREFD1_A0 MAA0_3 H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 DQA0_19 VREFD1_A1 MAA1_5 H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 DQA1_18
    BA3/A3 BA1/A5 DQ12 DQ20 N13 DQA0_18 Byte 2 BA3/A3 BA1/A5 DQ12 DQ20 N13 DQA1_19 Byte 2
    DQ13 DQ21 M11 DQA0_16 DQ13 DQ21 M11 DQA1_17
    MAA0_7 DQ14 DQ22 DQA0_17 MAA1_0 DQ14 DQ22 DQA1_16
    1

    1
    1 K4 M13 1 K4 M13
    RV1352 CV77 MAA0_1 H5 A8/A7 A10/A0 DQ15 DQ23 U4 DQA0_27 RV1353 CV78 MAA1_6 H5 A8/A7 A10/A0 DQ15 DQ23 U4 DQA1_27
    5.49K_0402_1% 1U_0402_6.3V6K MAA0_0 H4 A9/A1 A11/A6 DQ0 DQ24 U2 DQA0_28 5.49K_0402_1% 1U_0402_6.3V6K MAA1_7 H4 A9/A1 A11/A6 DQ0 DQ24 U2 DQA1_28
    @ @ MAA0_6 K5 A10/A0 A8/A7 DQ1 DQ25 T4 DQA0_26 @ @ MAA1_1 K5 A10/A0 A8/A7 DQ1 DQ25 T4 DQA1_26
    2 MAA0_8 J5 A11/A6 A9/A1 DQ2 DQ26 T2 DQA0_29 2 MAA1_8 J5 A11/A6 A9/A1 DQ2 DQ26 T2 DQA1_29
    A12/RFU/NC DQ3 DQ27 A12/RFU/NC DQ3 DQ27
    2

    DQA0_25

    2
    N4 N4 DQA1_25
    A5 DQ4 DQ28 N2 DQA0_30 Byte 3 A5 DQ4 DQ28 N2 DQA1_30 Byte 3
    U5 VPP/NC1 DQ5 DQ29 M4 DQA0_24 U5 VPP/NC1 DQ5 DQ29 M4 DQA1_24
    VPP/NC2 DQ6 DQ30 M2 DQA0_31 VPP/NC2 DQ6 DQ30 M2 DQA1_31
    DQ7 DQ31 DQ7 DQ31
    J1 +1.35VGS J1
    J10 MF J10 MF
    RV1360 1 PX@ 2 ZQ_UV3 J13 SEN B1 RV1363 1 PX@ 2 ZQ_UV4 J13 SEN B1
    ZQ VDDQ1 +1.35VGS ZQ VDDQ1 +1.35VGS
    +1.35VGS 120_0402_1% D1 +1.35VGS 120_0402_1% D1
    VDDQ2 F1 VDDQ2 F1
    ADBIA0 J4 VDDQ3 M1 ADBIA1 J4 VDDQ3 M1
    22 ADBIA0 G3 ABI# VDDQ4 P1 22 ADBIA1 G3 ABI# VDDQ4 P1
    RASA0# CASA1#
    22 RASA0# CSA0#_0 RAS# CAS# VDDQ5 22 CASA1# RAS# CAS# VDDQ5
    1

    1
    G12 T1 WEA1# G12 T1
    22 CSA0#_0 CS# WE# VDDQ6 22 WEA1# CS# WE# VDDQ6
    C RV1354 CASA0# L3 G2 RV1355 RASA1# L3 G2 C
    22 CASA0# CAS# RAS# VDDQ7 22 RASA1# CSA1#_0 CAS# RAS# VDDQ7
    2.37K_0402_1% WEA0# L12 L2 2.37K_0402_1% L12 L2
    22 WEA0# WE# CS# VDDQ8 B3 22 CSA1#_0 WE# CS# VDDQ8 B3
    @ @
    VDDQ9 D3 VDDQ9 D3
    VDDQ10 VDDQ10
    2

    2
    F3 F3
    VREFD2_A0 WCKA0#_0 VDDQ11 VREFD2_A1 WCKA1#_0 VDDQ11

    Vinafix.com
    D5 H3 D5 H3
    22 WCKA0#_0 WCKA0_0 WCK01# WCK23# VDDQ12 22 WCKA1#_0 WCKA1_0 WCK01# WCK23# VDDQ12
    D4 K3 D4 K3
    22 WCKA0_0 WCK01 WCK23 VDDQ13 M3 22 WCKA1_0 WCK01 WCK23 VDDQ13 M3
    WCKA0#_1 VDDQ14 WCKA1#_1 VDDQ14
    1

    1
    1 P5 P3 1 P5 P3
    22 WCKA0#_1 WCKA0_1 WCK23# WCK01# VDDQ15 22 WCKA1#_1 WCKA1_1 WCK23# WCK01# VDDQ15
    RV1356 CV79 P4 T3 RV1361 CV80 P4 T3
    22 WCKA0_1 WCK23 WCK01 VDDQ16 22 WCKA1_1 WCK23 WCK01 VDDQ16
    5.49K_0402_1% 1U_0402_6.3V6K E5 5.49K_0402_1% 1U_0402_6.3V6K E5
    @ @ VDDQ17 N5 @ @ VDDQ17 N5
    2 VREFD1_A0 A10 VDDQ18 E10 2 VREFD1_A1 A10 VDDQ18 E10
    VREFD1 VDDQ19 VREFD1 VDDQ19
    2

    VREFD2_A0

    2
    U10 N10 VREFD2_A1 U10 N10
    VREFC_A0 J14 VREFD2 VDDQ20 B12 VREFC_A1 J14 VREFD2 VDDQ20 B12
    VREFC VDDQ21 D12 VREFC VDDQ21 D12
    VDDQ22 F12 VDDQ22 F12
    VDDQ23 H12 VDDQ23 H12
    DRAM_RST J2 VDDQ24 K12 DRAM_RST J2 VDDQ24 K12
    22 DRAM_RST RESET# VDDQ25 RESET# VDDQ25
    M12 M12
    VDDQ26 P12 VDDQ26 P12
    +1.35VGS VDDQ27 T12 +1.35VGS VDDQ27 T12
    VDDQ28 G13 VDDQ28 G13
    H1 VDDQ29 L13 H1 VDDQ29 L13
    K1 VSS1 VDDQ30 B14 K1 VSS1 VDDQ30 B14
    VSS2 VDDQ31 VSS2 VDDQ31
    1

    1
    B5 D14 B5 D14
    RV1364 G5 VSS3 VDDQ32 F14 RV1365 G5 VSS3 VDDQ32 F14
    2.37K_0402_1% L5 VSS4 VDDQ33 M14 2.37K_0402_1% L5 VSS4 VDDQ33 M14
    PX@ T5 VSS5 VDDQ34 P14 PX@ T5 VSS5 VDDQ34 P14
    B10 VSS6 VDDQ35 T14 B10 VSS6 VDDQ35 T14
    VSS7 VDDQ36 VSS7 VDDQ36
    2

    2
    D10 D10
    VREFC_A0 G10 VSS8 VREFC_A1 G10 VSS8
    L10 VSS9 A1 L10 VSS9 A1
    P10 VSS10 VSSQ1 C1 P10 VSS10 VSSQ1 C1
    VSS11 VSSQ2 VSS11 VSSQ2
    1

    1
    1 T10 E1 1 T10 E1
    RV1366 CV81 H14 VSS12 VSSQ3 N1 RV1367 CV82 H14 VSS12 VSSQ3 N1
    5.49K_0402_1% 1U_0402_6.3V6K K14 VSS13 VSSQ4 R1 5.49K_0402_1% 1U_0402_6.3V6K K14 VSS13 VSSQ4 R1
    PX@ PX@ VSS14 VSSQ5 U1 PX@ PX@ VSS14 VSSQ5 U1
    B VSSQ6 VSSQ6 B
    2 H2 2 H2
    VSSQ7 VSSQ7
    2

    2
    +1.35VGS G1 K2 +1.35VGS G1 K2
    L1 VDD1 VSSQ8 A3 L1 VDD1 VSSQ8 A3
    G4 VDD2 VSSQ9 C3 G4 VDD2 VSSQ9 C3
    L4 VDD3 VSSQ10 E3 L4 VDD3 VSSQ10 E3
    C5 VDD4 VSSQ11 N3 C5 VDD4 VSSQ11 N3
    R5 VDD5 VSSQ12 R3 R5 VDD5 VSSQ12 R3
    C10 VDD6 VSSQ13 U3 C10 VDD6 VSSQ13 U3
    R10 VDD7 VSSQ14 C4 R10 VDD7 VSSQ14 C4
    D11 VDD8 VSSQ15 R4 D11 VDD8 VSSQ15 R4
    G11 VDD9 VSSQ16 F5 G11 VDD9 VSSQ16 F5
    L11 VDD10 VSSQ17 M5 L11 VDD10 VSSQ17 M5
    P11 VDD11 VSSQ18 F10 P11 VDD11 VSSQ18 F10
    G14 VDD12 VSSQ19 M10 G14 VDD12 VSSQ19 M10
    VDD13 VSSQ20
    (0.1U_0201_6.3V) *8 VDD13 VSSQ20
    L14 C11 (1U_0402_6.3V) *8 L14 C11
    VDD14 VSSQ21 R11 +1.35VGS VDD14 VSSQ21 R11
    VSSQ22 A12
    (10U_0603_6.3V) *3 VSSQ22 A12
    VSSQ23 C12 VSSQ23 C12
    (0.1U_0201_6.3V) *8

    PX_CD@

    PX_CD@

    PX_CD@
    VSSQ24 E12 VSSQ24 E12
    (1U_0402_6.3V) *8

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K
    VSSQ25 N12 VSSQ25 N12

    PX@

    PX@

    PX@

    PX@

    PX@
    +1.35VGS (10U_0603_6.3V) *3 VSSQ26 R12 VSSQ26 R12
    VSSQ27 1 1 1 1 1 1 1 1 VSSQ27
    170-BALL U12 170-BALL U12
    PX_CD@

    PX_CD@

    PX_CD@

    VSSQ28 H13 VSSQ28 H13


    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    VSSQ29 VSSQ29
    PX@

    PX@

    PX@

    PX@

    PX@

    SGRAM GDDR5 K13 SGRAM GDDR5 K13


    VSSQ30 A14 2 2 2 2 2 2 2 2 VSSQ30 A14

    CV101

    CV102

    CV103

    CV104

    CV105

    CV106

    CV107

    CV108
    1 1 1 1 1 1 1 1 VSSQ31 VSSQ31
    C14 C14
    VSSQ32 E14 VSSQ32 E14
    VSSQ33 N14 VSSQ33 N14
    2 2 2 2 2 2 2 2 VSSQ34 R14 +1.35VGS VSSQ34 R14
    CV109

    CV110

    CV111

    CV112

    CV113

    CV114

    CV115

    CV116

    VSSQ35 U14 VSSQ35 U14


    VSSQ36 VSSQ36

    PX_CD@

    PX_CD@

    PX_CD@
    +1.35VGS
    H5GQ1H24AFR-T2L_BGA170 H5GQ1H24AFR-T2L_BGA170
    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@
    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    @ @
    1 1 1 1 1 1 1 1 1 1 1
    PX_CD@

    PX_CD@

    PX_CD@
    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@
    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    A A
    2 2 2 2 2 2 2 2 2 2 2
    CV83

    CV84

    CV85

    CV86

    CV87

    CV88

    CV89

    CV90

    CV91
    CV507

    CV508

    1 1 1 1 1 1 1 1 1 1 1

    2 2 2 2 2 2 2 2 2 2 2
    CV92

    CV93

    CV94

    CV95

    CV96

    CV97

    CV98

    CV99
    CV505

    CV506

    CV100

    Security Classification LC Future Center Secret Data Title

    Issued Date 2016/08/16 Deciphered Date 2017/08/15 R17M-P1-50_GDDR5 VRAM1


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Custom
    330ARR 1.0

    Date: Friday, March 23, 2018 Sheet 23 of 52


    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B
    Vinafix.com B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2016/08/16 Deciphered Date 2017/08/15 R17M-P1-50_GDDR5 VRAM2
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 330ARR
    Date: Friday, March 23, 2018 Sheet 24 of 52
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    Vinafix.com
    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2016/08/16 Deciphered Date 2017/08/15 R17M-P1-50_Sequence
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 330ARR
    Date: Friday, March 23, 2018 Sheet 25 of 52
    5 4 3 2 1
    5 4 3 2 1

    F3 NEC@ 0.5A_32V_ERBRD0R50X
    1 2
    +3VS

    LCD POWER CIRCUIT 1


    J1 @
    2
    Need Short B+ to +LEDVDD POWER
    +LCDVDD_CON 1 2
    +3VS
    W=40 mils
    JUMP_43X39
    U9 +LEDVDD
    5 1 W=60mils LP2301ALT1G_SOT23-3 +3VS_CMOS V20B+
    IN OUT R22 NONEC@ 2A 80 mil
    2 Q7 3 1 1 2
    1U_0402_6.3V6K

    D
    RF_NS@
    0.1U_0201_6.3V6-K
    1 GND

    4.7U_0805_25V6-K
    C1

    C25

    33P_0402_50V8J

    0.01U_0402_25V7K
    4.7U_0402_6.3V6M
    PCH_ENVDD 4 3

    10U_0603_6.3V6M

    0.1U_0201_6.3V6-K
    1 @1 1 1 @ 1 0_0805_5% 1 1
    EN OCB C1323 C23

    C1322
    G
    1 1

    2
    2 0.1U_0201_6.3V6-K C1321 C3 F2 NEC@ 0.1U_0402_25V6
    D SY6288C20AAC_SOT23-5 @ 1 2 C23 0.1u for G HSW panel blink issue D
    2 2 2 2 @ 2 @ 2 2
    2 2

    C2

    C122

    C123
    3A_32V_ERBRD3R00X
    R5 1 @ 2 CMOS_ON#_R
    39 CMOS_ON#
    100K_0402_5%
    PCH_ENVDD 1
    C10
    6 PCH_ENVDD For RF 0.1U_0201_6.3V6-K
    1

    @
    R35 2
    100K_0402_5% JEDP1
    1
    +LEDVDD 1
    2
    2
    2

    3
    4 3
    APU_EDP_TX0+ C19 2 1 0.1U_0201_6.3V6-K EDP_TX0+ 5 4
    6 APU_EDP_TX0+ APU_EDP_TX0- C16 2 1 0.1U_0201_6.3V6-K EDP_TX0- 6 5
    APU output enable Voh min is 1.8V-0.45V=1.35V 6 APU_EDP_TX0- 6
    7
    APU_EDP_TX1+ C17 2 1 0.1U_0201_6.3V6-K EDP_TX1+ 8 7
    6 APU_EDP_TX1+ APU_EDP_TX1- C18 2 1 0.1U_0201_6.3V6-K EDP_TX1- 9 8
    6 APU_EDP_TX1- 10 9
    APU_EDP_AUX C20 2 1 0.1U_0201_6.3V6-K EDP_AUX 11 10
    6 APU_EDP_AUX APU_EDP_AUX# C21 2 1 0.1U_0201_6.3V6-K EDP_AUX# 12 11
    6 APU_EDP_AUX# 13 12
    DISPOFF# 14 13
    PCH_EDP_PWM R19 1 2 0_0402_5% INVT_PWM 15 14
    6 PCH_EDP_PWM
    @ AUX don't pull high and pull low for eDP panel INVT_PWM 16 15
    17 16
    17
    1

    +3VS 18
    R20 19 18
    1 2 6 APU_EDP_HPD 20 19
    100K_0402_5% R21 @
    @ 0_0402_5% 21 20
    C
    1 +LCDVDD_CON 21 C
    C22 W=60mils 22
    22
    2

    470P_0201_50V7-K 23
    +3VS 23
    @ 24
    2 36 DMIC_DATA 24
    36 DMIC_CLK 25
    26 25
    Need Short 26

    Vinafix.com
    27
    R182 1 @ 2 0_0402_5% USB20_P1_R 28 27

    +3VS
    CMOS Camera 31
    31
    USB20_P1
    USB20_N1
    R183 1 @ 2 0_0402_5% USB20_N1_R 29
    30
    28
    29
    +3VS_CMOS 30
    1 31
    32 G1
    C1320 W=40mils G2
    2

    .047U_0201_6.3V6K
    R10 EMC_NS@ DRAPH_FC5AF301-3181H
    4.7K_0402_5% L12 EMC_NS@ 2
    USB20_N1 USB20_N1_R ME@
    @ 1 2
    1 2
    1

    R12 1 @ 2 0_0402_5% DISPOFF# USB20_P1 4 3 USB20_P1_R


    39 BKOFF# 4 3
    EXC24CH900U_4P
    R14 1 @ 2 0_0402_5% ENBKL
    6 PCH_ENBKL ENBKL 39
    1

    R16 DMIC_CLK DISPOFF# INVT_PWM

    470P_0201_50V7-K

    470P_0201_50V7-K
    100K_0402_5%
    100P_0201_25V8J

    EMC_NS@

    EMC_NS@
    C11

    C12

    C13
    1 1 1
    2

    EMC@

    2 2 2

    B B

    EMC
    Touch Screen
    Touch Screen

    TS_NEC@
    USB20_P2_CONN F4 1 2 0.5A_32V_ERBRD0R50X
    +5VS +5VS_TS
    L33 USB20_N2_CONN
    USB20_N2 1 2 USB20_N2_CONN
    1 2
    3

    +5VS_TS R4675 1 2 0_0402_5%


    TS_NONEC@ 1 JTS1 ME@
    USB20_P2 4 3 USB20_P2_CONN C2079 1
    4 3 1
    1

    D42 0.1U_0201_6.3V6-K 2 7
    EXC24CH900U_4P TS@ R4677 1 @ 2 0_0402_5% TS_RS 3 2 GND1
    1

    2 39 EC_TS_ON 4 3 8
    EMC_NS@ USB20_N2_CONN 4 GND2
    R4678 1 @ 2 0_0402_5% 5
    31 USB20_N2 USB20_P2_CONN 6 5
    D41 R4676 1 @ 2 0_0402_5%
    31 USB20_P2 6
    AZC199-02S.R7G_SOT23-3
    For EMI
    2

    EMC_NS@ CVILU_CI1806M2HR0-NH
    AZ5725-01F.R7GR_DFN1006P2X2
    2

    EMC_NS@
    1

    For ESD

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/08 Deciphered Date 2013/08/05 eDP/CMOS/TS
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 330ARR
    Date: Friday, March 23, 2018 Sheet 26 of 52
    5 4 3 2 1
    5 4 3 2 1

    L2 EMC@
    HDMI_CLK-_C 1 2 HDMI_CLK-_CON 1 2 EMC_NS@
    1 2 C26 10P_0201_25V8G
    HDMI_CLK+_C 4 3 HDMI_CLK+_CON 1 2 EMC_NS@ +3VS
    4 3 C27 10P_0201_25V8G
    EXC24CH900U_4P
    D D
    L3 EMC@
    HDMI_TX0-_C 1 2 HDMI_TX0-_CON 1 2 EMC_NS@
    1 2 D3

    5
    C28 10P_0201_25V8G

    G
    Q1B HDMI_DET 1 1 10 9 HDMI_DET
    HDMI_TX0+_C 4 3 HDMI_TX0+_CON 1 2 EMC_NS@
    4 3 C29 10P_0201_25V8G HDMICLK_R 2 2 8 HDMICLK_R
    9
    EXC24CH900U_4P APU_DDC_CLK 4 3 HDMICLK_R

    S
    6 APU_DDC_CLK HDMIDAT_R HDMIDAT_R
    4 4 7

    D
    7
    L4 EMC@ 2N7002KDWH_SOT363-6
    HDMI_TX1-_C HDMI_TX1-_CON +5VS_HDMI +5VS_HDMI

    2
    1 2 1 2 EMC_NS@ 5 5 6 6

    G
    1 2 C30 10P_0201_25V8G Q1A
    3 3
    HDMI_TX1+_C 4 3 HDMI_TX1+_CON 1 2 EMC_NS@
    4 3 C31 10P_0201_25V8G APU_DDC_DATA 1 6 HDMIDAT_R 8

    S
    6 APU_DDC_DATA

    D
    EXC24CH900U_4P
    2N7002KDWH_SOT363-6
    L5 EMC@ AZ1045-04F_DFN2510P10E-10-9
    HDMI_TX2-_C 1 2 HDMI_TX2-_CON 1 2 EMC_NS@
    1 2 EMC_NS@
    C32 10P_0201_25V8G
    HDMI_TX2+_C 4 3 HDMI_TX2+_CON 1 2 EMC_NS@
    EMC
    4 3 C33 10P_0201_25V8G
    EXC24CH900U_4P

    EMC +5VS_HDMI

    +5VS +5VS_HDMI_F +5VS_HDMI

    2
    D4 D5
    +3VS 2 @ F1
    C @ 1 1 2 C
    3
    BAT54S-7-F_SOT23-3 RB491D_SOT23-3 1.1A_8V_1206L110THYR

    1
    HDMI_CLK-_C R29 1 2 499_0402_1%

    Vinafix.com
    HDMI_CLK+_C Follow Zx05 and beema

    1
    R30 1 2 499_0402_1% C LP2301ALT1G_SOT23-3 1 2
    Q43 2 R202 1 2 150K_0402_5% C34 CC1279
    HDMI_TX0-_C R31 1 2 499_0402_1% B 1 3 Q22 0.1U_0201_6.3V6-K 10U_0402_6.3V6M

    2
    1
    E MMBT3904WH_SOT323-3 @
    HDMI_TX0+_C 2 1

    3
    R32 1 2 499_0402_1% RP2
    6 APU_HDMI_HPD

    1
    2.2K_0404_4P2R_5%

    G
    2
    HDMI_TX1-_C

    1
    R33 1 2 499_0402_1% R257
    R910 100K_0402_5%
    14,41 SUSP

    3
    4
    HDMI_TX1+_C R34 1 2 499_0402_1% 100K_0402_5%
    HDMI_DET
    HDMI_TX2-_C

    2
    R37 1 2 499_0402_1%

    2
    +5VS_HDMI
    HDMI_TX2+_C R38 1 2 499_0402_1% JHDMI1 ME@

    18 15 HDMICLK_R
    +5V_Power SCL 16 HDMIDAT_R
    SDA
    1

    D Q13
    2 APU_HDMI_TX0+ C38 2 1 0.1U_0201_6.3V6-K HDMI_TX0+_C R46 2 @ 1 0_0402_5% HDMI_TX0+_CON 7
    +3VS 6 APU_HDMI_TX0+ APU_HDMI_TX0- HDMI_TX0-_C HDMI_TX0-_CON TMDS_Data0+
    G 2N7002KW_SOT323-3 C37 2 1 0.1U_0201_6.3V6-K R45 2 @ 1 0_0402_5% 9 13
    6 APU_HDMI_TX0- APU_HDMI_TX1+ HDMI_TX1+_C HDMI_TX1+_CON TMDS_Data0- CEC
    C40 2 1 0.1U_0201_6.3V6-K R48 2 @ 1 0_0402_5% 4 17
    6 APU_HDMI_TX1+ APU_HDMI_TX1- HDMI_TX1-_C HDMI_TX1-_CON TMDS_Data1+ DDC/CEC_Ground HDMI_DET
    S C39 2 1 0.1U_0201_6.3V6-K R47 2 @ 1 0_0402_5% 6 19
    6 APU_HDMI_TX1- TMDS_Data1- Hot_Plug_Detect
    3

    APU_HDMI_TX2+ C42 2 1 0.1U_0201_6.3V6-K HDMI_TX2+_C R50 2 @ 1 0_0402_5% HDMI_TX2+_CON 1


    6 APU_HDMI_TX2+ APU_HDMI_TX2- HDMI_TX2-_C HDMI_TX2-_CON TMDS_Data2+
    R42 1 @ 2 C41 2 1 0.1U_0201_6.3V6-K R49 2 @ 1 0_0402_5% 3
    6 APU_HDMI_TX2- TMDS_Data2-
    100K_0402_5% 8 14
    5 TMDS_Data0_Shield Utility
    2 TMDS_Data1_Shield
    B TMDS_Data2_Shield B
    20
    11 GND1 21
    APU_HDMI_CLK+ C36 2 1 0.1U_0201_6.3V6-K HDMI_CLK+_C R44 2 @ 1 0_0402_5% HDMI_CLK+_CON 10 TMDS_Clock_Shield GND2 22
    6 APU_HDMI_CLK+ APU_HDMI_CLK- HDMI_CLK-_C HDMI_CLK-_CON TMDS_Clock+ GND3
    C35 2 1 0.1U_0201_6.3V6-K R43 2 @ 1 0_0402_5% 12 23
    6 APU_HDMI_CLK- TMDS_Clock- GND4

    ALLTO_C128S9-K1935-L

    D6 D7
    HDMI_CLK+_CON 1 1 10 9 HDMI_CLK+_CON HDMI_TX1-_CON 1 1 10 9 HDMI_TX1-_CON

    HDMI_CLK-_CON 2 2 9 8 HDMI_CLK-_CON HDMI_TX1+_CON 2 2 9 8 HDMI_TX1+_CON

    HDMI_TX0+_CON 4 4 7 7 HDMI_TX0+_CON HDMI_TX2-_CON 4 4 7 7 HDMI_TX2-_CON

    HDMI_TX0-_CON 5 5 6 6 HDMI_TX0-_CON HDMI_TX2+_CON 5 5 6 6 HDMI_TX2+_CON

    3 3 3 3

    8 8

    AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9
    EMC_NS@ EMC_NS@

    EMC
    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/15 Deciphered Date 2013/08/15 HDMI_CONN
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 330ARR
    Date: Friday, March 23, 2018 Sheet 27 of 52
    5 4 3 2 1
    A B C D E

    +USB_VCCA

    C55 1 2

    +
    220U_6.3V_M

    C1117 1 2
    @ 47U_0805_6.3V6-M
    LEFT SIDE USB3.0 PORT x2 C125 1 2
    @ 1U_0402_10V6K

    +5VALW +USB_VCCA C127 1 2


    U2 @ 1U_0402_10V6K
    5 1
    IN OUT JUSB1 ME@
    1
    C128 2
    1U_0402_6.3V6K GND USB30_TX_P1 C126 1 2 0.22U_0402_16V6-K USB30_TX_C_P1 R95 1 @ 2 0_0402_5% USB30_TX_R_P1 9
    USB_OC1# 9 USB30_TX_P1 StdA_SSTX+
    4 3 1
    2 39 USB_ON# ENB OCB USB_OC1# 9 USB30_TX_N1 C124 1 USB30_TX_C_N1 USB30_TX_R_N1 VBUS
    2 0.22U_0402_16V6-K R96 1 @ 2 0_0402_5% 8
    9 USB30_TX_N1 USB20_P5 USB20_P5_R StdA_SSTX-
    SY6288D20AAC_SOT23-5 1 R97 1 @ 2 0_0402_5% 3
    9 USB20_P5 D+
    1 C140 7 1
    1000P_0201_50V7-K USB20_N5 R93 1 @ 2 0_0402_5% USB20_N5_R 2 GND_DRAIN 10
    9 USB20_N5 USB30_RX_P1 C8787 1 USB30_RX_C_P1 USB30_RX_R_P1 D- GND_2
    EMC_NS@ 2 0.33U_0402_10V6-K R94 1 @ 2 0_0402_5% 6 11
    Low Active 2A 2 9 USB30_RX_P1
    4 StdA_SSRX+ GND_3 12
    USB30_RX_N1 C8788 1 2 0.33U_0402_10V6-K USB30_RX_C_N1 R98 1 @ 2 0_0402_5% USB30_RX_R_N1 5 GND_1 GND_4 13
    9 USB30_RX_N1 StdA_SSRX- GND_5

    ALLTO_C190AG-10939-L

    L13 EMC@
    USB30_RX_C_N1 1 2 USB30_RX_R_N1
    1 2

    USB30_RX_C_P1 4 3 USB30_RX_R_P1
    4 3
    EXC24CH900U_4P USB20_P5_R
    +USB_VCCA
    USB20_N5_R D12 EMC@
    L16 EMC@ USB30_RX_R_N1 9 1USB30_RX_R_N1
    USB30_TX_C_N1 USB30_TX_R_N1 10 1
    1 2

    AZ5725-01F.R7GR_DFN1006P2X2
    1 2 USB30_RX_R_P1 8 2 USB30_RX_R_P1

    2
    D11 9 2
    D13

    1
    USB30_TX_C_P1 4 3 USB30_TX_R_P1 AZC199-02S.R7G_SOT23-3 USB30_TX_R_N1 7 4USB30_TX_R_N1
    7 4
    4 3 EMC@
    EXC24CH900U_4P USB30_TX_R_P1 6 5 USB30_TX_R_P1
    6 5
    3

    2
    3
    EMC@

    2
    L8 EMC@ 8
    USB20_P5 1 2 USB20_P5_R
    1 2 AZ1045-04F_DFN2510P10E-10-9
    USB20_N5 USB20_N5_R

    1
    4 3
    4 3
    EXC24CH900U_4P
    EMC
    EMC

    2 +USB_VCCA 2

    C2060 1 2
    @ 1U_0402_10V6K

    C2059 1 2
    @ 1U_0402_10V6K

    L30 EMC@ JUSB3 ME@


    USB30_RX_C_N2 1 2 USB30_RX_R_N2
    1 2 USB30_TX_P2 C2058 1 2 0.22U_0402_16V6-K USB30_TX_C_P2 R3119 1 @ 2 0_0402_5% USB30_TX_R_P2 9
    9 USB30_TX_P2 StdA_SSTX+
    1

    Vinafix.com
    USB30_RX_C_P2 4 3 USB30_RX_R_P2 USB30_TX_N2 C2057 1 2 0.22U_0402_16V6-K USB30_TX_C_N2 R3116 1 @ 2 0_0402_5% USB30_TX_R_N2 8 VBUS
    4 3 9 USB30_TX_N2 USB20_P6_S USB20_P6_R StdA_SSTX-
    R3103 1 @ 2 0_0402_5% 3
    EXC24CH900U_4P UARTA_P80_EN 7 D+
    USB20_N6_S R942 1 @ 2 0_0402_5% USB20_N6_R 2 GND_DRAIN 10
    USB30_RX_P2 C8789 1 2 0.33U_0402_10V6-K USB30_RX_C_P2 R3117 1 @ 2 0_0402_5% USB30_RX_R_P2 6 D- GND_2 11
    9 USB30_RX_P2 StdA_SSRX+ GND_3
    L29 EMC@ 4 12
    USB30_TX_C_N2 1 2 USB30_TX_R_N2 USB30_RX_N2 C8790 1 2 0.33U_0402_10V6-K USB30_RX_C_N2 R3114 1 @ 2 0_0402_5% USB30_RX_R_N2 5 GND_1 GND_4 13
    1 2 9 USB30_RX_N2 StdA_SSRX- GND_5

    USB30_TX_C_P2 4 3 USB30_TX_R_P2 ALLTO_C190AG-10939-L


    4 3
    EXC24CH900U_4P

    L17 EMC@
    USB20_P6_S 1 2 USB20_P6_R
    1 2

    1
    R537 R538
    USB20_N6_S USB20_N6_R

    2
    4 3

    2 Debug@
    4 3

    0_0402_5%

    100K_0402_5%
    EXC24CH900U_4P @

    D45 EMC@
    USB30_RX_R_N2 9 1USB30_RX_R_N2

    1
    10 1
    USB30_RX_R_P2 8 2 USB30_RX_R_P2
    9 2
    USB30_TX_R_N2 7 4USB30_TX_R_N2

    For USB Debug Function


    7 4
    USB30_TX_R_P2 6 5 USB30_TX_R_P2
    6 5

    3 3

    AZ1045-04F_DFN2510P10E-10-9

    3 2 Debug@ 1 USB_UART_SEL 3
    7 USBDEBUG
    R531 0_0402_5%

    FOR ESD Close to Connector


    USB20_P6_R +USB_VCCA
    U129
    USB20_N6_R

    R533 2 Debug@ 1 0_0402_5% EC_TX_C 1


    3

    10 R104562 Debug@ 1 0_0402_5%


    35,39 EC_TX 1D+ VCC +3VALW
    D43
    AZ5725-01F.R7GR_DFN1006P2X2

    R536 2 Debug@ 1 0_0402_5% EC_RX_C 2 9 USB_UART_SEL AZC199-02S.R7G_SOT23-3


    35,39 EC_RX 1D- S
    1

    EMC@
    3 8 USB20_P6_S D34
    9 USB20_P6
    1

    2D+ D+
    NCY3958Y USB20_N6_S
    4 7 EMC_NS@
    9 USB20_N6 2D- D-
    5 6
    GND1 OE#
    2

    11
    GND2
    2
    1

    NCT3958Y_DFN10_3X3
    Debug@

    USB20_P6 R539 2 @ 1 0_0402_5% USB20_P6_S

    USB20_N6 R541 2 @ 1 0_0402_5% USB20_N6_S

    USBDEBUG Kernel debug


    Set input Set input

    Set output Low ENABLE

    +3VALW

    4
    UARTA_P80_EN POST 80 4
    1

    Set input DISABLE R547


    Debug@ 10K_0402_5%
    Set output Low ENABLE

    USB_UART_SEL
    2
    1

    D
    UARTA_P80_EN 2
    OE# S FUNCTION G L2N7002KWT1G_SOT323-3
    Q56
    H X DISABLE S Debug@
    3

    Security Classification LC Future Center Secret Data Title


    L L D(+/-) to 1D(+/-)

    L H D(+/-) to 2D(+/-) Issued Date 2016/08/16 Deciphered Date 2017/08/15 USB3.0 PORT (LEFT)
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 330ARR
    Date: Friday, March 23, 2018 Sheet 28 of 52
    A B C D E
    5 4 3 2 1

    D
    Remove type-c redriver D

    +3VALW
    +3V_MUX +5VALW +5V_MUX
    R133 1 @ 2 0_0402_5% R173 1 @ 2 0_0402_5%

    +3VS +5VS
    VBUS_P0
    R134 1 @ 2 0_0402_5% R174 1 @ 2 0_0402_5%

    3A
    U26

    2 2
    +5VALW 1.5A
    TYPE_C_OCP# 16
    VBUS_EN OCP_DET 1
    15 CC1271 CC1272 1

    25
    26
    27
    28
    VBUS_EN 220P_0201_25V7-K 220P_0201_25V7-K C213 + C1333 JP1 ME@
    1 1 47U_0805_6.3V6-M 150U_B2_6.3VM_R35M
    VBUS_P0

    GND5
    GND6
    GND7
    GND8
    VMON 17 12 CC1 A5 @
    VMON CC1 14 CC2 B5 2 2 24 1
    C CC2 Power_GND_B12 GND_A1 C
    C_RX1_P_C 23 2 C_TX1_P_C
    11 MUX_TX2_N C2076 1 2 0.1U_0402_10V7K C_TX2_N U6 SSRXp1_B11 SSTXp1_A2
    B3
    C_TX2_1P/2N 10 MUX_TX2_P C2075 1 2 0.1U_0402_10V7K C_TX2_P B2 5 1 C_RX1_N_C 22 3 C_TX1_N_C
    C_TX2_1N/2P IN OUT SSRXn1_B10 SSTXn1_A3
    C2068 1 2 0.1U_0402_10V7K USB30_RX_N3_M 4 24 C_RX2_N A10 2 21 4
    9 USB30_RX_N3 USB30_RX_P3_M SSRX_1P/2N C_RX2_1P/2N C_RX2_P GND VBUS_B9 VBUS_A4
    C2067 1 2 0.1U_0402_10V7K 5 1 A11
    9 USB30_RX_P3 SSRX_1N/2P C_RX2_1N/2P VBUS_EN TYPE_C_OCP#
    10Gbps 2:1 MUX 4 3 20 5 CC1
    USB30_TX_N3_M MUX_TX1_N C2073 1 C_TX1_N EN OCB TYPE_C_OCP# 9 SBU2_B8 CC1_A5

    Vinafix.com
    C2065 1 2 0.1U_0402_10V7K 6 8 2 0.1U_0402_10V7K A3
    9 USB30_TX_N3 USB30_TX_P3_M SSTX_1P/2N C_TX1_1P/2N MUX_TX1_P C2074 1 C_TX1_P C_DM C_DP
    C2066 1 2 0.1U_0402_10V7K 7 9 2 0.1U_0402_10V7K A2 High active SY6288C20AAC_SOT23-5 1 19 6
    9 USB30_TX_P3 SSTX_1N/2P C_TX1_1N/2P Dn2_B7 Dp1_A6
    C8791
    2 C_RX1_N B10 1000P_0201_50V7-K C_DP 18 7 C_DM
    C_RX1_1P/2N 3 C_RX1_P B11 EMC_NS@ Dp2_B6 Dn1_A7
    C_RX1_1N/2P 2 CC2 17 8
    +5V_MUX CC2_B5 SBU1_A8
    13 16 9
    VCON_IN R171 1 @ 2 0_0402_5% VBUS_B4 VBUS_A9
    23 C_TX2_N_C 15 10 C_RX2_N_C
    Realtek

    0.1U_0201_6.3V6-K
    M1 21 NC 19 R172 1 2 0_0402_5% SSTXn2_B3 SSRXn2_A10

    10U_0402_6.3V6M
    22 RP_SEL_M1 5V_IN +3V_MUX C_TX2_P_C 14 11 C_RX2_P_C
    M0
    RP_SEL_M0 RTS5449 2 1 SSTXp2_B2 SSRXp2_A11
    20

    C2063

    C2077
    0.1U_0201_6.3V6-K
    LDO_3V3 13 12
    4.7U_0402_6.3V6M

    GND_B1 GND_A12
    C2064

    1 2

    GND12
    GND11
    GND10
    1 2

    GND9
    18 25
    VBUS_P0
    CC1273

    REXT E-PAD
    2

    VBUS_P0
    R3150 RTS5449-GR_QFN24_4X4 2 1 HIGHS_UB11246-15A0C-1H

    32
    31
    30
    29
    6.2K_0402_1%

    1
    Close Pin13
    1

    R3155

    4.7U_0805_25V6-K

    0.47U_0402_25V6K

    0.47U_0402_25V6K

    0.47U_0402_25V6K

    0.47U_0402_25V6K
    Close Pin19 200K_0402_1%

    10U_0805_25V6K
    1 1 1 1 1 09/02 Update Type-C Conn. DC021608291 wei

    C918

    C919

    C922

    C921

    C920

    C1334
    D38

    1
    VMON

    SPHV24-01ETG-C_SOD882-2
    @

    1
    2 2 2 2 2

    1
    EMC_NS@
    2
    +3V_MUX +3V_MUX
    Rp configuration
    R3149
    10K_0402_1%
    2

    2
    Rp:1.5A (now) 1
    R3139 R3142

    2
    10K_0402_5% @ 10K_0402_5%
    B
    M1 M0 Note B

    Rp:900mA 0 1 R3144/R3142 mount


    1

    M1 M0 R943 1 @ 2 0_0402_5% R3135 1 @ 2 0_0402_5% CC1 C_DP


    Rp:1.5A 1 0 R3139/R3143 mount CC2 C_DM
    2

    L23 EMC@ L31 EMC@


    Rp:3.0A 1 1 R3139/R3142 mount C_DP C_RX1_N C_RX1_N_C

    2
    R3144 R4674 1 2 4 3 D47 EMC_NS@ D48 EMC_NS@
    9 USB20_P7 1 2 4 3
    @ 10K_0402_5% 10K_0402_5%

    4 3 C_DM C_RX1_P 1 2 C_RX1_P_C


    9 USB20_N7 4 3 1 2
    1

    EXC24CH900U_4P EXC24CH900U_4P
    R3137 1 @ 2 0_0402_5%
    R91 1 @ 2 0_0402_5%

    +3V_MUX R3136 1 @ 2 0_0402_5%


    For C_VBUS
    R944 2 @ 1 0_0402_5%
    power switch enable pin L32 EMC@ AZC199-02S.R7G_SOT23-3 AZC199-02S.R7G_SOT23-3
    C_TX1_P C_TX1_P_C

    1
    2

    L24 EMC@ 4 3
    R3146 C_TX2_N 3 4 C_TX2_N_C 4 3
    10K_0402_5% 3 4
    @ 1 2
    C_TX2_P 2 1 C_TX2_P_C 1 2
    Power switch enable pin Note 2 1
    1

    EXC24CH900U_4P
    VBUS_EN EXC24CH900U_4P C_TX1_N R3138 1 @ 2 0_0402_5% C_TX1_N_C
    Low Active R3146 mount
    2

    R3107 2 @ 1 0_0402_5%
    R3141 High Active R3141 mount
    10K_0402_5%
    R100 2 @ 1 0_0402_5%
    1

    L25 EMC@
    C_RX2_P 3 4 C_RX2_P_C D36 EMC_NS@ D20 EMC_NS@
    3 4 C_TX2_P_C 9 1 C_TX2_P_C C_TX1_P_C 9 1 C_TX1_P_C
    10 1 10 1
    C_RX2_N 2 1 C_RX2_N_C C_TX2_N_C 8 2 C_TX2_N_C C_TX1_N_C 8 2 C_TX1_N_C
    9 2 9 2
    +3V_MUX 2 1
    For C_VBUS C_RX1_N_C 7 C_RX1_N_C C_RX2_N_C 7 C_RX2_N_C
    EXC24CH900U_4P 7 4 4 7 4 4
    power switch OCP pin
    PH at CPU side 09/06 wei C_RX1_P_C 6 C_RX1_P_C C_RX2_P_C 6 C_RX2_P_C
    2

    R101 2 @ 1 0_0402_5% 6 5 5 6 5 5
    R3147
    @ 10K_0402_5% 3 3 3 3

    Note 8 8
    Power switch OCP pin
    1

    A TYPE_C_OCP# AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9 A


    Low Active R3147 mount For ESD
    High Active R3140 mount
    2

    R3140
    @ 10K_0402_5%
    1

    Security Classification LC Future Center Secret Data Title


    Issued Date 2016/08/16 Deciphered Date 2017/08/15 Type-C RTS5449
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 330ARR
    Date: Friday, March 23, 2018 Sheet 29 of 52
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B
    Vinafix.com B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2016/08/16 Deciphered Date 2017/08/15 Blank
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    B
    330ARR 1.0

    Date: Friday, March 23, 2018 Sheet 30 of 52


    5 4 3 2 1
    5 4 3 2 1

    for USB HUB update to OHY50, manual modify PN to GL850G-OHY50 +VDD


    +3VS @
    @ RH15 1 2 V5
    RH1 1 2 0_0603_5% 0_0603_5%
    +5VALW
    D UH1 +3VALW +VDD D

    0604
    1 @ 2 V5
    USB20_N5_HUB_R 1 28 +VDD 1 2 RH2 0_0603_5%
    USB20_P5_HUB_R 2 DM0 V33 27 V5 @ RH3 0_0603_5%
    USB20_N1_C 3 DP0 V5 26 SDA_HUB 1 TP271 @
    USB20_P1_C DM1 PWREN1#/SDA
    4
    DP1 GL850G OVCUR1#/SMC
    25 ** External regulator mode：
    +AVDD 5 24
    USB20_N3 6 AVDD QFN28 OVCUR2#/SMD 23 PGANG
    RH1 install， RH2 non-install,RH15 install
    USB20_P3 7 DM2 PGANG 22 PSELF Internal regulator mode：
    RREF_HUB DP2 PSELF
    8
    RREF DVDD
    21 RH4 1 @ 2+VDD 1 RH1 non-install， RH2 install,RH15 non-install
    +AVDD 9 20 0_0402_5% CH1
    XTAL12_IN 10 AVDD1 OVCUR3# 19 0.1U_0201_6.3V6-K
    XTAL12_OUT 11 X1 OVCUR4# 18 TEST/SCL 1 TP270 @ USB_HUB@
    USB20_N2 12 X2 TEST/SCL 17 HUB_RESET# 2
    USB20_P2 13 DM3 RESET# 16 +VDD +AVDD +AVDD
    +AVDD 14 DP3 DP4 15
    AVDD2 DM4 RH6

    XTAL12_IN

    XTAL12_OUT
    YH1
    0604
    29 1 2

    CH4

    CH5

    CH6

    CH7

    CH8
    @
    PAD

    .1U_0402_10V6-K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    .1U_0402_10V6-K
    0.1U_0201_6.3V6-K
    1 3 1 0_0603_5% 1 1 1 1 1 1
    OSC1 OSC2 CH2 CH3
    2 4 10U_0603_6.3V6M 0.1U_0201_6.3V6-K
    C GND1 GND2 C
    GL850G-OHY50_QFN28_5X5 1 1 USB_HUB@ USB_HUB@ USB_HUB@ CD@
    USB_HUB@ 2 2 2 2 2 2 2

    Vinafix.com
    CH9 CH10 @ CD@
    15P_0402_50V8J 12MHZ_10PF_7V12000008 18P_0402_50V8J USB_HUB@
    2 2
    USB_HUB@ USB_HUB@ USB_HUB@ As close to GL850G
    PORT1 Camera CH2 close to PIN28
    CH3 PIN5 CH4/CH5 PIN9 CH6/CH15 PIN14
    PORT2 FP As close to GL850G
    PORT3 Touch Screen

    USB20_N5_HUB
    USB20_P5_HUB USB20_N5_HUB 9 +5VALW +VDD
    USB20_P5_HUB 9

    USB20_P1
    USB20_N1 USB20_P1 26
    USB20_N1 26 Camera Vienna change to 619 ohm for Eye Diagram test

    1
    USB20_P3 RH8 RH9
    USB20_N3 USB20_P3 40
    B USB20_N3 40 Finger Print 10K_0402_5% 10K_0402_5%
    RH11 B
    @ USB_HUB@
    USB20_P2 RREF_HUB 1 2
    USB20_P2 26

    2
    USB20_N2 Touch Screen
    USB20_N2 26 HUB_RESET# 680_0402_1%
    USB_HUB@

    1
    1
    CH11 RH12
    USB20_N5_HUB RH16 1 NFPTS@2 0_0201_5% USB20_N1 1U_0402_6.3V6K 47K_0402_5% PGANG 1 RH13 2 Individual Mode
    USB20_P5_HUB RH17 1 NFPTS@2 0_0201_5% USB20_P1 USB_HUB@ @ 100K_0402_5%
    2
    USB_HUB@

    2
    USB_HUB@ +VDD
    USB20_N5_HUB RH18 1 2 0_0201_5% USB20_N5_HUB_R
    USB_HUB@
    USB20_P5_HUB RH19 1 2 0_0201_5% USB20_P5_HUB_R
    PSELF 1 RH14 2 Self-power
    USB_HUB@ 10K_0402_5%
    USB20_N1_C RH20 1 2 0_0201_5% USB20_N1 USB_HUB@
    USB_HUB@
    USB20_P1_C RH21 1 2 0_0201_5% USB20_P1

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/15 Deciphered Date 2013/08/15 USB HUB
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    B
    330ARR 1.0

    Date: Friday, March 23, 2018 Sheet 31 of 52


    5 4 3 2 1
    5 4 3 2 1

    +3VALW TO +3VALW_LAN
    +3VALW_LAN rising t i me ( 10 %~90 %):
    +3VALW +3VALW_LAN
    0.5ms＜s pec＜ 1 0 0m
    s +3VALW_LAN +LAN_VDDREG
    Need short
    JL1 1 2 @ width : 40 mils RL1 1
    @
    2 0_0603_5%
    1 2
    JUMP_43X79
    D 1 1 D
    +3VALW LP2301ALT1G_SOT23-3 CL1 CL2

    4.7U_0402_6.3V6M

    4.7U_0402_6.3V6M

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K
    1 1 1 1 4.7U_0402_6.3V6M 0.1U_0201_6.3V6-K
    Q14 3 1 @ CL4 CL5 CL6 CL7

    D
    2 2

    0.01U_0201_10V6K
    SIT1CD@ SIT1CD@
    RL2 1 1
    100K_0402_5% CL8 CL9 2 2 2 2

    G
    2
    @ 0.1U_0201_6.3V6-K
    @ @

    2
    2 2
    SIT1CD@ SIT1CD@
    RL3 1 @ 2
    39 LAN_PWR_ON#
    47K_0402_5%
    Close to Pin11 Close to Pin32 Close to Pin11 Close to Pin32

    +3VALW_LAN +3VS

    2
    +3VALW_LAN

    2
    RL4

    G
    10K_0402_5% QL1
    2

    @
    RL5

    1
    10K_0402_5% UL1 LAN_CLKREQ#_R 1 3 @
    LAN_CLKREQ# 8
    @

    S
    2N7002KW_SOT323-3
    1

    RL7 1 @ 2 0_0402_5% PCIE_WAKE#_R


    7,35,39 PCIE_WAKE#
    C
    35,39 LAN_WAKE# RL6 1 @ 2 0_0402_5% RL18 1 @ 2 0_0402_5% C
    33
    32 +3VALW_LAN GND 16 CLK_PCIE_LAN#
    AVDD33_2 REFCLK_N CLK_PCIE_LAN CLK_PCIE_LAN# 8
    RL8 1 2 31 RSET 15

    Vinafix.com
    30 +LAN_VDD10 RSET REFCLK_P 14 PCIE_PTX_C_DRX_N2 CLK_PCIE_LAN 8
    2.49K_0402_1%
    29 LAN_XTALO AVDD10 HSIN 13 PCIE_PTX_C_DRX_P2 PCIE_PTX_C_DRX_N2 4 APU CLKREQ all both 3VS power plane
    28 LAN_XTALI CKXTAL2 HSIP 12 LAN_CLKREQ#_R PCIE_PTX_C_DRX_P2 4
    +3VS TL3 @ 1 27 CKXTAL1 CLKREQB 11 +3VALW_LAN
    LAN_PWR_ON# 1
    RL12 @ 2 LAN_DISABLE# 26 LED0 AVDD33_1 10 LAN_MDI3-
    LED1/GPIO MDIN3 LAN_MDI3+ LAN_MDI3- 33
    0_0402_5% TL4 @ 1 25 9
    +LAN_REGOUT LED2 MDIP3 +LAN_VDD10 LAN_MDI3+ 33
    1

    24 8
    RL9 +LAN_VDDREG 23 REGOUT AVDD10_2 7 LAN_MDI2-
    +LAN_VDD10 VDDREG MDIN2 LAN_MDI2+ LAN_MDI2- 33
    1K_0402_1% 22 6
    PCIE_WAKE#_R 21 DVDD10 MDIP2 5 LAN_MDI1- LAN_MDI2+ 33
    LANW AKEB MDIN1 LAN_MDI1+ LAN_MDI1- 33
    ISOLATE# 20 4
    ISOLATEB MDIP1 LAN_MDI1+ 33
    2

    PLT_RST# 19 3 +LAN_VDD10
    7,17,35 PLT_RST# PCIE_PRX_C_DTX_N2 PERSTB AVDD10_1 LAN_MDI0-
    4 PCIE_PRX_DTX_N2 CL10 2 1 0.1U_0201_6.3V6-K 18 2
    LAN_PWR_ON# HSON MDIN0 LAN_MDI0- 33
    ISOLATE# RL10 1 @ 2 CL11 2 1 0.1U_0201_6.3V6-K PCIE_PRX_C_DTX_P2 17 1 LAN_MDI0+
    4 PCIE_PRX_DTX_P2 HSOP MDIP0 LAN_MDI0+ 33
    0_0402_5% CL10 close to Pin18 2018/01/24: add AZ5815-01F.R7GR for
    1

    RL11 CL11 close to Pin17 RTL8111H Lan Surge issue


    15K_0402_5%
    @ +LAN_VDD10
    2

    RTL8111GUL-CG_QFN32_4X4
    8111GUL@

    1
    DL4

    1
    AZ5815-01F.R7GR_DFN1006P2E
    B B
    EMC_8111H@

    2
    2
    For RTL8111GUL/ RTL8106EUL (SWR mode)
    LAN_XTALI
    For RTL8111H (LDO mode) RL19 stuf f Change part number
    YL1 LAN_XTALO 8111H@ +LAN_VDD10
    RL19 1 2 0_0805_5%
    1 4
    OSC1 GND2
    2 3 +LAN_REGOUT LL1 1 2
    GND1 OSC2 2.2UH_NLC252018T-2R2J-N_5%
    1 1 8111GUL@ 1 1 1 1 1 1 1 1
    CL12 25MHZ_10PF_7V25000014 CL13
    Layout Note: LL1 must be CL15
    4.7U_0402_6.3V6M
    CL16
    0.1U_0201_6.3V6-K
    CL17
    0.1U_0201_6.3V6-K
    CL18
    0.1U_0201_6.3V6-K
    CL19
    0.1U_0201_6.3V6-K
    CL20
    0.1U_0201_6.3V6-K CL21
    CL22
    0.1U_0201_6.3V6-K
    10P_0402_50V8J 12P_0402_50V8-J within 200mil to Pin24, 1U_0402_6.3V6K @
    2 2 CL15,CL16 must be within 2 2 2 2 2 2 2 @ 2
    200mil to LL1
    +LAN_REGOUT: Width =60mil
    Close to Pin3, 8, 22, 30 Close to Pin22(Reserved)
    follow G CarrizoL 10pf

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/08 Deciphered Date 2013/08/05 LAN_RTL8111GUL
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Custom
    330ARR 1.0

    Date: Friday, March 23, 2018 Sheet 32 of 52


    5 4 3 2 1
    5 4 3 2 1

    TL1
    DL1 TCT 24 1 MCT
    LAN_MDI3+ 4 3 LAN_MDI2- MCT1 TCT1
    I/O3 I/O2 LAN_MDI0+ 23 2 LAN_MDO0+
    32 LAN_MDI0+ MX1+ TD1+
    LAN_MDI0- 22 3 LAN_MDO0-
    32 LAN_MDI0- MX1- TD1-

    1
    5 2 8111GUL@
    VDD GND 21 4 MCT RL17
    MCT2 TCT2 20_0603_5%
    LAN_MDI1+ LAN_MDO1+

    1
    20 5
    D LAN_MDI3- LAN_MDI2+ 32 LAN_MDI1+ MX2+ TD2+ D
    6 1 DL3

    1
    I/O4 I/O1

    2
    LAN_MDI1- 19 6 LAN_MDO1- BS4200N-C-LV_SMB-F2
    32 LAN_MDI1- MX2- TD2-
    AZ1135-04S.R7G_SOT23-6L-6 8111GUL@
    18 7 MCT EMC

    2
    EMC_8111H@
    MCT3 TCT3

    2
    LAN_MDI2+ 17 8 LAN_MDO2+
    32 LAN_MDI2+ MX3+ TD3+
    LAN_MDI2- 16 9 LAN_MDO2-
    32 LAN_MDI2- MX3- TD3-
    DL2 15 10 MCT
    LAN_MDI1+ 4 3 LAN_MDI0- MCT4 TCT4
    I/O3 I/O2 1 1
    LAN_MDI3+ 14 11 LAN_MDO3+ CL32 CL25
    32 LAN_MDI3+ MX4+ TD4+ 0.022U_0603_50V7K 1000P_1206_2KV7-K
    LAN_MDI3- 13 12 LAN_MDO3- 8111GUL@ 8111GUL@
    32 LAN_MDI3- MX4- TD4- 2 2
    5 2 1 EMC
    VDD GND CL24
    0.01U_0201_25V6-K BOTH_GST5009 LF
    8111GUL@ 8111GUL@
    LAN_MDI1- 6 1 LAN_MDI0+ 2
    I/O4 I/O1
    AZ1135-04S.R7G_SOT23-6L-6 EMC
    EMC_8111H@
    CHASSIS1_GND
    C C
    Place Close to TL1
    Change part number EMC

    Vinafix.com
    TL2
    LAN_MDI0+ 23 2 LAN_MDO0+
    TD1+ MX1+
    LAN_MDI0- 22 3 LAN_MDO0-
    TD1- MX1-
    LAN_MDI1+ 20 5 LAN_MDO1+
    TD2+ MX2+
    LAN_MDI1- 19 6 LAN_MDO1-
    TD2- MX2-
    LAN_MDI2+ 17 8 LAN_MDO2+
    TD3+ MX3+
    LAN_MDI2- 16 9 LAN_MDO2- JRJ1 ME@
    TD3- MX3- 12
    LAN_MDI3+ 14 11 LAN_MDO3+ GND_4
    TD4+ MX4+ 11
    LAN_MDI3- 13 12 LAN_MDO3- GND_3
    TD4- MX4- 10
    24 4 LAN_MDO0+ 1 GND_2
    TCT1 NC1 TX_DA+ 9
    21 7 LAN_MDO0- 2 GND_1
    B B
    TCT2 NC2 TX_DA-
    18 10 LAN_MDO1+ 3
    TCT3 NC3 RX_DB+ CHASSIS1_GND
    TCT 15 1 MCT LAN_MDO2+ 4
    TCT4 GND BI_DC+
    LAN_MDO2- 5
    AJOHO_N-8660GR BI_DC-
    @ LAN_MDO1- 6
    8111H@ RX_DB-
    RL14 1 2 0_0603_5%
    @ LAN_MDO3+ 7
    RL15 1 2 0_0603_5% BI_DD+
    @ LAN_MDO3- 8
    RL16 1 2 0_0603_5% BI_DD-
    MCT 1
    PJ5909
    2
    @
    @
    RL20 1 2 0_0603_5% 1 2 ALLTO_C10235-10839-L
    JUMP_43X39

    EMC CHASSIS1_GND

    CHASSIS1_GND

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/08 Deciphered Date 2013/08/05 LAN_Transformer
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Custom
    330ARR 1.0

    Date: Friday, March 23, 2018 Sheet 33 of 52


    5 4 3 2 1
    5 4 3 2 1

    R175 1 @ 2 0_0402_5% REMOTE1+

    Close to U1 REMOTE+_R R176 1 @ 2 0_0402_5% REMOTE2+ REMOTE1+


    Near GPU&VRAM REMOTE2+
    Near CPU core
    1
    REMOTE+_R

    1
    C46 C
    1

    1
    1 C45 C 100P_0201_25V8J 2 Q16
    C44 REMOTE-_R R177 1 @ 2 0_0402_5% REMOTE2- 100P_0201_25V8J 2 Q15 @ B MMBT3904WH_SOT323-3
    2200P_0402_25V7-K @ B MMBT3904WH_SOT323-3 2 E @

    3
    @ 2 E @ REMOTE2-

    3
    2 REMOTE-_R R178 1 @ 2 0_0402_5% REMOTE1- REMOTE1-

    D D
    +3VALW
    REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-: +3VALW
    Trace width/space:10/10 mil Near CPU
    Trace length:<8"

    1
    R17
    13.7K_0402_1% R25
    SMSC thermal sensor PX@ 13.7K_0402_1%

    placed near DIMM

    2
    NTC_V1

    2
    NTC_V2

    1
    +3VS

    1
    U1 PH2
    1 8 THERMAL_SMB_CK2 100K_0402_1%_NCP15WF104F03RC PH3
    VDD SCL THERMAL_SMB_CK2 39
    PX@ 100K_0402_1%_NCP15WF104F03RC
    REMOTE+_R 2 7 THERMAL_SMB_DA2
    1 D+ SDA THERMAL_SMB_DA2 39

    2
    C47

    2
    0.1U_0201_6.3V6-K REMOTE-_R 3 6
    D- ALERT#

    2
    @
    2

    2
    +3VS R51 2 @ 1 4 5 R184 R185
    10K_0402_5% T_CRIT# GND @ R191 R192
    0_0402_5% 0_0402_5%
    NCT7718W_MSOP8 @ 0_0402_5% 0_0402_5%
    @
    Address 1001_101xb @

    1
    @

    1
    +5VLP +5VLP EC_AGND
    C C
    +5VLP EC_AGND
    +3VS +3VS

    HW thermal sensor

    Vinafix.com 2
    1 R252 R253

    2
    1
    C4 21.5K_0402_1% 21.5K_0402_1%
    0.1U_0201_6.3V6-K @ @ R4688
    @ 2.2K_0404_4P2R_5%

    1
    2

    2
    @ @

    G
    U4

    3
    4
    1 8 TMSNS1 R196 1 @ 2 0_0402_5% NTC_V1 Q160A
    VCC TMSNS1 NTC_V1 39
    2 7 PHYST1 R6 1 @ 2 10K_0402_5% THERMAL_SMB_CK2 R4689 1 @ 2 1 6 @

    S
    GND RHYST1 EC_SMB_CK2 39,49

    D
    3 6 TMSNS2 R197 1 @ 2 0_0402_5% NTC_V2 0_0402_5% 2N7002KDWH_SOT363-6
    48 EC_ON_R OT1 TMSNS2 NTC_V2 39

    5
    G
    4 5 PHYST2 R7 1 @ 2 10K_0402_5%
    OT2 RHYST2 Q160B
    G718TM1U_SOT23-8
    THERMAL_SMB_DA2 R4690 1 @ 2 4 3 @

    S
    EC_SMB_DA2 39,49

    D
    over temperature threshold: 0_0402_5% 2N7002KDWH_SOT363-6
    RSET=3*RTMH +3VALW

    92+/-30C +3VS RTPM12 1 @ 2 0_0603_5%


    +3VS_TPM
    Hysteresis temperature threshold. RTPM1 1 TPM@ 2 0_0603_5%
    B
    RHYST=(RSET*RTML)/(3*RTML-RSET) 20mA 1 1
    B

    CTPM3
    56+/-30C CTPM1 0.1U_0201_6.3V6-K
    10U_0603_6.3V6M TPM@
    2 @ 2
    TPM
    +3VS_TPM
    UTPM1 TPM@
    1 24
    F5 NEC@ 2 NC_1 VDD3 10
    1 2 3 NC_2 VDD1
    FAN Conn RTPM13 1 @ 2 0_0402_5% 7 NC_3
    PP LPCPD#
    28 RTPM2 1 TPM@ 2 10K_0402_5%
    +5VS 1A_32V_ERBRD1R00X 27 SERIRQ_TPM RTPM5 1 TPM@ 2 0_0402_5%
    SERIRQ LPC_AD0_TPM SERIRQ 8,13,39
    6 26 RTPM6 1 TPM@ 2 0_0402_5%
    NC_4 LAD0 LPC_AD1_TPM LPC_AD0 8,13,39
    JFAN1 9 23 RTPM7 1 TPM@ 2 0_0402_5%
    +5VS_FAN NC_7 LAD1 LPC_FRAME#_TPM LPC_AD1 8,13,39
    R4682 1 2 0_0603_5% 1 22 RTPM8 1 TPM@ 2 0_0402_5%
    1 LFRAME# LPC_AD2_TPM LPC_FRAME# 8,13,39
    39 EC_FAN_SPEED 2 4 20 RTPM9 1 TPM@ 2 0_0402_5%
    2 GND_1 LAD2 LPC_AD3_TPM LPC_AD2 8,13,39
    NONEC@ 39 EC_FAN_PWM 3 11 17 RTPM10 1 TPM@ 2 0_0402_5%
    3 GND_2 LAD3 LPC_AD3 8,13,39
    1 1 2 4 18
    C2080 C2081 CC1280 5 4 GND_3 25 +3VS_TPM
    10U_0603_6.3V6M 0.1u_0201_10V6K 10U_0402_6.3V6M 6 GND1 RTPM14 1 @ 2 0_0603_5% 5 GND_4 21
    GND2 +3VALW NC_5 LCLK TPM_CLK 8
    @ @ 8 19
    2 2 1 ACES_85205-04001 RTPM15 1 @ 2 0_0603_5% 12 NC_6 VDD2 15 RTPM11 1 TPM@ 2 0_0402_5%
    +3VS NC_8 CLK_RUN#
    ME@ 13 RTPM16 1 TPM@ 2 0_0402_5% LPC_CLKRUN# 8,13
    14 NC_9 16
    NC_10 LRESET# APU_LPC_RST# 8,13,39

    A A
    Z32H320TC_TSSOP28

    Security Classification LC Future Center Secret Data Title

    Issued Date 2013/08/08 Deciphered Date 2013/08/05 Thermal sensor/FAN CONN/TPM


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 330ARR
    Date: Friday, March 23, 2018 Sheet 34 of 52
    5 4 3 2 1
    A B C D E

    Mini-Express Card(WLAN/WiMAX)

    1 1

    +3VS_W LAN
    +3VS Need short
    J2 @
    1 2 1
    1 2 C53
    JUMP_43X79 0.1U_0201_6.3V6-K
    @ +3VS_W LAN
    2

    JW LAN1 ME@
    1 2
    3 GND1 3.3VAUX1 4
    9 USB20_P0 USB_D+ 3.3VAUX2
    5 6 1 @ T7
    9 USB20_N0 USB_D- LED1#
    7 8
    9 GND2 PCM_CLK/I2S_SCK 10
    11 SDIO_CLK PCM_SYNC/I2S_WS 12
    13 SDIO_CMD PCM_IN/I2S_SD_IN 14
    15 SDIO_DATA0 PCM_OUT/I2S_SD_OUT 16 1 @ T6
    17 SDIO_DATA1 LED#2 18
    19 SDIO_DATA2 GND11 20
    21 SDIO_DATA3 UART_WAKE# 22
    23 SDIO_WAKE# UART_RXD
    2 SDIO_RESET# 2

    KEY E
    25 PIN24~PIN31 NC PIN 24
    27 26

    Vinafix.com
    29 28
    31 30

    33 32
    35 GND3 UART_TXD 34
    4 PCIE_PTX_C_DRX_P1 PETP0 UART_CTS
    37 36
    4 PCIE_PTX_C_DRX_N1 PETN0 UART_RTS
    39 38
    41 GND4 VENDOR_DEFINED1 40
    4 PCIE_PRX_DTX_P1 PERP0 VENDOR_DEFINED2
    43 42
    4 PCIE_PRX_DTX_N1 PERN0 VENDOR_DEFINED3
    45 44 R88 1 @ 2 0_0402_5%
    GND5 COEX3 EC_RX 28,39
    47 46
    8 CLK_PCIE_W LAN REFCLKP0 COEX2
    49 48
    8 CLK_PCIE_W LAN# REFCLKN0 COEX1 SUSCLK_R
    51 50 R55 1 2 0_0402_5%
    W LAN_CLKREQ_Q# GND6 SUSCLK PLT_RST# SUSCLK 8
    8 W LAN_CLKREQ# R61 1 @ 2 0_0402_5% 53 52
    PCIE_W AKE#_W LAN CLKREQ0# PERST0# BT_OFF# PLT_RST# 7,17,32
    R262 1 @ 2 0_0402_5% 55 54 R53 1 2 1K_0402_5%
    7,32,39 PCIE_W AKE# PEWAKE0# W_DISABLE2# W LAN_OFF# PCH_BT_OFF# 8
    R57 1 @ 2 0_0402_5% 57 56 R56 1 @ 2 0_0402_5%
    32,39 LAN_W AKE# GND7 W_DISABLE1# PCH_W LAN_OFF# 8

    59 58 APU_SMB_DATA_R R58 1 @ 2 0_0402_5%


    RSRVD/PETP1 I2C_DATA APU_SMB_CLK_R APU_SMB_DATA 7,14
    61 60 R59 1 @ 2 0_0402_5%
    RSRVD/PETN1 I2C_CLK APU_SMB_CLK 7,14
    63 62
    65 GND8 ALERT# 64 EC_TX_R R89 1 @ 2 0_0402_5%
    RSRVD/PERP1 RSRVD EC_TX 28,39
    67 66
    69 RERVD/PERN1 UIM_SWP/PERST1# 68 +3VS_W LAN
    GND9 UIM_POWER_SNK/CLKREQ1#

    1
    71 70
    3 73 RSRVD/REFCLKP1 UIM_POWER_SRC/GPIO1/PEWAKE1# 72 R186 3
    75 RSRVD/REFCLKN1 3.3VAUX3 74 100K_0402_5%
    GND10 3.3VAUX4
    77 76
    GND15 GND14

    2
    +3VS

    ARGOS_NASE0-S6701-TS40

    1
    C8793
    0.1U_0201_6.3V6-K
    @
    2
    U130
    5 1
    Vcc OE
    2 SUSCLK
    IN_A
    SUSCLK_R 4 3
    OUT_Y GND

    M74VHC1GT125DF2G_SC70-5
    @

    4 4

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/08 Deciphered Date 2013/08/05 NGFF WLAN
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 330ARR
    Date: Friday, March 23, 2018 Sheet 35 of 52
    A B C D E
    5 4 3 2 1

    DVDD_IO
    +3VALW

    RA213 1 @ 2 0_0402_5% Digital power for HDA link +1.8VS +1.8V_AUDIO

    +3VS RA225 2 @ 1 0_0402_5%


    2
    RA216 1 @ 2 0_0402_5% CA2 8/29 Add +1.8VS Circuit for Audio wei
    0.1U_0201_6.3V6-K
    +1.8VS Close to1 Pin7
    RA227 2 @ 1 0_0402_5%
    UA1
    +1.8VALW DMIC_DATA RA19 2 @ 1 0_0402_5% DMIC_DATA_R 1 30
    26 DMIC_DATA DMIC_CLK DMIC_CLK_R HD-GPIO0/DMIC-DATA CR-GPIO SD_CD#
    RA18 2 @ 1 0_0402_5% 2 31
    26 DMIC_CLK HDA_SDOUT_AUDIO 3 HD-GPIO1/DMIC-CLK CR-SD-CD 32 SD_WP SD_CD# 37
    RA228 2 @ 1 0_0402_5%
    7 HDA_SDOUT_AUDIO HDA_BITCLK_AUDIO 4 HD-SDATA-OUT CR-SD-WP 33 SD_D1_R SD_WP 37
    D 7 HDA_BITCLK_AUDIO 5 HD-BCLK CR-SD-DAT[1] 34 SD_D0_R SD_D1_R 37 D
    CA1 1 2
    Analog power for mixers, & IO ports Power supply for full-bridge left/Right channel HDA_SDIN0 RA16 1
    2.2U_0402_6.3V6M
    2 33_0402_5% SDATA_IN 6 HD-LDO3-CAP CR-SD-DAT[0] 35 SD_CLK_R SD_D0_R 37
    +5VS +5VA +5VS +5VD 7 HDA_SDIN0 7 HD-SDATA-IN CR-SD-CLK 36 SD_CLK_R 37
    +5VA
    DVDD_IO HDA_SYNC_AUDIO HD-DVDD-IO HD-AVDD1 LDO1_CAP
    EMC_NS@ 8 37 CA43 1 2 2.2U_0402_6.3V6M CA48 1 2 1U_0402_6.3V6K
    7 HDA_SYNC_AUDIO 2 100K_0402_1%PC_BEEP 9 HD-SYNC HD-LDO1-CAP 38
    @ LA25 1 2 BLM15PD600SN1D_2P
    +3VS RA205 1 CA44 1 2 1U_0402_6.3V6K
    RA7 1 2 0_0603_5% @ PLUG_IN RA204 1 2 200K_0402_1%JSENSE 10 HD-PCBEEP HD-VREF 39 MICBIASB
    RA10 1 2 0_0603_5% RING2_CONN 11 HD-JD1(HP/LINE1) HD-MIC2-VREFO 40 LINE1_VREF_L +1.8V_AUDIO
    RING3_CONN 12 HD-MIC2-L(RING) HD-LINE1-VREFO-L 41 HPOUT_L
    VDD_STB 13 HD-MIC2-R(SLEEVE) HD-HPOUT-L 42 HPOUT_R
    2 2 HD-3V5V-STB HD-HPOUT-R
    1 RA38 2 2.2K_0402_5% CA41 1 2 14 43 CA47 1 2 1U_0402_6.3V6K +1.8V_AUDIO

    CA178 10U_0603_6.3V6M

    CA18 0.1U_0201_6.3V6-K

    CA19 0.1U_0201_6.3V6-K
    1 2 2 2.2U_0402_6.3V6M
    CA42 CA20 LINE1_R 15 HD-MIC2-CAP HD-CPVEE 44
    0.1U_0201_6.3V6-K 1U_0402_6.3V6K MICBIASB 1 RA37 2 2.2K_0402_5% LINE1_L 16 HD-LINE1-R HD-CBN 45 4.7U_0603_6.3V6K 2 1 CA4
    1 1 17 HD-LINE1-L HD-CPVDD 46
    2 1 1 18 HD-LINE2-R HD-CBP 47 HD_LDO2 CA185 1 2 10U_0603_6.3V6M @
    SD_CMD_R 19 HD-LINE2-L HD-LDO2-CAP 48
    37 SD_CMD_R SD_D3_R 20 CR-SD-CMD HD-AVDD2 49
    37 SD_D3_R SD_D2_R 21 CR-SD-DAT[3] HD-PVDD1 50
    +5VD
    SPK_L+ Analog power for DACs, ADCs
    37 SD_D2_R 1 2 22 CR-SD-DAT[2] HD-SPKOUT-LP 51 SPK_L-
    CW1 1U_0402_6.3V6K 1
    23 CR-SDREG HD-SPKOUT-LN 52 SPK_R- +3VS
    CW2 1 2 1U_0402_6.3V6K 24 CR-TEST1 HD-SPKOUT-RN 53 SPK_R+ CC257
    RW11 1 2 6.2K_0402_1% RREF 25 CR-V18-CAP HD-SPKOUT-RP 54 +5VD 10U_0603_6.3V6M
    USB20_N4 RW12 2 1 0_0402_5% USB20_N4_R 26 CR-RREF HD-PVDD2 55 SPKR_MUTE# 2
    +3VALW 9 USB20_N4 USB20_P4 RW13 2
    @
    @ 1 0_0402_5% USB20_P4_R 27 CR-DM HD-PDB 56 Digital power for digital I/O circuit
    +3VS +3VS_CARD 9 USB20_P4 28 CR-DP HD-DVDD
    +3VS_CARD CR-3V3-IN
    29
    CARD_3V3 CR-SD-3V3 57 2 2
    GNDPAD
    1 1
    RA220 1 2 0_0402_5%

    0.1U_0201_6.3V6-K

    1U_0402_6.3V6K
    @ CW18 CW19 RTS5199-CG_QFN56_7X7 CA180 CA179
    4.7U_0402_6.3V6M 0.1U_0201_6.3V6-K
    1 1
    2 2
    RA219 1 @ 2 0_0402_5%
    1U_0402_6.3V6K

    1 ABR USB leakage issue, card reader power need 3VALW


    C2062

    C 2 C
    DA4
    EC_MUTE# 1 2 @ SPKR_MUTE#
    39 EC_MUTE#
    LINE1_L

    1
    LRB751V-40T1G_SOD323-2 CA45 1 2 1U_0402_6.3V6K

    Vinafix.com
    RA35 2 @ 1 0_0402_5% RA43
    10K_0402_5% LINE1_VREF_L RA41 1 2 4.7K_0402_5%
    Power for combo jack depop circuit at system HPOUT_L RA21 1 2 51_0402_1% A_HP_OUTL_R
    shutdown mode

    2
    HPOUT_R RA20 1 2 51_0402_1% A_HP_OUTR_R
    +3VL
    DA1 LINE1_VREF_L RA42 1 2 4.7K_0402_5%
    RA203 2 @ 1 0_0402_5% VDD_STB 2
    39 BEEP#
    1PC_BEEP1
    RA211 2 @ 1 0_0402_5% CA40 1 2 PC_BEEP LINE1_R CA46 1 2 1U_0402_6.3V6K
    7 PCH_BEEP
    3 0.1U_0201_6.3V6-K

    1
    To solve the background noise while combojack connecting to an
    active speaker and system entry into S3/S4/S5 without analog power. LBAT54CWT1G_SOT323-3 RA14
    10K_0402_5%

    2
    1
    RA217 @ 2 0_0402_5% @1 TC203
    7 HDA_RST_AUDIO#

    JSPK1 ME@
    RA223 1 CD@ 2 15_0402_5% SPK_R+ RA222 2 @ 1 0_0402_5% SPK_R+_CONN 1
    RA224 1 CD@ 2 15_0402_5% SPK_R- RA221 2 @ 1 0_0402_5% SPK_R-_CONN 2 1
    RA1 1 2 0_0402_5% RA32 1 CD@ 2 15_0402_5% SPK_L+ RA30 2 @ 1 0_0402_5% SPK_L+_CONN 3 2
    EMC_NS@ RA33 1 CD@ 2 15_0402_5% SPK_L- RA34 2 @ 1 0_0402_5% SPK_L-_CONN 4 3
    RA4 1 2 0_0402_5% 4
    EMC_NS@ 5
    6 GND1

    470P_0201_50V7-K

    470P_0201_50V7-K

    470P_0201_50V7-K

    470P_0201_50V7-K
    LW2

    CA183

    CA184

    CA29

    CA30
    220P_0201_25V7-K

    220P_0201_25V7-K

    220P_0201_25V7-K

    220P_0201_25V7-K
    USB20_N4 1 2 USB20_N4_R GND2

    CA31

    CA32

    CA181

    CA182
    B 1 2 2 2 2 2 B
    RA9 2 @ 1 0_0402_5% 1 1 1 1 ACES_88231-04001

    RA12 1 2 0_0402_5% USB20_P4 4 3 USB20_P4_R


    4 3 1 1 1 1

    EMC@

    EMC@

    EMC@

    EMC@
    EMC_NS@
    EXC24CH900U_4P 2 2 2 2
    EMC_NS@
    FOR EMI CD@ CD@ CD@ CD@

    GND GNDA
    8/16 Update Audio Jack P/N SP011509163 wei

    Audio Jack JHP1 ME@


    RING2_CONN 3
    R3124 1 @ 2 C232 1 2 A_HP_OUTL_R 1 G/M
    0_0402_5% @ 470P_0201_50V7-K L
    RING3_CONN PLUG_IN 5
    RING2_CONN 5
    A_HP_OUTL_R DMIC_CLK HDA_SYNC_AUDIO 6
    A_HP_OUTR_R EMC_NS@ HDA_SDOUT_AUDIO 6
    PLUG_IN DMIC_DATA RA27 1 2 27_0402_5%HDA_BITCLK_AUDIO R3123 1 @ 2 C184 1 2 A_HP_OUTR_R 2
    HDA_SDIN0 0_0402_5% @ 470P_0201_50V7-K R
    RING3_CONN 4
    CA38

    CA39
    100P_0201_25V8J

    100P_0201_25V8J

    M/G
    AZ5123-01F.R7GR_DFN1006P2X2

    AZ5123-01F.R7GR_DFN1006P2X2

    AZ5123-01F.R7GR_DFN1006P2X2

    AZ5123-01F.R7GR_DFN1006P2X2

    AZ5123-01F.R7GR_DFN1006P2X2

    EMC_NS@

    EMC_NS@

    CA23

    CA24

    CA25

    CA26

    1 1
    7
    22P_0201_258J

    22P_0201_258J

    33P_0201_50V8-J

    33P_0201_50V8-J

    MS
    1

    EMC_NS@

    EMC_NS@

    EMC_NS@
    47P_0201_25V8-J

    1 1 1 1
    DA5 DA6 DA7 DA8 DA9 SINGA_2SJ3095-140111F
    EMC_NS@

    100P_0201_25V8J

    100P_0201_25V8J
    1
    1

    C185 2 2
    1 1
    EMC_NS@

    EMC_NS@

    EMC_NS@

    EMC_NS@

    EMC_NS@

    EMC_NS@
    2 2 2 2 C182 C183
    A 2 EMC@ EMC@ A
    2 2
    2

    For EMI
    2

    8/16 Update Audio Jack P/N DC021608101 wei

    Security Classification LC Future Center Secret Data Title

    Issued Date 2016/08/16 Deciphered Date 2017/08/15 Codec & CR_RTS5199


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Custom
    330ARR 1.0

    Date: Friday, March 23, 2018 Sheet 36 of 52


    5 4 3 2 1
    5 4 3 2 1

    D D

    CARD_3V3

    SD / MMC

    4.7U_0402_6.3V6M
    1 1
    CW17
    SD_D0_R RW3 2 @ 1 0_0402_5% SD_D0 CW9 0.1U_0201_6.3V6-K
    36 SD_D0_R
    CW5 1 2 5.6P_0402_50V8-D @
    2 2
    EMC@

    JREAD1 ME@
    SD_D1_R RW4 2 @ 1 0_0402_5% SD_D1 SD_D3 1
    36 SD_D1_R SD_CMD CD/DAT3
    CW6 1 2 5.6P_0402_50V8-D 2
    3 CMD
    4 VSS1
    EMC@
    SD_CLK 5 VDD
    6 CLK
    SD_D2_R 2 1 0_0402_5% SD_D2 SD_D0 7 VSS2
    36 SD_D2_R
    RW5 @ Close to Connector SD_D1 DAT0
    CW7 1 2 5.6P_0402_50V8-D 8
    C SD_D2 9 DAT1 C
    DAT2

    Vinafix.com
    EMC@
    SD_CD# 10 12
    SD_D3_R SD_D3 36 SD_CD# SD_WP CARDDETECT SH1
    RW6 2 @ 1 0_0402_5% 11 13
    36 SD_D3_R 36 SD_WP W RITEPROTECT SH2
    CW8 1 2 5.6P_0402_50V8-D 14
    SH3 15
    SH4
    EMC@
    T-SOL_5-251301001000-6_NR
    SD_CMD_R SD_CMD
    Close to Connector
    RW7 2 @ 1 0_0402_5%
    36 SD_CMD_R
    CW11 1 2 5.6P_0402_50V8-D

    EMC@ CARD_3V3

    8/16 Update Conn. P/N SP07000WG00 wei


    SD_CLK_R SD_CLK

    1
    RW8 2 @ 1 0_0402_5%
    36 SD_CLK_R
    CW12 1 2 5.6P_0402_50V8-D DW1

    AZ5123-01F.R7GR_DFN1006P2X2
    EMC_NS@
    EMC@

    2
    2
    B B

    FOR ESD

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2016/08/16 Deciphered Date 2017/08/15 Cardreader


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 330ARR
    Date: Friday, March 23, 2018 Sheet 37 of 52
    5 4 3 2 1
    A B C D E F G H

    SATA HDD Conn.


    JHDD1

    10
    SATA_PTX_DRX_P0 C66 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_P0 9 10
    4 SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 SATA_PTX_C_DRX_N0 9
    4 SATA_PTX_DRX_N0 C67 1 2 0.01U_0201_10V6K 8
    7 8 12
    1 SATA_PRX_DTX_N0 C68 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_N0 6 7 GND2 1
    4 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 C69 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_P0 5 6
    4 SATA_PRX_DTX_P0 4 5
    3 4 11
    2 3 GND1
    1 2
    1
    ELCO_006809610010846
    Need short +5VS_HDD
    ME@
    J3 @
    1 2
    +5VS 1 2
    JUMP_43X79

    F6 NEC@
    1 2
    +5VS_HDD
    2A_32V_ERBRD2R00X

    1 1 1 1 1 FOR 15"
    C74 C75 C76 C77 C78

    SATA ODD FFC Conn


    1000P_0201_50V7-K 0.1U_0201_6.3V6-K 33P_0402_50V8J 10U_0603_6.3V6M 33P_0402_50V8J
    EMC_NS@ RF@ RF@
    2 2 2 2 2

    2 EMC 2

    Vinafix.com
    SATA 15 ODD P/N pin assgin is different from G SKL

    JODD2
    1
    +5VS to +5V_ODD SATA_PTX_DRX_N1 C198 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_N1_15 2 1
    ME@
    4 SATA_PTX_DRX_N1 SATA_PTX_DRX_P1 SATA_PTX_C_DRX_P1_15 2
    4 SATA_PTX_DRX_P1 C197 1 2 0.01U_0201_10V6K 3
    4 3
    SATA_PRX_DTX_P1 C200 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_P1_15 5 4
    4 SATA_PRX_DTX_P1 SATA_PRX_DTX_N1 C199 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_N1_15 6 5
    +5VS Need short +5V_ODD 4 SATA_PRX_DTX_N1 7 6
    +5V_ODD 8 7
    J4 @ 8
    1 2 9
    1 2 10 GND1
    JUMP_43X79 GND2
    1 1 1 1 HIGHS_FC5AF081-2931H
    F7 NEC@ C85 C86 C1324 C8792
    1 2 10U_0603_6.3V6M 0.1U_0201_6.3V6-K 33P_0402_50V8J 22P_0402_50V8-J
    RF@ RF_NS@
    3 2 2 2 2 3
    2A_32V_ERBRD2R00X

    4 4

    Security Classification LC Future Center Secret Data Title

    Issued Date 2013/08/08 Deciphered Date 2013/08/05 HDD/ODD CONN


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 330ARR
    Date: Friday, March 23, 2018 Sheet 38 of 52
    A B C D E F G H
    5 4 3 2 1

    @
    RE1 1 2 0_0603_5%
    +3VL

    1 2 0_0603_5%
    Close EC RE3 @ +3VALW

    +3VL_EC +3VL_EC +3VL_EC_R


    CE3 1 2 VCOREVCC @
    1 2 0_0603_5%
    0.1U_0201_6.3V6-K +3VL_EC All capacitors close to EC LE1

    0.1u_0201_10V6K

    0.1u_0201_10V6K

    0.1u_0201_10V6K
    CD@

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K
    1 1
    1 1 1 @1 1 @1 CE4 CE5
    0.1U_0201_6.3V6-K 1000P_0201_50V7-K
    +3VS +3VL_EC_R
    @ 2 2
    2 2 2 2 2 2 EC_AGND
    Change RE6 to 0ohm jump 1 2 0_0603_5%

    CE11
    D LE2 D

    CE6

    CE7

    CE8

    CE9

    CE10
    RE6 2 @ 1 0_0402_5%

    EC_AGND

    minimum trace width 12 mil

    127
    114
    121
    12

    26
    50
    92
    11

    74
    3
    UE1
    +3VS

    VCORE

    VSTBY(PLL)
    VSTBY1
    VSTBY2
    VSTBY3
    VSTBY4
    VSTBY5
    VBAT

    VCC

    AVCC
    EC_FAN_SPEED RE10 1 2 10K_0402_5%
    EC_FAN_PWM RE11 1 @ 2 10K_0402_5%
    ENBKL RE9 1 @ 2 100K_0402_5%
    SERIRQ RE81 1 @ 2 10K_0402_5%
    18 WRST# 4 24 EC_LID_OUT# 1 2
    RE93 @ 10K_0402_5%
    +3VL_EC 8 KBRST# 5 KBRST#/GPB6 PWM0/GPA0 25 PWR_LED# 40
    8,13,34 SERIRQ 6 SERIRQ/GPM6 PWM1/GPA1 28 BATT_CHG_LED# 40
    8,13,34 LPC_FRAME# 7 LFRAME#/GPM5 PWM2/GPA2 29 BATT_LOW_LED# 40 +5VALW
    2 8,13,34 LPC_AD3 8 LAD3/GPM3 PWM3/GPA3 30 VGA_AC_DET 18
    DE1 @1
    8,13,34 LPC_AD2 LAD2/GPM2 PW M PWM4/GPA4 EC_FAN_PWM LED_KB_PWM 40
    9 31
    8,13,34 LPC_AD1 10 LAD1/GPM1 PWM5/GPA5 32 EC_FAN_PWM 34 USB_ON# RE15 1 2 10K_0402_5%
    RB751V-40_SOD323-2 8,13,34 LPC_AD0 CLK_PCI_EC 13 LAD0/GPM0 PWM6/SSCK/GPA6 34 EC_APU_ALWEN BEEP# 36
    8,13 CLK_PCI_EC LPCCLK/GPM4 LPC PWM7/RIG1#/GPA7 HVB_EN EC_APU_ALWEN 49
    RE8 1 2 100K_0402_5% WRST# 14 120 PAD 1 @ +3VL_EC
    15 WRST# TMRI0/GPC4 124 SUSP# IT14
    7 EC_SMI# EC_RX 16 ECSMI#/GPD4 TMRI1/GPC6 SUSP# 41,48,49
    1 SUSP# RE18 1 @ 2 100K_0402_5%
    28,35 EC_RX EC_TX 17 PWUREQ#/BBO/SMCLK2ALT/GPC7 66 LAN_WAKE# RE5 1 2 10K_0402_5%
    CE12 28,35 EC_TX APU_LPC_RST# 22 LPCPD#/GPE6 ADC0/GPI0 67 NTC_V1 34 EC_ON RE72 1 @ 2 10K_0402_5%
    1U_0402_6.3V6K 8,13,34 APU_LPC_RST# EC_SCI# 23 LPCRST#/GPD2 ADC1/GPI1 68 NTC_V2 34
    2 8 EC_SCI# 1 PAD GATEA20 126 ECSCI#/GPD3 ADC2/GPI2 69 ENBKL BATT_TEMP 46,47 +3VL
    IT13
    @
    GA20/GPB5 ADC ADC3/GPI3 ENBKL 26
    70 RE2781 2 0_0402_5%
    EC_SCI# in APU internal pull high to 3VALW IT8586E/AX ADC4/GPI4
    ADC5/DCD1#/GPI5
    71
    72
    ADP_I 47
    RE276 2
    @

    @ 1 0_0402_5%
    IDCHG 47
    LID_SW# RE38 1 2 100K_0402_5%

    +3VS
    +3VL_EC
    40 KSI[0..7]
    KSI[0..7] KSI0 58
    LQFP-128L ADC6/DSR1#/GPI6
    ADC7/CTS1#/GPI7
    73 RE71 2 @ 1 0_0402_5%
    PSYS
    2_5VEN 47

    KSI1 59 KSI0/STB# 78
    KSO[0..17] 60 KSI1/AFD# DAC2/TACH0B/GPJ2 79 MAINPWON1_EC VR_APU_PWRGD 52 EC_VR_ON
    KSI2 RE26 1 @ 2 1K_0402_5% RE2821 2 100K_0402_5%
    40 KSO[0..17] 61 KSI2/INIT# DAC3/TACH1B/GPJ3 80 H_PROCHOT#_EC MAINPWON 48 2_5VEN
    KSI3 DAC RE2791 2 100K_0402_5%
    KSI4 62 KSI3/SLIN# DAC4/DCD0#/GPJ4 81 EC_APU_ALWEN RE66 1 2 100K_0402_5%
    C C
    KSI4 DAC5/RIG0#/GPJ5 EC_RTCRST#_ON 11
    2
    1

    2
    1

    KSI5 63 SUSP# RE19 1 2 100K_0402_5%


    RPE3 RPE2 KSI6 64 KSI5 85 EC_ON SYSON RE21 1 2 100K_0402_5%
    65 KSI6 PS2CLK0/TMB0/CEC/GPF0 86 EC_ON 48,49
    2.2K_0404_4P2R_5% 2.2K_0404_4P2R_5% KSI7 BKOFF# RE40 1 2 10K_0402_5%
    36 KSI7 PS2DAT0/TMB1/GPF1 87 EC_SMB_CK4 PBTN_OUT# 7 EC_ON
    @ KSO0 RE2832 @ 1 0_0402_5% RE2851 2 100K_0402_5%
    KSO0/PD0 GPF2 EC_SMB_DA4 THERMAL_SMB_CK2 34

    Vinafix.com
    KSO1 37 Int. K/B PS2 88 RE2842 @ 1 0_0402_5%
    EC_SMB_CK3 EC_SMB_CK1 KSO1/PD1 GPF3 GPU_EC_HOT# THERMAL_SMB_DA2 34
    3
    4

    3
    4

    KSO2 38 89 RE90 2 @ 1 0_0402_5%


    EC_SMB_DA3 EC_SMB_DA1 39 KSO2/PD2 Matrix PS2CLK2/GPF4 90 EC_LID_OUT# GPU_VR_HOT# 18,51
    KSO3
    KSO4 40 KSO3/PD3 PS2DAT2/GPF5 EC_LID_OUT# 40
    KSO4/PD4

    1
    AMD request SIC/SID（ EC_SMB3 ） pul l hig h 1K KSO5
    KSO6
    41
    42 KSO5/PD5 EXTERNAL SERIAL FLASH GPH3/ID3
    96
    97 EC_VR_ON CAPS_LED# 40 2
    QE8 D 1
    CE33
    KSO7 43 KSO6/PD6 GPH4/ID4 98 EC_VR_ON 52 G 47P_0201_25V8-J
    +3VL_EC +3VALW KSO8 44 KSO7/PD7 GPH5/ID5 99 LAN_PWR_ON# 32
    @
    KSO9 45 KSO8/ACK# GPH6/ID6 EC_SYS_PWRGD 7 S 2
    2N7002KW_SOT323-3
    KSO9/BUSY

    3
    SMBus1:Charger/Battery KSO10 46 101
    KSO10/PE NC1 @
    2

    SMBus2:PMIC/thermalsensor KSO11 51 102


    KSO12 52 KSO11/ERR# NC2 103
    RE74 RE73 SMBus3:APU/GPU KSO12/SLCT SPI Flash ROM NC3
    0_0402_5% 0_0402_5% KSO13 53 105
    @ KSO14 54 KSO13 NC4
    @ KSO15 55 KSO14
    KSO15
    1

    KSO16 56 108 ACIN#


    KSO17 57 KSO16/SMOSI/GPC3 AC_IN# 109 LID_SW#
    KSO17/SMISO/GPC5 UART LID_SW# LID_SW# 40
    2
    1

    40 ON/OFF ON/OFF 110 82


    EC_ON RE1041 2 0_0402_5% 111 PWRSW# EGAD/GPE1 83 APUALW_PWRGD EC_MUTE# 36
    RPE5 @
    EC_SMB_CK1 XLP_OUT SM Bus EGCS#/GPE2 APUALW_PWRGD 49
    2.2K_0404_4P2R_5% 115 84
    46,47 EC_SMB_CK1 EC_SMB_DA1 116 SMCLK1/GPC1 EGCLK/GPE3 CMOS_ON# 26
    46,47 EC_SMB_DA1 EC_SMB_CK2 117 SMDAT1/GPC2 77
    EC_SMB_CK2 34,49 EC_SMB_CK2 EC_SMB_DA2 SMCLK2/PECI/GPF6 GPIO GPJ1 PM_SLP_S5# 7,13
    3
    4

    118 100 GPG2


    EC_SMB_DA2 34,49 EC_SMB_DA2 EC_SMB_CK3 94 SMDAT2/PECIRQT#/GPF7 SSCE0#/GPG2 106 2 1 0_0402_5%
    RE286 @ 0.9V_PWRGD 49
    6,18 EC_SMB_CK3 EC_SMB_DA3 95 CRX1/SIN1/SMCLK3/GPH1/ID1 SSCE1#/GPG0 104
    6,18 EC_SMB_DA3 CTX1/SOUT1/GPH2/SMDAT3/ID2 DSR0#/GPG6 107 OTP_RESET 48 2 1 0_0402_5% SYSON
    RE85 @
    +3VL DTR1#/SBUSY/GPG1/ID7 119 BKOFF#
    CRX0/GPC0 123 BKOFF# 26 2 1 0_0402_5%
    RE280 @
    CTX0/TMA0/GPB2 APU_THERMTRIP# 6
    RE27 1 @ 2 0_0402_5% 112 18 PM_SLP_S3# 7
    LAN_WAKE# 125 VSTBY0 RI1#/GPD0 21 VDDGFX_PD PAD 1 @
    32,35 LAN_WAKE# GPE4 RI2#/GPD1 IT16
    WAKE UP 76 NOVO# 40
    TACH2/GPJ0 48
    B TACH1A/TMA1/GPD7 47 EC_FAN_SPEED EC_TS_ON 26 B
    USB_ON# TACH0A/GPD6 PCH_PWRBT# EC_FAN_SPEED 34
    33 19 PAD 1 @
    28 USB_ON# 35 GINT/CTS0#/GPD5 L80HLAT/BAO/GPE0 20 IT18
    41 PCH_CMOSP EC_RSMRST# RTS1#/GPE5 GPIO L80LLAT/GPE7 NUM_LED# 40
    93
    7 EC_RSMRST# CLKRUN#/GPH0/ID0

    2
    7,32,35 PCIE_WAKE# 128 CK32KE/GPJ7
    7 AC_PRESENT CK32K/GPJ6 Clock

    @
    1 2 RB751V-40_SOD323-2
    DE4
    H_PROCHOT#
    AVSS
    VSS1

    VSS2
    VSS3
    VSS4
    VSS5
    VSS6

    RE34 1 @ 2 0_0402_5%
    SYSON RE99 1 @ 2 0_0402_5% 47,52 VR_HOT#
    1_2VEN 49 IT8586E-AX_LQFP128_14X14
    1

    27
    49
    91
    113
    122

    75

    H_PROCHOT#_EC RE82 1 @ 2 0_0402_5% H_PROCHOT# 6,49


    @

    1
    DE5 1 2 RB751V-40_SOD323-2 QE1 D 1
    EC_AGND 2 CE14
    Mirror Core strap +3VL_EC RE1001 @ 2 1K_0402_5% 2_5VEN
    G 47P_0201_25V8-J
    @
    2_5VEN 49 S 2
    2N7002KW_SOT323-3

    3
    +3VL @
    GPG2 RE98 2 @ 1 10K_0402_5%
    RE97 2 1 10K_0402_5% CLK_PCI_EC RE1031 2 10_0402_5% EMC_NS@ CE29 1 2 10P_0201_25V8G
    EMC_NS@ +3VS
    APU_LPC_RST#
    1

    EMC_NS@ CE27 1 2 220P_0201_25V7-K


    for VR_APU_PWRGD undershoot issue
    when mirror, GPG2 pull high RE102
    100K_0402_5% SYSON EMC_NS@ CE31 1 2 0.1U_0201_6.3V6-K
    when no mirror, GPG2 pull low APUALW_PWRGD VR_APU_PWRGD BATT_TEMP EMC_NS@ CE28 1 2 100P_0201_25V8J 2
    2

    ACIN# RE1011 @ 2 0_0402_5%


    1 ACIN# EMC_NS@ CE26 1 2 100P_0201_25V8J CE32
    1 CE24 0.1U_0201_6.3V6-K
    EC_SMB_CK1 1
    1

    A 1 A
    PAD @ CE25 0.01U_0201_10V6K D QE7 ON/OFF EMC@ CE30 1 2 0.1U_0402_10V7K EMC_NS@
    EC_SMB_DA1 1 IT1 2
    PAD @ 0.1U_0402_25V6
    1 IT2 2 G ACIN 47
    PAD @ @
    1 IT3 2
    PAD @
    1 IT4
    PAD @ 2N7002KW_SOT323-3 S @
    IT5
    3

    EMC
    KSI7 PAD 1 @
    IT6
    KSI6 PAD 1 @
    IT7
    WRST# PAD 1 @ Title
    IT8 Security Classification LC Future Center Secret Data
    Issued Date 2016/08/16 Deciphered Date 2017/08/15 EC ITE8586LQFP
    Reserve Factory EC flash, need confirm with ITE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Custom
    330ARR 1.0

    Date: Friday, March 23, 2018 Sheet 39 of 52


    5 4 3 2 1
    5 4 3 2 1

    ON/OFF switch +3VL +3VALW


    Novo button NOVO_BTN#

    2
    SW2

    1
    R82 R83 4 D24

    1
    100K_0402_5% 100K_0402_5% AZ5123-01F.R7GR_DFN1006P2X2
    @ 5 EMC@
    R261 2 @ 1 0_0402_5%

    2
    NTC325-EKJ-A160T_3P

    2
    NOVO# D15 2
    39 NOVO#
    1 NOVO_BTN#
    ON/OFFBTN#
    ON/OFF R85 2 @ 1 0_0402_5% 3 @

    AZ5123-01F.R7GR_DFN1006P2X2
    BAT54CW_SOT323-3

    1
    D25

    1
    D D

    +3VALW +3VL

    LID switch

    2
    2

    2
    EMC@

    2
    R111 R114
    100K_0402_5% 100K_0402_5%
    @

    1
    ON/OFFBTN# R119 2 @ 1 0_0402_5% ON/OFF 1
    ON/OFF 39
    C1104
    U14 100P_0201_25V8J
    J5 1 2 @ 1
    GND 2
    1 LID_SW#
    SHORT PADS C1105 3
    0.01U_0201_10V6K OUTPUT LID_SW# 39
    J6 1 2 @
    R264 2 @ 1 0_0402_5% 2 +VCC_LID 2
    +3VL VCC
    SHORT PADS
    AH9247-W-7_SC59-3

    K/B Connector KSI[0..7]


    KSI[0..7] 39 KB Backlight Connector
    KSO[0..17] JKB1
    KSO[0..17] 39
    32 33 +5VS
    ON/OFFBTN# 31 32 GND1 34 @
    PWR_LED# R274 200_0402_1% PWR_LED#_R 31 GND2 +5VALW
    1 2 30 F11 1 2 0.5A_32V_ERBRD0R50X
    EMC_NS@ R279 1 2 200_0402_1% NUM_LED#_R 29 30 +VCC_KB_LED
    PWR_CAPS_LED 1 2 100P_0201_25V8J 39 NUM_LED# KSO17_R 28 29
    C133 KSO17 R281 1 @ 2 0_0402_5% Q31
    KSO16_R 28

    1
    KSO16 R280 1 @ 2 0_0402_5% 27 R265 LP2301ALT1G_SOT23-3
    KSI1 26 27 10K_0402_5% KBL@
    KSI7 25 26 KBL@ 3 1 R267 1 @ 2 0_0402_5%

    D
    KSI6 24 25
    KSO9 23 24
    23 1 1

    2
    KSI4 22 R266 C1106 C8786

    G
    22

    2
    KSI5 21 1 2 10U_0603_6.3V6M 0.1U_0201_6.3V6-K
    KSO0 20 21 KBL@ KBL@
    EMC@ KSI2 19 20 100K_0402_5% 2 2
    CAPS_LED# 19 1
    C117 1 2 100P_0201_25V8J KSI3 18 KBL@ C1108
    KSO5 17 18 0.01U_0201_10V6K
    C
    NUM_LED#_R C118 1 2 100P_0201_25V8J KSO1 16 17 KBL@ C
    KSI0 15 16 2
    EMC@ KSO2 14 15
    KSO4 13 14
    13 To be confirm Pin define
    KSO7 12
    12

    1
    KSO8 11 D
    KSO6 10 11 LED_KB_PWM 2 Q32
    CAPS_LED#_R NUM_LED#_R PWR_LED#_R 9 10 39 LED_KB_PWM
    KSO3 G 2N7002KW_SOT323-3 JKBL1 ME@
    KSO12 8 9 KBL@ +VCC_KB_LED 1
    8 1

    2
    KSO13 7 C1109 1 S 2
    7 2

    3
    KSO14 6 R4685 3 6
    6 0.1U_0201_6.3V6-K 3 GND2

    Vinafix.com
    KSO11 5 10K_0402_5% 4 5
    5 4 GND1
    1

    KSO10 4 KBL@ @ 1
    D22 D23 D46 KSO15 3 4 2 C1110 CVILU_CF50041D0RN-10-NH
    R275 200_0402_1%
    1

    CAPS_LED#_R 3

    1
    AZ5123-01F.R7GR_DFN1006P2X2 AZ5123-01F.R7GR_DFN1006P2X2 AZ5123-01F.R7GR_DFN1006P2X2 1 2 2 0.1u_0201_10V6K
    39 CAPS_LED# PWR_CAPS_LED 1 2
    EMC@ EMC@ EMC@ +3VALW R84 1 NONEC@2 0_0402_5% 1
    @
    2
    F8 NEC@
    1 2 CVILU_CF32321D0RONH
    2

    ME@
    2

    0.5A_32V_ERBRD0R50X
    For EMC

    Finger Print Connector TP/B Connector


    FP_PWR
    To be confirm Pin define +3VS TP_PWR
    NONEC@
    +3VS R141 1 2
    JFP1 0_0402_5%
    R3120 2 @ 1 0_0402_5% 1
    USB20_N3 R3122 2 @ 1 0_0402_5% USB20_N3_CONN 2 1 F10 NEC@
    31 USB20_N3 USB20_P3 R3121 USB20_P3_CONN 2 1
    F9 @ 2 @ 1 0_0402_5% 3 1 2
    1 2 31 USB20_P3 4 3
    1 C114
    5 4 0.5A_32V_ERBRD0R50X 0.1U_0201_6.3V6-K
    0.5A_32V_ERBRD0R50X C2061 6 5 2
    0.1U_0201_6.3V6-K 7 6
    2 FP@ 8 7
    USB20_N3_CONN 8
    9
    10 GND1 JTP1 ME@
    USB20_P3_CONN GND2 R4684 1 @ 2 0_0402_5% EC_LID_OUT#_R 1
    B TP_I2C0_SCL 39 EC_LID_OUT# 1 2 0_0402_5% TP_INT# 2 1 7 B
    HIGHS_FC5AF081-2931H R4683 @
    TP_I2C0_SDA 7 PCH_TP_INT# 3 2 GND1
    ME@ TP_I2C0_SDA_R TP_I2C0_SDA 3
    3

    R4681 1 @ 2 0_0402_5% 4 8
    TP_I2C0_SCL_R TP_I2C0_SCL 4 GND2

    2
    DT2 R4680 1 @ 2 0_0402_5% 5
    DT1 6 5
    TP_PWR 6
    FP_EMC@

    100P_0201_25V8J

    100P_0201_25V8J
    EMC_NS@ 1 1 ELCO_04-6809-606-110-846-+

    EMC_NS@

    EMC_NS@
    2 2

    C115

    C116
    AZC199-02S.R7G_SOT23-3
    1

    AZC199-02S.R7G_SOT23-3

    1
    For EMC

    BATT_LOW_LED# LED2 1 2 R143 1 2 470_0402_5% TP_PWR


    39 BATT_LOW_LED# +3VALW TP_PWR
    L-C192JFCT-LCFC_SUPER_AMBER
    1

    2
    1
    D18
    1

    AZ5725-01F.R7GR_DFN1006P2X2 RPC20
    EMC_NS@ 2.2K_0404_4P2R_5%

    5
    G

    3
    4
    2
    2

    TP_I2C0_SDA_R R4686 1 @ 2 0_0402_5% 3 4 TP_I2C0_SDA


    7,13 TP_I2C0_SDA_R

    S
    D
    BATT_CHG_LED# LED3 1 2 R144 1 2 1.5K_0402_5% Q159B
    39 BATT_CHG_LED# +5VALW

    2
    2N7002KDWH_SOT363-6

    G
    L-C192WDT-LCFC_WHITE
    1

    D19 TP_I2C0_SCL_R R4687 1 @ 2 0_0402_5% 6 1 TP_I2C0_SCL


    7,13 TP_I2C0_SCL_R
    1

    S
    AZ5725-01F.R7GR_DFN1006P2X2

    D
    EMC_NS@ Q159A
    2N7002KDWH_SOT363-6
    2
    2

    PWR_LED#
    A A

    PWR_LED# LED4 1 2 R4672 1 2 1.5K_0402_5%


    39 PWR_LED# +5VALW
    1

    L-C192WDT-LCFC_WHITE D16
    1

    AZ5725-01F.R7GR_DFN1006P2X2
    EMC_NS@
    2

    PWR_LED Change to M/B (310->320) 08/17


    2

    Security Classification LC Future Center Secret Data Title

    Issued Date 2016/08/16 Deciphered Date 2017/08/15 KBD/PWR/IO/LED/TP Conn.


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Re v
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 330ARR
    Date: Friday, March 23, 2018 Sheet 40 of 52
    5 4 3 2 1
    A B C D E

    +5VLP +5VALW

    1
    R156 R157
    100K_0402_5% 100K_0402_5%
    @

    2
    1 1
    SUSP
    14,27 SUSP

    1
    Q6 D
    2
    39,48,49 SUSP# G

    S 2N7002KW_SOT323-3

    +1.8VALW to +1.8VS AON6414AL


    VDS=30V VGS=20V, ID=50A, +0.9V to +0.9VS J602 @
    1 2 AON6414AL
    +1.8VALW Q39 +1.8VS +/- 5% 1.5A Rds=8mohm @ VGS=10V 1 2
    ID=50A,+0.9V
    +0.9VALW
    +/- 2% AON6414AL_DFN8-5
    VGS(th)=2.5V Max
    JUMP_43X118
    VDS=30V VGS=20V,
    +0.9V Q41 +0.9VS +/-5% 3.6A Rds=8mohm @ VGS=10V
    J603 @
    1 +/- 1.5% AON6414AL_DFN8-5
    VGS(th)=2.5V Max
    1
    1 2
    2
    2 1 1
    2 1 5 3 C142 1 JUMP_43X118 2
    C141 C2082 1U_0402_6.3V6K 2 1 1
    10U_0603_6.3V6M 10U_0603_6.3V6M 1 5 3 C147

    Vinafix.com
    2 2

    1
    @ 1 1 C146 C145 1U_0402_6.3V6K
    4

    2 C1325 C1326 0.01U_0201_10V6K R213 10U_0603_6.3V6M 10U_0603_6.3V6M


    2 2

    1
    0.1U_0201_6.3V6-K @ 470_0603_5% @ 1 @ 1

    4
    @ @ 2 C1327 C1328 0.01U_0201_10V6K R188 @
    2 2 0.1U_0201_6.3V6-K @ 470_0603_5%
    V20B+

    2
    @
    2 2 R206
    V20B+

    2
    R211 R194 R214 2 1 1.8VS_GATE
    1.8VS_GATE_R 2 @ 1 0_0402_5% 2 @ 1 1.8VS_GATE 2 1 0_0402_5%
    R193 @
    0_0402_5% 130K_0402_5% 1.05VS_GATE_R 2 1 1 R190 21.05VS_GATE 2 R189 1
    1

    1
    1 D Q45 D 0_0402_5% 470K_0402_5%
    C143 R212 2 SUSP 2 Q46 0_0402_5% @ @

    1
    0.01U_0201_25V6-K 1M_0402_5% G G 2N7002KW_SOT323-3 1 @ D Q37 D
    @ C144 R187 2 SUSP 2 Q40
    2 S 2N7002KW_SOT323-3 S 0.01U_0201_25V6-K 820K_0402_5% G G 2N7002KW_SOT323-3
    2

    3
    @ @ @
    2 S 2N7002KW_SOT323-3 S

    3
    @

    20VSB will change to 6V in DC mode, careful the Res divide voltage


    +3VALW to +3VALW_APU
    +0.6VS +2.5V
    For DisCharge +3VS CS31 CS34
    3 3
    +3VALW +3VALW_APU 1 2 1 2
    Need Short 1 +5VALW +3VALW +3VS +3VALW

    1
    J7 @ R159 R935 R940 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K
    1 2 47_0603_5% 47_0603_5% 47_0603_5%
    1 2 @ @ @
    JUMP_43X79
    2

    2
    +3VS +5VS +3VS +5VS
    Id=3.2A
    1

    1
    D Q8 D Q156 D Q158 1 1 1 1
    LP2301ALT1G_SOT23-3 2 SUSP 2 SUSP 2 SUSP CS28 CS24 CS27 CS25
    @ G G G 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K
    Q29 3 1
    S

    2N7002KW_SOT323-3 S @ 2N7002KW_SOT323-3 S @ 2N7002KW_SOT323-3 S @ 2 2 2 2


    0.01U_0201_10V6K

    3
    1 1
    C129 C130
    G
    2

    0.1U_0201_6.3V6-K
    @ @
    2 2

    R158 1 @ 2 0_0402_5% +3VALW +3VS +1.2V +5VS


    39 PCH_CMOSP +0.9V +0.9V +0.9V +0.9V
    1

    1 1 1 1 1
    C131 1 1 1 1 CS43 CS26
    R164 0.1U_0201_6.3V6-K C2083 C2084 C2085 C2086 0.1U_0402_10V7K CS42 CS44 0.1U_0402_10V7K
    100K_0402_5% @ 2200P_0402_25V7-K 2200P_0402_25V7-K 2200P_0402_25V7-K 2200P_0402_25V7-K 10U_0603_6.3V6M 0.1U_0201_6.3V6-K
    @ 2 EMC_NS@ EMC_NS@ EMC_NS@ EMC_NS@ 2 2 2 2
    2

    2 2 2 2
    4 4

    reserve to cut off APU 3VALW when clear CMOS

    Security Classification LC Future Center Secret Data Title

    Issued Date 2013/08/15 Deciphered Date 2013/08/15 DC V TO VS INTERFACE


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 330ARR
    Date: Friday, March 23, 2018 Sheet 41 of 52
    A B C D E
    5 4 3 2 1

    CPU Thermal Holex3 GPU Thermal Holex2 PCB Fedical Mark PAD
    H11 H12 H13 H8 H9
    Close to RJ45 Close to Audio jack
    HOLEA HOLEA HOLEA HOLEA HOLEA H4 H3
    HOLEA HOLEA FD1 FD2 FD3 FD4 FD5 FD6
    D 1 D

    1
    pad_c6p0d4p0 pad_c6p0d4p0 pad_c6p0d4p0 pad_c8p0d3p3 pad_c8p0d3p3 CHASSIS1_GND pad_ct7p0b8p0d3p0
    pad_ct7p0b8p0d3p0

    WLAN Standoff
    H15 H16
    H5 H6 H7 H10 H14 HOLEA HOLEA
    HOLEA HOLEA HOLEA HOLEA HOLEA

    1
    1

    1
    C C

    pad_o2p6x2p9d2p6x2p9n PAD_CB5P5D2P5 pad_c2p5d2p5n PAD_CT7P0D3P0 pad_d2p5

    Vinafix.com
    pad_c8p0d3p3 pad_c3p3d3p3n

    H17 H18
    HOLEA HOLEA
    1

    pad_d2p5 PAD_C2P5D2P5N

    SH1 ME@ SH2 ME@ SH3 ME@


    B B
    SH7 ME@ SH8 ME@
    1 1 1 SH12 ME@
    1 1 1 1 1
    1 1 1
    1

    SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64


    SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P
    SPRING_FINGER_6.2X1.64

    SH4 ME@ SH5 ME@ SH6 ME@

    1 1 1 SH13 ME@ SH9 ME@


    1 1 1 SH10 ME@ SH11 ME@
    1 1
    1 1 1 1
    1 1
    SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64

    SPRING_FINGER_6.2X1.64 SHIELDING_SUL-35A2M_9P2X3P3_1P
    SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P
    USB3.0 Shielding
    DDR4 Shielding
    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/08 Deciphered Date 2013/08/05 Hole
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    B
    330ARR 1.0

    Date: Friday, March 23, 2018 Sheet 42 of 52


    5 4 3 2 1
    5 4 3 2 1

    UL1 8111H@ UC2 UC2 UC2 UV1 R17@ UV1 R18@ ZZZ3 HDMI@

    RTL8111H-CG RAVEN RIDGE YM2700C4T4MFBA RAVEN RIDGE YM2500C4T4MFBA RAVEN RIDGE YM2200C4T2OFB 216-0905018-C3_FCBGA769 216-0915006_FCBGA769 HDMI PN
    SA000074W00
    LAN Chip R7@ R5@ R3@ SA00008DT20 SA00008XC00 RO00000040J
    SA00008QB10 SA00008QA10 SA00008UR10
    APU type GPU HDMI Royalty

    D D

    ZZZ9 DRAM_S4G@ ZZZ2 DRAM_M4G@ ZZZ7 DRAM_H4G@

    ZZZ5 S8GX2@ ZZZ8 H8GX2@ ZZZ12 M8GX2@ ZZZ4 S8GX2R18@ ZZZ6 H8GX2R18@ ZZZ10 M8GX2R18@

    Samsung Micron Hynix


    X7645A12004 X7645A12006 X7645A12005
    DRAM X76 BOM Samsung Hynix Micron Samsung Hynix Micron
    X7645A12002 X7645A12001 X7645A12003 X7645A12009 X7645A12007 X7645A12008
    VRAM X76 BOM

    UD1 MD_S8Gb@ UD2 MD_S8Gb@ UD3 MD_S8Gb@ UD4 MD_S8Gb@ RC1608 MD_S8Gb@ RC1609 MD_S8Gb@ UV3 S8G_VR@ UV4 S8G_VR@ RV1307 S8G_VR@ RV1304 S8G_VR@ RV1298 S8G_VR@

    K4A8G165WC-BCTD K4A8G165WC-BCTD K4A8G165WC-BCTD K4A8G165WC-BCTD 10K_0402_5% 2K_0402_5% K4G80325FB-HC28 K4G80325FB-HC28 5.1K_0402_5% 5.1K_0402_5% 5.1K_0402_5%
    SA00008PE00 SA00008PE00 SA00008PE00 SA00008PE00 SD02810028J SD02820018J SA000081C00 SA000081C00 SD02851018J SD02851018J SD02851018J

    DRAM_Samsung 4G VRAM_Samsung 8GX2

    UD1 MD_H8Gb@ UD2 MD_H8Gb@ UD3 MD_H8Gb@ UD4 MD_H8Gb@ RC1610 MD_H8Gb@ RC1607 MD_H8Gb@ UV3 H8G_VR@ UV4 H8G_VR@ RV1307 H8G_VR@ RV1304 H8G_VR@ RV1297 H8G_VR@
    C C

    Vinafix.com
    H5AN8G6NAFR-UHC H5AN8G6NAFR-UHC H5AN8G6NAFR-UHC H5AN8G6NAFR-UHC 10K_0402_5% 10K_0402_5% H5GC8H24MJR-R0C H5GC8H24MJR-R0C 5.1K_0402_5% 5.1K_0402_5% 5.1K_0402_5%
    SA00007X200 SA00007X200 SA00007X200 SA00007X200 SD02810028J SD02810028J SA000081600 SA000081600 SD02851018J SD02851018J SD02851018J

    DRAM_Hynix 4G VRAM_Hynix 8GX2

    UD1 MD_M8Gb@ UD2 MD_M8Gb@ UD3 MD_M8Gb@ UD4 MD_M8Gb@ RC1610 MD_M8Gb@ RC1608 MD_M8Gb@ UV3 M8G_VR@ UV4 M8G_VR@ RV1307 M8G_VR@ RV1303 M8G_VR@ RV1298 M8G_VR@

    MT40A512M16LY-075:E MT40A512M16LY-075:E MT40A512M16LY-075:E MT40A512M16LY-075:E 10K_0402_5% 10K_0402_5% MT51J256M32HF-70:A MT51J256M32HF-70:A 5.1K_0402_5% 5.1K_0402_5% 5.1K_0402_5%
    SA00008F930 SA00008F930 SA00008F930 SA00008F930 SD02810028J SD02810028J SA000081700 SA000081700 SD02851018J SD02851018J SD02851018J

    DRAM_Micron 4G VRAM_Micron 8GX2

    RC1609 DIMM_ONLY@ RC1607 DIMM_ONLY@


    UV3 S8G_VRR18@ UV4 S8G_VRR18@ RV1418 S8G_VRR18@

    B 2K_0402_5% 10K_0402_5% B
    SD02820018J SD02810028J K4G80325FB-HC28 K4G80325FB-HC28 4.75K_0402_1%
    SA000081C00 SA000081C00 SD03447518J
    DIMM ONLY
    VRAM_Samsung 8GX2 R18

    ZZZ13

    UV3 H8G_VRR18@ UV4 H8G_VRR18@ RV1415 H8G_VRR18@ RV1418 H8G_VRR18@

    PCB PN
    DAZ18700100
    H5GC8H24MJR-R0C H5GC8H24MJR-R0C 8.45K_0402_1% 2K_0402_1%
    PCB_MB SA000081600 SA000081600 SD000011R00 SD03420018J

    VRAM_Hynix 8GX2 R18

    UV3 M8G_VRR18@ UV4 M8G_VRR18@ RV1415 M8G_VRR18@ RV1418 M8G_VRR18@

    MT51J256M32HF-70:A MT51J256M32HF-70:A 4.53K_0402_1% 2K_0402_1%


    SA000081700 SA000081700 SD03445318J SD03420018J

    A VRAM_Micron 8GX2 R18 A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/08 Deciphered Date 2013/08/05 Virtual symbol
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Custom
    330ARR 1.0

    Date: Friday, March 23, 2018 Sheet 43 of 52


    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B
    Vinafix.com B

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2013/08/15 Deciphered Date 2013/08/15 Power sequence Block


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 330G-ARR
    Dat e: Friday, March 23, 2018 Sheet 44 of 52
    5 4 3 2 1
    5 4 3 2 1

    B+
    +5VLP/ 100mA

    +5VALW/8A
    Adaptor Richtek
    EC_ON EN PGOOD ALW_PWRGD
    LV5083AGQUF
    +3VLP/ 100mA
    D
    PMIC D

    FOR 3/5VALW +3VALW/6A

    EC_ON EN PGOOD +3VALW_PG

    LCFC +1.2V/6A
    LV5075B
    1.2VEN S5 PMIC +0.6VS/1A
    SUSP# S3
    TI FOR SYS
    POK_VDDQ
    BQ24780SRUYR +5VALW
    Battery Charger +0.9V/6A
    EC_APU_ALWEN EN
    PGOOD APUALW_PWRGD
    Switch Mode
    +3VALW +1.8VALW/3A
    C C

    EC_APU_ALWEN EN PGOOD APUALW_PWRGD

    Vinafix.com
    SMBus +1.8VALW
    +0.9VALW/1A
    APUALW_PWRGD EN

    +3.3VALW

    Battery 2.5VEN EN
    +2.5V/1A

    Li-ion
    2S1P
    Richtek
    LV5095BGQUF +1.35VGS /8A
    PMIC
    FOR 1.35VGS
    B B
    PXS_PWREN EN PGOOD

    Richtek
    +VDDC/28A
    RT3662ACGQW
    controller
    +VDDCI1/8A
    FOR VGA_CORE
    PXS_PWREN EN PGOOD VR_VGA_PWRGD

    APL5930KAI
    LDO +VDD_08_1/2A
    PXS_PWREN EN FOR VDD_08_1
    (R18M)

    Richtek VDDC_VDD/35A
    RT3662ACGQW
    A
    controller A

    APU_SVID VIDs
    VDDCR_SOC/10A
    EN FOR CPU CORE&NB PGOOD
    EC_VR_ON VR_APU_PWRGD

    Security Classification LC Future Center Secret Data Title

    Issued Date 2013/08/15 Deciphered Date 2013/08/15 Power Diagram


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Custom
    330G-ARR 1.0

    Date: Friday, March 23, 2018 Sheet 45 of 53


    5 4 3 2 1
    5 4 3 2 1

    PL101 EMC@
    VMB BATT+
    HCB2012KF-121T50_0805
    1 2 VIN PL103 EMC@
    HCB2012KF-121T50_0805
    1 2
    D PL102 EMC_NS@ GND4 16 D
    HCB2012KF-121T50_0805 GND3 15
    1 2 GND2 14 PL104 EMC@
    GND1 13 HCB2012KF-121T50_0805
    PJ101 @ 12 12 1 2
    JDCIN1 PF101 JUMP_43X79 11 11
    1 APDIN 1 2 APDIN1 1 2 10 10
    1 1 2

    1
    2 9 9 PC106 PC107
    GND1 3 7A_24VDC_429007.WRML 8 EC_SMCA 1000P_0402_50V7K 0.01U_0402_25V7K
    GND2 8
    4 7 EC_SMDA
    GND3 7 EMC@ EMC@

    2
    5 6 AZC199-02S.R7G_SOT23-3

    1000P_0402_50V7K

    1000P_0402_50V7K
    100P_0402_50V8J

    100P_0402_50V8J
    GND4 6 6 5 PD103

    PC101EMC@

    PC102EMC@

    PC103EMC@

    PC104EMC@
    GND5 5

    2
    7 4
    GND6 4 3
    3

    1
    2

    100_0402_1%

    100_0402_1%
    2

    2
    HIGHS_PJSS0026-8B01H 1

    PR106

    PR105
    1
    ME@ JBATT1
    SUYIN_125022HB012M200ZL

    2
    ME@

    EMC_NS@

    1
    EC_SMB_CK1 39,48

    C C
    EC_SMB_DA1 39,48
    100K_0402_1%

    Vinafix.com
    PR107
    1 2
    +3VALW

    BATT_TEMP_IN 1 2
    BATT_TEMP 39,48
    PR108 A/D
    10K_0402_1%

    B B

    PRTC1
    RTC_VCC
    VCCRTC +3VL

    BATT CR2032 3V 220MAH


    PD101 RTC@
    2
    1 JRTC1
    3 2 1 1
    2 1
    2
    PR104 3
    GC02001YB00-35mm cable , delete when layout
    1U_0402_10V6K

    2 LBAT54CWT1G_SOT323-3 GND1
    1K_0603_1% 4
    PC105

    GND2
    @
    1 HIGHS_WS33020-S0351-HF
    ME@

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2013/08/15 Deciphered Date 2013/08/15 DCIN / RTC


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 330G-ARR
    Date: Friday, March 23, 2018 Sheet 46 of 53
    5 4 3 2 1
    5 4 3 2 1

    V20B+
    D D

    PQ201
    AON6414AL_DFN8-5
    PQ202 @
    P2 AON7408L_DFN8-5 P3 PJ201 PR201
    JUMP_43X79 0.01_1206_1%
    1 1
    2 2 S1 5 2 1 1 4
    5 3 3 S2 D 2 1
    VIN S3 2 3

    220P_0402_50V7K

    470P_0402_50V7K

    680P_0402_50V7K

    220P_0402_50V7K

    470P_0402_50V7K

    680P_0402_50V7K
    4700P_0402_50V7-K

    6800P_0402_25V7-K

    4700P_0402_50V7-K

    6800P_0402_25V7-K
    0.01U_0402_50V6-K

    0.01U_0402_50V6-K
    10U_0603_25V6-M

    10U_0603_25V6-M
    1 4

    5
    PC329

    PC330

    PC331

    PC332

    PC333

    PC334

    PC335

    PC336

    PC337

    PC338

    PC339

    PC340
    470P_0402_50V7K

    0.022U_0402_25V7K

    1
    EMC_NS@

    EMC_NS@
    4.7_0603_5%
    1

    1
    PC201

    PR202

    2
    EMC_NS@

    EMC_NS@

    EMC_NS@

    EMC_NS@

    EMC_NS@

    EMC_NS@

    EMC_NS@

    EMC_NS@

    EMC_NS@

    EMC_NS@

    EMC_NS@

    EMC_NS@
    PC202

    PC203

    PC204
    2

    2
    2

    2
    780s_BATDRV 4
    2

    PQ203

    0.01U_0402_25V7K
    AON6324_DFN8-5

    499K_0402_1%
    1

    3
    2
    1
    1
    780s_ACDRV_R

    PR203

    PC208
    2
    2
    1 2
    VIN VIN BATT+
    PC205
    0.1U_0402_25V6

    0.1U_0402_25V6

    0.1U_0402_25V6
    LBAT54CWT1G_SOT323-3
    1

    1
    4.02K_0603_1%

    4.02K_0603_1%

    1
    PR206

    PR207

    PC206

    PC207
    2

    2
    V20B+

    PD201
    2

    43K_0402_1%
    1

    PR208

    C C

    EMC_NS@

    10U_0805_25V6K

    10U_0805_25V6K
    0.1U_0402_25V6
    2

    2
    PC209

    PC211

    PC212
    BQ24780S_VDD

    ACN
    ACP
    Vinafix.com
    PR209
    0.01U_0402_25V7K

    1
    10_1206_5%
    7.15K_0402_1%
    2

    1
    2
    PC215

    PR210

    2
    PC213 2.2U_0603_10V6-K

    ACN
    ACP

    5
    1U_0603_25V6K PC214
    1

    1 2 780s_VCC 28 24 1 2
    VCC REGN chock：
    1

    AON6380_DFN8-5
    780s_ACDET 6
    ACDET 2.2_0603_5% 0.047U_0603_16V7K DCR=7mohm

    PQ205
    780s_BS 1
    BTST
    25 2 2 1 4
    Idc=12A
    780s_CMSRC 3 26 780s_HG
    PR211 PC216
    Isat=18A
    CMSRC HIDRV PR213

    3
    2
    1
    780s_ACDRV 4 0.01_1206_1%
    ACDRV PL201
    27 780s_LX 1 2 1 4
    ACOK_10k pull high +3VL of open drain output at EC @ 780s_ACOK
    PHASE 2.2UH_PCMB063T-2R2MS_8A_20% BATT+
    0_0402_5% 1 2 PR215 5 2 3

    BQ24780SRUYR_QFN28_4X4

    10U_0805_25V6K

    10U_0805_25V6K

    10U_0805_25V6K
    ACOK

    1
    39 ACIN
    @ 780s_SDA

    1
    0_0402_5% 1 2 PR217 11 PR216

    PC221

    PC217

    PC230
    39,47 EC_SMB_DA1 SDA

    AON6380_DFN8-5
    23 780s_LG
    SMBUS_10k pull high +3VL_EC of open drain output at EC @
    4.7_0805_5%
    LODRV
    EMC_NS@

    PQ206
    PU201

    2
    0_0402_5% 1 2 PR218 780s_SCL 12 22 1 2
    39,47 EC_SMB_CK1 SCL GND

    2
    4
    @ PC228

    0.1U_0402_25V6

    0.1U_0402_25V6
    780s_IADP

    1
    0_0402_5% 1 2 PR219 7 29 PC222 0.1U_0402_25V6
    39 ADP_I IADP PAD

    1
    @ 1000P_0402_50V9-J

    PC223

    PC224
    0_0402_5% 1 2 PR220 780s_IDCHG 8 18 780s_BATDRV
    39 IDCHG IDCHG BATDRV EMC_NS@

    3
    2
    1

    2
    @ 10_0603_5%

    2
    0_0402_5% 1 2 PR221 780s_PMON 9 PR222
    B 39 PSYS PMON 780s_BATSRC 780s_BATSRC_R B
    17 1 2
    BATSRC
    20 780s_SRP 1 2 780s_SRP_R
    780s_VR_HOT 10 SRP
    PROCHOT# PR224 charge：
    100P_0402_50V8J

    100P_0402_50V8J

    100P_0402_50V8J

    PR231
    13
    CMPIN
    10_0603_5%
    current=5A
    BATPRES#

    volatge=2S 595490
    1

    TB_STAT#

    20K_0402_1% 14
    PC225

    PC226

    PC227

    CMPOUT 19 780s_SRN 1 2 780s_SRN_R


    SRN
    780s_ILIM 21
    ILIM fsw=800K/REG0x12[9:8] = 01
    2

    PR225
    10_0603_5%
    16

    15
    2

    0_0402_5% 1 2 PR232
    @ PR226
    39,53 VR_HOT# 0_0402_5%
    780s_TB#

    @
    VR_HOT_10k pull high +3VS_APU of open drain output at APU
    1

    1 2 780s_ILIM_R 1 2
    +3VALW BATT_TEMP 39,47
    PR227 PR228
    143K_0402_1% 32.4K_0402_1%
    100K_0402_1%
    0.1U_0402_25V6

    1
    1

    Charge current limit 7A, discharge current 10A limit during turbo
    PC229

    PR230
    2

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2013/08/08 Deciphered Date 2013/08/05 CHARGER


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    C
    330G-ARR 1.0

    Date: Friday, March 23, 2018 Sheet 48 of 53


    5 4 3 2 1
    5 4 3 2 1

    3VALW:
    TDC=6A
    +5VLP OCP=8A
    OVP=120%
    PJ3501 @
    Fsw=500KHz
    V20B+ 2 1
    2 1 +3VALW_VIN
    5VALW:
    JUMP_43X79 TDC=8A

    10U_0805_25V6K

    10U_0805_25V6K
    0.1U_0402_25V6
    EC_ON pull high reserve at EC，

    EMC@
    OCP=10A

    1
    PC3535

    25
    no need mirror code--enable=3.3V normal mode PU3501 10_0603_5% 0.1U_0603_25V7K
    OVP=120%

    PC3534

    PC3536
    D D
    PR3511 PC3541

    VDDSW
    +3VALW_BS 1

    2
    3 2 1 2
    11
    VIN1
    BOOT1
    PL3501 Fsw=500KHz
    1 +3VALW_LX 1 2 +3VALW_P
    2
    PJ3502 @
    1
    0_0402_5% @ 0_0402_5% @ LX1_1 2 2 1 +3VALW
    PR5996 PR3507
    1 2 1 2 +3VALW_EN +3VALW_EN 10 LX1_2 35 1.5UH_PCMB063T-1R5MS_10A_20% JUMP_43X79

    0.1U_0402_25V6

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    39,50 EC_ON EN1 LX1_3

    @
    +3VALW_P

    1
    6

    PC3537
    1 2 1 2 +5VALW_EN +3VALW_PG 9 VOUT1

    PC3539

    PC3544

    PC3543

    PC3542
    39 MAINPWON PGOOD1
    @

    2
    PD3501
    LRB751V-40T1G_SOD323-2
    PR3510
    0_0402_5%
    @ PC3538
    4
    1 2 7 VBYP3 +3VALW
    34 EC_ON_R VCC1
    +3VLP
    +3VALW 1U_0402_6.3V6K 5
    100mA 2
    PJ3505 @
    1
    2
    PJ3503
    1
    @ +5VALW_VIN LDO3 2 1 +3VL
    V20B+ 2 1 PC3545 1 2 4.7U_0603_6.3V6K
    JUMP_43X39
    JUMP_43X79 10_0603_5%

    0.1U_0402_25V6

    10U_0805_25V6K

    10U_0805_25V6K
    1

    1
    EMC@
    PR3512

    PC3546

    PC3547

    PC3548
    14 22 +5VALW_BS 1 2 PC3554 1 2 0.1U_0603_25V7K
    VIN2 BOOT2
    PL3502

    2
    2

    23 PJ3504 @
    100K_0402_5%
    100K_0402_5%

    LX2_1 +5VALW_LX +5VALW_P


    2

    24 1 2 2 1
    +5VALW
    PR3513

    LX2_2 36 2 1
    @ @
    PR3514

    +5VALW_EN 15 LX2_3 1.5UH_PCMB063T-1R5MS_10A_20% JUMP_43X79

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    EN2 +5VALW_P

    LV5083AGQUF_UQFN36_5X4
    19 1

    0.1U_0402_25V6
    VOUT2
    1

    1
    @
    1

    1
    + PC3572

    PC3549

    PC3555

    PC3552

    PC3553

    PC3551
    ALW_PWRGD 16 150U_B2_6.3VM_R35M
    +3VALW_PG

    ALW_PWRGD

    PGOOD2

    2
    @

    2
    2
    21
    PC3550 VBYP5 +5VALW
    1 2 18
    VCC2
    +5VLP PC3559
    C 20
    100mA 1 2 C
    1U_0402_6.3V6K LDO5
    4.7U_0603_6.3V6K

    +3VALW 33

    1U_0402_6.3V6K
    22U_0603_6.3V6-M
    VINSW1
    @

    +3VALW_LX

    +5VALW_LX
    PJ3506 @

    Vinafix.com
    29 +3VS_SW 1 2 +3VS
    PC3566

    PC3530
    VOUTSW1 1 2
    2

    2
    JUMP_43X79
    0_0402_5% 31 3VS_SS 1 2
    PR3517 SS1
    +3VS_EN

    1
    1 2 30 PC3562
    39,41,50 SUSP# ENSW1
    @ 2200P_0402_25V7-K PR3508
    2.2_0805_5%
    PR3509
    2.2_0805_5%
    @2 1 1U_0402_6.3V6K
    PC3569 PJ3507 @ EMC_NS@ EMC_NS@
    34 28 +5VS_SW 1 2 +5VS
    +5VALW VINSW2 VOUTSW2 1 2

    1+3VALW_SN 2

    1+5VALW_SN 2
    22U_0603_6.3V6-M

    @ JUMP_43X79
    1U_0402_6.3V6K

    1U_0402_6.3V6K
    5VS_SS 1
    1

    1
    0_0402_5% 26 2
    PC3531

    PC3568
    SS2
    PR3518 @
    PC3565

    +5VS_EN

    PGND_2

    PGND_1

    AGND_2

    AGND_3

    AGND_1
    SUSP# 1 2 27 PC3561
    ENSW2
    2

    2
    @ 2200P_0402_25V7-K

    PC3570
    @2 1 1U_0402_6.3V6K PC3532 PC3533
    1000P_0402_50V7K 1000P_0402_50V7K

    2
    13

    12

    17

    32
    EMC_NS@ EMC_NS@

    B B

    PD3502
    PD3503 1SS355VMTE-17
    PTC
    0_0402_5%
    PR3519
    1SS355VMTE-17 PR3520
    100K_0402_1%
    PR3521
    10K_0402_1%
    1 2
    VIN (DC/DC FET protection)
    1 2 2 1 1 2 1 2
    49,57 EC_ON 1
    NEC@2
    @ V20B+
    NEC@ NEC@ NEC@
    2

    PD3504 1SS355VMTE-17
    NEC@
    3

    E
    2
    B
    PQ3501 PR3522
    PMBT3906 750K_0402_5%
    1

    C
    NEC@
    1

    NEC@ VDDQ_1.2V Charger APU_VDD PHASE1 APU_VDD PHASE2


    540_0402NEW_30% 540_0402NEW_30% 540_0402NEW_30% 540_0402NEW_30%
    1

    C PRT01 PRT02 PRT03 PRT04


    PQ3502 2 2 1 2 1 2 1 2 1
    PMBT3904 B
    E
    NEC@ NEC@ NEC@ NEC@
    1U_0603_25V7K
    3

    D
    2

    NEC@ 2
    PC3571

    OTP_RESET 42
    G
    1

    S
    3

    PQ3503
    2N7002WT1G PRT08 PRT07 PRT06 PRT05
    NEC@ NEC@
    540_0402NEW_30%
    2 1
    540_0402NEW_30%
    2 1
    540_0402NEW_30%
    2 1
    540_0402NEW_30%
    2 1

    NEC@
    A GPU_VDDC PHASE2 GPU_VDDC PHASE1 GPU_VDDCI APU_SOC A

    @ @ @
    PRT08 NEC_R17 R18 part on PTC,NEC_UMA part on 0ohm
    PRT07:NEC_R17 R18 part on PTC,NEC_UMA part in 0ohm
    PRT06:NEC_R17part on PTC,NEC_R18 UMA part on 0ohm
    Security Classification LC Future Center Secret Data Title

    Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR_3VALW/5VALW


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    C
    330G-ARR 1.0

    Date: Friday, March 23, 2018 Sheet 49 of 53


    5 4 3 2 1
    5 4 3 2 1

    LV5075_VCC

    @ LV5075_VDDQ_EN
    10_0603_5%
    PR1902 1 2 0_0402_5% PR1907 @
    39 1_2VEN 1 2 PR1901 1 2 0_0402_5%
    +5VLP
    SYSON-1_2VEN EC_ON 39,49

    PC1909 2 1 0.1U_0402_10V6-K 2 1 1 2
    @ @
    @ LV5075_VTT_EN
    PC1902 PC1903
    PR1904 1 2 0_0402_5% 2.2U_0603_6.3V6K 0.1U_0402_10V6-K

    LV5075_LX_0.9VS
    39,41,49,50 SUSP#

    LV5075_LX_1P8
    D D
    PR1909

    LV5075_PMIC_EN
    1 2
    +1.2V_B+

    LV5075_VSYS
    PC1908 2 1 0.1U_0402_10V6-K
    @ 10_0402_5%
    1 2
    @ LV5075_0.9VS_EN
    PR1906 1 2 0_0402_5% PC1901

    2
    39,41,49,50 SUSP#

    EMC_NS@

    EMC_NS@
    4.7_0603_5%

    4.7_0603_5%
    1U_0402_25V6-K

    PR1918

    PR1919
    28

    27

    41
    PU1901

    9
    PR1913 1 2 0_0402_5%
    39,50 EC_APU_ALWEN
    @

    VSYS

    PMIC_EN
    VCC

    GND

    1
    LV5075_0.9ALW_EN 29 25 LV5075_EC_SMB_DA2 @
    PR1925 1 2 0_0402_5%
    2 1 0.1U_0402_10V6-K EN_LDO1 SDA EC_SMB_DA2 34,39
    PC1907
    LV5075_2.5V_EN 1 26 LV5075_EC_SMB_CK2 @
    PR1926 1 2 0_0402_5%

    680P_0402_50V7K

    680P_0402_50V7K
    @ EN_LDO2 SCL EC_SMB_CK2 34,39

    EMC_NS@

    EMC_NS@
    @ LV5075_1P8VA_EN LV5075_0.9VS_EN LV5075_ALERT# 0.9V:

    1
    PR1908 1 2 0_0402_5% 11 24 PR1912 1 @ 2 0_0402_5%

    PC1930

    PC1931
    39,50 EC_APU_ALWEN EN_V1P0A T_ALERT_B PR1915 2 @ 1 100K_0402_5%
    H_PROCHOT# 6,39 0.9VS/VDDP=4A
    EC Push,no pull high,not support 1.8V SPI mirror code LV5075_1P8VA_EN 16 22 0.9V_PWRGD +3VALW TDC=6A
    EN_V1P8A POK_V1P0A 0.9V_PWRGD 39

    2
    PC1906 2 1 0.1U_0402_10V6-K LV5075_VDDQ_EN 31 21 APUALW_PWRGD
    PR1927 2 1 100K_0402_5%
    +3VALW OCP=10A
    @
    EN_VDDQ POK_V1P8A APUALW_PWRGD 39 OVP=120%
    APUALW_PWRGD @ LV5075_0.9ALW_EN
    LV5075_VTT_EN 36
    EN_VTT POK_VDDQ
    23 Fsw=1M
    PR1910 1 2 0_0402_5% PJ1901 @
    1 2 LV5075_0.9VS_VIN

    22U_0603_6.3V6-M 22U_0603_6.3V6-M
    APUALW_PWRGD need delay to EC after 0.9VALW power up +5VALW 1 2 12 LV5075_LX_0.9VS
    @

    0.1U_0402_25V6
    PL1901 PJ1902
    LX_V1P0A_12 +0.9VS_P

    LV5075BGQV_VQFN40_5X5
    EMC_NS@ EMC_NS@
    7 13 1 2 2 1

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    PC1910

    PC1911
    JUMP_43X39
    PC1905 2 1 0.1U_0402_10V6-K 8 VIN_V1P0A_7 LX_V1P0A_13 14 0.47UH_CMMB062D-R47MS_15A_20% 2 1 +0.9V
    VIN_V1P0A_8 LX_V1P0A_14

    1
    @ 15

    PC1912

    PC1913

    PC1914

    PC1915

    PC1916

    PC1917
    JUMP_43X79
    LX_V1P0A_15

    2
    @ 10
    LV5075_2.5V_EN VO_V1P0A

    2
    PR1911 1 2 0_0402_5% PJ1903 @
    39 2_5VEN 1 2 LV5075_V1P8_VIN
    @ @
    EC-2_5VEN +3VALW 1 2 17 LV5075_LX_1P8
    @

    0.1U_0402_25V6
    PL1902 PJ1904
    LX_V1P8A_17 +1.8VA_P

    1
    19 18 1 2 2 1

    PC1918

    PC1919
    JUMP_43X39
    PC1904 2 1 0.1U_0402_10V6-K VIN_V1P8A_19 LX_V1P8A_18 1UH_PH041H-1R0MS_3.8A_20% 2 1 +1.8VALW
    @ 20

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    VO_V1P8A_20
    JUMP_43X79
    1.8VALW:

    1
    PC1920

    PC1921

    PC1922

    PC1923
    APU_VDD18+GPU_VDD18=2A+1A=3A(TDC)
    C
    UGATE_VDDQ
    33 LV5075_UG_1.2V
    TDC=3A C

    2
    +1.2V_P
    38
    VIN_VTT 32 LV5075_BST_1.2V 1
    PR1916
    2
    PC1925
    1 2
    OCP=6A
    1 2 BOOT_VDDQ @ @ OVP=120%
    39
    VTT LV5075_LX_1.2V
    0_0603_5% 0.1U_0603_25V7K Fsw=1M
    PC1924 34

    Vinafix.com
    PHASE_VDDQ
    2
    PJ1905
    1 +0.6VSP
    10U_0603_6.3V6M
    40 35 LV5075_LG_1.2V +1.2V_B+ 1
    PJ1908
    2
    @
    +0.6VS 2 1 VSNS_VTT LGATE_VDDQ 1 2 V20B+

    1
    @

    10U_0805_25V6K

    10U_0805_25V6K
    0.1U_0402_25V6
    +1.2V_P

    EMC_NS@
    22U_0603_6.3V6-M PR1917 @ 37 JUMP_43X39 JUMP_43X39
    2 LV5075_CS 30 VSNS_VDDQ

    1
    1 @

    PC1929

    PC1932

    PC1933
    JUMP_43X39 PC1926 PJ1907
    CS_VDDQ

    2
    33K_0402_1% 1 2 @
    JUMP_43X39 1 2 +0.9VALW

    2
    5
    1
    PJ1906
    2
    @ LV5075_0.9VALW_VIN 5 6 +0.9VALW_P 1 2 0.9V:

    AON7408L_DFN8-5
    +1.8VALW VDDP_S5=1A

    D
    1 2 VIN_LDO1 LDO1

    PQ1901
    PC1928
    PC1927 10U_0603_6.3V6M
    10U_0603_6.3V6M LV5075_UG_1.2V
    4
    G

    2
    JUMP_43X39
    3 +2.5V_P 1
    PJ1910
    2
    @
    PJ1909 @ +2.5V

    S3
    S2
    S1
    1 2 LV5075_2.5V_VIN 4 LDO2 1 2 0.47UH_CMMB062D-R47MS_15A_20%
    +3VALW 1 2 VIN_LDO2 2 @

    10.5K_0402_1% 24.9K_0402_1%
    JUMP_43X39 PL1903 PJ1911
    FB_LDO2 LV5075_LX_1.2V +1.2V_P

    3
    5 2
    1
    1

    1
    1 2
    1A 1 2 2
    2 1
    1
    +1.2V

    PR1920
    PC1934

    +2.5V_FB

    2
    10U_0603_6.3V6M JUMP_43X79
    2

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    PC1935
    2.5V: PR1922

    AON7506_DFN8-5
    10U_0603_6.3V6M 4.7_0805_5%
    ICCMAX=240mA

    1
    PQ1902
    EMC_NS@

    PC1937

    PC1938

    PC1939

    PC1940

    PC1941

    PC1942
    LV5075_LG_1.2V 4

    1
    1

    2
    PR1921

    1
    PC1943
    680P_0402_50V7K
    EMC_NS@ @ @

    3
    2
    1

    2
    1.2V:
    VDDIO_MEM_S3=6A DRAM=7A
    B TDC=10A B

    OCP=20A
    OVP=120%
    Fsw=1M

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2014/02/20 Deciphered Date 2014/02/20 System PMIC
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    A2
    330G-ARR 1.0

    Date: Friday, March 23, 2018 Sheet 50 of 53


    5 4 3 2 1
    A B C D

    1 1

    +1.35VGS:
    modify symbol PN： ，need update new SYMBO
    SA00008WM00, S IC LV5095BGQUF UQFN 29P PMIC L VMEMIO=2A/8A memory=6A
    FB=0.6V
    PJ3601 @ +1.35V_BST
    10_0603_5%
    PR3615 TDC=10A
    V20B+ 2 1 1 2
    OCP=13A

    0.1U_0603_25V7K
    2 1

    10U_0805_25V6K

    10U_0805_25V6K
    JUMP_43X39 PX@
    OVP=130%

    1
    PC3601 PX@

    PC3602 PX@

    PC3603
    Fsw=500Khz

    1
    PX@

    18

    2
    5
    PU3601 PL3601 @

    2
    0.68UH_PCMB063T-R68MN_16A_20% PJ3602

    AGND

    VBOOT
    +1.35V_VIN 12 3 +1.35V_LX 1 2 +1.35V_P 2 1
    VIN4 SW_1 PX@ 2 1 +1.35VGS

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    PX@ JUMP_43X79
    +1.35V_EN

    1
    PR3602 1 2 200K_0402_1% 16 4

    42.2K_0402_1% 10_0402_1%
    7,52 PXS_PWREN
    EN4 SW_2

    1
    PR3613

    PC3611

    PC3606

    PC3608

    PC3607

    PC3612

    PC3609
    PR3603 PX@
    2.2_0603_5%

    PC3613

    PC3610
    PX@
    PC3604 1 2 0.1U_0402_25V6 15 EMC_NS@ 1K_0402_1%
    FB

    2
    25 PR3606
    NC_3

    1 2

    2
    1 2
    23

    560P_0402_50V7-K
    NC_2

    1
    22 PC3619 PX@
    NC_1 PX@ PX@ @ @ PX@ PX@ @ @

    PC3620

    PR3607
    1000P_0402_50V7K
    +5VALW

    2
    6 EMC_NS@ PX@ PX@
    PGND_1

    1
    7
    PGND_2

    2
    PC3616 PX@ 2 11U_0402_6.3V6K 24 PR3614
    VCC_SW 8 +1.35V_FB
    PGND_3 0_0402_5%
    PC3614 PX@ 1 2 0.1U_0402_25V6

    32.4K_0402_1%
    1
    9 @
    PXS_PWREN +3VGS_EN PGND_4

    2
    PR3604 1 2 0_0402_5% 19

    PR3609
    EN2 10 PX@
    PX@
    PGND_5
    @ 21 11
    +3VALW VIN2 PGND_6

    2
    2 GPU_VMEMIO_SENSE 23 2

    PC3615 PX@ 2 1 1U_0402_6.3V6K


    VOUT2
    20 +3VGS
    PXS_PWREN PR3608 PX@1 2 20K_0402_1% +1.8VGS_EN 28

    10U_0603_6.3V6M

    1U_0402_6.3V6K
    EN3

    1
    PC3621 PX@ 1 2 0.1U_0402_25V6

    PC3617

    PC3618
    +3VGS:

    Vinafix.com
    1 26 @ PX@
    +1.8VALW VIN3_1 VOUT3_1
    VDD_33=10mA

    2
    2 1 2 27
    PX@ VIN3_2 VOUT3_2
    PC3622 29
    1U_0402_6.3V6K VIN3_3

    TH_ALT

    PGOOD
    +1.8VGS

    VCC
    Loadcapacity：

    10U_0603_6.3V6M
    rail1=0.5A,Rdson=36mohm

    1U_0402_6.3V6K
    14

    17

    13
    rail2=1A,Rdson=18mohm

    1
    PC3623

    PC3624
    @ PX@
    rail3=3.5A,Rdson=5mohm +1.8VGS:

    2
    VDD_18=1A
    PR3611 PR3610
    100K_0402_1% 100K_0402_1%
    @ @

    1
    1
    PC3629
    1U_0402_6.3V6K
    PX@

    3 3

    4 4

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/15 Deciphered Date 2013/08/15 PWR_1.35VGS
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    A2
    330G-ARR 1.0

    Date: Friday, March 23, 2018 Sheet 51 of 53


    A B C D
    5 4 3 2 1

    PC602 EMC_PX@
    V20B+

    10U_0805_25V6K

    10U_0805_25V6K
    0.1U_0402_25V6

    PC604 PX@

    PC605 PX@
    1

    1
    5
    PQ601

    2
    AON6380_DFN8-5

    VDDC_UGATE1
    4
    L=0.22uH
    DCR=0.98m ohm
    Irms=34A
    PR601 PX@ Isat=35A

    3
    2
    1
    0_0402_5%
    1 2
    PX@
    PX@ PL601 S i z e ：6 . 8 * 7 . 6 * 4
    20 GPU_VSSC_SENSE 0.22UH_PCME064T-R22MS0R985_28A_20%
    VDDC_PHASE1 VDDC_PHASE1
    PR603 PX@ 1 2

    1
    100_0402_1%
    2 PR602 EMC_NS@ @ @
    +VDDC
    PC606 1 1

    0.1U_0402_25V6
    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    330P_0402_50V8J PC612 PX@ 2.2_0603_5%
    VDDC_BOOT1

    1
    330U_D2_2V_Y

    330U_D2_2V_Y
    100_0402_1% PX@ PC611 68P_0402_50V8J 1 2 1 2 PQ602 PR604 PJ601 PJ602 + +

    PC607

    PC608

    PC609

    EMC_PX@ PC610
    PC4362

    PC4363
    D PR606 PX@ 1 2 1 2 4.7_0603_5% D
    AON6324_DFN8-5 JUMPER JUMPER

    PC654
    1

    1
    1 2 PX@
    +VDDC 0.1U_0603_25V7K

    2
    2 2
    VDDC_LGATE1

    1
    PX@ 4

    R18@

    @
    0_0402_5%
    R18 LL=1mohm,PR609=18.7K @ @ @

    PX@
    PR607 PX@ PR609 R17@ PR612
    2.94K_0603_1%
    20 GPU_VDDC_SENSE 1 2 1 2 1 2
    R17 LL=0.6mohm,PR609=31.6K EMC_NS@

    2
    PX@
    PR608 PX@ 31.6K_0402_1% PC613

    3
    2
    1

    2
    10K_0402_1% 680P_0402_50V7K
    VR_VGA_PWRGD PX@

    1
    17

    2
    1 2 PR611 1
    @ 2 0_0402_5% PR628

    PC614
    @ 2.94K_0603_1%
    PX@
    330P_0201_25V7-K R17-P1-50-18W:+VDDC
    LL=0.6m

    1
    3662_VREF
    VDDC_ISEN1P
    PC616 PX@ TDC=20A
    2 1
    EDC=50A
    0.1U_0402_25V7-K OCP=80A
    10K_0402_1% 1_0402_1%
    PR610 PX@
    VDDC_ISEN1N
    PR618 PX@ DC tolerance=VID-VDDCX0.6 +/- 20mV
    1 2 +3VGS 1 2 AC tolerance: overshoot 120mV, undershoot 90mV
    1

    PR614 PR615 PR616 2 1


    5.9K_0402_1%
    PR621 PX@ R18-M2-60-18W:+VDDC merger VDDCI
    VDDC_ISEN2P
    665K_0402_1%
    PX@
    64.9K_0402_1%
    PX@
    255K_0402_1%
    PC618 PX@
    1 2 LL=1.0m
    R17@ 0.1U_0402_25V6 TDC=25A

    VR_VGA_PWRGD
    +3VGS
    2

    EDC=60A

    VDDC_ISEN1N

    VDDC_ISEN1P

    VDDC_ISEN2P

    VDDC_COMP
    VDDC_VSEN

    3662_RGND
    VDDC_BOOT2
    OCP=80A

    VDDC_FB
    VDDC_UGATE2
    PX@ PX@ DC tolerance=VID-VDDCX1.0 +/- 15mV
    AC tolerance: overshoot TDB, undershoot TDB
    1

    1
    PR619 PR620 PR617 V20B+
    1.43K_0402_1% 4.53K_0402_1% 4.7K_0402_1%

    10

    6
    8
    9

    1
    PX@ R17@ 100K_0402_1%_NCP15WF104F03RC @

    EMC_PX@
    PH601

    FB
    VSEN
    ISEN1N

    COMP

    RGND
    ISEN1P

    ISEN2P

    PGOOD

    BOOT2

    UGATE2
    2

    0.1U_0402_25V6
    PX@
    VDDC_PHASE2

    10U_0805_25V6K

    10U_0805_25V6K
    1

    1
    1 2 40

    PC619
    PHASE2
    @

    PC620

    PC623
    GPU_VR_HOT# VDDC_LGATE2
    18,39 GPU_VR_HOT# PR661 1 2 0_0402_5% 11 39
    VRHOT_L LGATE2

    2
    5
    VDDC_TSEN_R VDDC_TSEN VDDC_TSEN VDDC_BOOT1
    1 2 12 38 PQ603

    PR626 PX@
    GPU_VR_HOT# pull high to +3VGS at GPU 3662_SET1
    13
    TSEN BOOT1
    37 VDDC_UGATE1 AON6380_DFN8-5

    60.4K_0402_1% SET1 UGATE1


    VDDC_IMON VDDC_PHASE1 VDDC_UGATE2
    0.47U_0402_25V6K 3.9_0402_1% 14 PU601 36 4
    3662_SET1 IMON PHASE1
    PC640 PX@ PR647 PX@ RT3662ACGQW_WQFN40_5X5
    3662_VREF VDDC_LGATE1
    2 1 2 1 15 35
    PX@ VREF_PINSET LGATE1 @
    VDDCI_IMON 3662_PVCC
    60.4K_0402_1% PR4396 1 2 4.7K_0402_1% 16 PX@ 34 PR622 1 2 0_0603_5% +5VALW PX@
    +1.8VGS IMON_NB PVCC

    3
    2
    1
    PR629 R17@ @ PL602
    VDDCI_TSEN_R VDDCI_TSEN VGA_PWROK GPU_POK_R 3662_VCC PX@
    1 2 PR623 1 2 18 17 1 2 0.22UH_PCME064T-R22MS0R985_28A_20%
    17 VGA_PWROK PWROK VCC VDDC_PHASE2 VDDC_PHASE2
    C 1 2 C
    18 GPU_SVC
    0_0402_5% 19
    SVC LGATE_NB
    33 VDDCI_LGATE
    PR624 PX@ +VDDC

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    4.7_0402_5% PR633 EMC_NS@

    2.2U_0402_6.3V6-K
    VDDCI_PHASE 1 1

    0.1U_0402_25V6
    1 2 20 32 1 1 2.2_0603_5% @ @
    18 GPU_SVD SVD PHASE_NB VDDC_BOOT2
    1

    1
    330U_D2_2V_Y

    330U_D2_2V_Y
    1 2 1 2 PQ604 PR636 + +

    2.2U_0402_6.3V6-K
    PX@ PC624

    PX@ PC625

    PC627

    PX@ PC628

    R18@ PC630

    R18@ PC631

    PC632
    PC4364

    PC4365
    VDDCI_UGATE
    PH602 R17@ 21 31 AON6324_DFN8-5 4.7_0603_5% PJ603 PJ604
    18 GPU_SVT SVT UGATE_NB

    ISENN_NB
    PR630 PR631 100K_0402_1%_NCP15WF104F03RC PC626 PX@ JUMPER

    ISENP_NB

    COMP_NB
    PX@

    BOOT_NB
    JUMPER

    TSEN_NB
    Vinafix.com

    2
    2 2 2 2

    EMC_PX@
    33.2K_0402_1% 24.3K_0402_1% 0.1U_0603_25V7K

    R18@
    VDDC_LGATE2

    FB_NB
    VDDIO

    1
    PX@ R17@ 4 @ @
    VBOOT Pull high/low portion

    GND
    2

    1
    EMC_NS@

    VIN

    EN

    2
    PR644
    1

    PC634 2.94K_0603_1%

    41

    22

    23

    24

    25

    26

    27

    28

    29

    30
    PR637 PR634 PR635 680P_0402_50V7K

    3
    2
    1

    1
    16K_0402_1% 402_0402_1% 100_0402_1% PX@
    PX@

    2 2
    PX@ PX@ R17@

    3662_VDDIO
    2

    PR627

    VDDCI_COMP

    VDDCI_BOOT
    VDDCI_TSEN

    VDDCI_EN_1
    2.2_0402_1% 2.94K_0603_1%
    PR632 PX@
    +1.8VGS 1 2

    1
    PX@
    0.1U_0402_25V7-K
    2 1 PC638 PX@
    3662_VREF 0.1U_0402_25V6 1 2 VDDC_ISEN2P
    2 1
    PC633 PX@ PC653 PXS_PWREN 7,51,52
    R17@

    3662_VIN
    1U_0402_6.3V6K 2 1 PR638 PX@
    100K_0402_1%
    PR648
    VDDCI_ISEN1N VDDC_ISEN1N
    1 2 1 2
    1

    10.5K_0402_1% PR660 PC4360 PX@ PX@ 1_0402_1%


    PR4377

    VDDCI_FB
    PR646 PX@ 0_0402_5% 0.1U_0402_25V6
    VDDCI_ISEN1P PR652
    1 2 2 1 R18@
    +5VALW VDDCI_ISEN1P
    1 2 VDDC_ISEN1P
    1 2
    V20B+
    2

    10K_0402_1% PR639 PX@ 5.9K_0402_1% PX@


    1 2VDDC_IMON_R 1 2 1 2 1 2 VDDC_IMON
    R18@ 4.7_0402_5%

    PH603 PX@ PR649 PX@ PR650 PX@ PR651 PX@ 1 2


    100K_0402_1%_NCP15WF104F03RC 15.8K_0402_1% 1.33K_0402_1% 0_0402_5% R18M-M2-60 -disable VDDCI
    PC635 PX@
    14.7K_0402_1% 0.1U_0402_25V6 V20B+
    1 2

    EMC_R17@
    0.1U_0402_25V6

    PC644 R17@

    PC645 R17@
    PR653 R17@

    PC642
    330P_0402_50V8J 68P_0402_50V8J
    VDDCI_IMON_R VDDCI_IMON

    10U_0805_25V6K

    10U_0805_25V6K
    1

    1
    1 2 1 2 1 2 1 2 PC636 R17@ PC637 R17@
    R17-P1-50:+VDDCI merger +VDD_08

    5
    1 2 1 2
    100_0402_1%
    L=0.36uH
    PH604 R17@ PR654 R17@ PR655 R17@ PR656 R17@ PR640 R17@ 0.875V

    D
    DCR=1.4m ohm

    2
    100K_0402_1%_NCP15WF104F03RC 11.8K_0402_1% 8.87K_0402_1% 0_0402_5% 1 2
    +VDDCI
    Irms=24A TDC=8A
    1 2 VDDCI_FB_R
    1 2 1 2 VDDCI_UGATE
    4
    PQ605
    AON7408L_DFN8-5 Isat=24A EDC=12A
    20 GPU_VDDCI_SENSE G
    R17@ S i z e ：6 . 8 * 7 . 3 * 4 OCP=14A
    PR641 R17@ PR642 R17@ PR643 R17@
    DC tolerance: +/-3%

    S3
    S2
    S1
    0_0402_5% 10K_0402_1% 71.5K_0402_1%
    AC tolerance: +/-3%

    3
    2
    1
    B R17@ B
    1

    PL603
    PC639@ 0.36UH_PDME064TR36MS1_24A_20%
    VDDCI_PHASE VDDCI_PHASE
    330P_0201_25V7-K 1 2
    +VDDCI1
    2

    PR657 EMC_NS@

    EMC_R17@
    1

    0.1U_0402_25V6
    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    2.2_0603_5% @ @
    VDDCI_BOOT

    1
    330U_D2_2V_Y
    1 2 1 2 +

    R17@

    R17@

    R17@
    PR658

    PC647

    PC650
    4.7_0603_5% PJ605 PJ606

    PC648

    PC649
    PC646 R17@
    R17@ JUMPER JUMPER

    2
    2

    1
    0.1U_0603_25V7K PQ606
    VDDCI_LGATE

    1
    4 AON7506_DFN PR659
    1.65K_0603_1%
    R17@
    EMC_NS@ R17@

    2
    PC651

    3
    2
    1
    680P_0402_50V7K

    2
    PR662 330U change PN from SGA00008Q00 to SGA20331E1J 7/24
    1.65K_0603_1%
    R17@ @
    PJ2404

    1
    +VDDCI1 2 1
    PC652 2 1 +VDDCI
    VDDCI_ISEN1P
    2 1 JUMP_43X79

    0.1U_0402_25V7-K @
    PJ2406
    R17@ +VDDCI1 2
    2 1
    1
    +VDD_08
    JUMP_43X79
    VDDCI_ISEN1N

    R17M-P1-50 -PJ2404 PJ2406short

    0.95V for R18M-M2-60 +VDD_08_1


    +5VALW 0.95V
    TDC:2A
    1U_0402_10V6K Max: 3A
    PC701 R18@ @
    2 1 PJ2403
    +VDDC 2 1
    2 1 +VDDCI
    R18@
    +1.2V 10U_0603_6.3V6M PU701 APL5930CKAI-TRG_SO8
    JUMP_43X79

    PC702 6 7
    2
    R18@
    1 5 VCNTL POK
    VIN 3
    VOUT1 4 +VDD_08_1

    PR703 R18@

    PC705 R18@

    PC706 R18@

    PC707 R18@
    +VDD_08_1_EN VOUT2
    A 7,51,52 PXS_PWREN 1 2 8 A
    EN +VDD_08_1_FB
    9 2

    GND
    EPAD FB

    4.53K_0402_1%

    220P_0402_50V7K
    1

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    PR701 @

    @
    1

    1
    40.2K_0402_1% PJ2405
    +1.2V +VDD_08_1
    2 1

    0.1U_0402_25V7-J
    PC703
    R18@ 2 1 +VDD_08

    1
    1
    PC6083 R18@

    PC6084 R18@

    PC6082 R18@
    @

    PC704
    2

    2
    JUMP_43X79

    2
    2
    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    PR702 R18@
    1

    24K_0402_1%
    R18M-M2-60 -PJ2403 PJ2405short

    2
    add 3pcs 22*uf capacity for 1.2V current add with R18 M2 60 GPU
    Security Classification LC Future Center Secret Data Title

    Issued Date 2017/06/24 Deciphered Date 2018/06/23 PWR-GPU_CORE_AMD


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Custom
    330G-ARR 1.0

    Date: Friday, March 23, 2018 Sheet 52 of 53


    5 4 3 2 1
    5 4 3 2 1

    V20B+

    6A

    2200P_0402_25V7-K
    PR5902 close to APU side

    10U_0805_25V6-K

    10U_0805_25V6-K
    0.1U_0402_25V6
    1 1

    EMC@

    EMC@

    22U_25V_M

    68U_25V_M
    1

    1
    2 1 + +
    L=0.24uH

    PC6069

    PC5905

    PC5903

    PC5904

    PC5986

    PC5987
    5
    PR5902 DCR=1.14m ohm

    AON6380_DFN8-5

    2
    20_0402_1% 2 2
    @ Irms=35A
    1 2 follow richtek suggestion Isat=32A

    PQ5901
    6 VDDCR_VSS_SENSE VDDCR_UGATE2
    4
    PR5901
    PC6076
    @
    PR5991
    @1
    S i z e ：7 . 4 * 6 . 8 * 3
    D
    10_0402_1% 1 2 2 +VDDC_VDD D

    680P_0402_50V7K 100_0402_5%
    PC5907

    3
    2
    1
    PL5901
    Kelvin routing 1 2 1 2 VDDCR_PHASE2 VDDCR_PHASE2 0.24UH_PCME063T-R24MS1R145_35A_20%
    1 2 35A
    PC5906 56P_0402_50V8-J

    EMC_NS@
    220P_0402_50V7K
    PR5906 PC5908 @ @ APU_VDDCR

    2
    PR5907

    4.7_0805_5%
    VDDCR_BOOT2 VDDCR_BOOT2_R
    2 1 1 2 1 2 1 2 1 2 PJ5903 PJ5904 1 1 1 1 FSW=400KHz

    330U_D2_2V_Y

    330U_D2_2V_Y

    330U_D2_2V_Y

    330U_D2_2V_Y
    6 VDDCR_VCC_SENSE

    AON6324_DFN8-5

    AON6324_DFN8-5

    PR5908
    PR5905

    PC5957

    PC5956
    JUMPER JUMPER
    Slew rate:12.5mv/us

    1 1

    1
    PR5904 10K_0402_1% 31.6K_0402_1% 2.2_0603_5% 0.22U_0603_25V7K + + + +

    PC5911

    PC5912
    10_0402_1% TDC=35A EDC=45A
    Kelvin routing

    PQ5902

    PQ5903
    PC5909 VDDCR_LGATE2

    2
    @ 4 4 PR5909
    OCP=67.5A

    VDDCR_SN2
    1 2 1 2 PR5993 1 2 0_0402_5% 2.74K_0603_1% 2 2 2 2
    +VDDC_VDD
    PR5903 OVP=VID+300mV

    1000P_0402_50V7K
    20_0402_1% 330P_0402_50V7K Load Line=0.7mohm

    1 2
    EMC_NS@
    3
    2
    1

    3
    2
    1
    PR5903 close to APU side
    @
    Ripple:+/-20mv

    1
    PR5958

    PC5919
    2.74K_0603_1% MAX AC: VID_VDDC +95mv
    MIN AC: VID_VDDC -80mv

    2
    +3VS PC5920

    2
    VDDCR_ISEN2P
    1 2

    1
    PR5971 0.1U_0402_25V7-K

    VDDCR_ISEN1P 10K_0402_1% VDDCR_ISEN1N PR5913


    1 2
    APU_VREF

    2
    @

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    PR5916 1 2 0_0402_5% 1_0402_1%
    VDDCR_ISEN1N VR_APU_PWRGD 39
    PR5959

    1
    PC5921

    PC5923

    PC5925

    PC5973

    PC5974

    PC5975

    PC5977

    PC5978

    PC5979

    PC5980

    PC5963

    PC5959
    VDDCR_ISEN2P
    V20B+ VDDCR_ISEN1P
    1 2

    2
    5.49K_0402_1%

    VDDCR_COMP
    VDDCR_VSEN
    +3VS
    261K_0402_1%

    261K_0402_1%
    26.7K_0402_1%

    APU_PGOOD
    PC5927
    2

    VR-HOT indicator,close to VDDCR_VDD chock

    APU_RGND
    VDDCR_FB
    VDDCR_BOOT2
    1 2

    EMC_NS@

    EMC_NS@
    PR5919

    PR5921

    PR5920

    100K_0402_1%_NCP15WF104F03RC

    2200P_0402_25V7-K
    VDDCR_UGATE2
    1 2 0.1U_0402_25V6

    10U_0805_25V6-K

    10U_0805_25V6-K
    0.1U_0402_25V6
    1

    PH5901 PR5995
    PU5901

    1
    4.7K_0402_1%

    PC5990

    PC5932

    PC5930

    PC5931
    10
    VDDCR_TSEN

    1
    6
    RT3662ACGQW_WQFN40_5X5

    5
    1 2 @

    Vinafix.com
    ISEN1P

    ISEN2P

    FB

    COMP
    ISEN1N

    VSEN

    RGND

    PGOOD

    AON6380_DFN8-5
    BOOT2

    UGATE2
    2

    2
    PR5929 VDDCR_PHASE2
    C 60.4K_0402_1% 40 C
    PHASE2
    @

    PQ5904
    APU_SET1 APU_VR_HOT_L VDDCR_LGATE2 VDDCR_UGATE1
    PR5956 1 2 0_0402_5% 11 39 4
    39,48 VR_HOT# VRHOT_L LGATE2
    VDDCR_TSEN VDDCR_BOOT1
    12 38
    60.4K_0402_1% TSEN BOOT1
    PR5934 SOC_TSEN
    APU_SET1
    13 37
    VDDCR_UGATE1 +VDDC_VDD
    SET1 UGATE1

    3
    2
    1
    1 2 0.47U_0402_25V6K 3.9_0402_1% PL5902
    VDDCR_IMON VDDCR_PHASE1
    14 36 0.24UH_PCME063T-R24MS1R145_35A_20%
    PH5902
    fixed 0.8V output reference output voltage PC5954 PR5943
    APU_VREF
    IMON PHASE1
    VDDCR_LGATE1
    +5VALW VDDCR_PHASE1 VDDCR_PHASE1
    1 2
    2 1 1 2 15 35
    VREF_PINSET LGATE1

    1
    1 2

    EMC_NS@
    @

    4.7_0805_5%

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    SOC_IMON APU_PVCC PC5994
    2

    5
    16 34 PR5925 1 2 0_0603_5%
    delete PWROK pull high EEside pull high
    PR5974
    620_0402_1%

    24K_0402_1%
    24.3K_0402_1%

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M
    IMON_NB PVCC VDDCR_BOOT1 VDDCR_BOOT1_R

    PR5924
    100K_0402_1%_NCP15WF104F03RC @ 1 2 1 2
    PR5936

    APU_POK_R APU_VCC

    AON6324_DFN8-5

    AON6324_DFN8-5

    1
    PR5926 1 2 18 17 1 2 @ @
    VR-HOT indicator,close to VDDCR_SOC chock
    0_0402_5%
    PR5935

    PR5937

    PC515

    PC516

    PC517

    PC518
    6 APU_PWROK PWROK VCC

    1
    PR5927 2.2_0603_5% 0.22U_0603_25V7K

    PC5962

    PC5976

    PC5958

    PC5960

    PC5961

    PC5922

    PC5924

    PC5926

    PC6094

    PC6091

    PC6092

    PC6093
    SOC_LGATE

    2
    19 33 2.2_0603_5% PJ5905 PJ5906

    PQ5905

    PQ5906
    6 APU_SVC SVC LGATE_NB VDDCR_LGATE1

    VDDCR_SN1
    1

    2
    4 4 JUMPER JUMPER

    2.2U_0402_6.3V6-K

    2.2U_0402_6.3V6-K
    SOC_PHASE

    1 1

    2
    20 32 1 1
    6 APU_SVD SVD PHASE_NB
    Kelvin routing

    PC5934

    PC5935

    1000P_0402_50V7K
    SOC_UGATE
    21 31

    EMC_NS@
    PR5932
    6 APU_SVT SVT UGATE_NB 2.74K_0603_1%

    ISENN_NB

    ISENP_NB

    COMP_NB

    BOOT_NB
    TSEN_NB
    2 2

    3
    2
    1

    3
    2
    1

    PC5936
    FB_NB
    VDDIO
    APU_VREF

    GND

    2
    VIN

    EN

    2
    41

    22

    23

    24

    25

    26

    27

    28

    29

    30

    1
    10.5K_0402_1%
    PR5942 PR5960
    1 2 2.74K_0603_1%

    1.5K_0402_1%
    PC5918

    2
    APU_VDDIO

    SOC_COMP

    SOC_BOOT

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    SOC_TSEN
    PR5947 PH5903 PR5948 VDDCR_ISEN1P
    1 2

    SOCI_FB

    APUPWR_EN_R
    VDDCR_IMON
    1 2 1 2 1 2 2.2_0603_5%

    1
    PR5938

    PC519

    PC520

    PC521

    PC522

    PC523

    PC514

    PC6085

    PC6086

    PC6087

    PC6088

    PC6089

    PC6090
    2 1 0.1U_0402_25V7-K
    15.8K_0402_1% 100K_0402_1%_NCP15WF104F03RC +1.8VS PR5933
    VDDCR_ISEN1N

    2
    19.6K_0402_1% PC5937 1 2
    PR5951 2 1 PC5938
    1 2 1 2
    21.5K_0402_1% 1U_0402_6.3V6K 1_0402_1% @ @ @ @ @ @ @ @ @ @ @ @
    PR5961
    PR5952 PH5904 PR5953 SOC_ISEN1N
    0.1U_0402_25V6
    PR5975 1
    @ 2 0_0402_5%
    VDDCR_ISEN2P
    1 2
    SOC_IMON EC_VR_ON 39
    1 2 1 2 1 2
    SOC_ISEN1P PC6071
    6.98K_0402_1% 100K_0402_1%_NCP15WF104F03RC 1 2 5.49K_0402_1%

    APU_VIN
    0.1U_0402_25V6
    B B

    4.7_0603_5%
    PR5939
    1 2
    +1.8VS V20B+
    PR5941 close to APU side PC5945
    PC5940 VDDCR_SOC
    +VDDCR_SOC 1 2 1 2 1 2 1 2 FSW=300KHz
    PR5941
    PC5944 56P_0402_50V8-J 0.1U_0402_25V6 Slew rate :12.5mv/us
    APU_SVC 100_0402_1%
    220P_0402_50V7K 1A TDC=10A EDC=13A
    V20B+
    2

    2200P_0402_25V7-K
    PR5945
    PR5981 PR5986 PR5985 2 1
    SOC_FB_R
    1 2 1 2 OCP=20A

    10U_0805_25V6-K

    10U_0805_25V6-K

    0.1U_0402_25V6
    APU_SVD 6 VDDCR_SOC_VCC_SENSE
    10K_0402_1% 10K_0402_1% 10K_0402_1% PR5944 OVP=VID+300mA

    1
    EMC@

    EMC@
    PR5946

    PC5941

    PC5942

    PC5943

    PC5992
    10_0402_1% 10K_0402_1% Ripple:+/-20mv

    5
    35.7K_0402_1%
    APU_SVT
    Kelvin routing
    1

    1
    APU_SVC MAX AC: VID_VDDCR_SOC +70mv

    AON6380_DFN8-5
    @ @ @

    2
    PR5992
    100_0402_5% MIN AC: VID_VDDCR_SOC -40mv
    0.1U_0402_25V7-J

    0.1U_0402_25V7-J

    0.1U_0402_25V7-J

    APU_SVD
    reserved

    PQ5907
    SOC_UGATE
    1

    4
    PC6079

    PC6080

    PC6081

    APU_SVT

    2
    PC5947
    330P_0402_50V7K @ follow richtek suggestion +VDDCR_SOC
    2

    1
    2

    @
    1
    PR5982 PR5983 PR5984 @ @ @

    3
    2
    1
    PC6077 PL5903
    10K_0402_1% 10K_0402_1% 10K_0402_1%
    680P_0402_50V7K 0.24UH_PCME063T-R24MS1R145_35A_20% 10A
    SOC_PHASE SOC_PHASE
    2
    1 2
    @
    1

    @ @ @ PC5946
    @ @

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    SOC_BOOT SOC_BOOT_R

    2
    1 2 1 2

    EMC_NS@
    4.7_0805_5%
    1 1

    330U_D2_2V_Y

    330U_D2_2V_Y
    5
    PJ5907 PJ5908

    PR5950

    PC5964
    PR5949

    1
    + +

    PC6070

    PC5951

    PC5953

    PC5966

    PC5968

    PC5971

    PC5972

    PC524
    2.2_0603_5% JUMPER JUMPER

    AON6324_DFN8-5
    0.22U_0603_25V7K

    11

    1
    PR5957 Kelvin routing

    2
    2 2

    2
    2.74K_0603_1%

    PQ5908
    SOC_LGATE
    4

    SOC_SN1

    1 2
    EMC_NS@
    680P_0402_50V7K
    PR5955

    3
    2
    1

    1
    2.74K_0603_1%

    PC5955
    PC5939

    2
    1 2
    +VDDCR_SOC
    0.1U_0402_25V7-K
    A A
    PR5940
    SOC_ISEN1P
    2 1

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    10U_0402_6.3V6M

    10U_0402_6.3V6M
    5.49K_0402_1%

    1
    PC6095

    PC6096

    PC525

    PC526

    PC527

    PC528

    PC529

    PC530
    SOC_ISEN1N
    PR5977 1
    @ 2 0_0402_5%

    2
    @ @ @ @ @ @

    Security Classification LC Future Center Secret Data Title

    Issued Date 2017/03/14 Deciphered Date 2017/03/01 PWR-VDDCR/SOC


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    Size
    Custom
    Document Number
    330G-ARR Rev
    1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Date: Friday, March 23, 2018 Sheet 53 of 53
    5 4 3 2 1

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