Dell Inspiron 5379 5579 7773 16888-1 Starlord ROR-L A00

5 4 3 2 1
D D
Starlord KBL_Refresh Schematics

KabyLake-R
C 2017-05-25 C
REV : A00
B B
A DY : None Installed <Core Design> A
UMA: UMA only installed Wistron Corporation

2 1F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
OPS: DISCRTE OPTIMUS installed TTitle

itle
Taipei Hsien 221, Taiwan, R.O.C.
Cover Page
Size Document Number Rev
A3
Starlord KBL-R A 00
Date: Monday, August 28, 2017 Sheet 1 of 106
5 4 3 2 1
5 4 3 2 1
Project code: 4PD0CF010001(SL13_R) C HARGER

ISL88739 44
4PD0CG010001(SL15_R) SENSOR IO MB
PCB P/N: 16888

4PD0CH010001(SL17_B) Star lord KBL Block Diagram ROR 17A18-SA 17A17-SA 17810-1
INPUTS
AD+
OUTPUTS
DCBATOUT
BT+
BBY 17A18-SA 17A16-SA 16888-1
Revision: A00 S YSTEM DC/DC
SY8288CRAC-GP 45
INPUTS OUTPUTS
DDR4
PWR_5V
D
GPU Channel A
S ODIMM A
5V_S5
DCBATOUT 5V_AUX_S5
D
VRAM(GDDR5) *4 NVDIA Intel CPU

N17S-G1 PCIE x 4 12
2GB/4GB
GDDR5 18W KBL/KBL-R C PU Core Power
PCIE Lane1~Lane4 NCP81208MNTXG-GP 46~50
3 3
U22 / U42 DDR4
NCP81382MNTXG-1-GP
GPU BOARD Channel B NCP81382MNTXG-1-GP
S ODIMM B NCP81253MNTBG-GP
13
HDMI V1.4 57
HDMI H DMI Level Shifter HDMI INPUTS OUTPUTS
57
DCBATOUT VCC_CORE
10 USB 2.0/1.1 ports DCBATOUT +VCCGT
13.3"/15.6"/17.3" DP MUX and Redriver
eDP 6 USB 3.0 ports DCBATOUT +VCCSA_VR
(HD/FHD) High Definition Audio
TI DP/USB 3.0 USB3.0 type c
Touch panel 55 USB2.0 U SB2.0 LANE7
3 SATA ports
USB3.0 TUSB546-DCI Port1
6 PCIE ports D DR4
USB3.0 LANE4 3 8
LPC I/F SY8288RAC-GP
USB3.0 51
USB3.0 Port2
U SB3.0 LANE1 ACPI 5.0 CCG4 APL5338XAI-TRG-GP
I2C
USB PowerShare
CYPRESS (To KBC) INPUTS OUTPUTS
USB2.0 CYPD4125
Power share TI USB2.0 LANE1 37
1D2V_S3
C 34 TPS2544RTER BBY only DCBATOUT C
USB2.0/I2C MUX 0D675V_S0

USB2.0/I2C
USB2.0 TI
USB3.0 USB2.0 LANE4 38
C PU DCDC-V1D00A
TS3DS10224 3
USB3.0 Port3 USB3.0 LANE3
8 AOZ1268QI-02-GP 52
USB2.0 INPUTS OUTPUTS
ROR only 35 USB2.0 LANE2 SATA/PCIex2/PCIEx4(Optane) M.2 SSD 63 DCBATOUT 1D0V_S5
7mm HDD SATA L DO-V1D5V

CardReader S-1339D15-M5001-GP 54
SD 3.0 SD Card Slot INPUTS OUTPUTS
USB2.0 x 1
USB2.0 LANE8 Realtak 3D3V_S5 1D5V_S0
RTS5176E
Free fall LDO-V1D8V
INT2 Gsensor APL5930KAI-TRG-GP 54
ST
70 PCIE LANE5
PCIe INPUTS OUTPUTS
LNG2DMTR
NGFF WLAN 3D3V_S5 1D8V_S5
USB2.0 5V/3V S0
USB2.0 LANE6
E-compass G5016KD1U 40
ST I2C INPUTS OUTPUTS
LIS3MDLTR
B
IO Board 5V_S5
3D3V_S5
5V_S0
3D3V_S0 B
USB2.0
Gyro USB2.0 LANE3 USB2.0 Port4 VCCSTG
ST M5938ARD1U-GP-U 40
LSM6DS3USTR
INPUTS OUTPUTS
Sensor BD +VCCSTG
1D0V_S5
on Panel side Camera (HD/IR)
USB2.0 x 1 VCCST
USB2.0 LANE5
D-MIC TPS22965DSGR-GP-U 40
eSPI debug port eSPI 55 INPUTS OUTPUTS
68
1D0V_S5 +V1.00U_CPU
HDA
HDA 2CH SPEAKER SYSTEM DC/DC
I2C
(To CCG4 CODEC (2CH 2W/4ohm) TPS51225RUKR-GP 45
Thermal KBC & USB2.0/I2C MUX) INPUTS OUTPUTS

NUVOTON SMBUS SMSC Realtek 3D3V_AUX_S5
NCT7718W SPI SPI 3D3V_S5
26
MEC1416 ALC3253
24 27 DCBATOUT PWR_3D3V
Fan Control TPM Flash ROM MIC_IN/GND

PS2 NUVOTON 16MB
PWM 26 NPCT650JB2YX Quad Read 25
A HP_R/L A
U niversal Jack
Int. Touch PAD I2C
FAN Image sensor
<Core Design>
KB
Wistron Corporation
2 1F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
T itle
Block Diagram
WWW.AliSaler.Com
C Starlord KBL-R A00
Date: Monday, August 28, 2017 Sheet 2 o f 106
5 4 3 2 1
5 4 3 2 1
SSID = CPU
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
TTitle
itle
(Reserved)
A3
S tarlord KBL-R A00
5 4 3 2 1
5 4 3 2 1
SSID = CPU #544669 CRB Rev0.52

+ VCCST_CPU
1
R 419
1KR2J-1-GP
+ VCCSTG
+VCCSTG = 1.0 V +VCCSTG = 1.0 V
2
P CH_THERMTRIP#
+ VCCSTG
1
E D401
D D
AZ5725-01FDR7G-GP
1
R 401 X DP_TMS 1 2
Rb
DY X DP_TDI
DY
[PECI] and [PROCHOT#] 1KR2J-1-GP EMI DVT1 0210
51R2J-2-GP1 DY 2 R 421
Impedance control: 50 ohm T P401 C PU1D 4 OF 20 R 422
51R2J-2-GP
X DP_TDO_CPU 1 2
TPAD14-OP-GP DY
2
Vince,20170106 1 H _CATERR# D63 SKYLAKE_ULT
51R2J-2-GP R 423
CATERR# PH in P.99
A54
[24] H _PECI_CPU H _PROCHOT#_R PECI
499R2F-2-GP 1 R 403 2 C65 JTAG
[24,44,46] H _PROCHOT# P CH_THERMTRIP# C63
PROCHOT# P CH_JTAG_TDI 1 2
Ra 1S KTOCC# THERMTRIP# X DP_TCLK
T P402 A65 B61 51R2J-2-GP R 408
TPAD14-OP-GP SKTOCC# PROC_TCK X DP_TDI P CH_JTAG_TDO 1 2
CPU MISC D60
1X DP_BPM0 PROC_TDI X DP_TDO_CPU R 409
T P405 C55 A61 51R2J-2-GP
TPAD14-OP-GP 1X DP_BPM1 BPM#[0] PROC_TDO X DP_TMS P CH_JTAG_TMS 1 2
T P406 D55 C60
TPAD14-OP-GP 1X DP_BPM2 BPM#[1] PROC_TMS X DP_TRST# R 416
T P407 B54 B59 51R2J-2-GP
TPAD14-OP-GP 1X DP_BPM3 BPM#[2] PROC_TRST# X DP_TCK_JTAGX 1 2
TPAD14-OP-GP
T P408 C56
BPM#[3] DY R 417
1KR2J-1-GP
Vince,20161107 1 C AM_EN# A6 B56 P CH_JTAG_TCK
T P403 GPP_E3/CPU_GP0 PCH_JTAG_TCK
TPAD14-OP-GP 1 T OUCH_PANEL_INTR#
A7 D59 P CH_JTAG_TDI
T P409 GPP_E7/CPU_GP1 PCH_JTAG_TDI R 402
TPAD14-OP-GP T OUCH_PAD_INTR# P CH_JTAG_TDO X DP_TRST# 1 2
1 T
BA5
GPP_B3/CPU_GP2 PCH_JTAG_TDO
A56
P CH_JTAG_TMS X DP_TCLK R 406 1
DY 2
51R2J-2-GP
T P404 OUCH_PANEL_PD#AY5 C59 51R2J-2-GP
3 D3V_S5_PCH TPAD14-OP-GP GPP_B4/CPU_GP3 PCH_JTAG_TMS X DP_TRST# P CH_JTAG_TCK R 407 1 2
R 404 2 1 C PU_POPIRCOMP PCH_TRST#
C61
X DP_TCK_JTAGX
DY 51R2J-2-GP
AT16 A59
1 2 2 R 1 P PROC_POPIRCOMP JTAGX
DY 49D9R2F-GP 412 CH_POPIRCOMP AU16
1 E DRAM_OPIO_RCOMP H66 PCH_OPIRCOMP
Vince,20161031 49D9R2F-GP 2 R 413 OPCE_RCOMP
100KR2J-1-GP 49D9R2F-GP 2 R 414 1 E OPIO_RCOMP H65
R 415 OPC_RCOMP
49D9R2F-GP
SKYLAKE-U-GP
C C
1 R 410 2
Vince,20161031 0R0402-PAD
,65] TP_W AKE_KBC#
Add resistor by NON DS3 function
(#543016) PROCHOT# Routing Guidelines
B B
M1,2,3,4,5: <3 inches

M6: 1-11 inches
MCPU: 0.3-1.5 inches
Mt <0.3 mils
Main route(M1+M2+M3+M4+M5+M6+MCPU): 1-12 inches
A <Core Design> A
Wistron Corporation
TTitle
itle
CPU_(JTAG/CPU SIDE BAND)
A3
S tarlord KBL-R A00
WWW.AliSaler.Com 5 4 3 2
Date: Friday, December 08, 2017 Sheet
1
4 of 106
5 4 3 2 1
SSID = CPU
DDR4 ball type: Interleaved Type
D D
PU1C
C 3 OF 20
PU1B
C 2 OF 20
SKYLAKE_ULT M _A_DQ32 AY39 SKYLAKE_ULT AN45

M _A_DQ0 AL71 AU53 [12] M _A_DQ32 M _A_DQ33 AW39 D DR0_DQ[32]/DDR1_DQ[0] D DR1_CKN[0] AN46 M _B_CLK#0 [13]
[12] M _A_DQ0 M _A_DQ1 AL68 D DR0_DQ[0] D DR0_CKN[0] AT53 M _A_CLK#0 [12] [12] M _A_DQ33 M _A_DQ34 AY37 D DR0_DQ[33]/DDR1_DQ[1] D DR1_CKN[1] AP45 M _B_CLK#1 [13]
[12] M _A_DQ1 M _A_DQ2 AN68 D DR0_DQ[1] D DR0_CKP[0] AU55 M _A_CLK0 [12] [12] M _A_DQ34 M _A_DQ35 AW37 D DR0_DQ[34]/DDR1_DQ[2] D DR1_CKP[0] AP46 M _B_CLK0 [13]
[12] M _A_DQ2 M _A_DQ3 AN69 D DR0_DQ[2] D DR0_CKN[1] AT55 M _A_CLK#1 [12] [12] M _A_DQ35 M _A_DQ36 BB39 D DR0_DQ[35]/DDR1_DQ[3] D DR1_CKP[1] M _B_CLK1 [13]
[12] M _A_DQ3 M _A_DQ4 AL70 D DR0_DQ[3] D DR0_CKP[1] M _A_CLK1 [12] M_A_DQ[32:39] [12] M _A_DQ36 M _A_DQ37 BA39 D DR0_DQ[36]/DDR1_DQ[4] AN56
M_A_DQ[0:7] [12] M _A_DQ4 M _A_DQ5 AL69 D DR0_DQ[4] BA56 [12] M _A_DQ37 M _A_DQ38 BA37 D DR0_DQ[37]/DDR1_DQ[5] D DR1_CKE[0] AP55 M _B_CKE0 [13]
[12] M _A_DQ5 M _A_DQ6 AN70 D DR0_DQ[5] D DR0_CKE[0] BB56 M _A_CKE0 [12] [12] M _A_DQ38 M _A_DQ39 BB37 D DR0_DQ[38]/DDR1_DQ[6] D DR1_CKE[1] AN55 M _B_CKE1 [13]
[12] M _A_DQ6 M _A_DQ7 AN71 D DR0_DQ[6] D DR0_CKE[1] AW56 M _A_CKE1 [12] [12] M _A_DQ39 M _A_DQ40 AY35 D DR0_DQ[39]/DDR1_DQ[7] D DR1_CKE[2] AP53
[12] M _A_DQ7 M _A_DQ8 AR70 D DR0_DQ[7] D DR0_CKE[2] AY56 [12] M _A_DQ40 M _A_DQ41 AW35 D DR0_DQ[40]/DDR1_DQ[8] D DR1_CKE[3]
[12] M _A_DQ8 M _A_DQ9 AR68 D DR0_DQ[8] D DR0_CKE[3] [12] M _A_DQ41 M _A_DQ42 AY33 D DR0_DQ[41]/DDR1_DQ[9] BB42
[12] M _A_DQ9 M _A_DQ10 AU71 D DR0_DQ[9] AU45 [12] M _A_DQ42 M _A_DQ43 AW33 D DR0_DQ[42]/DDR1_DQ[10] D DR1_CS#[0] AY42 M _B_CS#0 [13]
[12] M _A_DQ10 M _A_DQ11 AU68 D DR0_DQ[10] D DR0_CS#[0] AU43 M _A_CS#0 [12] [12] M _A_DQ43 M _A_DQ44 BB35 D DR0_DQ[43]/DDR1_DQ[11] D DR1_CS#[1] BA42 M _B_CS#1 [13]
[12] M _A_DQ11 M _A_DQ12 AR71 D DR0_DQ[11] D DR0_CS#[1] AT45 M _A_CS#1 [12] M_A_DQ[40:47] [12] M _A_DQ44 M _A_DQ45 BA35 D DR0_DQ[44]/DDR1_DQ[12] D DR1_ODT[0] AW42 M _B_DIMB_ODT0 [13]
M_A_DQ[8:15] [12] M _A_DQ12 M _A_DQ13 AR69 D DR0_DQ[12] D DR0_ODT[0] AT43 M _A_DIMA_ODT0 [12] [12] M _A_DQ45 M _A_DQ46 BA33 D DR0_DQ[45]/DDR1_DQ[13] D DR1_ODT[1] M _B_DIMB_ODT1 [13]
[12] M _A_DQ13 M _A_DQ14 AU70 D DR0_DQ[13] D DR0_ODT[1] M _A_DIMA_ODT1 [12] [12] M _A_DQ46 M _A_DQ47 BB33 D DR0_DQ[46]/DDR1_DQ[14] AY48 M _B_A5
[12] M _A_DQ14 D DR0_DQ[14] [12] M _A_DQ47 D DR0_DQ[47]/DDR1_DQ[15] D DR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] M _B_A5 [13]
M _A_DQ15 AU69 BA51 M _A_A5 M _B_DQ32 AU40 AP50 M _B_A9
[12] M _A_DQ15 D DR0_DQ[15] D DR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] M _A_A5 [12] [13] M _B_DQ32 D DR1_DQ[32]/DDR1_DQ[16] D DR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] M _B_A9 [13]
[13] M _B_DQ0 AF65 BB54 M _A_A9 M _B_DQ33 AT40 BA48 M _B_A6
M _B_DQ0 D DR1_DQ[0]/DDR0_DQ[8]D DR0_DQ[16] D DR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] M _A_A9 [12] [13] M _B_DQ33 D DR1_DQ[33]/DDR1_DQ[17] D DR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] M _B_A6 [13]
[13] M _B_DQ1 AF64 BA52 M _A_A6 M _B_DQ34 AT37 BB48 M _B_A8
M _B_DQ1 D DR1_DQ[1]/DDR0_DQ[9] DDR0_DQ[17] D DR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] M _A_A6 [12] [13] M _B_DQ34 D DR1_DQ[34]/DDR1_DQ[18] D DR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] M _B_A8 [13]
[13] M _B_DQ2 AK65 AY52 M _A_A8 M _B_DQ35 AU37 AP48 M _B_A7
M _B_DQ2 D DR1_DQ[2]/DDR0_DQ[10]DDR0_DQ[18] D DR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] M _A_A8 [12] [13] M _B_DQ35 D DR1_DQ[35]/DDR1_DQ[19] D DR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] M _B_A7 [13]
M _B_DQ3 AK64 AW52 M _A_A7 M _B_DQ36 AR40 AP52
[13] M _B_DQ3
M _B_DQ4 AF66 D DR1_DQ[3]/DDR0_DQ[11]DDR0_DQ[19] D DR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AY55
M _A_A7 [12] M_B_DQ[32:39] [13] M _B_DQ36
M _B_DQ37 AP40 D DR1_DQ[36]/DDR1_DQ[20] D DR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] AN50 M _B_A12 M _B_BG0 [13]
M_B_DQ[0:7] [13] M _B_DQ4
M _B_DQ5 AF67 D DR1_DQ[4]/DDR0_DQ[12]DDR0_DQ[20] D DR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] AW54 M _A_A12 M _A_BG0 [12] [13] M _B_DQ37
M _B_DQ38 AP37 D DR1_DQ[37]/DDR1_DQ[21] D DR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AN48 M _B_A11
M _B_A12 [13]
[13] M _B_DQ5 D DR1_DQ[5]/DDR0_DQ[13]DDR0_DQ[21] D DR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] M _A_A12 [12] [13] M _B_DQ38 D DR1_DQ[38]/DDR1_DQ[22] D DR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] M _B_A11 [13]
[13] M _B_DQ6 AK67 BA54 M _A_A11 M _B_DQ39 AR37 AN53 M _B_ACT_N
M_B_DQ6 D DR1_DQ[6]/DDR0_DQ[14]DDR0_DQ[22]D DR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] M _A_A11 [12] [13] M _B_DQ39 D DR1_DQ[39]/DDR1_DQ[23] D DR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# M _B_ACT_N [13]
[13] M _B_DQ7 AK66 BA55 [13] _B_DQ40 M _B_DQ40 AT33 AN52
M_B_DQ7
M _B_DQ8 AF70 D DR1_DQ[7]/DDR0_DQ[15]DDR0_DQ[23] D DR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# AY54 M _A_ACT_N [12] M
M _B_DQ41 AU33 D DR1_DQ[40]/DDR1_DQ[24] D DR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] M _B_BG1 [13]
[13] M_B_DQ8 D DR1_DQ[8]/DDR0_DQ[24] D DR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] M _A_BG1 [12] [13] M _B_DQ41 D DR1_DQ[41]/DDR1_DQ[25]
[13] M _B_DQ9 AF68 [13] _B_DQ42 M _B_DQ42 AU30 BA43 M _B_A13
M_B_DQ9 D DR1_DQ[9]/DDR0_DQ[25] M D DR1_DQ[42]/DDR1_DQ[26] D DR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] M _B_A13 [13]
[13] M _B_DQ10 AH71 AU46 M _A_A13 M _B_DQ43 AT30 AY43 M _B_A15
M_B_DQ10 D DR1_DQ[10]/DDR0_DQ[26] D DR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] M _A_A13 [12] [13] M _B_DQ43 D DR1_DQ[43]/DDR1_DQ[27] D DR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] M _B_A15 [13]
M _B_DQ11 AH68 AU48 M _A_A15 M _B_DQ44 AR33 AY44 M _B_A14
[13] M_B_DQ11
M _B_DQ12 AF71 D DR1_DQ[11]/DDR0_DQ[27] D DR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] AT46 M _A_A14
M _A_A15 [12] M_B_DQ[40:47] [13] M _B_DQ44
M _B_DQ45 AP33 D DR1_DQ[44]/DDR1_DQ[28] D DR1_WE#/DDR1_CAB[2]/DDR1_MA[14] AW44 M _B_A16 M _B_A14 [13]
M_B_DQ[8:15] [13] M_B_DQ12
M _B_DQ13 AF69 D DR1_DQ[12]/DDR0_DQ[28] D DR0_WE#/DDR0_CAB[2]/DDR0_MA[14] AU50 M _A_A16
M _A_A14 [12] [13] M _B_DQ45
M _B_DQ46 AR30 D DR1_DQ[45]/DDR1_DQ[29] D DR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] BB44
M _B_A16 [13]
[13] M_B_DQ13 D DR1_DQ[13]/DDR0_DQ[29] D DR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] M _A_A16 [12] [13] M _B_DQ46 D DR1_DQ[46]/DDR1_DQ[30] D DR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] M _B_BA0 [13]
[13] M _B_DQ14 AH70 AU52 [13] _B_DQ47 M _B_DQ47 AP30 AY47 M _B_A2
M_B_DQ14 D DR1_DQ[14]/DDR0_DQ[30] D DR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] M _A_BA0 [12] M D DR1_DQ[47]/DDR1_DQ[31] D DR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] M _B_A2 [13]
[13] M _B_DQ15 AH69 AY51 M _A_A2 M _A_DQ48 AY31 BA44
M_B_DQ15 D DR1_DQ[15]/DDR0_DQ[31] D DR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] M _A_A2 [12] [12] M _A_DQ48 D DR0_DQ[48]/DDR1_DQ[32] D DR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] M _B_BA1 [13]
M _A_DQ16 BB65 AT48 M _A_DQ49 AW31 AW46 M _B_A10
[12] M_A_DQ16 D DR0_DQ[16]/DDR0_DQ[32] D DR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] M _A_BA1 [12] [12] M _A_DQ49 D DR0_DQ[49]/DDR1_DQ[33] D DR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] M _B_A10 [13]
M _A_DQ17 AW65 AT50 M _A_A10 M _A_DQ50 AY29 AY46 M _B_A1
[12] M_A_DQ17 D DR0_DQ[17]/DDR0_DQ[33] D DR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] M _A_A10 [12] [12] M _A_DQ50 D DR0_DQ[50]/DDR1_DQ[34] D DR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] M _B_A1 [13]
M _A_DQ18 AW63 BB50 M _A_A1 M _A_DQ51 AW29 BA46 M _B_A0
C
[12] M_A_DQ18 M _A_DQ19 AY63 D DR0_DQ[18]/DDR0_DQ[34] D DR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] AY50 M _A_A0 M _A_A1 [12] M_A_DQ[48:55] [12] M _A_DQ51 M _A_DQ52 BB31 D DR0_DQ[51]/DDR1_DQ[35] D DR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] BB46 M _B_A3 M _B_A0 [13] C
M_A_DQ[16:23] [12] M_A_DQ19 M _A_DQ20 BA65 D DR0_DQ[19]/DDR0_DQ[35] D DR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] BA50 M _A_A3 M _A_A0 [12] [12] M _A_DQ52 M _A_DQ53 BA31 D DR0_DQ[52]/DDR1_DQ[36] D DR1_MA[3] BA47 M _B_A4 M _B_A3 [13]
[12] M_A_DQ20 D DR0_DQ[20]/DDR0_DQ[36] D DR0_MA[3] M _A_A3 [12] [12] M _A_DQ53 D DR0_DQ[53]/DDR1_DQ[37] D DR1_MA[4] M _B_A4 [13]
M _A_DQ21 AY65 BB52 M _A_A4 M _A_DQ54 BA29
[12] M_A_DQ21 D DR0_DQ[21]/DDR0_DQ[37] D DR0_MA[4] M _A_A4 [12] [12] M _A_DQ54 D DR0_DQ[54]/DDR1_DQ[38]
M _A_DQ22 BA63 M _A_DQ55 BB29 BA38 M _A_DQS_DN4
[12] M_A_DQ22 M _A_DQ23 D DR0_DQ[22]/DDR0_DQ[38] _A_DQS_DN0 [12] M _A_DQ55 _A_DQ56 D DR0_DQ[55]/DDR1_DQ[39] D DR0_DQSN[4]/DDR1_DQSN[0] _A_DQS_DP4
[12] M_A_DQ23
BB63
D DR0_DQ[23]/DDR0_DQ[39] D DR0_DQSN[0]
AM70 M
[12] M _A_DQ56
M AY27
D DR0_DQ[56]/DDR1_DQ[40] D DR0_DQSP[4]/DDR1_DQSP[0]
AY38 M M_A_DQS4
M _A_DQ24 BA61 AM69 M _A_DQS_DP0 M_A_DQS0 M _A_DQ57 AW27 AY34 M _A_DQS_DN5
[12] M_A_DQ24 M _A_DQ25 D DR0_DQ[24]/DDR0_DQ[40] D DR0_DQSP[0] _A_DQS_DN1 [12] M _A_DQ57 _A_DQ58 D DR0_DQ[57]/DDR1_DQ[41] D DR0_DQSN[5]/DDR1_DQSN[1] _A_DQS_DP5
[12] M_A_DQ25
AW61
D DR0_DQ[25]/DDR0_DQ[41] D DR0_DQSN[1]
AT69 M
[12] M _A_DQ58
M AY25
BA34 M M_A_DQS5
M _A_DQ26 BB59 AT70 M _A_DQS_DP1 M_A_DQS1 M _A_DQ59 AW25 AT38 M _B_DQS_DN4
[12] M_A_DQ26 M _A_DQ27 D DR0_DQ[26]/DDR0_DQ[42] D DR0_DQSP[1] _B_DQS_DN0 M_A_DQ[56:63] [12] M _A_DQ59 _A_DQ60 D DR0_DQ[59]/DDR1_DQ[43] D DR1_DQSN[4]/DDR1_DQSN[2] _B_DQS_DP4
M_A_DQ[24:31] [12] M_A_DQ27
AW59
D DR0_DQ[27]/DDR0_DQ[43] D DR1_DQSN[0]/DDR0_DQ[2]
AH66 M
[12] M _A_DQ60
M BB27
AR38 M M_B_DQS4
M _A_DQ28 BB61 AH65 M _B_DQS_DP0 M _A_DQ61 BA27 AT32 M _B_DQS_DN5
[12] M_A_DQ28 M _A_DQ29 D DR0_DQ[28]/DDR0_DQ[44] D DR1_DQSP[0]/DDR0_DQ[2] _B_DQS_DN1 M_B_DQS0 [12] M _A_DQ61 _A_DQ62 D DR0_DQ[61]/DDR1_DQ[45] D DR1_DQSN[5]/DDR1_DQSN[3] _B_DQS_DP5
[12] M_A_DQ29
AY61
D DR0_DQ[29]/DDR0_DQ[45] D DR1_DQSN[1]/DDR0_DQ[3]
AG69 M
[12] M _A_DQ62
M BA25
AR32 M M_B_DQS5
M _A_DQ30 BA59 AG70 M _B_DQS_DP1 M _A_DQ63 BB25 BA30 M _A_DQS_DN6
[12] M_A_DQ30 M _A_DQ31 D DR0_DQ[30]/DDR0_DQ[46] D DR1_DQSP[1]/DDR0_DQ[3] _A_DQS_DN2 M_B_DQS1 [12] M _A_DQ63 _B_DQ48 D DR0_DQ[63]/DDR1_DQ[47] D DR0_DQSN[6]/DDR1_DQSN[4] _A_DQS_DP6
[12] M_A_DQ31
AY59
D DR0_DQ[31]/DDR0_DQ[47] D DR0_DQSN[2]/DDR0_DQSN[4]
BA64 M [13] M _B_DQ48 M AU27
D DR1_DQ[48] D DR0_DQSP[6]/DDR1_DQSP[4]
AY30 M M_A_DQS6
[13] M _B_DQ16 AT66 AY64 M _A_DQS_DP2 M_A_DQS2 [13] _B_DQ49 M _B_DQ49 AT27 AY26 M _A_DQS_DN7 1 D2V_S3
M_B_DQ16 D DR1_DQ[16]/DDR0_DQ[48] D DR0_DQSP[2]/DDR0_DQSP[4] M D DR1_DQ[49] D DR0_DQSN[7]/DDR1_DQSN[5]
[13] M _B_DQ17 AU66 AY60 M _A_DQS_DN3
[13] _B_DQ50 M _B_DQ50 AT25 BA26 M _A_DQS_DP7 M_A_DQS7
M_B_DQ17 D DR1_DQ[17]/DDR0_DQ[49] D DR0_DQSN[3]/DDR0_DQSN[5] M D DR1_DQ[50] D DR0_DQSP[7]/DDR1_DQSP[5]
M _B_DQ18 AP65 BA60 M _A_DQS_DP3 M_A_DQS3 M _B_DQ51 AU25 AR25 M _B_DQS_DN6
[13] M_B_DQ18
M _B_DQ19 D DR1_DQ[18]/DDR0_DQ[50] D DR0_DQSP[3]/DDR0_DQSP[5] _B_DQS_DN2 M_B_DQ[48:55] [13] M _B_DQ51
_B_DQ52 D DR1_DQ[51] D DR1_DQSN[6] _B_DQS_DP6 M_B_DQS6
1
AN65 AR66 M M AP27 AR27 M
M_B_DQ[16:23] [13] M_B_DQ19
M _B_DQ20 AN66 D DR1_DQ[19]/DDR0_DQ[51] D DR1_DQSN[2]/DDR0_DQSN[6] AR65 M _B_DQS_DP2
[13] M _B_DQ52
M _B_DQ53 D DR1_DQ[52] D DR1_DQSP[6] M _B_DQS_DN7
[13] M_B_DQ20 D DR1_DQ[20]/DDR0_DQ[52] D DR1_DQSP[2]/DDR0_DQSP[6]
M_B_DQS2 [13] M _B_DQ53 AN27
D DR1_DQ[53] D DR1_DQSN[7]
AR22 R 505
[13] M _B_DQ21 AP66 AR61 M _B_DQS_DN3
[13] _B_DQ54 M _B_DQ54 AN25 AR21 M _B_DQS_DP7 M_B_DQS7 470R2F-GP
M_B_DQ21 D DR1_DQ[21]/DDR0_DQ[53] D DR1_DQSN[3]/DDR0_DQSN[7] M D DR1_DQ[54] D DR1_DQSP[7]
[13] M _B_DQ22 AT65 AR60 M _B_DQS_DP3 M_B_DQS3 [13] _B_DQ55 M _B_DQ55 AP25
M_B_DQ22 D DR1_DQ[22]/DDR0_DQ[54] D DR1_DQSP[3]/DDR0_DQSP[7] M D DR1_DQ[55]
[13] M _B_DQ23 AU65 [13] _B_DQ56 M _B_DQ56 AT22 AN43
M_B_DQ23 D DR1_DQ[23]/DDR0_DQ[55] M D DR1_DQ[56] D DR1_ALERT# M _B_ALERT_N [13]
2
[13] M _B_DQ24 AT61 AW50 [13] _B_DQ57 M _B_DQ57 AU22 AP43
M_B_DQ24 D DR1_DQ[24]/DDR0_DQ[56] D DR0_ALERT# M _A_ALERT_N [12] M D DR1_DQ[57] D DR1_PAR M _B_PARITY [13]
M _B_DQ25 AU61 AT52 M _B_DQ58 AU21 AT13 S M_DRAMRST# 1 R 504 2
[13] M_B_DQ25
M _B_DQ26 AP60 D DR1_DQ[25]/DDR0_DQ[57] D DR0_PAR M _A_PARITY [12] M_B_DQ[56:63] [13] M _B_DQ58
M _B_DQ59 AT21 D DR1_DQ[58] D RAM_RESET# AR18 S M_RCOMP_0 1 R 501 2 121R2F-GP
D DR4_DRAMRST# [12,13]
[13] M_B_DQ26 D DR1_DQ[26]/DDR0_DQ[58] [13] M _B_DQ59 D DR1_DQ[59] D DR_RCOMP[0]
M _B_DQ27 AN60 AY67 M _B_DQ60 AN22 AT18 S M_RCOMP_1 1 R 502 2 80D6R2F-L-GP 0R0402-PAD
M_B_DQ[24:31] [13] M_B_DQ27
M _B_DQ28 AN61 D DR1_DQ[27]/DDR0_DQ[59] D DR_VREF_CA AY68 V _SM_VREF_CNTA [12] [13] M _B_DQ60
M _B_DQ61 AP22 D DR1_DQ[60] D DR_RCOMP[1] AU18 S M_RCOMP_2 1 R 503 2 100R2F-L1-GP-U
[13] M_B_DQ28 D DR1_DQ[28]/DDR0_DQ[60] D DR0_VREF_DQ [13] M _B_DQ61 D DR1_DQ[61] D DR_RCOMP[2]
[13] M _B_DQ29 AP61 BA67 [13] _B_DQ62 M _B_DQ62 AP21
M_B_DQ29 D DR1_DQ[29]/DDR0_DQ[61] D DR1_VREF_DQ V _SM_VREF_CNTB [13] M D DR1_DQ[62]
[13] M _B_DQ30 AT60 [13] _B_DQ63 M _B_DQ63 AN21 DDR CH - B
M_B_DQ30 D DR1_DQ[30]/DDR0_DQ[62] M D DR1_DQ[63]
M _B_DQ31 S M_PGCNTL
2
[13] AU60 AW67 #543016
M_B_DQ31 D DR1_DQ[31]/DDR0_DQ[63] DDR CH - A D DR_VTT_CNTL
SKYLAKE-U-GP
SKYLAKE-U-GP
E D501
AZ5725-01FDR7G-GP
1
Layout Note:
Design Guideline:
SM_RCOMP keep routing length less than 500 mils.
DQ Bit Swapping is allowed within the same byte, and Byte Swapping is allowed within the same channel. 3 D3V_S0
Clock (CLK and CLK#) and Strobe (DQS and DQS#) differential signal swapping within a pair is not allowed. Also differential close to CPU
B B
clock pair to clock pair swapping within a channel is not allowed.
1 D2V_S3
1
R 506
220KR2F-GP
Q 501
G
2
PDG: DDR/ODT D
S M_PGCNTL_R [51]
S M_PGCNTL S
PJA138KA-GP
2015/11/18 Modify
M _A_DQS_DN[7:0] [12] M _B_DQS_DN0 M _B_DQS_DN[7:0] [13]

M _A_DQS_DN0 M _B_DQS_DN1
M _A_DQS_DN7
M _B_DQS_DP0 M _B_DQS_DP[7:0] [13]

M _B_DQS_DP1
M _B_DQS_DP2
M _A_DQS_DP0 M _A_DQS_DP[7:0] [12] M _B_DQS_DP3
M _A_DQS_DP1 M _B_DQS_DP4
A M _A_DQS_DP4 M _B_DQS_DP7 A
M _A_DQS_DP5
M _A_DQS_DP6
M _A_DQS_DP7
<Core Design>
W istron Corporation
itle
T Title
C PU_(DDR)
A 2
S tarlord KBL-R A 00
Date: Friday, December 08, 2017 Sheet 5 o f 106
5 4 3 2 1
5 4 3 2 1
Main Func = CPU
PU1S
C 1 9 OF 20
RESERVED SIGNALS-1
D D
TPAD14-OP-GP T P618 1 C FG0 E68 SKYLAKE_ULT BB68 R SVD_TP_BB68 1
TPAD14-OP-GP T P619 FG1 B67 C FG[0] R SVD_TP_BB68 BB69 R SVD_TP_BB69
1 C
FG[1]
1 T P603 TPAD14-OP-GP
TPAD14-OP-GP T P620 1 C FG2 D65 C R SVD_TP_BB69 T P604 TPAD14-OP-GP
TPAD14-OP-GP T P621 FG3 D67 C FG[2] AK13
1 C
TPAD14-OP-GP T P622 FG4 E70 C FG[3] R SVD_TP_AK13 AK12
1 C
TPAD14-OP-GP T P623 FG5 C68 C FG[4] R SVD_TP_AK12
1 C
TPAD14-OP-GP T P624 FG6 D68 C FG[5] BB2
1 C
TPAD14-OP-GP T P625 FG7 C67 C FG[6] R SVD_BB2 BA3
1 C
TPAD14-OP-GP T P626 FG8 F71 C FG[7] R SVD_BA3
1 C
TPAD14-OP-GP T P627 FG9 G69 C FG[8]
1 C
TPAD14-OP-GP T P628 FG10 F70 C FG[9] AU5 T P5_AU5
1 C 1
TPAD14-OP-GP T P629 FG11 G68 C FG[10] T P5 AT5 T P6_AT5
1 C
FG[11]
1 T P607 TPAD14-OP-GP
TPAD14-OP-GP T P630 1 C FG12 H70 C T P6 T P608 TPAD14-OP-GP
TPAD14-OP-GP T P631 FG13 G71 C FG[12]
1 C
TPAD14-OP-GP T P632 FG14 H69 C FG[13] D5
1 C
TPAD14-OP-GP T P633 FG15 G70 C FG[14] R SVD_D5 D4
1 C
C FG[15] R SVD_D4 B2
E63 R SVD_B2 C2
TPAD14-OP-GP T P634 1 C FG16
TPAD14-OP-GP T P635 1 C FG17 F63 C FG[16] R SVD_C2
C FG[17] B3
TPAD14-OP-GP T P636 1 C FG18 E66 R SVD_B3 A3
TPAD14-OP-GP T P637 1 C FG19 F66 C FG[18] R SVD_A3
C FG[19] AW1
49D9R2F-GP 2 1 R 601 C FG_RCOMP E60 R SVD_AW1
C FG_RCOMP E1
TPAD14-OP-GP T P638 1 I TP_PMODE E8 R SVD_E1 E2
I TP_PMODE R SVD_E2
AY2 BA4
AY1 R SVD_AY2 R SVD_BA4 BB4
R SVD_AY1 R SVD_BB4
D1 A4
D3 R SVD_D1 R SVD_A4 C4
R SVD_D3 R SVD_C4
K46 BB5 T P4_BB5 1
K45 R SVD_K46 T P4 T P609 TPAD14-OP-GP
R SVD_K45 A69
AL25 R SVD_A69 B69
AL27 R SVD_AL25 R SVD_B69
R SVD_AL27 AY3
C71 R SVD_AY3
C B70 R SVD_C71 D71 C
R SVD_B70 R SVD_D71 C70
F60 R SVD_C70
R SVD_F60 C54
A52 R SVD_C54 D54
R SVD_A52 R SVD_D54
1 R SVD_TP_BA70 BA70 AY4 T P1_AY4 1
TPAD14-OP-GP T P601 1 R SVD_TP_BA68 BA68 R SVD_TP_BA70 T P1 BB3 T P2_BB3 1 T P610 TPAD14-OP-GP
TPAD14-OP-GP T P602 R SVD_TP_BA68 T P2 T P611 TPAD14-OP-GP
J71 AY71 V SS_AY71 1 R 602 2 #54469 CRB.
J68 R SVD_J71 V SS_AY71 AR56 Z VM# 0R0402-PAD1
R SVD_J68 Z VM# T P616 TPAD14-OP-GP
Vince,20161027
1 R SVD_F65 F65 AW71 R SVD_TP_AW71 1
TPAD14-OP-GP T P612 1 R SVD_G65 G65 V SS_F65 R SVD_TP_AW71 R SVD_AW71 AW70 R SVD_TP_AW70 1 T P614 TPAD14-OP-GP + VCCST_CPU
TPAD14-OP-GP T P613 V SS_G65 RSVD_TP_AW70 R SVD_AW70
T P615 TPAD14-OP-GP
F61 AP56 M SM# 1
E61 R SVD_F61 M SM# C64 T P617 TPAD14-OP-GP
R SVD_E61 P ROC_SELECT#
P ROC_SELECT# 1 DY2
SKYLAKE-U-GP
R 603
100KR2J-1-GP
PCH strap pin: 2016/01/11 modify

C FG3
1
[BDW Only]PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)

R 604
1KR2J-1-GP 0 : ENABLED
DY
CFG[3] SET DFX ENABLED BIT IN DEBUG INTERFACE MSR
2
1 : DISABLED
(#543016)
C FG4
1
DISPLAY PORT PRESENCE STRAP

R 605
1KR2J-1-GP
0 : ENABLED
CFG[4] An external Display Port device is connected to the Embedded Display Port.
B B
2
1 : DISABLED (Default)
No Physical Display Port attached to Embedded DisplayPort*. No connect for disable.
SKL(#543016):
Processor strap CFG[4] should be pulled low to enable embedded DisplayPort*
A A
<Core Design>
Title
C PU_(RESERVED)
WWW.AliSaler.Com
5 4 3 2
Size
A 2
Document Number
S tarlord KBL-R
Date: Friday, December 08, 2017
1
Sheet 6 o f
Rev
A 00
106
5 4 3 2 1
SSID = CPU
For U22 & U42

C 12 OF 20 C 13 OF 20
VCC_CORE CC_CORE
V VCCGT
+
A30 PU1L CPU POWER 1 OF 4 G32 T_CORE
G PU1M CPU POWER 2 OF 4 N70
A34 CC_A30 CC_G32 G33 A48 CCGT N71
A39 VCC_A34 VCC_G33 G35 A53 CCGT CCGT
V R63
A44 VCC_A39 SKYLAKE_ULT VCC_G35 G37 A58 CCGT
V SKYLAKE_ULT
CCGT
V R64 D2V_S3
1
AK33 VCC_A44 VCC_G37 G38 A62 CCGT
V CCGT
V R65
VCCGT
AK35 VCC_AK33 VCC_G38 G40 + A66 CCGT
V CCGT
V R66
AK37 VCC_AK35 VCC_G40 G42 AA63 CCGT
V CCGT
V R67
AK38 VCC_AK37 VCC_G42 J30 AA64 CCGT
V CCGT
V R68
AK40 VCC_AK38 VCC_J30 J33 AA66 CCGT
V CCGT
V R69
AL33 VCC_AK40 VCC_J33 J37 AA67 CCGT
V CCGT
V R70
AL37 VCC_AL33 VCC_J37 J40 AA69 CCGT
V CCGT
V R71
1
AL40 VCC_AL37 VCC_J40 K33 AA70 CCGT
V CCGT
V T62 719
C
VCCIO
+
AM32 VCC_AL40 CC_K33
V K35 AA71 CCGT
V CCGT
V U65 SC1U10V2KX-1GP C 14 OF 20
AM33 VCC_AM32 VCC_K35 K37 AC64 CCGT
V CCGT
V U68
2
+VCCIO(ICCMAX.=2.73A
V CCGT
V U71 AU23 PU1N CPU POWER 3 OF 4 AK28
V CCGT
V W 63 AU28 DDQ_AU23 CCIO AK30
D AM38 VCC_AM37 VCC_K40 K42 AC67 CCGT
V CCGT
V W 64 AU35 DDQ_AU28
V CCIO
V AL30 D
G30 VCC_AM38 VCC_K42 K43 AC68 CCGT
V CCGT
V W 65 AU42 DDQ_AU35
V SKYLAKE_ULT
CCIO
V AL42
VCC_G30 VCC_K43 AC69 CCGT
V CCGT
V W 66 BB23 DDQ_AU42
V CCIO
V AM28
K32 V V E32 AC70 CCGT
V CCGT
V W 67 BB32 DDQ_BB23
V CCIO
V AM30
TPAD14-OP-GP CCG0 CC_SENSE E33 AC71 CCGT
V CCGT
V CCIO
V AM42
TP701 1 +VCCCOREG0 RSVD_K32
AK32 V VSS_SENSE CC_SENSE [46]
V T_CORE
G J43 CCGT
V CCGT
V CCIO
V VCCSA
+
TPAD14-OP-GP CCG1 V B63 SS_SENSE [46]
V J45 CCGT
V CCGT
V V AK23
TP707 1 +VCCCOREG1 RSVD_AK32 IDALERT# CCGT CCGT DDQ_BB51 CCSA
AB62 V A63 _CPU_SVIDALRT#
H J46 V V W 71 VDDQ_CPU_CLK
+ V AK25
P62 CCOPC_AB62 V IDSCK D64 _CPU_SVIDCLK
H J48 CCGT
V CCGT
V Y62 Vince,20170202 V CCSA
V G23
V62 VCCOPC_P62 IDSOUT
V _CPU_SVIDDAT
H VCCSTG
+ J50 CCGT
V CCGT
V SC10U6D3V3MX-GP 2 1 715
C AM40 CCSA
V G25
VCCOPC_V62 V 703
R CCGT
V V DDQC CCSA
V
G20 J52 VCCST_CPU
+ G27
H63 V CCSTG_G20 VCCGT J53 CCGT
V AK42 TX_CORE A18 V CCSA
V G28
+VCCFUSEPRG 1 2 + G
CC_OPC_1P8_H63 V J55 CCGT
V CCGTX_AK42 AK43 SC1U10V2KX-1GP CCST CCSA
V J22
2 1 716
C 0.04 A
G61 V 0R0603-PAD J56 CCGT
V CCGTX_AK43
V AK45 VCCSTG A22 V CCSA
V J23
+
CC_OPC_1P8_G61 J58 CCGT
V CCGTX_AK45
V AK46 CCSTG_A22 CCSA
V J27
AC63 V J60 CCGT
V CCGTX_AK46
V AK48 SC1U10V2KX-1GP AL23 V CCSA
V K23
2 1 717
C
AE63 CCOPC_SENSE T_CORE
G K48 CCGT
V CCGTX_AK48
V AK50 CCPLL_OC CCSA
V K25
VSSOPC_SENSE K50 CCGT
V CCGTX_AK50
V AK52 DY D2V_S3
1 K20 V CCSA
V K27
V 712
R CCGT
V CCGTX_AK52
V CCPLL_K20 CCSA
V
AE62 K52 AK53 K21 K28
Vince,20161012 AG62 CCEOPIO
VCCEOPIO
VCCGT
+
2 DY 1 22_POWER_K52
U K53 CCGT
V
CCGT
V
CCGTX_AK53
V
CCGTX_AK55
V
AK55 Follow Kyloren 13" SCH 2 1 718
C
CCPLL_K21
V
V
CCSA
V
CCSA
V
K30
VCCGT K55 AK56
V + CCGT
V CCGTX_AK56
V SCD1U16V2KX-3DLGP V
AL63 K56 AK58 AM23
CCEOPIO_SENSE 0R2J-2-GP CCGT
V CCGTX_AK58
V VCCSFR CCIO_SENSE
AJ62 K58 AK60 + AM22
VSSEOPIO_SENSE U22 only K60 CCGT
V CCGTX_AK60
V AK70 SSIO_SENSE
V
V L62 CCGT
V CCGTX_AK70
V AL43 TX_CORE
G V H21
L63 CCGT
V CCGTX_AL43
V AL46 SSSA_SENSE H20
CCGT
V CCGTX_AL46
V
0.12 A CCSA_SENSE
V
SSSA_SENSE
V [46]
1
L64 AL50
Vince,20161012 L65 CCGT
V CCGTX_AL50
V AL53 720
C 721
C V CCSA_SENSE
V [46]
SKYLAKE-U-GP
L66 CCGT
V CCGTX_AL53
V AL56 SCD1U16V2KX-3DLGP
S
CCGT
V CCGTX_AL56
V
2
L67 AL60
CCGT CCGTX_AL60
CD1U16V2KX-3DLGP
L68 V V AM48 TX_CORE
G
CCGT
V CCGTX_AM48
V SKYLAKE-U-GP
L69 AM50
L70 CCGT
V CCGTX_AM50
V AM52
L71 CCGT
V CCGTX_AM52
V AM53
M62 CCGT
V CCGTX_AM53
V AM56
N63 CCGT
V CCGTX_AM56
V AM58
N64 CCGT
V
CCGT
V
CCGTX_AM58
V
CCGTX_AU58
V
AU58 For U42 only Vince,20170622
N66 AU63
N67 CCGT
V CCGTX_AU63
V BB57
N69 CCGT
V CCGTX_BB57
V BB66
V
CCGT V
CCGTX_BB66
J70 V V AK62 T_CORE
G
J69 CCGT_SENSE CCGTX_SENSE AL61 CC_CORE
V VCCGT
+
[46] CCGT_SENSE
V 707
R 706
R
V
SSGT_SENSE V
SSGTX_SENSE
[46] SSGT_SENSE
V V V 1 2 1 2
U42 U22
D0002R5J-GP-U D0002R5J-GP-U
SKYLAKE-U-GP
CC_CORE
V TX_CORE
G CC_CORE
V
708
R
1 U42 2
1
D0002R5J-GP-U 719
R
100R2F-L1-GP-U
C C
VCCSA
2
+
CC_SENSE
V [46]
SS_SENSE
V [46]
1
#544669 CRB.
1
735
R
720
R Layout Note: 100R2F-L1-GP-U
D2V_S3
1 VDDQ_CPU_CLK
+ 100R2F-L1-GP-U
1. Place close to CPU
2. VCC_SENSE/ VSS_SENSE
2
705
R
impedance=50 ohm CCSA_SENSE
2
1 2 V
3. Length match<25mil SSSA_SENSE
V
0R0805-PAD
1
VCCGT
+ 734
R
100R2F-L1-GP-U
2016/02/16 modify
2
1
721
R
100R2F-L1-GP-U
2
CCGT_SENSE
V [46]
SSGT_SENSE
V [46]
1
722
R
100R2F-L1-GP-U
2
SVID_543016:
Layout Note:
SVID DATA The total Length of Data and Clock (from CPU to each VR) must be equal (±0.1 inch).
Route the Alert signal between the Clock and the Data signals.
VCCST_CPU
+
#544669
1
CLOSE TO CPU
726
R
100R2F-L1-GP-U
2
B B
_CPU_SVIDDAT
H 709
1 R 2
R_SVID_DATA
V [46]
0R0402-PAD
V
+CCST_CPU
SVID CLOCK #544669

1
CLOSE TO VR
723
R
DY 54D9R2F-L1-GP
2
_CPU_SVIDCLK
H 1 R
732 2 R_SVID_CLK
V [46]
0R0402-PAD
VCCST_CPU
+
#544669
1
CLOSE TO CPU
727
R
56R2J-4-GP
2
728
R
H_CPU_SVIDALRT# 2 1 R_SVID_ALERT#
V [46]
220R2J-L2-GP
A A
<Core Design>
1F,288, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
C PU(VCC_CORE)
1 A
tSarlord KBL-R A 00
Date: Friday, December 08, 2017 Sheet 7 f o 106
5 4 3 2 1
5 4 3 2 1
SSID = CPU
D D
C PU1A 1 OF 20
E55 SKYLAKE_ULT C47

[57] H DMI_DATA2# F55
DDI1_TXN[0] EDP_TXN[0]
C46
E DP_TX0_DN [55]
[57] H DMI_DATA2 E58
DDI1_TXP[0] EDP_TXP[0]
D46
E DP_TX0_DP [55]
[57] H DMI_DATA1# F58
C45
E DP_TX1_DN [55]
[57] H DMI_DATA1 DDI1_TXP[1] EDP_TXP[1] E DP_TX1_DP [55]
HDMI
F53 A45
[57] H DMI_DATA0# G53
B45
E DP_TX2_DN [55]
[57] H DMI_DATA0 F56
DDI1_TXP[2] EDP_TXP[2]
A47
E DP_TX2_DP [55]
[57] H DMI_CLK# G56
B47
E DP_TX3_DN [55]
[57] H DMI_CLK DDI1_TXP[3] EDP_TXP[3] E DP_TX3_DP [55]
C50 E45
[38] P CH_DPC_N0 DDI2_TXN[0] DDI EDP_AUXN E DP_AUX_DN [55]
Dummy, Vendor suggest [38] P CH_DPC_P0
D50
DDI2_TXP[0]
EDP
EDP_AUXP
F45 E DP_AUX_DP [55]
DP and DP to VGA
20141117 C52
[38] P CH_DPC_N1 D52
DDI2_TXN[1]
B52 E DP_DISP_UTIL 1
[38] P CH_DPC_P1 A50
DDI2_TXP[1] EDP_DISP_UTIL T P801 TPAD14-OP-GP
[38] P CH_DPC_N2 B50
DDI2_TXN[2]
G50
[38] P CH_DPC_P2 D51
DDI2_TXP[2] DDI1_AUXN
F50
[38] P CH_DPC_N3 C51
DDI2_TXN[3] DDI1_AUXP
E48
3 D3V_S0 [38] P CH_DPC_P3 DDI2_TXP[3] DDI2_AUXN
F48
D PB_AUXN [38]
DDI2_AUXP D PB_AUXP [38]
G46
DISPLAY SIDEBANDS DDI3_AUXN
SRN2K2J-1-GP F46
DDI3_AUXP
HDMI
C L13 C
1 4 C PU_DP1_CTRL_DATA [57] C PU_DP1_CTRL_CLK L12
GPP_E18/DDPB_CTRLCLK
L9
2 DY 3 C PU_DP1_CTRL_CLK [57] C PU_DP1_CTRL_DATA GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0
L7 C PU_DP2_HPD C PU_DP1_HPD [57]
C PU_DP2_CTRL_CLK GPP_E14/DDPC_HPD1 S IO_EXT_SMI#
R N801 C PU_DP2_CTRL_DATA
N7
N8
GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2
L6
N9
Vince,20161018
GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3
L10 E DP_HPD [55]
+ VCCIO GPP_E17/EDP_HPD
Check N11
GPP_E22/DDPD_CTRLCLK
R 801
N12 R12 L _BKLT_EN [24,55]
GPP_E23/DDPD_CTRLDATA EDP_BKLTEN
R11 L _BKLT_CTRL [55]
3 D3V_S0 1 2 E DP_COMP EDP_BKLTCTL
E52 U13 E DP_VDD_EN [55]
EDP_RCOMP EDP_VDDEN
R N803 SKYLAKE-U-GP
24D9R2F-L-GP
1 4 C PU_DP2_CTRL_DATA
2 3 C PU_DP2_CTRL_CLK
(#543016) The Skylake U/Y processor supports only two DDI ports - Port 1 and Port 2.
SRN2K2J-1-GP
(#543016) eDP_RCOMP Guideline C PU_DP2_HPD R 804 1 2 0R2J-2-GP C PU_DP_HPD_R [37,38,57]

TypeC
Signal Trace Isolation Resistor Length
2
Width Spacing Value
R 803
eDP_RCOMP 20 mils 25 mils 24.9 Ω ±1% Max = 100 mils TypeC 100KR2J-1-GP
1
B B
(#543016) DDI Disabling and Termination Guidelines 3 D3V_S0

Port Strap Enable Port Disable Port
PU to 3.3 V with 2.2-k
Port 1 DDPB_CTRLDATA ±5% resistor NC S IO_EXT_SMI# 1 R 802 2 10KR2J-3-GP
PU to 3.3 V with 2.2-k

Port 2 DDPC_CTRLDATA ±5% resistor NC
A <Core Design> A
Wistron Corporation
Design Guideline:
Skylake processor signal eDP_RCOMP should be connected to the VCCIO rail via a single 24.9 ±1% Ω resistor. Title
CPU_(DISPLAY)
A3
S tarlord KBL-R A00
WWW.AliSaler.Com5 4 3 2
1
8 of 106
5 4 3 2 1
Main Func = CPU
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
TTitle
itle
(Reserved)
A3
S tarlord KBL-R A00
5 4 3 2 1
D
A 00
Rev
106
o
f
C PU_(Power CAP1)
10
Sheet
tSarlord KBL-R
Friday, December 08, 2017
Document Number
1
1
<Core Design>
1 A
itleT
Date:
Title
Size
2
2
Vince,20160922
S C22U6D3V3MX-1-GP
C1035
U42
P
1 2
S C22U6D3V3MX-1-GP
C1082
U42
P
1 2
S C22U6D3V3MX-1-GP
3
3
C1079
U42
P
1 2
S C22U6D3V3MX-1-GP
Vince,20160922
C1081
U42
P
1 2
S C22U6D3V3MX-1-GP
C1080
U42
P
1 2
S C22U6D3V3MX-1-GP
S CD1U25V2KX-L-GP
C1033
C1001
For U42
U42
P
E
1 2
1 2
DY
S CD1U25V2KX-L-GP
C1007
E
Vince,20161005
CC_CORE
1 2
DY
2015/10/16 modify (Power team request)

V
S C22U6D3V3MX-1-GP
U42
C1085
U42
(#543016 PDG)
P
1 2
S C22U6D3V3MX-1-GP
C1083
U42
P
Remove PC1033 and PC1035 (power team request)
1 2
S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP
C1036
C1057
C1070
DY
P
P
1 2 1 2 1 2
S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP
C1056
C1069
EMI reserve , 20141118
DY
P
P
C1004
S CD1U25V2KX-L-GP 1 2 1 2
E
C1034
C1055
C1068
1 2
DY
DY
P
P
1 2 1 2 1 2
C1003
S CD1U25V2KX-L-GP S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP
P1054
P1001
E
DY
C
C
1 2 1 2 1 2 S C22U6D3V3MX-1-GP
DY
P1078
DYCE1006
S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP
C1002
C1021
C1032
P1053
P1067
S CD1U25V2KX-L-GP S CD1U25V2KX-L-GP
C
1 2
DY
DY
E
C
1 2 1 2 1 2 1 2
1 2 S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP 1 2 S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP
DY
C1020
C1031
P1052
P1066
P1077
20140814 DAVID
S C1U10V2KX-1GP
C
P
E1005
1 2 1 2 1 2 1 2 1 2
C1010
S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP
C
C1019
C1030
P 1051
P 1065
1 2 S C22U6D3V3MX-1-GP
P
P 1076
C
C
P
1 2 1 2 1 2 1 2 1 2
C
S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP 1 2
C1009
C1018
C1029
C1043
C1050
C1064
S C22U6D3V3MX-1-GP
P
C1075
4
4
1 2 1 2 1 2 1 2 1 2 1 2
S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP
P
C1008
C1017
C1028
C1042
C1049
C1063
1 2
IccMax current-10ms max[A] = 67 A

P
P
1 2 1 2 1 2 1 2 1 2 1 2 S C22U6D3V3MX-1-GP
C1074
C1007
C1016
C1027
C1041
C1048
C1062
P
IccMax current-10ms max = 34 A
1 2
SLICED GT
P
P
1 2 1 2 1 2 1 2 1 2 1 2
WWW.AliSaler.Com
S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP
C1006
C1015
C1026
C1040
C1047
C1061
C1073
22U 0603 x35 (5 DY)
P
P
1 2 1 2 1 2 1 2 1 2 1 2 1 2
22U 0603 x 35(5 DY)

C1005
C1014
C1025
C1039
C1046
C1060
22U 0603 x13 (5 DY)

S C22U6D3V3MX-1-GP
C1072
P
P
U-line 23e 28W
1 2 1 2 1 2 1 2 1 2 1 2
P
S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP 1 2
C1004
C1013
C1024
C1038
C1045
C1059
VCCSA
U-line 23e 28W
S C22U6D3V3MX-1-GP
C1071
P
P
CORE
1 2 1 2 1 2 1 2 1 2 1 2
PC1003
PC1012
PC1023
PC1037
PC1044
PC1058
P
1 2
+VCCSA
1 2 1 2 1 2 1 2 1 2 1 2
PC1002
PC1011
PC1022
1 2 1 2 1 2
+VCCGT
VCC_CORE
5
5
SSID = CPU
A
5 4 3 2 1
Main Func = CPU
PCH DERIVED RAILS UNSLICED GT VCCIO

+ VCCGT + VCCIO
1 D0V_S5
+VCCIO(ICCMAX.=2.73A)
D D
1
+ VCCPRIM_CORE C 1102 C 1103 C 1104 C 1105 C 1106 C 1107 1U 0402 x 6 C 1108 C 1109 C 1110 C 1111
1 R 1101 2
DY DY DY DY DY
2
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
0R1206-PAD
+ V1.00A_SIP
R 1102
1 2
SC22U6D3V3MX-1-GP
Dummy : 20150123
C1112
Dummy : 20150123
1
0R0603-PAD
DY
2
3D3V_S5_PCH + V3.3A_SIP
R 1103
1 2 +VCCMPHYGTAON_1P0(ICCMAX.=2.12A)
SC22U6D3V3MX-1-GP
C1113
C C
1
0R0603-PAD
DY
2
Layout Note:
+ VCCMPHYGTAON_1P0_LS_SIP + VCCMPHYGTAON_1P0_LS_SIP + VCCMPHYGTAON_1P0_LS_SIP + VCCMPHYGTAON_1P0_LS_SIP 1uF:
C1174 near N15
C1180 near K15
SC1U10V2KX-1GP
SC22U6D3V3MX-1-GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC22U6D3V3MX-1-GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
C1114
C1115
C1116
C1117
C1118
C1119
C
1121
1
1
+ V1.8A + V1.8A_SIP C1173 near AF20
SC10U6D3V3MX-GP
C
1120
R 1104
1 2
DY DY DY C1172 near N18
C1175 near AB19
2
2
SC22U6D3V3MX-1-GP
C1122
22uF :
1
0R0603-PAD
DY C1182 C1184 near N15
10uF:
2
C1176 near N15

+ VCCPRIM_CORE
+ VCCIO
+VCCIO(ICCMAX.=2.73A)
PC1102
PC1103
PC1104
1
B B
DY 1 D2V_S3
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
2
1
P C1105
P C1106
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
2
P C1107
P C1108
P C1109
P C1110
P C1111
P C1112
P C1113
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
1
1
P C1114 SC10U6D3V3MX-GP
P C1101 SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
2
2
Size:0805 change to 0603
20141117
Change to 0.1uF at 20150427 for Power team
+ V3.3A_SIP P C1115
1
E C1102 E C1103
SC22U6D3V3MX-1-GP
1
SC2D2U10V2KX-GP
SC2D2U10V2KX-GP
VCC_CORE DY DY DY DY
1U 0402 x 5
2
2
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
2
1
SC10U6D3V3MX-GP
C1123
DY
2
<Core Design>
A A
1
C1124 C1125 C1126 C1101 C1127
Wistron Corporation
2
2
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP

RF request 2016/01/12 modify
TTitle
itle
CPU_(Power CAP2)
A3
U-line 23e 28W S tarlord KBL-R A00
IccMax current-10ms max = 34 A Date: Friday, December 08, 2017 Sheet 11 of 106
5 4 3 2 1
5 4 3 2 1
D M1A 1 OF 4
D M1D 4 OF 4
144 8
[5] M _A_A0 133 A0 D Q0 7 M _A_DQ0 [5] 1 99
[5] M _A_A1 _A_DQ1 [5] D M1B 2 OF 4
132 A1 D Q1 20 M 2 V SS V SS 102
[5] M _A_A2 _A_DQ2 [5]
131 A2 D Q2 21 M 11 M _A_DQS_DN0 5 V SS V SS 103
[5] M _A_A3 _A_DQ3 [5]
128 A3 D Q3 4 M D QS0_C 13 M _A_DQS_DP0 6 V SS V SS 106
[5] M _A_A4 _A_DQ4 [5]
126 A4 D Q4 3 M D QS0_T 32 M _A_DQS_DN1 9 V SS V SS 107
[5] M _A_A5 _A_DQ5 [5]
[5] M _A_A6 _A_DQ6 [5]
[5] M _A_A7 _A_DQ7 [5]
[5] M _A_A8 _A_DQ8 [5]
[5] M _A_A9 A9 D Q9 M _A_DQ9 [5] D QS3_C V SS V SS
146 41 76 M _A_DQS_DP3 19 175
[5] M _A_A10 A 10/AP D Q10 M _A_DQ10 [5] D QS3_T V SS V SS
120 42 177 M _A_DQS_DN4 22 176
[5] M _A_A11 A 11 D Q11 M _A_DQ11 [5] D QS4_C V SS V SS
119 24 179 M _A_DQS_DP4 23 180
[5] M _A_A12 A 12 D Q12 M _A_DQ12 [5] D QS4_T V SS V SS
158 25 198 M _A_DQS_DN5 26 181
[5] M _A_A13 A 13 D Q13 M _A_DQ13 [5] D QS5_C V SS V SS
151 38 200 M _A_DQS_DP5 27 184
[5] M _A_A14 W E#/A14 D Q14 M _A_DQ14 [5] D QS5_T V SS V SS
156 37 219 M _A_DQS_DN6 30 185
[5] M _A_A15 C AS#/A15 D Q15 M _A_DQ15 [5] D QS6_C V SS V SS
152 50 221 M _A_DQS_DP6 31 188
[5] M _A_A16 R AS#/A16 D Q16 M _A_DQ16 [5] D QS6_T V SS V SS
49 240 M _A_DQS_DN7 35 189
D
150 D Q17 62 M _A_DQ17 [5] D QS7_C 242 M _A_DQS_DP7 36 V SS V SS 192
D
[5] M _A_BA0 B A0 D Q18 M _A_DQ18 [5] D QS7_T V SS V SS
[5]
145 63 95 1 D2V_S3 39 193
M _A_BA1 115 B A1 D Q19 46 M _A_DQ19 [5] D QS8_C 97 40 V SS V SS 196
[5] M _A_BG0 B G0 D Q20 M _A_DQ20 [5] D QS8_T V SS V SS
113 45 43 197
[5] M _A_BG1 B G1 D Q21 M _A_DQ21 [5] V SS V SS
58 12 44 201
92 D Q22 59 M _A_DQ22 [5] D M0#/DBI0# 33 47 V SS V SS 202
91 C B0/NC D Q23 70 M _A_DQ23 [5] D M1#/DBI# 54 48 V SS V SS 205
101 C B1/NC D Q24 71 M _A_DQ24 [5] D M2#/DBI2# 75 51 V SS V SS 206
C B7/NC D Q30 80 M _A_DQ30 [5] D M8#/DBI#/NC 64 V SS V SS 218
137 D Q31 174 M _A_DQ31 [5] 65 V SS V SS 222
[5] M _A_CLK0 C K0_T D Q32 M _A_DQ32 [5] DR4-260P-65-GP V SS V SS
139 173 D 68 223
[5] M _A_CLK#0 C K0_C D Q33 M _A_DQ33 [5] V SS V SS
[5]
138 187 3 D3V_S0 69 226
M _A_CLK1 140 C K1_T/NF D Q34 186 M _A_DQ34 [5]
1 D2V_S3 72 V SS V SS 227
[5] M _A_CLK#1 _A_DQ35 [5] D M1C 3 OF 4
C K1_C/NF D Q35 170 M 73 V SS V SS 230
109 D Q36 169 M _A_DQ36 [5] 111 255 77 V SS V SS 231
[5] M _A_CKE0 C KE0 D Q37 M _A_DQ37 [5] V DD V DDSPD V SS V SS
110 183 112 78 234
[5] M _A_CKE1 C KE1 D Q38 M _A_DQ38 [5] V DD V SS V SS
182 117 2 D5V_S3 81 235
149 D Q39 195 M _A_DQ39 [5] 118 V DD 257 82 V SS V SS 238
[5] M _A_CS#0 _A_DQ40 [5] C 1228
C S0# D Q40 M V DD V PP V SS V SS
1
157 194 123 259 R 1216 85 239
S
DY
CD1U16V2KX-L-GP
[5] M _A_CS#1 C S1# D Q41 M _A_DQ41 [5] V DD V PP V SS V SS
162 207 124 86 243
S
C2D2U10V3KX-L-GP
165 C 0/CS2#/NC D Q42 208 M _A_DQ42 [5] 129 V DD 258 89 V SS V SS 244
C 1/CS3#/NC D Q43 M _A_DQ43 [5] V DD V TT 0 D6V_S0 DY V SS V SS
2
191 130 90 247
155 D Q44 190 M _A_DQ44 [5] 135 V DD 93 V SS V SS 248
[5] M _A_DIMA_ODT0 O DT0 D Q45 M _A_DQ45 [5] V DD V SS V SS
161 203 136 94 251
[5] M _A_DIMA_ODT1 O DT1 D Q46 M _A_DQ46 [5] V DD V SS V SS
204 141 98 252
S A0_CHA_DIM0 256 D Q47 216 M _A_DQ47 [5] 142 V DD V SS V SS
S A1_CHA_DIM0 260 S A0 D Q48 215 M _A_DQ48 [5] 147 V DD 261
S A2_CHA_DIM0 166 S A1 D Q49 228 M _A_DQ49 [5] 148 V DD 2 61 262 D
DR4-260P-65-GP
S A2 D Q50 229 M _A_DQ50 [5] 153 V DD 2 62
254 D Q51 211 M _A_DQ51 [5] 154 V DD
[13,18] P CH_SMBDATA 253 S DA D Q52 212 M _A_DQ52 [5] 159 V DD NP1
[13,18] P CH_SMBCLK S CL D Q53 224 M _A_DQ53 [5] 160 V DD N P1 NP2 20170104
D Q54 225 M _A_DQ54 [5] 163 V DD N P2
108 D Q55 237 M _A_DQ55 [5] V DD
1D2V_S3 [5,13] D DR4_DRAMRST# 114 R ESET# D Q56 236 M _A_DQ56 [5]
[5] M _A_ACT_N
116 A CT# D Q57 249 M _A_DQ57 [5] D
DR4-260P-65-GP UN 0225
C [5] M _A_ALERT_N C
T S#_DIMM0_1 134 A LERT# D Q58 250 M _A_DQ58 [5]
1 DY 2
E VENT#/NF D Q59 232 M _A_DQ59 [5] 0 D6V_S0 0 D6V_S0
R 1215 240R2F-1-GP
_A_DQ60 [5]
143 D Q60 233 M 0 D6V_S0
[5] M _A_PARITY P ARITY D Q61 M _A_DQ61 [5]
DDR4_DRAMRST# 245
M _VREF_CA_DIMMA 164 D Q62 246 M _A_DQ62 [5]
V REFCA D Q63 M _A_DQ63 [5] 20170307 DTC Dummy
1
DR4-260P-65-GP
1
ED1217 D C 1225 C 1226 C 1223 C 1230 C 1224 C 1227
1 D2V_S3
1
AZ5725-01FDR7G-GP
C 1229
SC1U10V2KX-1GP
SC1U10V2KX-1GP
DDR4 SWAP 0212
2
SCD1U16V2KX-3DLGP
2
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
2
跟sw確認
3 D3V_S0
1
C 1208 C 1202 C 1209 C 1203 C 1204 C 1205 C 1206 C 1210
Layout note: closed to Dimm DY DY DY
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
2
2
2 R 1204DY
1 10KR2F-L1-GP S A0_CHA_DIM0
1 R 1205 2
1D2V_S3 0R0402-PAD
2 D5V_S3
RN1201 R 1206
1 4 3 D3V_S0
2 3 M _VREF_CA_DIMMA1 2
V _SM_VREF_CNTA [5]
1
C 1214 C 1215 C 1216 C 1217 C 1218 C 1219 C 1220 C 1221 E C1202
1 10KR2F-L1-GP S A1_CHA_DIM0
1
SRN1KJ-7-GP 2R2F-GP 2 R 1208DY C 1211 C 1231 C 1232 C 1212 C 1207 C 1213
SC2D2U10V2KX-GP
DY DY DY DY DY DY
1
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
C 1222
2
SCD022U16V2KX-3GP 1 R 1210 2
2
2
0R0402-PAD
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
+ V_VREF_PATH1
1
R 1209
24D9R2F-L-GP
3 D3V_S0

2
B 1 10KR2F-L1-GP S A2_CHA_DIM0
2 R 1211DY B
1 R 1212 2
M _A_DQS_DN[7:0] [5]
0R0402-PAD M _A_DQS_DN0
M _A_DQS_DN1
M _A_DQS_DN2
M _A_DQS_DN3
M _A_DQS_DN4
M _A_DQS_DN5
M _A_DQS_DN6
M _A_DQS_DN7
M _A_DQS_DP0 M _A_DQS_DP[7:0] [5]

M _A_DQS_DP1
M _A_DQS_DP2
M _A_DQS_DP3
M _A_DQS_DP4
M _A_DQS_DP5
M _A_DQS_DP6
M _A_DQS_DP7
A A
<Core Design>
itle
T Title
D DR3-SODIMM1
Size
A 2
Document Number
S tarlord KBL-R
1
Sheet 12 o f
Rev
A 00
106
5 4 3 2 1
By layou modify 20150916 3 D3V_S0

D M2A 1 OF 4
[5] 144 8 1 D2V_S3

M _B_A0 133 A0 D Q0 7 M _B_DQ8 [5]
[5] M _B_A1 M _B_DQ9 [5] D M2C 3 OF 4 D M2D 4 OF 4
132 A1 D Q1 20
[5] M _B_A2 M _B_DQ10 [5]
131 A2 D Q2 21 111 255 1 99
[5] M _B_A3 M _B_DQ11 [5]
128 A3 D Q3 4 112 V DD V DDSPD 2 V SS V SS 102
[5] M _B_A4 M _B_DQ12 [5]
126 A4 D Q4 3 117 V DD 2 D5V_S3 5 V SS V SS 103
[5] M _B_A5 M _B_DQ13 [5]
127 A5 D Q5 16 118 V DD 257 6 V SS V SS 106
[5] M _B_A6 M _B_DQ14 [5]
122 A6 D Q6 17 123 V DD V PP 259 9 V SS V SS 107
1
[5] M _B_A7 M _B_DQ15 [5] C 1329 DY
125 A7 D Q7 28 124 V DD V PP 0 D6V_S0 DY C 1328 10 V SS V SS 167
C
S2D2U10V3KX-L-GP
[5] M _B_A8 A8 D Q8 M _B_DQ0 [5] V DD V SS V SS
121 29 129 258 14 168
C
SD1U16V2KX-L-GP
[5] M _B_A9 A9 D Q9 M _B_DQ1 [5] V DD V TT V SS V SS
2
[5] 146 41 130 15 171
M _B_A10 120 A 10/AP D Q10 42 M _B_DQ2 [5]
135 V DD 18 V SS V SS 172
[5] M _B_A11 A 11 D Q11 M _B_DQ3 [5] V DD V SS V SS
[5] 119 24 136 19 175
M _B_A12 158 A 12 D Q12 25 M _B_DQ4 [5]
141 V DD 22 V SS V SS 176
[5] M _B_A13 A 13 D Q13 M _B_DQ5 [5] V DD V SS V SS
[5] 151 38 142 23 180
M _B_A14 156 W E#/A14 D Q14 37 M _B_DQ6 [5]
147 V DD 261 26 V SS V SS 181
[5] M _B_A15 C AS#/A15 D Q15 M _B_DQ7 [5] V DD 2 61 V SS V SS
[5] 152 50 148 262 27 184
D M _B_A16 R AS#/A16 D Q16 49 M _B_DQ16 [5]
153 V DD 2 62 30 V SS V SS 185
D
150 D Q17 62 M _B_DQ17 [5]

154 V DD 31 V SS V SS 188
[5] M _B_BA0 145 B A0 D Q18 63 M _B_DQ18 [5]
159 V DD NP1 35 V SS V SS 189
[5] M _B_BA1 115 B A1 D Q19 46 M _B_DQ19 [5]
160 V DD N P1 NP2 36 V SS V SS 192
[5] M _B_BG0 113 B G0 D Q20 45 M _B_DQ20 [5]
163 V DD N P2 39 V SS V SS 193
[5] M _B_BG1 B G1 D Q21 58 M _B_DQ21 [5] V DD 40 V SS V SS 196
92 D Q22 59 M _B_DQ22 [5]
43 V SS V SS 197
91 C B0/NC D Q23 70 M _B_DQ23 [5] DR4-260P-64-GP
44 V SS V SS 201
D
101 C B1/NC D Q24 71 M _B_DQ24 [5]
47 V SS V SS 202
105 C B2/NC D Q25 83 M _B_DQ25 [5]
48 V SS V SS 205
88 C B3/NC D Q26 84 M _B_DQ26 [5]
51 V SS V SS 206
87 C B4/NC D Q27 66 M _B_DQ27 [5]
52 V SS V SS 209
100 C B5/NC D Q28 67 M _B_DQ28 [5]
56 V SS V SS 210
104 C B6/NC D Q29 79 M _B_DQ29 [5] By layou modify 20150916 57 V SS V SS 213
C B7/NC D Q30 80 M _B_DQ30 [5]
60 V SS V SS 214
M _B_DQ31 [5] D M2B 2 OF 4
137 D Q31 174 61 V SS V SS 217
[5] M _B_CLK0 139 C K0_T D Q32 173 M _B_DQ32 [5]
11 _B_DQS_DN1 64 V SS V SS 218
M
[5] M _B_CLK#0 138 C K0_C D Q33 187 M _B_DQ33 [5] D QS0_C 13 _B_DQS_DP1 M _B_DQS_DN1 [5]
65 V SS V SS 222
M
[5] M _B_CLK1 140 C K1_T/NF D Q34 186 M _B_DQ34 [5] D QS0_T 32 _B_DQS_DN0 M _B_DQS_DP1 [5]
68 V SS V SS 223
M
[5] M _B_CLK#1 C K1_C/NF D Q35 170 M _B_DQ35 [5] D QS1_C 34 _B_DQS_DP0 M _B_DQS_DN0 [5]
69 V SS V SS 226
M
D Q36 M _B_DQ36 [5] D QS1_T _B_DQS_DN2 M _B_DQS_DP0 [5] V SS V SS
109 169 53 M 72 227
[5] M _B_CKE0 C KE0 D Q37 M _B_DQ37 [5] D QS2_C _B_DQS_DP2 M _B_DQS_DN2 [5] V SS V SS
110 183 55 M 73 230
[5] M _B_CKE1 C KE1 D Q38 M _B_DQ38 [5] D QS2_T _B_DQS_DN3 M _B_DQS_DP2 [5] V SS V SS
182 74 M 77 231
D Q39 M _B_DQ39 [5] D QS3_C _B_DQS_DP3 M _B_DQS_DN3 [5] V SS V SS
149 195 76 M 78 234
[5] M _B_CS#0 C S0# D Q40 M _B_DQ40 [5] D QS3_T _B_DQS_DN4 M _B_DQS_DP3 [5] V SS V SS
157 194 177 M 81 235
[5] M _B_CS#1 C S1# D Q41 M _B_DQ41 [5] D QS4_C _B_DQS_DP4 M _B_DQS_DN4 [5] V SS V SS
162 207 179 M 82 238
C 0/CS2#/NC D Q42 M _B_DQ42 [5] D QS4_T _B_DQS_DN5 M _B_DQS_DP4 [5] V SS V SS
165 208 198 M 85 239
C 1/CS3#/NC D Q43 M _B_DQ43 [5] D QS5_C _B_DQS_DP5 M _B_DQS_DN5 [5] V SS V SS
191 200 M 86 243
D Q44 M _B_DQ44 [5] D QS5_T _B_DQS_DN6 M _B_DQS_DP5 [5] V SS V SS
155 190 219 M 89 244
[5] M _B_DIMB_ODT0 O DT0 D Q45 M _B_DQ45 [5] D QS6_C _B_DQS_DP6 M _B_DQS_DN6 [5] V SS V SS
161 203 221 M 90 247
[5] M _B_DIMB_ODT1 O DT1 D Q46 M _B_DQ46 [5] D QS6_T _B_DQS_DN7 M _B_DQS_DP6 [5] V SS V SS
204 240 M 93 248
D Q47 M _B_DQ47 [5] D QS7_C M _B_DQS_DN7 [5] V SS V SS
S A0_CHB_DIM0 256 216 242 M _B_DQS_DP7 94 251
S A0 D Q48 M _B_DQ48 [5] D QS7_T M _B_DQS_DP7 [5] V SS V SS
S A1_CHB_DIM0 260 215 95 98 252
S A1 D Q49 M _B_DQ49 [5] D QS8_C V SS V SS
S A2_CHB_DIM0 166 228 97 1 D2V_S3
S A2 D Q50 M _B_DQ50 [5] D QS8_T
229
D Q51 M _B_DQ51 [5] DR4-260P-64-GP
254 211 12 D
[12,18] PCH_SMBDATA S DA D Q52 M _B_DQ52 [5] D M0#/DBI0#
253 212 33
[12,18] PCH_SMBCLK S CL D Q53 M _B_DQ53 [5] D M1#/DBI#
224 54
D Q54 M _B_DQ54 [5] D M2#/DBI2#
225 75
D Q55 M _B_DQ55 [5] D M3#/DBI3#
108 237 178
[5,12] D DR4_DRAMRST# R ESET# D Q56 M _B_DQ56 [5] D M4#/DBI4#
C 1D2V_S3 114 236 199 C
[5] M _B_ACT_N A CT# D Q57 M _B_DQ57 [5] D M5#/DBI5#
116 249 220
1 R1312 2
[5] M _B_ALERT_N T S#_DIMM1_1 134 A LERT# D Q58 250
M _B_DQ58 [5] D M6#/DBI6# 241
UN 0225
DY 240R2F-1-GP
E VENT#/NF D Q59 232
M _B_DQ59 [5] D M7#/DBI7# 96 20170104
D Q60 M _B_DQ60 [5] D M8#/DBI#/NC
143 233
[5] M _B_PARITY P ARITY D Q61 M _B_DQ61 [5]
245 0 D6V_S0 0 D6V_S0 0 D6V_S0 2 D5V_S3
D Q62 M _B_DQ62 [5] DR4-260P-64-GP
M _VREF_CA_DIMMB 164 246 D
V REFCA D Q63 M _B_DQ63 [5]
DR4-260P-64-GP
D
DDR4 SWAP 0212 1 D2V_S3
1
1
C 1311 C 1330 C 1331 C 1312 C 1313 C 1314
20170307 DTC Dummy
1
DDR4_DRAMRST# C 1301 C 1324 C 1325
跟sw確認
1
SCD1U16V2KX-3DLGP C 1326 C 1327
2
2
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
2
2
3 D3V_S0
1
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
2
2
ED1302
AZ5725-01FDR7G-GP DY S A0_CHB_DIM0
1
2 R 1302 1 10KR2F-L1-GP C 1303 C 1304 C 1305 C 1306 C 1307 C 1308 C 1309 C 1310
1 R 1303 2
DY DY DY DY
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
2
2
0R0402-PAD
Layout note: closed to Dimm 3 D3V_S0
2 R 1306 1 10KR2F-2-GP S A1_CHB_DIM0 E C1303

1
1
C 1315 C 1316 C 1317 C 1318 C 1319 C 1320 C 1321 C 1322
2 R 1307 1 0R2J-L-GP
SC2D2U10V2KX-GP
DY DY DY DY DY DY _B_DQS_DN0 M _B_DQS_DN[7:0] [5]
1
M
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
DY
2
2
M _B_DQS_DN1
M _B_DQS_DN2
2
M _B_DQS_DN3
3 D3V_S0 M _B_DQS_DN4
M _B_DQS_DN5
1D2V_S3 M _B_DQS_DN6
DY S A2_CHB_DIM0 M _B_DQS_DN7
2 R 1310 1 10KR2F-L1-GP
RN1301 1 R 1311 2
R 1305 M _B_DQS_DP0 M _B_DQS_DP[7:0] [5]
1 4
B 2 3 M_VREF_CA_DIMMB1 2 0R0402-PAD M _B_DQS_DP1 B
V _SM_VREF_CNTB [5] RF request 2016/01/12 modify M _B_DQS_DP2
SRN1KJ-7-GP 2R2F-GP 3 D3V_S5 M _B_DQS_DP3
_B_DQS_DP4
1
C 1323 M
SCD022U16V2KX-3GP M _B_DQS_DP5
E C1302 M _B_DQS_DP6
2
_B_DQS_DP7
1
M
SC2D2U10V2KX-GP
+ V_VREF_PATH2 DY
1
R 1309
2
24D9R2F-L-GP
2
A A
<Core Design>
itle
T Title
D DR3-SODIMM1
A 2
5 4 3 2 1
5 4 3 2 1
D D
C
(Blanking) C
B B
<Core Design>
A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
(Reserved)_SODIMM _SODIMM4
A4
Starlord KBL-R A 00
WWW.AliSaler.Com
5 4 3
Date: Monday, August 28, 2017
2
Sheet 14
1
of 106
5 4 3 2 1
Main Func = PCH

3 D3V_S0
R 1503
9 OF 20 W IFI_RF_EN 2
C PU1I
DY 1
CSI-2 SKYLAKE_ULT
10KR2J-3-GP
A36 C37
CSI2_DN0 CSI2_CLKN0
B36 D37
CSI2_DP0 CSI2_CLKP0 Change to Dummy
D C38 C32 20150402 D
CSI2_DN1 CSI2_CLKN1
D38 D32
CSI2_DP1 CSI2_CLKP1
C36 C29
CSI2_DN2 CSI2_CLKN2 DC resistance < 0.5ohm.
D36 D29
CSI2_DP2 CSI2_CLKP2
A38 B26
CSI2_DN3 CSI2_CLKN3
B38 A26
CSI2_DP3 CSI2_CLKP3
C31 E13 C SI2_COMP 1 R 1501 2 100R2F-L1-GP-U
CSI2_DN4 CSI2_COMP
D31 B7 W IFI_RF_EN [66]
CSI2_DP4 GPP_D4/FLASHTRIG
C33
CSI2_DN5
D33
CSI2_DP5 EMMC
A31
CSI2_DN6
B31 AP2
CSI2_DP6 GPP_F13/EMMC_DATA0 [#545659 Rev0.7]
A33 AP1
CSI2_DN7 GPP_F14/EMMC_DATA1
B33 AP3
CSI2_DP7 GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
AN3 GPP_F: VCCPGPPF = 1.8V Only
A29 AN1
B29 AN2
C28 AM4
D28 AM1
A27
CSI2_DN10
B27 AM2
CSI2_DP10 GPP_F21/EMMC_RCLK
C27 AM3
CSI2_DN11 GPP_F22/EMMC_CLK
D27 AP4 R 1502
CSI2_DP11 GPP_F12/EMMC_CMD
AT1 E MMC_RCOMP1 2
EMMC_RCOMP
SKYLAKE-U-GP
200R2F-L-GP
C C
B B
A <Core Design> A
Wistron Corporation
Title
CPU_(CS-2/EMMC)
A3
S tarlord KBL-R A00
Date: Friday, December 08, 2017 Sheet 15 of 106
5 4 3 2 1
5 4 3 2 1
SSID = PCH
#543016:
220 nF nominal capacitors are recommended for Gen 3. C 8 OF 20
100 nF nominal capacitors are recommended for Gen 2. PU1H SKYLAKE_ULT
SSIC / USB3 H8
PCIE/USB3/SATA SB3_1_RXN G8
H13 USB3_1_RXP C13 SB30_RX_CPU_N1
U [36] (#545659) The xHCI controller supports USB Debug port on all USB3.0 capable ports.
G13 CIE1_RXN/USB3_5_RXN USB3_1_TXN D13 SB30_RX_CPU_P1
U [36]
[66] CPU_RXN_C_dGPU_TXN0 SB30_TX_CPU_N1 [36]
SCD22U10V2KX-1GP B17 PCIE1_RXP/USB3_5_RXP SB3_1_TXP
U U
[66] CPU_RXP_C_dGPU_TXP0 SB30_TX_CPU_P1 [36]
C1606 1 2OPS PEG_TX_CPU_N0 A17 PCIE1_TXN/USB3_5_TXN U J6 U
[66] dGPU_RXN_C_CPU_TXN0
C1605 1 2OPS PEG_TX_CPU_P0 PCIE1_TXP/USB3_5_TXP SB3_2_RXN/SSIC_1_RXN H6
[66] dGPU_RXP_C_CPU_TXP0 SB3_2_RXP/SSIC_1_RXP SB30_RX_CPU_N2 [36]
SCD22U10V2KX-1GP G11 P U B13 U
F11 CIE2_RXN/USB3_6_RXN USB3_2_TXN/SSIC_1_TXN A13 SB30_RX_CPU_P2
U [36]
SCD22U10V2KX-1GP D16 PCIE2_RXP/USB3_6_RXP SB3_2_TXP/SSIC_1_TXP
U U
C1608 1 2OPS PEG_TX_CPU_N1 C16 PCIE2_TXN/USB3_6_TXN U J10 U
C1607 1 2OPS PEG_TX_CPU_P1 PCIE2_TXP/USB3_6_TXP SB3_3_RXN/SSIC_2_RXN H10
[66] dGPU_RXP_C_CPU_TXP1 SB3_3_RXP/SSIC_2_RXP
SCD22U10V2KX-1GP H16 P U B15
G16 CIE3_RXN USB3_3_TXN/SSIC_2_TXN A15
GPU Cutomer remove IO board USB3.0
[66] CPU_RXN_C_dGPU_TXN2
SCD22U10V2KX-1GP D17 PCIE3_RXP SB3_3_TXP/SSIC_2_TXP
U
[66] CPU_RXP_C_dGPU_TXP2
C1610 1 2OPS PEG_TX_CPU_N2 C17 PCIE3_TXN U E10
C1609 1 2OPS PEG_TX_CPU_P2 PCIE3_TXP SB3_4_RXN F10
[66] dGPU_RXP_C_CPU_TXP2 SB3_4_RXP SB30_RX_CPU_N4 [38]
SCD22U10V2KX-1GP G15 P U C15 U
F15 CIE4_RXN USB3_4_TXN D15 SB30_RX_CPU_P4
U [38]
D SCD22U10V2KX-1GP B19 PCIE4_RXP SB3_4_TXP
U U
D
C1612 1 2OPS PEG_TX_CPU_N3 A19 PCIE4_TXN U AB9 U
C1611 1 2OPS PEG_TX_CPU_P3 PCIE4_TXP SB2N_1 AB10
[66] dGPU_RXP_C_CPU_TXP3 SB2P_1 SB_CPU_PN0
U [34]
SCD22U10V2KX-1GP F16 P U
E16 CIE5_RXN U AD6
SB_CPU_PP0
U [34] USB3.0 port1
Vince,20170105 C19 PCIE5_RXP SB2N_2 AD7 SB_CPU_PN1 [36]
D19 PCIE5_TXN SB2P_2
U U
PCIE5_TXP U AH3
SB_CPU_PP1
U [36] USB3.0 port2 ROR only
G18 P SB2N_3 AJ3
CIE6_RXN SB2P_3 SB_CPU_PN2
U [66]
F18 U
TBD
[66] PCIE_RX_CPU_N6
D20 PCIE6_RXP U AD9
SB_CPU_PP2
U [66] USB3.0 port3
WLAN [66] PCIE_RX_CPU_P6
[66] PCIE_TX_WLAN_N6 C1601 1 2 SCD1U16V2KX-3DLGP PCIE_TX_CPU_N6 C20 PCIE6_TXN
PCIE6_TXP
SB2N_4
SB2P_4
AD10 SB_CPU_PN3
U [38]
C1602 1 2 SCD1U16V2KX-3DLGP PCIE_TX_CPU_P6 U
[66] PCIE_TX_WLAN_P6
F20 P U AJ1
SB_CPU_PP3
U [38] Type C
E20 CIE7_RXN/SATA0_RXN SB2N_5 AJ2
[60] SATA_RX_CPU_N0 SB_CPU_PN4
U [55]
B21 PCIE7_RXP/SATA0_RXP SB2P_5
U
HDD1 [60] SATA_RX_CPU_P0
[60] SATA_TX_CPU_N0 A21 PCIE7_TXN/SATA0_TXN
PCIE7_TXP/SATA0_TXP
USB2
U
SB2N_6
AF6
SB_CPU_PP4
U [55] CAMERA
[60] SATA_TX_CPU_P0 AF7 SB_CPU_PN5 [66]
P SB2P_6
U U
G21
F21 CIE8_RXN/SATA1A_RXN U AH1
SB_CPU_PP5
U [66] Card Reader
D21 PCIE8_RXP/SATA1A_RXP SB2N_7 AH2 SB_CPU_PN6
U [66]
C21 PCIE8_TXN/SATA1A_TXN SB2P_7
U
PCIE8_TXP/SATA1A_TXP U AF8
SB_CPU_PP6
U [66] WLAN
Vince,20160922 E22 P SB2N_8 AF9 SB_CPU_PN7 [55]
D3V_S0
3
CIE9_RXN SB2P_8
U U
[63] PCIE_RX_CPU_N9 E23 SB_CPU_PP7 [55] Touch Panel
PCIE9_RXP U U
[63] PCIE_RX_CPU_P9 B23 AG1
A23 PCIE9_TXN SB2N_9 AG2
[63] PCIE_TX_CPU_N9
PCIE9_TXP SB2P_9
U
[63] PCIE_TX_CPU_P9 IO_EXT_SCI#
F25 P U AH7 S 2 1
E25 CIE10_RXN SB2N_10 AH8 1608
R 10KR2J-3-GP
[63] PCIE_RX_CPU_N10
D23 PCIE10_RXP SB2P_10
U
[63] PCIE_RX_CPU_P10
[63] PCIE_TX_CPU_N10 C23 PCIE10_TXN U AB6
DC resistance < 0.5ohm. Vince,20161201
PCIE10_TXP SB2_COMP AG3 SBCOMP
U 1 1603
R 2 113R2F-GP
[63] PCIE_TX_CPU_P10
F5 P U SB2_ID AG4 SB2_ID
U
PCIE_RCOMPN E5 CIE_RCOMPN SB2_VBUSSENSE
U SB2_VBUSSENSE
U
R1604 1 2 PCIE_RCOMPP PCIE_RCOMPP U A9
100R2F-L1-GP-U D56 P PP_E9/USB2_OC0# C9
SSD TPAD14-OP-GP TP1605 1 XDP_PRDY# D61 ROC_PRDY# PP_E10/USB2_OC1#
G D9
SB_OC0#
U
SB_OC1#
[34,35]
[66]
TPAD14-OP-GP TP1606 1 XDP_PREQ# BB11 PROC_PREQ# PP_E11/USB2_OC2#
G B9 SB_OC2#
U U
PPP_A7/PIRQA# PP_E12/USB2_OC3#
G SB_OC3#
U
PIRQA#
E28 G G J1
E27 CIE11_RXN/SATA1B_RXN PP_E4/DEVSLP0 J2
[63] PCIE_RX_CPU_N11
PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 IO_EXT_SCI# DD_DEVSLP
H [60] (#543016) When used as DEVSLP, no external pull-up or pull-down
D24 J3 S
[63] PCIE_RX_CPU_P11
PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2 IO_EXT_SCI#
S termination required from SATA Host DEVSLP.
[63] PCIE_TX_CPU_N11 C24 SD_DEVSLP
S [63]
E30 PCIE11_TXP/SATA1B_TXP G H2
[63] PCIE_TX_CPU_P11
F30 PCIE12_RXN/SATA2_RXN PP_E0/SATAXPCIE0/SATAGP0 H3 PP_E0/SATAXPCIE0/SATAGP0
G 1 P1602
T TPAD14-OP-GP
[63] SATA_RX_CPU_N12
A25 PCIE12_RXP/SATA2_RXP G
PP_E1/SATAXPCIE1/SATAGP1 G4 PP_E1/SATAXPCIE1/SATAGP1
G 1 P1603
T TPAD14-OP-GP D3V_S5_PCH
3
[63] SATA_RX_CPU_P12
B25 PCIE12_TXN/SATA2_TXN G
PP_E2/SATAXPCIE2/SATAGP2
[63] SATA_TX_CPU_N12
[63] SATA_TX_CPU_P12
PCIE12_TXP/SATA2_TXP G H1
2_SSD_PEDET
M [63] Vince,20160922 N1601
R
P PP_E8/SATALED# SB_OC2#
U 8 1
G ATA_LED#
S [64] SB_OC3#
U 7 2
SB_OC0#
U 6 3
SB_OC1#
U 5 4
1. Trace Width: 4 mils min (breakout) 12-15 mils (trace)
N1602
Layout Note: Note: Must maintain low DC resistance routing (<0.1 ohm).
2. Isolation Spacing: At least 12 mils to any adjacent
SKYLAKE-U-GP
SB2_ID
U 1
R
4
SB2_VBUSSENSE
U 2 3 SRN10KJ-6-GP
high speed I/O. D3V_S0
3
SRN0J-6-GP
C C
Vince,20161014 1606
R
+V1.8A Follow SKL PDG design guide ATA_LED#
S 2 1
USB 2.0 Table
10KR2J-3-GP
Pair Device (#543016) Unused SATAGP[2:0]/GPP_E[2:0] pins must be terminated to either 3.3 V rail or GND
R1607 1 2 10KR2J-3-GP PIRQA# using 8.2 KΩ to 10 KΩ on the motherboard. (#543611)
Do not use both pull-up and pull-down. Either pull-up or pull-down is acceptable. The SATALED# signal is open-collector and requires a weak external pull-up (8.2 kΩ to 10 kΩ) to Vcc3_3.
0 USB3.0 port1
1 USB3.0 Port2 (Debug Port/IOBD)
2 USB3.0 Port3 (IOBD)
3 Sensor HUB
4 CAMERA
5 WLAN
6 Touch Panel
7 Card Reader
#545659 (SKL_PCH_U_Y_EDS Rev0.7)
B B
Dell_CY17_CSB_HSIO_Port_Assignment_Rev0.7_2016-10-18_Release (Wistron)_DELL
A A
<Core Design>
Title
Size
1 A
Date:
Document Number
Friday, December 08, 2017

1
C PU_(PCIE/SATA/USB)
tSarlord KBL-R
Sheet 16 f o
Rev
106
A 00
5 4 3 2 1
Main Func = PCH

Remove Power rail +V3.3A_SIP and R1712(DY), 20141118
R1709,R1723,R1703,R1724 merge to RN1704

3D3V_S5
R N1704
1 8 A C_PRESENT 3 D3V_S5 + VCCPDSW_3P3
2 7 P CH_WAKE# R 1711
3 6 P CH_BATLOW# 1 2
4 5 G PD11/LANPHYPC
0R0603-PAD
GPD11 pull high by Intel PDG1.3 request
SRN10KJ-6-GP Layout note: 3 PAD SHARING
D D
R TC_AUX_S5 + V3.3A_SIP
R 1730 #544669 (CRB): 330k.

330KR2J-L1-GP
S M_INTRUDER#
1
1 2
R 1701 PU1K
10KR2J-3-GP C 1 1 OF 20
[ #543016 Rev0.7] SYSTEM POWER MANAGEMENT
2
+ V3.3A_SIP EXT_PWR_GATE#: Due to a bug on A0, a temporary pull-up resistor will be required to overcome the internal 20k AT11
pull-down that is active during the early portion of the power up sequence SKYLAKE_ULT G PP_B12/SLP_S0# AP15 S IO_SLP_S0# [24,40,60,91]
P CH_PLTRST# AN10 G PD4/SLP_S3# BA16 S IO_SLP_S3# [27,40,51,54]
X DP_DBRESET# B5 G PP_B13/PLTRST# G PD5/SLP_S4# AY16 S IO_SLP_S5# S IO_SLP_S4# [40,54]
1 1
R 1731 P M_RSMRST# AY17 S YS_RESET# G PD10/SLP_S5# T P1703 TPAD14-OP-GP
T P1709 Vince,20161031
1 2 E XT_PWR_GATE# TPAD14-OP-GP R SMRST# AN15 S LP_SUS# 1
H _CPUPWRGD A68 S LP_SUS# AW15 S LP_LAN# T P1711 TPAD14-OP-GP
1 1
H _VCCST_PWRGD B65 P ROCPWRGD S LP_LAN# BB17 A UX_EN_WOWL T P1704 TPAD14-OP-GP
#544669 Rev0.52 CRB: T P1705 1
T P1710 TPAD14-OP-GP
20KR2J-L2-GP TPAD14-OP-GP V CCST_PWRGD G PD9/SLP_WLAN# AN16 S IO_SLP_A# 1
No PL resistor on THERMTRIP#. G PD6/SLP_A# T P1706 TPAD14-OP-GP
S YS_PWROK B6
[24] S YS_PWROK
H _CPUPWRGD 1 R 1706 2 0R0402-PAD P M_PCH_PWROK BA20 S YS_PWROK BA15
[24,26] R ESET_OUT# S IO_PWRBTN# [24]
P M_RSMRST# 1 R 1704 2 0R0402-PAD P CH_DPWROK BB20 P CH_PWROK G PD3/PWRBTN# AY15 A C_PRESENT
D SW_PWROK G PD1/ACPRESENT
E D1701
AZ5725-01FDR7G-GP
AU13 P CH_BATLOW#
1
M E_SUS_PWR_ACK_R AR13 G PD0/BATLOW#
BATLOW#:
S USACK#_R AP11 G PP_A13/SUSWARN#/SUSPWRDNACK
1
G PP_A15/SUSACK# Pull-up required even if not implemented.
AU11 P ME# 1
DY P CH_WAKE# BB15 G PP_A11/PME# AP16 S M_INTRUDER#
DY T P1707 TPAD14-OP-GP
R 1714 R 1707 1 2 10KR2J-3-GP G PD2/LAN_WAKE# AM15 W AKE# I NTRUDER#
+ VCCPDSW_3P3 AW17 G PD2/LAN_WAKE# AM10 E XT_PWR_GATE#
2
10KR2J-3-GP G PD11/LANPHYPC
AT15 G PD11/LANPHYPC G PP_B11/EXT_PWR_GATE# A C_PRESENT
2
AM11 V RALERT# 1
G PD7/USB2_WAKEOUT# G PP_B2/VRALERT# T P1708 TPAD14-OP-GP
RN1703
1 4 PM_RSMRST# (PDG#543016) E C1707
SKYLAKE-U-GP
1
2 3 PM_PCH_PWROK WAKE#: Ensure that WAKE# signal Trise (Maximum) is <100 ns. DY
S CD1U16V2KX-3GP
EMI DVT1 0210
SRN10KJ-5-GP
S YS_PWROK
2
R1717 2 DY 1
100KR2J-1-GP 1 R 1732 2 G PD2/LAN_WAKE#
[24] L ANWAKE#
0R2J-2-GP
DY
C
Vince,20161107 Vince,20161121 C
+V1.8A
R 1739 1 2 10KR2J-3-GP M E_SUS_PWR_ACK_R

DY
Vince,20161017
[24,40] R UNPWROK
AOZ Power switch, P/N: 074.01334.0093 H _VCCST_PWRGD 1 R 1713 2 P CH_PLTRST#

[63,66,91]P LT_RST#
Low Rds(on)= 5m Ohm
E D1708
AZ5725-01FDR7G-GP
1
1
0R0402-PAD
Turn on rise time = 10us
SCD01U50V2KX-1GP
C 1711
1
1
R 1715 C 1701
100KR2J-1-GP DY DY SC220P50V2KX-3GP
Vince,20161121 DY
2
2
3 D3V_S5
+VCCMPHYGTAON_1P0
2
1 2 R1722 & EC1708 modify to 100k and 0.01uF at DVT1
R 1716
SKL: 1.0V
E D1709
AZ5725-01FDR7G-GP
1
E C1713 100KR2F-L1-GP
1
SC2D2U10V2KX-GP
+VCCMPHYGTAON_1P0(ICCMAX.=2.12A)
DY DY R 1719
47KR2F-GP #543016 Rev0.7
2
EMI DVT1 0210 1. VCCST_PWRGD is only 1.0 V tolerant.
1 D0V_S5 + VCCMPHYGTAON_1P0_LS_SIP 2. VCCST_PWRGD must go low during Sx pwr states, regardless of the voltage level of VCCST
2
EMI DVT1 0210
R 1724
1 2 RF request 2016/01/12 modify
E C1710
1
0R6J-L-GP
SC2D2U10V2KX-GP
DY C 1704
1
SC10U6D3V3MX-GP
2
X DP_DBRESET# D 1701
B S YS_PWROK RB751V-40H-GP B
P LT_RST#
R ESET_OUT# A K
3 V_5V_POK A COK_IN_M [43,44]
RF request 2016/01/12 modify 3 D3V_AUX_S5
Q 1702
E D1702
E D1703
E D1704
E D1705
1
1
AZ5725-01FDR7G-GP
AZ5725-01FDR7G-GP
AZ5725-01FDR7G-GP
AZ5725-01FDR7G-GP
1 4 3 A C_PRESENT
DS3 BOM Option DY DY DY
ote:ZZ.27002.F7C01
E C1706 5 2 P M_RSMRST#_R
1 R 1720 2 P M_RSMRST#
S C1KP50V2KX-1GP
E MI DVT1 0210 R 1737

Vince,20161017
2
1 2 P M_RSMRST#_M 6 1 0R0402-PAD
2
N
ME_SUS_PWR_ACK_R 1 R 1708 2 S USACK#_R P CH_DPWROK R 17181 2 0R2J-2-GP 100KR2J-1-GP 2N7002KDW-1-GP
DY 3 V_5V_POK [40,45,52,54]
Vince,20170307
0R0402-PAD Change dummy property from DS3 to DY
1
E D1711
AZ5725-01FDR7G-GP
Reserve by NON DS3 function 20150413

DY
2
3D3V_AUX_S5 R 1727
100KR2J-1-GP
1 2
Change location to net PCH_DPWROK
2
R1726
10KR2J-3-GP
Q 1701
1KR2J-1-GP
1
R 1702
4 3 P M_RSMRST# 1 2
S2 D2 P CH_RSMRST# [24]
3V_5V_POK#5 2 3 V_5V_POK_C 1 R 1728 2
G2 G1 3 V_5V_POK [40,45,52,54]
6 1 0R0402-PAD E C1712
1
1
SCD47U10V2KX-GP
D1
C 1710
S1
DY
SCD1U16V2KX-3GP
A DY A
PJT138KA-GP
2
Vince,20161031
<Core Design>
Dummy C1710 by it's useless
EC1711 modify to 100k and 0.01uF at DVT1 20150203
Title
C PU_(POWER MANAGEMENT)
A 2
5 4 3 2 1
5 4 3 2 1
SSID = PCH PCH strap pin: PCH Prim

PCH strap pin: PCH Prim
eSPI or LPC Sampled at rising edge of RSMRST# 3 D3V_S5_PCH
BOOT HALT 3 D3V_S5_PCH
This signal has a weak internal pull-down. 3 D3V_S5_PCH
SML0ALERT# /
0 = ENABLED
1
GPP_C5 0 = LPC Is selected for EC. SPI0_MOSI
1
1 = eSPI Is selected for EC. R 1822 1 = DISABLED
1KR2J-1-GP WEAK INTERNAL PU DY R 1824 R N1807
This signal has a weak internal pull-down. 1KR2J-1-GP S ML1_SMBDATA 8 1
This signal has a weak internal pull-up. S ML1_SMBCLK 7 2
S ML0_SMBDATA
2
6 3
S ML0_ALERT# Vince,20161013 S ML0_SMBCLK
2
5 4
S PI_SI_CPU
1
SRN2K2J-4-GP
1
DY R 1823
R 1825 D VT1 0210, Reserve by Intel MOW
1KR2J-1-GP DY
1KR2J-1-GP
D S ML1ALERT# 2 1 D
2
150KR2J-GP R 1837
2
R1835 and R1834 merge to RN1802
2015/10/06 modify R 1836
S MB_ALERT# 2 1
3D3V_S5_PCH 2K2R2J-2-GP
R N1811
R N1802
1 4 S PI_HOLD_ROM M EM_SMBCLK 4 1
2 3 S PI_WP_ROM M EM_SMBDATA 3 2
SRN1KJ-7-GP
E SPI_IO[3..0] SRN2K2J-1-GP
[24,68] E SPI_IO[3..0]
R N1806
E SPI_IO0 8 1 P CH_ESPI_IO0
R1806,R1807,R1808,R1809 merge to RN1803 E SPI_IO1 7 2 P CH_ESPI_IO1
E SPI_IO2 6 3 P CH_ESPI_IO2
2015/10/06 modify SPI_IO3 CH_ESPI_IO3
E 5 4 P
Vince,20161013 R N1803 SRN15J-GP
+ V1.8A
[25,91] S PI_CLK_ROM 1 8 C
PU1E
5 OF 20 Vince,20170106
[25,91] S PI_SO_ROM 2 7
3 6 SPI - FLASH
[25,91] S PI_SI_ROM SMBUS, SMLINK
R 1820 4 5 S PI_CLK_CPU AV2 SKYLAKE_ULT R7 M EM_SMBCLK
S IO_RCIN# [25] S PI_WP_ROM S PI_SO_CPU AW3 S PI0_CLK G PP_C0/SMBCLK R8 M EM_SMBDATA
1 2
10KR2J-3-GP SRN10J-1-GP S PI_SI_CPU AV3 S PI0_MISO G PP_C1/SMBDATA R10 S MB_ALERT#
S PI_WP_CPU AW2 S PI0_MOSI Strap G PP_C2/SMBALERT#
R 1821 10R2F-L-GP 1 2 R 1811 S PI_HOLD_CPU AU4 S PI0_IO2 R9 S ML0_SMBCLK
E SPI_ALERT# [25] S PI_HOLD_ROM S PI0_IO3 G PP_C3/SML0CLK
1 2 [25] S PI_CS_ROM_N0 0R0402-PAD 1 2 R 1812 S PI_CS_CPU_N0 AU3 W2 S ML0_SMBDATA
10KR2J-3-GP AU2 S PI0_CS0# G PP_C4/SML0DATA W1 S ML0_ALERT# 3 D3V_S0
0R2J-2-GP 1 P CH_SPI_CS2# AU1 S PI0_CS1# Strap G PP_C5/SML0ALERT# + V1.8A
2 R 1826
SERIRQ PH:
[91] S PI_CS2#_R TPM S PI0_CS2# W3 S ML1_SMBCLK R 1818
Vince,20161017
G PP_C6/SML1CLK V3 S ML1_SMBDATA S ML1_SMBCLK [24,26,66] 8K2R2F-1-GP R N1810
PDG: 8.2k SPI - TOUCH G PP_C7/SML1DATA S ML1_SMBDATA [24,26,66]
R 1808 AM7 S ML1ALERT# C LKRUN# 1 DY 2 4 1
CRB: 10k Vince DVT2,20170511 2 1 T PM_SPI_IRQ# M2 G PP_B23/SML1ALERT#/PCHHOT# 3 2
3 D3V_S0
[91] S PI_IRQ#_TPM2 DY 0R2J-2-GP M3 G PP_D1/SPI1_CLK
[70] F FS_INT1 J4 G PP_D2/SPI1_MISO
[60] H DD_EN_PCH TPAD14-OP-GP T P1804 C PU_D4_TP V1 G PP_D3/SPI1_MOSI SRN10KJ-5-GP
1
TPAD14-OP-GP T P1805 1 C PU_D5_TP V2 G PP_D21/SPI1_IO2 Q 1801
ote:ZZ.27002.F7C01
TPAD14-OP-GP T P1806 H DD_DET# M1 G PP_D22/SPI1_IO3 AY13 P CH_ESPI_IO0 M EM_SMBDATA
1 LPC 6 1
N
G PP_D0/SPI1_CS# G PP_A1/LAD0/ESPI_IO0 BA13 P CH_ESPI_IO1 P CH_SMBDATA [12,13]
C C
G PP_A2/LAD1/ESPI_IO1 BB13 P CH_ESPI_IO2 5 2
C LINK G PP_A3/LAD2/ESPI_IO2 AY12 P CH_ESPI_IO3 Vince,20170106
G3 G PP_A4/LAD3/ESPI_IO3 BA12 4 3
Vince,20161017 G2 C L_CLK G PP_A5/LFRAME#/ESPI_CS# BA11 E SPI_CS# [24,68]
G1 C L_DATA G PP_A14/SUS_STAT#/ESPI_RESET# 2N7002KDW-1-GP
C L_RST# E SPI_RESET# [24,68]
AW9 P CH_ESPI_CLK
S IO_RCIN# AW13 G PP_A9/CLKOUT_LPC0/ESPI_CLK AY9 G PP_A10/CLKOUT_LPC1 1 T P1808 TPAD14-OP-GP
RCIN#: G PP_A0/RCIN# G PP_A10/CLKOUT_LPC1 P CH_SMBCLK [12,13]
Frequency to Avoid: 33 MHz AW11 C LKRUN#
E SPI_ALERT# AY11 G PP_A8/CLKRUN# C LKRUN# [24]
[24,68] E SPI_ALERT# G PP_A6/SERIRQ Vince,20161027 M EM_SMBCLK
Vince,20161017 SKYLAKE-U-GP
Vince,20161013
R 1806
P CH_ESPI_CLK 1 2
E SPI_CLK [24,68]
15R2F-2-GP
SC10P50V2JN-4GP
1
EC1804
DY
2
Vince,20161017
Vince,20170110
Vince,20170120 common part request Metal cover XTAL
B B
Vince,20170117 R TC_X1
1 2 R TC_X2
R 1804 C 1801
3D3V_S0 R 1815 10MR2J-L-GP
X TAL24_IN 2 1X TAL24_IN_R 2 1
U22
R1827 1 2 C LK_PCIE_SD_REQ#
DY 10KR2J-3-GP 1
X 1802
2 0R2J-2-GP SC15P50V2JN-2-GP
1
R N1812
1 4 C LK_PCIE_PEG_REQ# XTAL-32D768KHZ-91-GP X 1801
C LK_PCIE_NVME_REQ# U22
1
2 3 U22 XTAL-24MHZ-87-GP
1
C 1804 C 1803 R 1802
SRN10KJ-5-GP 1MR2J-1-GP
SC9P50V2DN-GP SC9P50V2DN-GP U22
4
2
C PU1J 1 0 OF 20
R 1805 C 1802
1
R N1813
4 C LK_PCIE_TBT_REQ# Vince,20170328 X TAL24_OUT 2 1X TAL24_OUT_R 2 1
2 3 C LK_PCIE_LAN_REQ#
CLOCK SIGNALS U22
DY D42 0R2J-2-GP
[66] C LK_PCIE_VGA#
SRN10KJ-5-GP C42 C LKOUT_PCIE_N0 SKYLAKE_ULT SC15P50V2JN-2-GP
[66] C LK_PCIE_VGA
R1828 1 2 C LK_PCIE_WLAN_REQ# AR10 C LKOUT_PCIE_P0
10KR2J-3-GP
[66] C LK_PCIE_PEG_REQ# G PP_B5/SRCCLKREQ0# Vince,20161223
U22
B42
WLAN [66] P EG_CLK1_CPU#
[66] P EG_CLK1_CPU
A42 C LKOUT_PCIE_N1 F43 P CIE_CLK_XDP_N 1 T P1802 TPAD14-OP-GP
AT7 C LKOUT_PCIE_P1 C LKOUT_ITPXDP# E43 P CIE_CLK_XDP_P 1
[66] C LK_PCIE_WLAN_REQ# G PP_B6/SRCCLKREQ1# C LKOUT_ITPXDP_P
Vince,20170203 S USCLK
D41 BA17 S USCLK R 18072 1 R TC_AUX_S5
Vince,20161026 C41 C LKOUT_PCIE_N2 G PD8/SUSCLK DY S US_CLK [24]
2
0R2J-2-GP
C LK_PCIE_LAN_REQ# AT8 C LKOUT_PCIE_P2 E37 X TAL24_IN + V1.00A_SIP C1803
G PP_B7/SRCCLKREQ2# X TAL24_IN E35 X TAL24_OUT + V1.05S_AXCK_LCPLL
DY E
S C4D7P50V2BN-GP
X TAL24_OUT
1
D40
C40 C LKOUT_PCIE_N3 X CLK_BIASREF
1
2
E42 1 R 1803 2
C LK_PCIE_SD_REQ# AT10 C LKOUT_PCIE_P3 X CLK_BIASREF 2K7R2F-GP R N1801
G PP_B8/SRCCLKREQ3# AM18 R TC_X1
Vince,20161026 B40 R TCX1 AM20 R TC_X2 I ntel recommend: 2.71k ohm 1%
SRN20KJ-1-GP
[63] M SATA_CLK_CPU#
A40 C LKOUT_PCIE_N4 R TCX2
[63] M SATA_CLK_CPU C LK_PCIE_NVME_REQ# AU8 C LKOUT_PCIE_P4 AN18 S RTC_RST#
[63] C LK_PCIE_NVME_REQ# G PP_B9/SRCCLKREQ4# S RTCRST#
4
3
AM16 R TC_RST#
A E40 R TCRST# A
SSD E38 C LKOUT_PCIE_N5
C LK_PCIE_TBT_REQ# AU7 C LKOUT_PCIE_P5 S RTC_RST#
G PP_B10/SRCCLKREQ5# R TC_RST#
[25] R TC_RST#
SC1U10V2KX-1GP
2
1
<Core Design>
C 1806
G 1801
1
SKYLAKE-U-GP C 1805
1
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
GAP-OPEN
SC1U10V2KX-1GP
EC1806
EC1807
DY DY
2
Vince,20161027 2 1F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
2
( #514849)
itle
T Title
C PU_(LPC/SPI/SMBUS/CL/CLK)
WWW.AliSaler.Com 5 4 3
Layout: Place at the open door area.
2
Size
A 2
Document Number

S tarlord KBL-R
1
Sheet 18 o f
Rev
A 00
106
5 4 3 2 1
SSID = PCH Strap pin:

Port B /
Port C Detected Sampled at rising edge of PCH_PWROK
0 = Port B is not detected.

DDPB_CTRLDATA * 1 = Port B is detected.
0 = Port C is not detected.

DDPC_CTRLDATA * 1 = Port C is detected.
D D
C PU1G 7 OF 20
These two signals have weak internal pull-down.
AUDIO
SKYLAKE_ULT
H DA_SYNC BA22
H DA_BITCLK HDA_SYNC/I2S0_SFRM
AY22
H DA_SDOUT HDA_BLK/I2S0_SCLK
BB22 SDIO/SDXC
HDA_SDO/I2S0_TXD
BA21
[27] H DA_SDIN0 HDA_SDI0/I2S0_RXD
Vince,20161107 3 D3V_S5 H DA_RST#
AY21
AW22
HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD
AB11
AB13 G C6_THM_DIS#
HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0 G C6_THM_DIS# [24]
J5 AB12
GPP_D23/I2S_MCLK GPP_G2/SD_DATA1
Vince,20161102 AY20
I2S1_SFRM GPP_G3/SD_DATA2
W12
1
AW20 W11
I2S1_TXD GPP_G4/SD_DATA3
fTPM: SW TPM R 1913
GPP_G5/SD_CD#
W10
P ROJECT_ID1
TPM:HW TPM
fTPM 10KR2J-3-GP
P ROJECT_ID0
AK7
AK6
GPP_F1/I2S2_SFRM GPP_G6/SD_CLK
W8
W7
K B_LED_BL_DET [65]
P ROJECT_ID2 GPP_F0/I2S2_SCLK GPP_G7/SD_WP
AK9
GPP_F2/I2S2_TXD Vince,20161026
2
P ROJECT_ID3 AK10 BA9

T PM_ID GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 C PU_A16_TP 1
BB9 T P1902
GPP_A16/SD_1P8_SEL TPAD14-OP-GP
1 D MIC_PCH_CLK H5 AB7 S D_RCOMP 1 R 1901 2
T P1906 GPP_D19/DMIC_CLK0 SD_RCOMP
1
TPAD14-OP-GP D7
R 1912 GPP_D20/DMIC_DATA0
T PM_ID 200R2F-L-GP
TPM 10KR2J-3-GP D8
C8
GPP_D17/DMIC_CLK1 GPP_F23
AF13
[24,66] D GPU_PW ROK GPP_D18/DMIC_DATA1
2
S PKR AW5
C [27] GPP_B14/SPKR C
PCH strap pin: SKYLAKE-U-GP

Vince,20170106
PCH strap pin: Vince,20170721
Flash Descriptor Security Overide/ NO REBOOT
3 D3V_S0 + V1.8A + V1.8A + V1.8A + V1.8A
Intel ME Debug Mode
1KR2J-1-GP
Low = Default * * Low = Enable (Default) R 2006
2
HDA_SDOUT HDA_SPKR 1 2 S PKR
High = Enable High = Disable DY R 1915 R 1916 R 1918 R 1920
The internal pull-down is disabled after RORL
10KR2J-3-GP RORL
10KR2J-3-GP DY 10KR2J-3-GP DY 10KR2J-3-GP
PLTRST# deasserts The internal pull-down is disabled after
PLTRST# deasserts
1
P ROJECT_ID0 P ROJECT_ID1 P ROJECT_ID2 P ROJECT_ID3
2
R 1914 R 1917 R 1919 R 1921
DY 10KR2J-3-GP DY 10KR2J-3-GP DY 10KR2J-3-GP DY 10KR2J-3-GP
1 R 1908 2 H DA_SYNC
[27] H DA_CODEC_SYNC
1
0R0402-PAD
E C1901
1 2 H DA_CODEC_BITCLK
B B
DY Vince,20170106
SC10P50V2JN-4GP
SRN33J-5-GP-U
2 3 H DA_BITCLK
H DA_RST# [27] H DA_CODEC_BITCLK 1 4 H DA_SDOUT
[27] H DA_CODEC_SDOUT
R N1902
1
DY E C1902 M E_FW P_EC R 1909 1 2 1KR2J-1-GP

[24]
SCD1U16V2KX-3GP
2
R1907,R1912 merge to RN1902

2015/10/06 modify
A <Core Design> A
Wistron Corporation
Title
CPU_(AUDIO/SDIO/SDXC)
A3
S tarlord KBL-R A00
5 4 3 2 1
5 4 3 2 1
SSID = PCH 3 D3V_S0
R N2007
SRN1KJ-7-GP
I SH_I2C0_SCL 1 4
E C2002 2 1 I SH_I2C0_SDA 2 3
D GPU_HOLD_RST# [66]
SC1KP50V2KX-1GP
R N2008
PU1F
R N2009 C 6 OF 20 I 2C1_SCL 1 4
1 4 D GPU_HOLD_RST# I 2C1_SDA 2
DY 3
2 3 D GPU_PWR_EN LPSS ISH
OPS SKYLAKE_ULT
SRN10KJ-5-GP G PU_EVENT_MCP# AN8 P2 3 D_CAM_DET# SRN2K2J-1-GP
[66] G PU_EVENT# R 2003 1GC6_202 0R2J-2-GP 1 T P2006 TPAD14-OP-GP
R 2004 1GC6_202 0R2J-2-GP G C6_FB_EN_MCP AP7 G PP_B15/GSPI0_CS# G PP_D9/ISH_SPI_CS# P3 D GPU_HOLD_RST#
[66] G C6_FB_EN V RAM_ID1 AP8 G PP_B16/GSPI0_CLK G PP_D10/ISH_SPI_CLK P4 (PDG#543016) Ensure that all I2C interface on-board terminations are pulled up
N RB_BIT AR7 G PP_B17/GSPI0_MISO G PP_D11/ISH_SPI_MISO P1 R TC_DET# I R_CAM_DET# [55]
to the same voltage rail as the device/end point.
G PP_B18/GSPI0_MOSI G PP_D12/ISH_SPI_MOSI R TC_DET# [25]
3D3V_S0 AM5
Strap M4 I SH_I2C0_SDA R 2021 1 2 0R2J-2-GP
[55] D BC_PANEL_EN
AN7 G PP_B19/GSPI1_CS# G PP_D5/ISH_I2C0_SDA N3 I SH_I2C0_SCL R 2020 1 ISH 2 0R2J-2-GP S ENSOR_I2C_SDA [55,70]
D Vince,20161012 AP5 G PP_B20/GSPI1_CLK G PP_D6/ISH_I2C0_SCL ISH S ENSOR_I2C_SCL [55,70] D
S D_READ_MODE AN5 G PP_B21/GSPI1_MISO N1 I 2C1_SDA

G PP_B22/GSPI1_MOSI G PP_D7/ISH_I2C1_SDA N2 I 2C1_SCL
DEBUG2 1.8V Only G PP_D8/ISH_I2C1_SCL Vince,20161102
51KR2J-1-GP 1 R 2048 U ART_2_CTXD_DRXD AB1
51KR2J-1-GP 1 2 R 2049 U ART_2_CRXD_DTXD [29] S PK_ID AB2 G PP_C8/UART0_RXD AD11 M EM_CHB_EN 1 T P2007 TPAD14-OP-GP
[66] B LUETOOTH_EN
W4 G PP_C9/UART0_TXD G PP_F10/I2C5_SDA/ISH_I2C2_SDA AD12
DEBUG B OARD_ID2 AB3 G PP_C10/UART0_RTS# G PP_F11/I2C5_SCL/ISH_I2C2_SCL Vince,20161026
C hange to Dummy 20150402 Vince,20161012 G PP_C11/UART0_CTS#
10KR2J-3-GP 1 2 R 2042 B LUETOOTH_EN AD1 U1
10KR2J-3-GP
DY D BC_PANEL_EN
[68] U ART_2_CRXD_DTXD
AD2 G PP_C20/UART2_RXD G PP_D13/ISH_UART0_RXD/SML0BDATA U2 V RAM_ID2 D GPU_PWR_EN [66]
1 2 R 2043 1
10KR2J-3-GP 1 2 R 2044 F FS_INT2 [68] U ART_2_CTXD_DRXD AD3 G PP_C21/UART2_TXD G PP_D14/ISH_UART0_TXD/SML0BCLK U3 U ART0_RTS# 1
10KR2J-3-GP K B_DET# [24] S IO_EXT_WAKE# AD4 G PP_C22/UART2_RTS# G PP_D15/ISH_UART0_RTS# U4 U ART0_CTS# T P2013 TPAD14-OP-GP
1 2 R 2045 1
10KR2J-3-GP 1 2 R 2046 I R_CAM_DET# [65] K B_DET# G PP_C23/UART2_CTS# G PP_D16/ISH_UART0_CTS#/SML0BALERT#
10KR2J-3-GP 1 2 R 2047 S PK_ID AC1 B OARD_ID1
U7 G PP_C12/UART1_RXD/ISH_UART1_RXD AC2
[65] I 2C0_SDA_TCH_PAD PP_C16/I2C0_SDA G PP_C13/UART1_TXD/ISH_UART1_TXD F FS_INT2 [70]
U6 G AC3 U ART1_RTS# 1
[65] I 2C0_SCL_TCH_PAD G PP_C17/I2C0_SCL G PP_C14/UART1_RTS#/ISH_UART1_RTS# T P2016 TPAD14-OP-GP
AB4 U ART1_CTS# 1
I 2C0_SDA_TCH_PNL U8 G PP_C15/UART1_CTS#/ISH_UART1_CTS# T P2017 TPAD14-OP-GP
T P2027 TPAD14-OP-GP 1
PTP T P2028 TPAD14-OP-GP 1 I 2C0_SCL_TCH_PNL U9 G
G
PP_C18/I2C1_SDA
PP_C19/I2C1_SCL G PP_A18/ISH_GP0
AY8 I SH_KB_DISABLE
BA8 G SEN_INT1_ISH 2023 1 2 0R2J-2-GP
PCH strap pin: PCH Prim T P2020 TPAD14-OP-GP 1 M EM_CONFIG0 AH9
PP_F4/I2C2_SDA
G PP_A19/ISH_GP1 BB7 G SEN_INT2_ISH
R
R 2024 1 2 0R2J-2-GP G SEN_INT1 [55]
SEN_INT2 [55]
AH10 G G PP_A20/ISH_GP2 BA7 G SEN2_INT1_ISH R 2025 1 2 0R2J-2-GP G
+ V1.8A_SIP G PP_F5/I2C2_SCL G PP_A21/ISH_GP3 AY7 G SEN2_INT2_ISH G SEN2_INT1_C [70]
No Reboot Sampled at rising edge of PCH_PWROK R 2026 1 2 0R2J-2-GP
SEN2_INT2_C [70] (PDG#543016) If the UART/GPIO functionality is also not used,
3 D3V_S5_PCH AH11 G PP_A22/ISH_GP4 AW7 G YRO_INT_ISH 2027 1 2 0R2J-2-GP G
PP_F6/I2C3_SDA G PP_A23/ISH_GP5
R DY G YRO_INT_C [70] the signals can be left as no-connect.
AH12 G AP13 G YRO_DRDY_ISH 2028 1 2 0R2J-2-GP
0 = Disable “No Reboot” mode. G PP_F7/I2C3_SCL G PP_A12/BM_BUSY#/ISH_GP6
R DY G YRO_DRDY [55]
GSPI0_MOSI /
1
1 = Enable “No Reboot” mode (PCH will disable the TCO AF11
GPP_B18 AF12 G PP_F8/I2C4_SDA
Timer system reboot feature). This function is useful DY R 2007 PP_F9/I2C4_SCL R 2031 R 2032
G G SEN_INT1_ISH1 2 G SEN_INT2_ISH 1 2
when running ITP/XDP. 1KR2J-1-GP DY DY
SKYLAKE-U-GP
100KR2J-1-GP 100KR2J-1-GP Vince,20170111
Vince,20161026
2
The signal has a weak internal pull-down.

N RB_BIT
3 D3V_S5
1
R 2035 R 2033
R 2019 G SEN2_INT1_ISH 1 2 G SEN2_INT2_ISH 1 2
DY DY DY
1KR2J-1-GP
1
100KR2J-1-GP 100KR2J-1-GP
Vince,20161014 R 2001
2
10KR2J-3-GP Vth(max)=1.1V
C C
R 2034 R 2036 Q 2001
2
G YRO_DRDY_ISH 1 2 G YRO_INT_ISH 1 2
Vince,20161123 DY DY I SH_KB_DISABLE_R 6 D1 S1 1
#570213 Intel CRB 5 G2 1G 2 I SH_KB_DISABLE
4 S2 D2 3
3 D3V_S0 N B_MODE# [24]
3D3V_S5_PCH PJT138KA-GP
3 D3V_S0 3 D3V_S0
3 D3V_S0
1
R 2055
DY
1
150KR2J-GP GPP_C11
BIOS strap pin: D3V_S5
1
R 2010 R 2005 3
2029 BBY 10KR2J-3-GP OPS 10KR2J-3-GP
DY R10KR2J-3-GP
2
S D_READ_MODE BIOS UMA/DIS Strap pin BOARD_ID2

R2040 1 2 10KR2J-3-GP R TC_DET#
2
R2041 1 2 10KR2J-3-GP S IO_EXT_WAKE#
2
B OARD_ID1 B OARD_ID2
1
2
UMA 0
R 2056 V RAM_ID1 2050
DY 20KR2J-L2-GP
R
10KR2J-3-GP
1
DIS 1
1
R 2009 R 2008
2
1
R 2030 10KR2J-3-GP 10KR2J-3-GP
10KR2J-3-GP ROR UMA
DY N B_MODE#
2
2
B B
A A
<Core Design>
Title
C PU_(LPSS/ISH)
Size
A 2
Document Number

S tarlord KBL-R
1
Sheet 20 o f
Rev
A 00
106
5 4 3 2 1
Main Func = PCH
Vince,20161013
D D
+ V1.00A_SIP PU1O
C 1 5 OF 20
+ V1.8A_SIP
CPU POWER 4 OF 4
AB19
AB20 V CCPRIM_1P0 AK15 + V3.3A_SIP
+ VCCPRIM_CORE P18 V CCPRIM_1P0 SKYLAKE_ULT V CCPGPPA AG15 + VCCPRTC_3P3
V CCPRIM_1P0 V CCPGPPB Y16
Layout Note:
AF18 V CCPGPPC Y15
2.57A 0.1uF:
SC1U10V2KX-1GP
AF19 V CCPRIM_CORE V CCPGPPD T16
C
2118
2117
C2118 near AK19
SCD1U16V2KX-3DLGP
V CCPRIM_CORE V CCPGPPE
1
V20 AF16
V CCPRIM_CORE 1.8V Only V CCPGPPF + V1.8A_SIP
V21 AD15
+ V3.3A_SIP
1uF:
+ VCCDSW_1P0 V CCPRIM_CORE V CCPGPPG
C2117 near Ak19
2
C 2120 AL1 V19
+ V1.00A_SIP D CPDSW_1P0 V CCPRIM_3P3_V19
1
E C2101
S
DY
C1U10V2KX-1GP
K17 T1
L1 V CCMPHYAON_1P0 V CCPRIM_1P0_T1 + V1.00A_SIP
S
CD1U25V2KX-GP
V CCMPHYAON_1P0
2
+ VCCMPHYGTAON_1P0_LS_SIP AA1
N15 V CCATS_1P8 + V1.8A_SIP
N16 V CCMPHYGT_1P0_N15 AK17
N17 V CCMPHYGT_1P0_N16 V CCRTCPRIM_3P3 + V3.3A_SIP + VCCPRTC_3P3
P15 V CCMPHYGT_1P0_N17 AK19
P16 V CCMPHYGT_1P0_P15 V CCRTC_AK19 BB14
+ VCCAMPHYPLL_1P0 V CCMPHYGT_1P0_P16 V CCRTC_BB14
K15 BB10V CCRTCEXT C 21121 2
L15 V CCAMPHYPLL_1P0 D CPRTC SCD1U16V2KX-3DLGP
+ VCCAPLL_1P0 V CCAMPHYPLL_1P0 A14
V15 V CCCLK1 + V1.00A_SIP
+ V1.00A_SIP V CCAPLL_1P0 K19
AB17 V CCCLK2 + VCCCLK2
Y18 V CCPRIM_1P0_AB17 L21
1 D5V_S0 + VCCPDSW_3P3 V CCPRIM_1P0_Y18 V CCCLK3 + V1.00A_SIP
AD17 N20
AD18 V CCDSW_3P3_AD17 V CCCLK4 + VCCCLK4
R 2102 1 DY 2
+ V3.3A_SIP 0R2J-2-GP AJ17 V CCDSW_3P3_AD18 L19 R TC_AUX_S5 + VCCPRTC_3P3
+ VCCPAZIO V CCDSW_3P3_AJ17 V CCCLK5 + VCCCLK5 R 2106
1 R 2101 2 AJ19 A10 1 2
V CCHDA V CCCLK6 + V1.00A_SIP
0R0402-PAD AJ16 AN11V 0.85A_VID0 1 T P2101 TPAD14-OP-GP 0R0603-PAD
+ V3.3A_SIP V CCSPI G PP_B0/CORE_VID0 AN13V 0.85A_VID1 1 T P2102 TPAD14-OP-GP
C AF20 G PP_B1/CORE_VID1 + VCCMPHYGTAON_1P0_LS_SIP + VCCAMPHYPLL_1P0 C
+ VCCMPHYGTAON_1P0_LS_SIP AF21 V CCSRAM_1P0 R 2107
T19 V CCSRAM_1P0 1 2
T20 V CCSRAM_1P0
+ V3.3A_SIP V CCSRAM_1P0 0R0603-PAD
AJ21
+ V1.00A_SIP V CCPRIM_3P3_AJ21
AK20 + V1.00A_SIP + VCCAPLL_1P0
V CCPRIM_1P0_AK20 R 2108
N18 1 2
+ VCCMPHYGTAON_1P0_LS_SIP V CCAPLLEBB
0R0603-PAD
SKYLAKE-U-GP
+ V1.00A_SIP + VCCCLK2
R 2109
1 2
0R0603-PAD
R 2110
1 2
0R0603-PAD
R 2111
1 2
0R0603-PAD
+ V3.3A_SIP + V1.8A_SIP + VCCPRIM_CORE + VCCDSW_1P0 + V1.00A_SIP

Layout Note:
Layout Note:
1uF:
1uF: C2101 near AB19
C2105
C2106
C2107
C2109
C2110
C2111
C2108
C2102
C2103
C2101
C2104
C2121
B B
C2105 near V19 C2104 near K17
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SCD1U16V2KX-3DLGP
SCD1U16V2KX-3DLGP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
1
1
C2106 near AK17 DY C2116 near A10
C2107 near AG15 C2121 near AL1
2
2
C2109 near Y16
C2110 near T16
C2111 near AJ19
+ VCCAMPHYPLL_1P0 + VCCAPLL_1P0 + V1.00A_SIP + VCCCLK2 + VCCCLK4 + VCCCLK5

Layout Note:
Layout Note: Layout Note:
1uF:
22uF: 22uF: C2116 near A10
C2113 near K15 C2113 near K15 22uF:
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC1U10V2KX-1GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
C2113
C2114
C2116
C2115
C2119
C2122
1
C2115 near K19

DY DY DY DY DY C2119 near N20
C2122 near L19
2
A A
<Core Design>
Title
C PU_(POWER1)
A 2
5 4 3 2 1
5 4 3 2 1
Main Func = PCH
D D
CPU1T 20 OF 20
SKYLAKE_ULT
SPARE
AW69 F6
AW68 RSVD_AW69 RSVD_F6 E3 XTAL24_IN_U42
AU56 RSVD_AW68 RSVD_E3 C11
AW48 RSVD_AU56 RSVD_C11 B11
XTAL24_OUT_U42 C7 RSVD_AW48 RSVD_B11 A11
U12 RSVD_C7 RSVD_A11 D12
U11 RSVD_U12 RSVD_D12 C12
H11 RSVD_U11 RSVD_C12 F52
RSVD_H11 RSVD_F52
SKYLAKE-U-GP
Vince,20170110
Metal cover XTAL
C C
For U42
R2202 C2201
XTAL24_IN_U42 2 1XTAL24_IN_U42_R 2 1
U42
U42
0R2J-2-GP SC15P50V2JN-2-GP
1
X2201
1
R2201
U42 XTAL-24MHZ-87-GP
1MR2J-1-GP
U42
4
2
R2203 C2202
XTAL24_OUT_U42 2 1XTAL24_OUT_U42_R 2U42 1
U42
B B
0R2J-2-GP SC15P50V2JN-2-GP
Vince,20161223
<Core Design>
A
Title
CPU_(RSVD)
A4
Starlord KBL-R A 00
WWW.AliSaler.Com
5 4 3
2
Sheet 22
1
of 106
5 4 3 2 1
Main Func = PCH
C PU1Q 17 OF 20
GND 2 OF 3 C PU1R 18 OF 20
C PU1P 16 OF 20
AT63 SKYLAKE_ULT BA49 GND 3 OF 3
GND 1 OF 3 VSS VSS
D AT68 BA53 F8 L18 D
VSS VSS VSS VSS
AT71 BA57 G10 L2
1 A 5_TP A5 SKYLAKE_ULT VSS VSS VSS SKYLAKE_ULT VSS
AL65 AU10 BA6 G22 L20
TPAD14-OP-GP T P2309 1 A 67_TP A67 VSS VSS
AL66 AU15
VSS VSS
BA62 G43
VSS VSS
L4
TPAD14-OP-GP T P2311 1 A 70_TP A70 VSS VSS
AM13 AU20
VSS VSS
BA66 G45
VSS VSS
L8
TPAD14-OP-GP T P2310 AA2
VSS VSS
AM21 AU32
VSS VSS
BA71 B A71_TP 1 G48
VSS VSS
N10
VSS VSS VSS VSS T P2303 TPAD14-OP-GP VSS VSS
AA4 AM25 AU38 BB18 G5 N13
VSS VSS 1 A V1_TP VSS VSS VSS VSS
AA65 AM27 AV1 BB26 G52 N19
AA68
VSS VSS
AM43 TPAD14-OP-GP T P2307 AV68
VSS VSS
BB30 G55
VSS VSS
N21
VSS VSS VSS VSS VSS VSS
AB15 AM45 AV69 BB34 G58 N6
AB16 AM46 AV70 BB38 G6 N65
VSS VSS 1 A V71_TP VSS VSS VSS VSS
AB18 AM55 AV71 BB43 G60 N68
AB21
VSS VSS
AM60 TPAD14-OP-GP T P2304 AW10
VSS VSS
BB55 G63
VSS VSS
P17
AB8 AM61 AW12 BB6 G66 P19
AD13 AM68 AW14 BB60 H15 P20
AD16 AM71 AW16 BB64 H18 P21
VSS VSS VSS VSS B B67_TP 1 VSS VSS
AD19 AM8 AW18 BB67 T P2302 TPAD14-OP-GP H71 R13
VSS VSS VSS VSS B B70_TP 1 VSS VSS
AD20 AN20 AW21 BB70 T P2301 TPAD14-OP-GP J11 R6
VSS VSS VSS VSS C 1_TP 1 VSS VSS
AD21 AN23 AW23 C1 T P2308 TPAD14-OP-GP J13 T15
AD62 AN28 AW26 C25 J25 T17
AD8 AN30 AW28 C5 J28 T18
AE64 AN32 AW30 D10 J32 T2
AE65 AN33 AW32 D11 J35 T21
AE66 AN35 AW34 D14 J38 T4
AE67 AN37 AW36 D18 J42 U10
AE68 AN38 AW38 D22 J8 U63
AE69 AN40 D25 K16 U64
VSS VSS VSS VSS VSS
AF1 AN42 AW41 D26 K18 U66
AF10 AN58 AW43 D30 K22 U67
C AF15 AN63 AW45 D34 K61 U69 C
AF17 AP10 AW47 D39 K63 U70
AF2 AP18 AW49 D44 K64 V16
AF4 AP20 AW51 D45 K65 V17
AF63 AP23 AW53 D47 K66 V18
AG16 AP28 AW55 D48 K67 W13
AG17 AP32 AW57 D53 K68 W6
AG18 AP35 AW6 D58 K70 W9
AG19 AP38 AW60 D6 K71 Y17
AG20 AP42 AW62 D62 L11 Y19
AG21 AP58 AW64 D66 L16 Y20
AG71 AP63 AW66 D69 L17 Y21
AH13 VSS VSS AP68 AW8 VSS VSS E11 VSS VSS
AH6 VSS VSS AP70 AY66 VSS VSS E15
AH63 VSS VSS AR11 B10 VSS VSS E18
AH64 VSS VSS AR15 B14 VSS VSS E21
AH67 VSS VSS AR16 B18 VSS VSS E46 SKYLAKE-U-GP
AJ15 VSS VSS AR20 B22 VSS VSS E50
AK11 VSS VSS AR42 B44 VSS VSS E65
AK16 VSS VSS AR43 B48 VSS VSS E71 E 71_TP 1
VSS VSS VSS VSS T P2313 TPAD14-OP-GP
AK18 AR45 B53 F1
AK21 VSS VSS AR46 B58 VSS VSS F13
AK63 VSS VSS AR50 1 B 71_TP B71 VSS VSS F23
VSS VSS TPAD14-OP-GP T P2312 1 B A1_TP VSS VSS
AK68 AR52 BA1 F27
B VSS VSS TPAD14-OP-GP T P2305 VSS VSS B
AK69 AR53 BA10 F28
AK8 VSS VSS AR55 BA14 VSS VSS F32
AL2 VSS VSS AR58 BA18 VSS VSS F33
AL28 VSS VSS AR63 1 B A2_TP BA2 VSS VSS F35
VSS VSS TPAD14-OP-GP T P2306 VSS VSS
AL32 AR8 BA23 F37
AL35 VSS VSS AT2 BA28 VSS VSS F38
AL45 VSS VSS AT28 F68 VSS VSS F42
AL48 VSS VSS AT35 BA45 VSS VSS BA41
AL52 VSS VSS AT4 VSS VSS
AL55 VSS VSS AT42
AL58 VSS VSS AT56
AL64 VSS VSS AT58
VSS VSS SKYLAKE-U-GP
SKYLAKE-U-GP
A <Core Design> A
Wistron Corporation
TTitle
itle
CPU_(VSS)
A3
S tarlord KBL-R A00
5 4 3 2 1
5 4 3 2 1
Vince,20170721
Main Func = KBC Vince,20161013 D3V_S5
3
3D3V_S5 3VALW_EC
+ 3VALW_EC
+
V1.8A
+ 1.8VALW_EC
+ Vince,20170525
1
R2446
2462
R
1D0V_S5 2442
1
1 2 R
R2402 2 1 2443 200KR2F-L-GP StarlordR-L[KBL-U]
VREF_CPU
A00 R
49K9R2F-L-GP
1 2 0R0603-PAD
2
1
C
0R0402-PAD PCB_REV MODEL_ID
0R0402-PAD ODEL_ID
2
M
2406
SCD1U16V2KX-3DLGP
OARD_ID
2
B
1
C
2441
1
Just for Starload placement 2408 2444
R
100KR2F-L1-GP
2407
C R
2015/09/23 modify 100KR2F-L1-GP
1
StarlordR-L[KBL-R]
SCD1U16V2KX-3DLGP
If don't need RTC alarm wake up,
2
S
2421
2416
2420
2412
2411
2410
2414
2413
can change to 3D3V_AUX_S5
2
C
2
CD1U16V2KX-3DLGP
1
1
C_AGND
StarlordR-L[SKL-U]
E
2423
SCD1U16V2KX-3DLGP
SCD1U16V2KX-3DLGP
SCD1U16V2KX-3DLGP
SCD1U16V2KX-3DLGP
SCD1U16V2KX-3DLGP
SCD1U16V2KX-3DLGP
SCD1U16V2KX-3DLGP
SCD1U16V2KX-3DLGP
C_AGND
E
Layout Note:
C
TC_AUX_S5
1
R
D D
Need very close to EC
2
SCD1U16V2KX-3DLGP
2
2472
R
0R0402-PAD
Just for Starload placement
1
2015/09/23 modify CVBAT
E
2428
1
C
CD1U16V2KX-3DLGP
2
+3VALW_EC
BC24 54
122
103
K
43
82
19
65
TR_33_18
5
V
[65] KSO[0..16] Vince,20161013
BAT
TR
TR
TR
TR
TR
TR
V
V
V
V
V
V
RN2412 2
V
PIO027/KSO00/PVT_IO1
1 8 KSO0 SO0
K 14 8
S
GPIO015/KSO01/PVT_CS# PIO007/SMB01_DATA/SMB01_DATA18 BAT_CHG_SMBDAT
P D3V_S0
2 7
non-PreDrive KSO1 SO1
K 15 9 BAT_CHG_SMBDAT [43,44]
3
GPIO016/KSO02/PVT_SCLK G PIO010/SMB01_CLK/SMB01_CLK18 BAT_CHG_SMBCLK
P P D3V_S5
3 6 KSO2 SO2
K 16 11 BAT_CHG_SMBCLK [43,44] 12461
R 2 3
GPIO017/KSO03/PVT_IO0 PIO012/SMB02_DATA/SMB02_DATA18
G PU_THM_SMBDAT
G P
4 5 KSO3 SO3
K 37 12
SO4 38 GPIO045/BCM_INT1#/KSO04 G PIO013/SMB02_CLK/SMB02_CLK18 89 PU_THM_SMBCLK
G 0R0402-PAD
K Change symbol part number, because origin symbol is DELL OBS part
SO5 GPIO046/BCM_DAT1/KSO05 PIO130/SMB03_DATA/SMB03_DATA18
G ypeC_SMBDA
T
2
K 39 91 Vince,20161018
SRN100KJ-5-GP SO6 50 GPIO047/BCM_CLK1/KSO06 G PIO131/SMB03_CLK/SMB03_CLK18 96 ypeC_SMBCLK
T 2430 2496
K For Typec SMBUS R 2415 R
SO7 46 GPIO025/KSO07/PVT_IO2 PIO141/SMB04_DATA/SMB04_DATA18
G 97 B_MODE#
N 10KR2J-3-GP 2403 Q
RN2409 K B_MODE#
N [20] D 100KR2J-1-GP
DY
1 8 KSO4 SO8
K 68 GPIO055/PW M2/KSO08/PVT_IO3 G PIO142/SMB04_CLK/SMB04_CLK18 ID_CL_SIO_TAB#
L RB751V-40H-GP S
PIO102/KSO09/CR_STRAP [70] B_CLOSE#_2
K
2 7 KSO5 SO9 72 G G 40
non-PreDrive K
GPIO106/KSO10 PIO050/TACH0 AN1_TACH ID_CL_SIO_TAB#
1
3 6 KSO6 SO10
K 74 41 F A K AN_TACH1 [26] D L
GPIO110/KSO11 PIO051/TACH1
G F
4 5 KSO7 SO11
K 75 OL_DOWN#
V [66] Vince,20161114 DY
+3VALW_EC SO12
K 76 GPIO111/KSO12 G 44 G 2N7002K-2-GP
PIO112/PS2_CLK1A/KSO13 PIO053/PW M0 3VALW_EC
+
SO13
K 77 G 45
PIO113/PS2_DAT1A/KSO14 PIO054/PW M1 B_LED_PWM
K [65]
SRN100KJ-5-GP SO14
K 86 G G
PIO125/KSO15 EEP
B [27]
RN2403 SO15 G G
RN2410 K 92 47
1 8 KSO8 1 8 KSI0 SO16
K 93 GPIO132/KSO16 PIO056/PW M3 34
AP_LED# AN1_PWM
F [26]
2 7 KSO10 2 7 KSI1 C GPIO140/KSO17 PIO030/BCM_INT0#/PW
G M4 35
non-PreDrive
3 6 KSO11
non-PreDrive
3 6 KSI2 98 G PIO031/BCM_DAT0/PWM5
G 36
OL_UP#
V [66] Vince,20161114
[65] KSI[0..7] ANWAKE#
L [17]
4 5 KSO12 4 5 KSI3 SI0
K 99 PIO143/KSI0/DTR# G
PIO032/BCM_CLK0/PW M6 4
CIE_WAKE# S_ID
P [43]
SI1
K 6 GPIO144/KSI1/DCD# G PIO002/PW M7 P 1
SI2
K 7 GPIO005/SMB00_DATA/SMB00_DATA18/KSI2 G 1 P2407TPAD14-OP-GP
T
SRN100KJ-5-GP SRN10KJ-6-GP SI3 GPIO006/SMB00_CLK/SMB00_CLK18/KSI3 PIO157/LED0/TST_CLK_OUT AT2_LED#
B
eDP backlight Control from PCH
K 104 106 2435
GPIO147/KSI4/DSR# G PIO156/LED1 AT1_LED#
B R D3V_S5
RN2411 RN2404 SI4
K 105 70 Vince,20161018 3
1 8 KSO13 1 8 KSI7 SI5
K 107 GPIO150/KSI5/RI# G
PIO104/LED2 REATH_LED#
B 1 P2405
T
_BKLT_EN_EC
L 1 2 _BKLT_EN
L [8,55]
2 7 2 7 KSI6 SI6 108 GPIO151/KSI6/RTS# G 80 TPAD14-OP-GP N2405
non-PreDrive KSO14 non-PreDrive K
GPIO152/KSI7/CTS# PIO116/TFDP_DATA/UART_RX
R
1
3 6 3 6 KSI5 SI7 81 1 8
4 5
KSO15
4 5 KSI4
K
G G PIO117/TFDP_CLK/UART_TX E_FWP_EC
M [19] Vince,20170206 2436 0R0402-PAD
2 7
KSO16
[65] CLK_TP_SIO
78
79 PIO114/PS2_CLK0 G 90
OST_DEBUG_TX
H [68] Vince,20161012 R
100KR2J-1-GP ID_CL_SIO#
L 3 6
52 GPIO115/PS2_DAT0 PIO035/SB-TSI_CLK 94 4 5
[65] DAT_TP_SIO G G _PECI TP_DIS#_R
P [65] 2416
Q [65] P_EN#
T
SRN100KJ-5-GP SRN10KJ-6-GP PIO026/PS2_CLK1B PIO033/PECI_DAT/SB_TSI_DAT H 1 2
Vince,20161011 [17] SIO_PWRBTN# C_SLP_S0IX#
88
GPIO127/PS2_DAT1B G _PECI_CPU
H [4] TC_AUX_S5 D3V_AUX_S5 D3V_AUX_S5 AT2_LED#
2
[17,40,60,91] SIO_SLP_S0# R2423 1 2E 95 2437
R R 3 3
Vince,20161018 B 1 6 ATT_WHITE_LED# [64]
N
G REF_CPU REF_CPU
V B
0R0402-PAD 43R2J-GP SRN100KJ-5-GP
SC100P50V2JN-3GP
59
C 2405
[18,68] ESPI_IO[3..0] SPI_IO0 V
E PIO040/LAD0/ESPI_IO0
1
60 101 D3V_S5
3
2 5 D3V_S5
3
SPI_IO1
E GPIO041/LAD1/ESPI_IO1 PIO145/ICSP_CLOCK CSP_CLOCK
I
1
Vince,20160926 61 102 DY
ote:ZZ.27002.F7C01
SPI_IO2
E GPIO042/LAD2/ESPI_IO2 G PIO146/ICSP_DATA CSP_DATA
I 2464 2463 3 4 AT1_LED#
B
SPI_IO3
62
GPIO043/LAD3/ESPI_IO3 G CSP_MCLR
87
CSP_CLR
R
DY 1KR2J-1-GP R
DY 1KR2J-1-GP [64] HG_AMBER_LED#
C
2
E 58 I
GPIO044/LFRAME#/ESPI_CS# I
1
C 2415 C
MASK_SATA_LED#
Vince,20161013 [18,68] ESPI_CS# 56
G
119 Need very close to EC, PDG: <0.5 inches. 2417
Q
C
2N7002KDW-1-GP
[64] MASK_SATA_LED# 57
G
PIO064/LRESET# GPO/GPIO004
B
120
YSPWR_PRES B_MUTE#
N [27] 1 DY
PIO034/PCI_CLK/ESPI_CLK YSPW R_PRES/GPIO003
2
S G
S CD1U16V2KX-3DLGP
[18,68] ESPI_CLK LKRUN#_EC
63
GPIO067/CLKRUN# S CI_OUT/GPIO036
121
CD_VCC_TEST_EN Q2412 and Q2413 merge
2
R2476 1 2 C LWON L
[18] CLKRUN# DY 55
GPIO063/SER_IRQ/ESPI_ALERT# V
CI_IN1#/GPIO162
126 A
DMI_EC_DET#
H
LWON
A [40]
3 CD_VCC_TEST_EN
L [55]
1
0R2J-2-GP [18,68] ESPI_ALERT# PU_PWR_LEVEL
G
10
GPIO011/SMI#/EMI_INT# V
CI_IN0#/GPIO163
127
OWER_SW_IN#
P 3VALW_EC
+
DY D
D3V_S5
3
[66] OVER_CURRENT_P8# 1 R2474 2 49 128 2454
R 24014/12/23 modify
0R0402-PAD TP_EN# GPIO060/KBRST V
CI_OVRD_IN/GPIO164 100KR2J-1-GP
53
GPIO061/LPCPD#/ESPI_RESET# V w_ACAV_IN
h [44] 2S
Vince,20161018 [18,68] ESPI_RESET# 66
GPIO100/EC_SCI# PIO160/DAC_0
23
C6_THM_DIS#_EC
G
Vince,20161018
1
[19,66] DGPU_PWROK R2477 1 DY 2 [70] LID_CL_SIO# 24 1 2420
R 2 C6_THM_DIS#
G [19]
G G W_ACAVIN_NB 2N7002K-2-GP
2
32 PIO161/DAC_1 22 H 0R0402-PAD 2424
R 2434
R
0R2J-2-GP PIO126/SHD_SCLK G AC_VREF 20KR2F-L-GP 100KR2J-1-GP
[37] NT#_Typec
I 28 3VALW_EC
+
GPIO133/SHD_IO0 D SCD1U16V2KX-3DLGP 2429
C 1 2
[17] SYS_PWROK 29 85
GPIO134/SHD_IO1 PIO124/CMP_VOUT0 MP_VOUT0
C
[43] PBAT_PRES# 30 20 MP_VOUT0
C [26]
G G MP_VIN0 SB_EN# D3V_S0
2
[40,54] 1D8V_S5_PWROK 31 PIO135/SHD_IO2 PIO020/CMP_VIN0 25 C 2 2470
R 1 MP_VIN0_R [26]
U
SB_EN# [35,66] 3
G G C U
27 PIO136/SHD_IO3 PIO165/CMP_VREF0 CREF0
V 0R0402-PAD Vref = 1.117
[25] RTCRST_ON G G temp around 85
PIO123/SHD_CS# 83
[17] PCH_RSMRST# G PIO120/CMP_VOUT1
2
ROCHOT
P
L_BKLT_EN_EC KLT_EN_EC
B
67
PIO101/SPI_CLK G PIO021/CMP_VIN1 21 MP_VIN1
C
Vince,20161018
1 R2422 2 69 26 Vince,20161018 2489
R
GPIO103/SPI_IO0 G
PIO166/CMP_VREF1/UART_CLK CD_TST
L
1
[43] 0R0402-PAD 2409
C 2448
R 100KR2J-1-GP
AC_DIS 71 G G CD_TST
L [55] W_ACAVIN_NB
PIO105/SPI_IO1 H
1
[34] USB_POWERSHARE_VBUS_EN 42 118
TP2402 1 PIO052/SPI_IO2
G GPIO052/SPI_IO2 PIO024/ADC7
S CD01U50V2KX-1GP
1 0KR2F-2-GP
33 G G 117 SB_PWR_SHR_EN_L#
U [34] AP_LED#
1
TPAD14-OP-GP PIO062/SPI_IO3 PIO023/ADC6/A20M C S
Vince,20161018 [4,65] TP_WAKE_KBC# 3 G G 116 ANEL_BKEN_EC
P [55]
2
PIO001/SPI_CS#/32KHZ_OUT PIO022/ADC5 109 IO_EXT_WAKE# [20] 2475
R 2 1 C_IN_OK [43]
G G O
MDEL_ID S D
2
13 PIO153/ADC4 110 0R0402-PAD D AP_LED#_R [65]
SB_EN#
U G _ADP_R
I C
48 ESET_IN#/GPIO014 PIO154/ADC3 111
RPIO057/VCC_PW RGD G
PIO155/ADC2 OARD_ID
B G
ALL_SYS_PWRGD assert,
[17,40] RUNPWROK
[17,26] RESET_OUT#
73 GPIO107/RESET_OUT# G
PIO122/ADC1
113
114
CD_VCC_TEST_EN
L Vince,20160929 For Typec charge detect modfy 2016/01/04 D3V_S0
3
2N7002K-2-GP
G G _BATT 2414
SS_VBAT
PIO121/ADC0 I Q
delay 10ms; PCH_PWROK assert. EC_XTAL2 125 R_CAP G DC_VREF 115
R2425 1 2 M TAL2
[18] SUS_CLK DY EC_XTAL1_R 123
M X A 3VALW_EC
+
VSS
0R2J-2-GP TAL1
SS
SS
SS
SS
SS
X
V
V
V
V
V
V
Vince,20161101 Vince,20170203 MEC1416-NU-D0-GP Vince,20160929 Vince,20161031

124
84
51
17
64
100
112
18
1
2422
C
For eSPI
E_AGND
V_CAP
2
S D1U16V2KX-3DLGP
GPIO102 (CR_STRAP) GPIO123 (BSS_STRAP)
C
+3VALW_EC
1
2
C418
C_AGND
Vince,2017328 common part request
S C1U10V2KX-1GP
E
_ADP_R
I 2 1
Already pull low D_IA
A [44]
2
2
2401
C
X
R2450 on CPU side 1 2 2421
R
330R2J-3-GP
SC2200P50V2KX-2GP
100KR2J-1-GP
1
XTAL-32D768KHZ-91-GP
2435
1
C
PCH_RSMRST# 2445
R
1
1 C2425 2424
150KR2F-L-GP
KSO9 TP2406 C
R2455
SC18P50V2JN-1DLGP SC18P50V2JN-1DLGP 1 2
1
TPAD14-OP-GP
DY
P
2
C_AGND
R2449
0R0402-PAD Vince,20160929 E
2
DY 100KR2J-1-GP
Layout Note:
B
DMI_EC_DET#
H [57] Move schematic, 20141118 B
1
Microchip: Use CL=9p Xtal，C = 10p C

E_AGND Connect GND and AGND planes via either Vince,20170105
0R resistor or connect directly. MP_VIN1
C
2426
R
_BATT
I 2 1 PU_THM_SMBDAT
G 12447
R 2 ML1_SMBDATA
S
oost_mon
b [44] ML1_SMBDATA
S [18,26,66]
1
SC2200P50V2KX-2GP
115KR2F-GP
0R0402-PAD
1
330R2J-3-GP
DY
2436
2456
PU_THM_SMBCLK
G ML1_SMBCLK
S
SC2200P50V2KX-2GP
DY 12459
R 2
Layout Note: ML1_SMBCLK
S [18,26,66]
2441
1
0R0402-PAD Reserve by NON DS3 function 20150413
R
2
Need very close to EC
2
2
Need very close to EC 3VALW_EC
+
Vince,20170203
3VALW_EC
+
C_AGND
E
2
1
N2604
R
SRN2K2J-1-GP
Vince,20161107 Touch Panel PH internally. D3V_S0
3
C6_THM_DIS#_EC
G 2
R471 2 1 0R2J-2-GP
DY GPU_PWROK
D [19,66] OUCH_REPORT_SW
3
4
T 2429
R 1 210KR2J-3-GP 2605
DY Q
ypeC_SMBDA
T
2
1 6
N
[37] CG4_I2C_SDA
C ypeC_SMBDA
T [38]
R2418 2431
R
ote:ZZ.27002.F7C01
0R2J-2-GP 10KR2J-3-GP
DY 2 TypeC5
1 2 D3V_S5
3
DY R2498,R2499 merge to RN2407
2015/09/22 modify 2015/10/06 modify Just for Starload placement 3 4
1
Q2408 2015/09/23 modify 2N7002KDW-1-GP

OL_UP#
V
N2407
R Vince,20161123
PROCHOT G 4 1
OL_DOWN#
V 3 2
[37] CG4_I2C_SCL
C
D H_PROCHOT# [4,44,46] ypeC_SMBCLK
T
1
SRN10KJ-5-GP
ypeC_SMBCLK
T [38]
R2417 S
1
100KR2J-1-GP
DY Change symbol part number, because origin symbol is DELL OBS part 20150116 2040
ED2401
AZ5725-01FDR7G-GP
2N7002K-2-GP
2
2402
D
2
RB751V-40H-GP
ID_CL_SIO#
L
Vince,20161107
K A
OUCH_REPORT_SW
T [55]
EMI DVT1 0210
+3VALW_EC 3VALW_EC
+
A RN2402 A
PBAT_CHG_SMBCLK 3 2 3VALW_EC
+ Power Switch Logic(PSL)
PBAT_CHG_SMBDAT 4 1
3VALW_EC
+
Vince,20161013 SRN4K7J-8-GP 2480
R
100KR2J-1-GP TC_AUX_S5
R
B
D3
USB_PWR_SHR_EN_L#
2
R2473 1 2 10KR2J-3-GP 7
2
1
4K7R2J-2-GP
Vince,20161031
R2414
CSP_CLOCK
I 2 2451
DY CSP_DATA
I 3
R
100KR2J-1-GP
EC Debug
1
+3VALW_EC 4
2432
R
1
HOST_DEBUG_TX 5
1
PBAT_PRES# R2415 1 2 10KR2J-3-GP CSP_CLR

I 6 1 2 OWER_SW_IN#
P
[66] BC_PWRBTN#
K <Core Design>
8
SIO_EXT_SCI#
SIO_EXT_SCI# [16] 1KR2J-1-GP
1
2426
C
SC2D2U10V3KX-1DLGP-U
ACES-CON6-58-GP 1F,288, Sec.1, Hsin Tai Wu Rd., Hsichih,
2
Vince,20161018 itleT
Title
Just for Starload placement Vince,20170516 K BC Nuvoton NPCE285PA0DX
WWW.AliSaler.Com
2015/09/23 modify
1 A
S tarlord KBL-R 0A0
Date: Friday, December 08, 2017 Sheet 24 f o 106
5 4 3 2 1
5 4 3 2 1
Main Func = SPI Flash

3 D3V_S5_PCH
Source QUAD/DUAL fast read DUAL fast read SFDP
1
R 2515
72.25128.0B1 O O O
SPI Flash ROM(8M) for PCH 3 D3V_S5_PCH 3 D3V_SPIVCC1 0R0402-PAD
2
O O O
1
D C 2501 O O O D
SC10U10V5KX-2GPDY DYC 2502
2
SCD1U16V2KX-3GP
2
R 2501
4K7R2J-2-GP
1
Change to Dummy 20150402
S PI25 3 D3V_SPIVCC1
1 8
[18] S PI_CS_ROM_N0 S PI_SO_ROM_R 2
CS# VCC
7 S PI_HOLD_ROM_R R 2503 1 2
S PI_W P_ROM_R SO/SIO1 SIO3 S PI_CLK_ROM_R S PI_HOLD_ROM [18]
3 6 10R2F-L-GP
SIO2 SCLK S PI_SI_ROM_R R 2505
4 5
GND SI/SIO0 S PI_CLK_ROM_R 1 2 S PI_CLK_ROM [18,91]
S PI_SI_ROM_R 1 2
10R2F-L-GP S PI_SI_ROM [18,91]
1
R 2506 10R2F-L-GP
E C2501
MX25L12873FM2I-10G-GP
SC4D7P50V2BN-GP
DY DY E C2503
1
SC10P50V2JN-4GP Vince,20161018
2
E C2502 DY
SC4D7P50V2BN-GP
2
R 2507 1 2 S PI_SO_ROM_R
[18,91] S PI_SO_ROM 1 2 S PI_W P_ROM_R
10R2F-L-GP
C [18] S PI_W P_ROM R 2508 C
10R2F-L-GP
Vince,20161018
Delivery Voltage 3.19V

(when R2510 1K6 ohm)
3 D3V_AUX_S5
1
R 2510
0R2J-2-GP
2
B 3 D3V_RTC_SYS B
Main Func = RTC

1
R 2517
+ RTC_VCC R TC_AUX_S5
DY 47KR2F-GP
2
D 2501
1
2
1
C 2503
BAS40C-2-GP SCD47U25V3KX-1-DL-GP
2
Q 2503
1 6
Note:ZZ.27002.F7C01
R TC_DET# [20]
2 5 R TCRST_ON [24]
A <Core Design> A
1
3 4
[18] R TC_RST#
R 2504 R 2509
10MR2J-L-GP
2N7002KDW-1-GP 100KR2J-1-GP
Wistron Corporation
1

SCD1U16V2KX-3GP
2

EC2504
DY
2
Title
Vince,20161027 Flash/RTC
A3
S tarlord KBL-R A00
5 4 3 2 1
5 4 3 2 1
Main Func = Thermal Sensor

3 D3V_S0 3 D3V_S0
PWM FAN1
1
2
R N2602
SRN2K2J-1-GP
7718 5 V_S0 Layout Note:
3 D3V_S0 R 2612 Signal Routing Guideline:
Q 2601 F AN_VCC_1
4
3
ote:ZZ.27002.F7C01
1 2 Trace width = 15mil
6 1 T HM_SML1_DATA 0R0402-PAD
N
[18,24,66] S ML1_SMBDATA
D 2601
SC10U6D3V3MX-GP
SC4D7U6D3V3KX-GP
SCD1U16V2KX-3DLGP
SC2200P50V2KX-2GP
C 2601
R B551V30-GP
K
5 2
C
2604
2605
2603
7718
1
1
1
4 3
D
DY 7718 C 2602 DY
DY D
2
SCD1U16V2KX-3DLGP 2N7002KDW-1-GP
2
A
T HM_SML1_CLK
[18,24,66] S ML1_SMBCLK
F AN1
5
N CT7718_DXP F AN_VCC_1 1
T HM261
2
T HM_SML1_CLK F AN_TACH1_C
3
1 8 R 2613 1 2 3
V DD S CL [24] F AN_TACH1
Q2603 1 C 2606 2607 2 7 T HM_SML1_DATA R 2614 1 0R0402-PAD
2 F AN_PWM1_C 4
PMBS3904-1-GP SC470P50V3JN-2GP 7718CSC2200P50V2KX-2GP 3 D + 7718 S DA 6 A LERT#
[24] F AN1_PWM
0R0402-PAD 6
DY
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
T _CRIT# D- A LERT#
2
4 5
7718 T _CRIT# G ND
C 2608
C 2609
N CT7718_DXN
2
1
A FTP2604 1 ACES-CON4-29-GP
DY DY
2.System Sensor, Put on palm rest NCT7718W-GP
2
1
F AN_TACH1_C
1 A FTP2601
DY 0R2J-2-GP
R 2601 Q 2602 F AN_PWM1_C1 A FTP2602
Layout Note: [17,24] R ESET_OUT# G
F AN_VCC_1 1
2
C2607 close THM2601 A FTP2603

D
P URE_HW_SHUTDOWN# [40]
T HERM_SYS_SHDN# S
SCD1U16V2KX-3GP
C 2610
C MP_VOUT0
1
1 DY 2
Layout Note: 2N7002K-2-GP
DY R 2615 0R2J-2-GP DVT1 0210, for T8 function
Both DXN and DXP routing 10 mil trace width and 10 mil spacing.
2
C 3D3V_S0 C
1 2 7K5R2F-1-GP A LERT# 3 D3V_S5

R2603
R2604 1
7718
7718 2 7K5R2F-1-GP T _CRIT#
KBC T8 R 2607 1 2 10KR2J-3-GP
R 2602
1 2
C MP_VOUT0 [24]
0R0402-PAD
Close to KBC
Close to Thermal sensor VD_IN1 for system thermal sensor
3 D3V_S0 + 3VALW_EC
1
R 2609 R 2608
27KR2F-L-GP
DY 10R2F-L-GP
D VT1 0210, for T8 function
2
C MP_VIN0_R [24]
1
R 2610
NTC-100K-8-GP C 2612 C 2613
SCD1U16V2KX-3DLGP
2
SC100P50V2JN-3GP
2
R 2611
V D_IN1_C 1 2
0R0402-PAD
B B
A A
<Core Design>
Title
T HERMAL NCT7718W/Fan
Size
A 2
Document Number
S tarlord KBL-R
1
Sheet 26 o f
Rev
A 00
106
5 4 3 2 1
Main Func = Audio
moat
+ 5V_AVDD 5 V_S0
Width>40mil, to improve Headpohone Crosstalk noise R 2703

3 D3V_S0 + 3V_AVDD 1 2
Change it to sharp will be better. 0R0603-PAD
R 2731
Add 2 vias (>0.5A) when trace layer change. C 2710
1
1 2 C 2711
CD1U16V2KX-3DLGP
S
S C4D7U6D3V3KX-GP
0R0805-PAD
D
1 D8V_S0 C PVDD Layout Note: Layout Note: D
2
R 2724 Place close to Pin 40
1 2
0R0402-PAD [29] R ING2
[29] S LEEVE moat

SC10U6D3V3MX-GP 2 1 C 2713 M IC_CAP A UD_AGND
A UD_AGND M IC2_VREFO_R [29] C27071 SC1KP50V2KX-1GP
E DY 2
R 2723 E C27061 DY 2 SC1KP50V2KX-1GP
A UD_PC_BEEP_R A UD_PC_BEEP M IC2_VREFO_L [29]
1
1
1 2 E C27051 DY 2 SCD1U25V2KX-GP
C 2701 C 2724 0R0402-PAD E C27041 DY 2 SC1KP50V2KX-1GP
SCD1U16V2KX-3DLGP SC4D7U6D3V3KX-GP A UD_HP1_JACK_L [29] C27031 SCD1U25V2KX-GP
[29] L INE1_R
E DY 2
2
2
A UD_HP1_JACK_R [29]
Close pin 21 [29] L INE1_L
A UD_AGND
1.5A
5 V_S0 + 5V_PVDD R 2706
1 2
R 2702
1 2
0R0805-PAD
36
35
34
33
32
31
30
29
28
27
26
25
0R0805-PAD
C 2706 C 2707 C 2708 C 2709 H DA27
S C10U6D3V3MX-GP
S C10U6D3V3MX-GP
1
1
R 2704
L INE1-L/PORT-C-L
M IC2-CAP
M IC2-VREFO-L
L INE2-L/PORT-E-L
H POUT-L/PORT-I-L
P CBEEP
M IC2-R/PORT-F-R/SLEEVE
M IC2-L/PORT-F-L/RING2
L INE2-R/PORT-E-R
L INE1-R/PORT-C-R
M IC2-VREFO-R
S
H POUT-R/PORT-I-R
CD1U16V2KX-3DLGP
CD1U16V2KX-3DLGP
1 2
0R0805-PAD
2
A UD_AGND
37 24 C PVEE A UD_AGND Layout Note:
C 2705 A VSS1 C PVEE
SC2D2U10V3KX-1GP 1 2 A UD_VREF 38 23 C BN C 2703 2 1 SC1U50V3KX-GP
V REF C BN
L DO1_CAP
2
C 27021 2 39 22 C BP
A UD_AGND SC10U6D3V3MX-GP L DO1-CAP C BP C 2704
40 21
Layout Note: Layout Note: + 5V_AVDD A VDD1 C PVDD C PVDD SC1U50V3KX-GP
1
R 27111 2 100KR2J-1-GP
Close pin41 Close pin46 41 20
+ 5V_PVDD P VDD1 H POUT2-R/PORT-B-R A UD_AGND
C
moat A UD_AGND A UD_SPK_L+ 42 19 C
[29] A UD_SPK_L+ S PK-OUT-L+ H POUT2-L/PORT-B-L
1D8V_S0 A UD_SPK_L- 43 18
+ 3V_1D8V_AVDD Layout Note: [29] A UD_SPK_L- S PK-OUT-L- A VSS2 A UD_AGND
A UD_SPK_R- 17 L DO2_CAP
S PDIF-OUT/GPIO2/DMIC-DATA34
Speaker trace width >40mil @ 2W4ohm speaker power 44 C 2712 2 1 SC10U6D3V3MX-GP
[29] A UD_SPK_R- S PK-OUT-R- L DO2-CAP A UD_AGND
R2713 1 2
3D3V_S0 1D5V_S0 0R0402-PAD A UD_SPK_R+ 45 16
[29] A UD_SPK_R+ S PK-OUT-R+ A VDD2 + 3V_1D8V_AVDD
R2705 1 2 Vince,20161004 46 15
DY 0R2J-2-GP R TC_AUX_S5 + 5V_PVDD P VDD2 L INE1-VREFO-R-E/MONO L INE1_VREFO_R [29]
R 2725
G PIO0/DMIC-DATA12
5 V_STB
1
R2710 1DY 2 0R2J-2-GP 1 2 47 14

5 VSTB/AUXMODE L INE1-VREFO-L-E L INE1_VREFO_L [29]
G PIO1/DMIC-CLK
H P/LINE1-JD/JD1
C 2715 0R0402-PAD
48 13
D C-DET/EAPD
SC4D7U6D3V3KX-GP
H P2/LINE2-JD/JD2 L DO3-CAP moat
L DO3_CAP
2
S DATA-OUT
+ 3V_AVDD 49
S DATA-IN
Close pin16
D VDD-IO
G ND
R 2722
D VDD
S YNC
B CLK
A UD_AGND
A UD_SENSE_A
P D
2 1
C 2718
1
ALC3253-VA3-CG-GP
10
11
12
100KR2J-1-GP
D 2701
Azalia I/F EMI Layout Note:
S C10U6D3V3MX-GP
2
+ 3V_AVDD
Place close to Pin 1 R N2701 H DA_SPKR_R 1
[19] 2 3 C 2720
S PKR A UD_PC_BEEP_C1 UD_PC_BEEP_R
[24] 1 4 3 2A
H DA_CODEC_SDOUT B EEP
R 2709
H DA_CODEC_BITCLK 2 1 A UD_SENSE_A C 2719 K BC_BEEP_R 2
[29] A UD_SENSE SCD1U16V2KX-3DLGP
1
200KR2F-L-GP SRN1KJ-7-GP
SCD1U16V2KX-3DLGP
+ 3V_AVDD
1
E C2708 E C2709
1
T P2702 1C OMBO-GPI BAT54C-11-GP 2717

SC33P50V2JN-3GP
2
R 2728 2K2R2J-2-GP
DY DY SC33P50V2JN-3GP 2 1
DY
2
+ 3V_AVDD E APD#
R 2708
2
100KR2J-1-GP
1 2 E APD#
[24] N B_MUTE#
0R0402-PAD
1
C 2716 C 2717
EMI suggest change to 33p SC4D7U6D3V3KX-GP SCD1U16V2KX-3DLGP
2015/12/02
2
B B
R 2714
D MIC_DATA_R 2 1 D MIC_DATA_R
[55] D MIC_DATA C ODEC_SDOUT_R 2 R 2719 1
R 2716 100R2F-L1-GP-U
1 D VSS
D MIC_CLK_R H DA_CODEC_SDOUT [19]
0R2J-2-GP
E C2701 2 1 0R0402-PAD
[55] D MIC_CLK H DA_CODEC_SDIN0
1
100R2F-L1-GP-U 2 R 2718 1
SC33P50V2JN-3GP
0R0402-PAD H DA_SDIN0 [19]

DY
2
2
H DA_CODEC_SYNC
R 2732
C 2723DY 2017/03/27 modify by EMI suggest
SC33P50V2JN-3GP DY H DA_CODEC_SYNC [19]
1
C ODEC_BITCLK_R 2 R 2720 1
H DA_CODEC_BITCLK [19]
Close pin6 0R0402-PAD
2
+ V1.8A 1 D8V_S0
Q 2702
DMG3415U-GP
150mA S D
C 2722
1
1
SCD1U16V2KX-3DLGP
R 2726 C 2721
G
SCD1U16V2KX-3GP
10KR2J-3-GP C 2714 DY
2
SC1U10V2KX-1GP
2
2
2
1 R 2727 2 1 D8V_EN_R#
1 D8V_EN#
Q 2701 20KR2J-L2-GP
G
[17,40,51,54] SIO_SLP_S3#
D
2N7002K-2-GP
A A
<Core Design>
Title
A udio Codec ALC3246

A 2
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
<Core Design>
itleT
Title
WWW.AliSaler.Com
5 4 3 2
Size
1 A
Date:
Document Number
1
( Reserved)
tSarlord KBL-R
Monday, August 28, 2017 Sheet 28 f o
Rev
106
A 00
5 4 3 2 1
SSID = Audio
Layout Speaker
Speaker Note:
trace width >40mil @ 2W4ohm speaker power
S PK1
7
E L2902 1 2 A UD_SPK_L+_C 1
HCB1005KF-121T20-GP
D [27] A UD_SPK_L+ CONN Pin Net name D
E L2901 1 2 A UD_SPK_L-_C 2
HCB1005KF-121T20-GP
[27] A UD_SPK_L- E L2903 1 2 HCB1005KF-121T20-GP
A UD_SPK_R-_C 3 Pin1 SPK_L+
[27] A UD_SPK_R- E L2904 1 2 HCB1005KF-121T20-GP
A UD_SPK_R+_C 4
[27] A UD_SPK_R+ 5 Pin2 SPK_L-
[20] S PK_ID
6
main: 68.00358.031 8 Pin3 SPK_R-
2nd: 068.00006.0041
SC1KP50V2KX-1DLGP
SC1KP50V2KX-1DLGP
SC1KP50V2KX-1DLGP
SC1KP50V2KX-1DLGP
HR-CON6-1-GP-U Pin4 SPK_R+
Pin5 SPK_DET#
E C2910
E C2912
E C2909
E C2911
1
1
SC100P50V2JN-3GP
SC100P50V2JN-3GP
SC100P50V2JN-3GP
SC100P50V2JN-3GP
DY DY DY DY Pin6 GND
E C2901
E C2902
E C2903
E C2904
2
2
A UD_SPK_L-_C 1 A FTP2901
A UD_SPK_L+_C 1 A FTP2902
A UD_SPK_R-_C 1 A FTP2903
A UD_SPK_R+_C 1 A FTP2904
2017/03/27 modify by EMI suggest
C Universal Jack (Moved to I/O Board) C
R N2901
1 4
[27] M IC2_VREFO_R 2 3
[27] M IC2_VREFO_L H PMIC1
S LEEVE_R 3
SRN2K2J-1-GP 1 R 2906 2 0R0603-PAD R ING2_R A UD_PORTA_L_R_B 1
[27] R ING2
1 R 2907 2 0R0603-PAD A UD_HP1_JACK_L1 10R2F-L-GP 1 R 2908 2 A UD_PORTA_L_R_B
[27] A UD_HP1_JACK_L C 2907 1 2 L INE1-L_C 1 R 2922 2 0R0402-PAD J ACK_PLUG 5
[27] L INE1_L R 2912 1 2 2K2R2J-2-GP J ACK_PLUG_DET 6
[27] L INE1_VREFO_L
SC10U6D3V3MX-GP DY A UD_PORTA_R_R_B 2
1 R 2909 2 0R0603-PAD A UD_HP1_JACK_R1 10R2F-L-GP 1 R 2910 2 A UD_PORTA_R_R_B R ING2_R 4
[27] A UD_HP1_JACK_R C 2908 1 2 L INE1-L_R 1 R 2921 2 0R0402-PAD 1 R 2911 2 0R0603-PAD S LEEVE_R MS
[27] L INE1_R R 2913 1 2 2K2R2J-2-GP
[27] L INE1_VREFO_R
SC10U6D3V3MX-GP DY Audio(IP/NK comb)
SC100P50V2JN-3GP
SC100P50V2JN-3GP
SC100P50V2JN-3GP
SC100P50V2JN-3GP
EC2908
EC2907
EC2906
EC2905
10KR2J-3-GP
1 AUDIO-JK522-GP
R 29191
[27] S LEEVE
1
10KR2J-3-GP
R2920
DY 2 DY
2
DY DY DY DY A UD_AGND
2
2
Delay circuit
B B
(JACK_PLUG_DET: on IO Board)
A UD_AGND A UD_AGND
J ACK_PLUG_DET J ACK_PLUG 10 mils 1 R 2923 2 0R0603-PAD 10 mils

10 mils A UD_SENSE [27]
CLOSS TO HPMIC1
1
1
R 2905 DY C 2902
0R0402-PAD SC10U6D3V3MX-GP
2
R ING2_R
A UD_PORTA_L_R_B
2
J ACK_PLUG A UD_AGND
J ACK_PLUG_DET
A UD_PORTA_R_R_B
AUD_AGND S LEEVE_R
AZ5725-01FDR7G-GP
AZ5725-01FDR7G-GP
AZ5725-01FDR7G-GP
AZ5725-01FDR7G-GP
ED2902
ED2903
ED2904
ED2905
A
A
1
E D2901 E D2906
A <Core Design> A
DF2B6D8E-1-GP DF2B6D8E-1-GP
Wistron Corporation
2
2
K

Title
Audio IO
A3
Starlord KBL-R A 00
5 4 3 2 1
5 4 3 2 1
Main Func = Audio
D D
(Blanking)
C C
B B
<Core Design>
A
Title
(Reserved)
A4
Starlord KBL-R A00
WWW.AliSaler.Com
5 4 3
Date:
2
Monday, August 28, 2017 Sheet 30
1
of 106
5 4 3 2 1
Main Func = LAN
D D
(Blanking)
C C
B B
A A
<Core Design>
itle
T Title
L AN RTL8106
A 2
5 4 3 2 1
5 4 3 2 1
SSID = LAN
D D
(Blanking)
C C
B B
A <Core Design> A
Wistron Corporation
TTitle
itle
XFOM&RJ45
A3
S tarlord KBL-R A00
WWW.AliSaler.Com
5 4 3 2
Date: Monday, August 28, 2017 Sheet
1
32 of 106
5 4 3 2 1
Main Func = Card Reader
D D
C C
(Blanking)
B B
A A
<Core Design>
itle
T Title
Size
C ard Reader-RTS5170
Document Number Rev
A 2
5 4 3 2 1
5 4 3 2 1
Main Func = USB3.0 Port1
D D
USB Charger Port1

U SB30_VCCA
20170118, vendor recommend 5 V_S5 U SB_OC0# [16,35] 20170118, vendor recommend
C 3406 C 3402
1
SC10U6D3V3MX-DL-GP
SCD1U16V2KX-3DLGP
C 3403 C 3401 C 3404 C 3405 C 3407
1
SCD1U16V2KX-3DLGP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC1KP50V2KX-1DLGP
DY
SC1U10V2KX-1GP
2
2
13
12
1
9
U 3401
C X02 0414 C
NC#9
FAULT#
IN
OUT
5 3
[24] U SB_POW ERSHARE_VBUS_EN EN DP_OUT
2
U SB_CPU_PP0 [16]
DM_OUT U SB_CPU_PN0 [16]
20170118, vendor recommend R 3405 1 2 10KR2J-3-GP I LIM_SEL 4
5 V_S5 ILIM_SEL
R 3403 1 2 20KR2F-L-GP I LIM_LO 15
DY Device Control Pins
10 U SB_PP0_R [36]
R 3404 1 2 22K1R2F-L-GP I LIM_HI 16 ILIM_LO DP_IN
11 U SB_PN0_R [36]
ILIM_HI DM_IN
CTL1
CTL1
CTL2
CTL3
GND
GND
(EC control) CTL2 CTL3 ILIM_SEL
TPS2544RTER-GP
14
17
6
7
R 3401 1 2 0R0402-PAD C TL1 8 CDP 1 1 1 1
R 3406 1 2 10KR2J-3-GP C TL2
[24] U SB_PW R_SHR_EN_L# 5 V_S5
R 3402 1 2 10KR2J-3-GP
DCP Auto
C TL3
0 1 1 X
20170118, vendor recommend
B B
A <Core Design> A
Wistron Corporation
Title
(Reserved)
A3
S tarlord KBL-R A00
1
34 of 106
5 4 3 2 1

Vince, 20170206
D BOM option: D
ROR(2A):074.06288.009B
BBY(3.4A):074.05172.007F
5V_S5 USB30_VCCB
U3501
5 1
C3502 IN OUT 2
GND
1
C3503 4 3
SCD1U16V2KX-3DLGP
[24,66] USB_EN# EN# OC# USB_OC0# [16,34]

DY Active Low
SCD1U16V2KX-3GP
2
SY6288DAAC-GP
C C
B B
Layout Note: Close USB3

USB30_VCCB
Vince, 20170206
USB3.0 Port2 2A
100KR2J-1-GP
1
R3501
C3507 C3513 C3514

C3508
1
1
SCD1U16V2KX-3DLGP
C3512
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
DY
SC22U6D3V5MX-2GP
2
2
SC1U10V2KX-1GP
2
Vince,20170721 <Core Design>
A
for starlord placement modify
Title
USB switch
Starlord KBL-R A 00
5 4 3 2 1
5 4 3 2 1
SSD = USB3.0 Port1 E D3601
USB2.0 Port2 and USB2.0 Port3 are on IOBD U SB30_RXDN1_C 1 10 U SB30_RXDN1_C
U SB30_RXDP1_C 2 9 U SB30_RXDP1_C
USB3.0 Port1 3 8
U SB30_TXDN1_C 4 7 U SB30_TXDN1_C
U SB30_TXDP1_C 5 6 U SB30_TXDP1_C
R 3605 R 3609
C 3601
1 2 U SB30_TXDN1_R 1 2 U
USB30_TXDN1_C
SB30_TXDN1_C 1 2 U SB30_RXDN1_C
[16] USB30_TX_CPU_N1 [16] U SB30_RX_CPU_N1
SCD1U16V2KX-3DLGP L05ESDL5V0NA-4-GP Vince, 20170206
D D
0R0402-PAD 0R0402-PAD
U SB30_VCCA
E D3602
U SB20_DN0_C 1 6 U SB20_DP0_C
I/O1 I/O4
2 5
GND VDD
U SB20_DN1_C 3 4 U SB20_DP1_C
I/O2 I/O3
R 3606 R 3610
C 3602
1 2 U SB30_TXDP1_R 1 2 U
USB30_TXDP1_C
SB30_TXDP1_C 1 2 U SB30_RXDP1_C
[16] USB30_TX_CPU_P1 [16] U SB30_RX_CPU_P1
SCD1U16V2KX-3DLGP AZC099-04S-1-GP
0R0402-PAD 0R0402-PAD
BOM change
U SB20_DP0_C U SB30_VCCA
[34] U SB_PP0_R
U SB2
USB 3.0 Connector
U SB20_DN0_C
Pin definition
1 2
VBUS D- U SB20_DP0_C
COIL-90OHM-100MHZ-5-GP 3
D+
4 3 1 POWER
U SB30_RXDN1_C
C 1 2
Vince,20161121 U SB30_RXDP1_C
5
6
STDA_SSRX-
7 2 USB 2.0 D- C
STDA_SSRX+ GND_DRAIN
E L3605 U SB30_TXDN1_C 8 3 USB 2.0 D+
U SB30_TXDP1_C STDA_SSTX-
9 10
STDA_SSTX+ GND
GND
11 4 GND
12 4
CHASSIS#12 GND
13
CHASSIS#13 5 StdA_SSRX- SuperSpeed RX
U SB20_DN0_C
[34] U SB_PN0_R
6 StdA_SSRX+
SKT-USB13-221-GP
7 GND
8 StdA_SSTX- SuperSpeed TX
9 StdA_SSTX+
USB3.0 Port2
E D3603
R 3611 R 3612
C 3603
1 2U SB30_TXDN2_R 1 2 U SB30_TXDN2_C 1 2 U SB30_RXDN2_C U SB30_RXDN2_C 1 10 U SB30_RXDN2_C
[16] U SB30_TX_CPU_N2 [16] U SB30_RX_CPU_N2
SCD1U16V2KX-3DLGP
U SB30_RXDP2_C 2 9 U SB30_RXDP2_C
ROR 0R0402-PAD 0R0402-PAD 3 8
ROR
U SB30_TXDN2_C 4 7 U SB30_TXDN2_C
B U SB30_TXDP2_C 5 6 U SB30_TXDP2_C B
L05ESDL5V0NA-4-GP
Vince,20170206
R 3614 R 3613
C 3604
1 2U SB30_TXDP2_R 1 2 U SB30_TXDP2_C 1 2 U SB30_RXDP2_C
USB30_RXDP2_C
[16] U SB30_TX_CPU_P2 [16] U SB30_RX_CPU_P2
SCD1U16V2KX-3DLGP
ROR 0R0402-PAD 0R0402-PAD
BOM change
U SB30_VCCB
U SB20_DP1_C
[16] USB_CPU_PP1
U SB3
1 2 U SB20_DN1_C
VBUS D- 3 U SB20_DP1_C
D+
COIL-90OHM-100MHZ-5-GP
4 3 U SB30_RXDN2_C 5
U SB30_RXDP2_C 6 STDA_SSRX-ROR 7
1
ROR 2 STDA_SSRX+ GND_DRAIN
U SB30_TXDN2_C 8
A
U SB30_TXDP2_C STDA_SSTX- <Core Design> A
EL3606 9 10
STDA_SSTX+ GND 11
GND
12
13 CHASSIS#12
CHASSIS#13
GND
4
Wistron Corporation
U SB20_DN1_C Taipei Hsien 221, Taiwan, R.O.C.
[16] USB_CPU_PN1
SKT-USB13-221-GP
Title
USB30
A3
S tarlord KBL-R A00
1
36 of 106
5 4 3 2 1
V DDIO V DDD U 3701

V CC3PD V DDD V DDIO
CCG4 40-QFN PD Function
31 11 P D_VBUS_P_CTRL1 [43]
R 3732 1 VDDD VBUS_P_CTRL_P1
TypeC 20R2J-2-GP
32 12 P D_VBUS_C_CTRL1 [43]
VDDIO VBUS_C_CTRL_P1
R 3733 1 TypeC 20R2J-2-GP 20
S C1U10V2KX-1GP
VBUS_DISCHARGE_P1 P D_VBUS_DISCHG [43]
P D_VCCD 33
VCCD V DDD
1
V DDD 5 V_S5 5 V_VCONN_P1
TypeC
C 3715
1
2
D For VCONN OCP R 3725 DY D
S C1U10V2KX-1GP U 3703 PL 100K to GND
S CD1U16V2KX-3GP
S CD1U16V2KX-3GP
10KR2F-2-GP
TypeC R 3737
TypeC TypeC 2 6 1 25 V_VCONN_P1_CCG4 8 on CPU side
IN OUT_0 V5V_P1
2
1
5 18 C PU_DP_HPD_MUX R 1 TypeC 2 0R2J-2-GP

OUT_1 0R3J-0-U-GP HPD_P1/GPIO 3729 C PU_DP_HPD_R
C 3701 C 3702 C 3703 [8,38,57]
TypeC TypeC 23
NC#23
1
C 3719 C 3718 4
FAULT#
2
R 3734 1 7 P D_CC2 R 3727 1 TypeC 2

GND CC2_P1 U SBC1_CC2_CONN [38]
1 2 5 V_VCONN_EN
SCD1U16V2KX-3GP
SC10U6D3V3MX-GP
TypeC TypeC TypeC 3
EN PAD
7
2
3 0R2J-2-GP
I2C_SDA_SCB2_AR/VSEL_1_P1
100KR2J-1-GP
AP2151DFMG-7-GP-U 4
I2C_SCL_SCB2_AR
5 9 P D_CC1 R 3728 1 TypeC 2
[38] C CG4_FLIP# I2C_INT_AR_P1 CC1_P1 U SBC1_CC1_CONN [38]
5 V_S5 6
GPIO#6 0R2J-2-GP
V DDIO
V CCPD_VBUS Vince,20161028
TypeC Vendor 2016/10/28 confirm
S C1U10V2KX-1GP
S CD1U16V2KX-3GP
R 3730 1 2 100KR2F-L1-GP P D_VBUS_R 13

R 3726 1 2 VBUS_MON_P1/GPIO
TypeC TypeC S C1U10V2KX-1GP TypeC 10KR2F-2-GP SDA_3/MUX_CTRL_3_P1/VSEL_2_P1
26 D OCK_USB_EN_A [38]
1
C 3717 1 2 SCD1U16V2KX-3GP 28
SDA_4/MUX_CTRL_2_P1 I 2C_DATA_PD [38]
C 3705 C 3704 29
SCL_4/MUX_CTRL_1_P1 I 2C_CLK_PD [38]
C 3721 C 3723 TypeC
2
TypeC
I2C to MUX
SCD1U16V2KX-3DLGP
SCD1U16V2KX-3DLGP
C 3722
TypeC VBUS monitor for OVP
TypeC TypeC 37 U SBC1_CC1_CONN
GPIO#37
2
C
Vince,20161117 U SBC1_CC2_CONN C
1
30 C 3711
P D_SW D_IO GPIO#30
V DDD
1
SWD_IO/AR_RST# TypeC
S
Vince,20170119
C390P50V2KX-GP-U
2
1
5 V_VCONN_P1 P D_SW D_CLK 2 22 C 3712
R N3701 SWD_CLK/I2C_CFG_EC NC#22
2 3 I2C_CLK_PD
S
TypeC
C390P50V2KX-GP-U
2
1 4 I2C_DATA_PD R 3731 1 2 I NT#_Typec_R V DDD V DDD
TypeC
[24] I NT#_Typec
15
I2C_INT_EC TypeC
0R2J-2-GP
1
16
V DDD SRN2K2J-1-GP [24] C CG4_I2C_SDA I2C_SDA_SCB1_EC
24
NC#24
1
R 3706 DY 17
R N3702 [24] C CG4_I2C_SCL I2C_SCL_SCB1_EC
1MR2J-1-GP R 3750 R 3752
1 4 C CG4_I2C_SDA DY 30KR2F-GP TypeC 30KR2F-GP
2
2 TypeC 3 C CG4_I2C_SCL
V CONN_MON_P1 19
VCONN_MON_P1/GPIO
2
SRN2K2J-1-GP Vince,20161011 14 C CG4_ID_1 C CG4_ID_2
[43] C CG4_OVP_TRIP_P1 OVP_TRIP_P1
1
+ 3VALW_EC R 3735
Vince,20160922 GPIO#34
34
35
GPIO#35
1
2MR2-GP DY Vince,20170119 C CG4_ID_1 25 GPIO#36
36
D OCK_USB_EN_B [38] R 3751 R 3753
V DDD SCL_3
TypeC 3KR2F-GP TypeC 10KR2F-L1-GP
2
C CG4_ID_2 27
GPIO#27
1
2
R 3707 38
GPIO#38
1
TypeC 2K2R2J-2-GP 21
GPIO#21 39
TypeC GPIO#39
R 3724
2
B B
4K7R2J-2-GP 40
GPIO#40
2
INT#_Typec_R
P D_XRES 10
XRES
For Dead Battery modify GND
41
1
C 3716
From System Vince,20160922 TypeC SCD1U16V2KX-3GP
CYPD4125-40LQXIT-12-GP
Vince,20170330
2
3 D3V_S5 V CC3PD
A
D 3701
TypeCK
D 3702
KTypeC A For Debug
SBA0520Q-R1-00001-GP-U SBA0520Q-R1-00001-GP-U P D_SW D_IO
2
V CCPD_VBUS VBUS to 3.3V DY
R 3736
0R2J-2-GP
U3702 3 D3V_S5 V CCPD_VBUS
P D_SW D_CLK
1
6 1
5 IN OUT 2
V REG3PD
Vince,20161110
NC#5 NC#2
1
TPS70933_EN 4 3 T P3703 1 TPAD14-OP-GP P D_XRES

EN GND R 3739
7 TypeC R 3738 TypeC 100KR2J-1-GP
GND
10KR2J-3-GP TypeC
2
2
SC2D2U10V3KX-1GP
C3710
TPS70933DRVR-GP-U C 3709 Q 3701 TypeC

SCD1U16V2KX-3GP
1
T PS70933_EN_G <Core Design>

SC1U50V3KX-GP
G
C3707
A A
D T PS70933_EN
Wistron Corporation
2
RF C 3720
TypeC S 2 1F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
TypeC Vince,20161110 TypeC TypeC Taipei Hsien 221, Taiwan, R.O.C.
1
SCD22U10V2KX-1GP
2N7002K-2-GP
Title
(Reserved)
A3
S tarlord KBL-R A00
5 4 3 2 1
5 4 3 2 1
R 3832 1 0R0402-PAD
Main Func = TYPEC MUX 3 D3V_MUX 2
T YPEC_CON_TXP1
1
Vince,20161012 R 3818
10KR2J-3-GP TypeC
R 3821
4K7R2J-2-GP M UX_TYPEC_TXP1 C 3864 1TypeC
2 SCD1U16V2KX-3GP M UX_TYPEC_TXP1_C
DY
M UX_TYPEC_TXN1 C 3863 1TypeC
2 SCD1U16V2KX-3GP M UX_TYPEC_TXN1_C
3 D3V_MUX T YPEC_CON_TXN1
2
U 3801 C AD_SNK
1 38 E Q0
6 V CC E Q0 35 E Q1 H PDIN
20 V CC E Q1
28 V CC 32 H PDIN R 3833 1 2 0R0402-PAD
V CC H PDIN/DCI_CLK 29 C AD_SNK R 3836 1 2 0R0402-PAD
DisplayPort Source C AD_SNK/DCI_DAT
C 3812 1TypeC
2 SCD1U16V2KX-3GP P CH_DPC_P0_C 9 17 I 2CEN R 3834 1 2 0R0402-PAD
[8] PCH_DPC_P0 D P0P I 2C_EN
C 3813 1TypeC
2 SCD1U16V2KX-3GP P CH_DPC_N0_C 10
D [8] PCH_DPC_N0 D P0N D
C 3814 1TypeC
2 SCD1U16V2KX-3GP P CH_DPC_P1_C 12
[8] PCH_DPC_P1 D P1P
C 3807 1TypeC
2 SCD1U16V2KX-3GP P CH_DPC_N1_C 13 27 U SBC_DPAUX1 M UX_TYPEC_RXP2 T YPEC_CON_RXP2 T YPEC_CON_RXP1
[8] PCH_DPC_N1 D P1N S BU1
C 3809 1TypeC
2 SCD1U16V2KX-3GP P CH_DPC_P2_C 15 26 U SBC_DPAUX2
[8] PCH_DPC_P2 D P2P S BU2
C 3808 1TypeC
2 SCD1U16V2KX-3GP P CH_DPC_N2_C 16 TypeC M UX_TYPEC_RXP1
[8] PCH_DPC_N2 D P2N
C 3811 1TypeC
2 SCD1U16V2KX-3GP P CH_DPC_P3_C 18 24 D PB_AUXP_C SCD1U16V2KX-3GP 2 1 C 3801
[8] PCH_DPC_P3 D P3P A UXP D PB_AUXP [8]
C 3810 1TypeC
2 SCD1U16V2KX-3GP P CH_DPC_N3_C 19 TypeC 25 D PB_AUXN_C SCD1U16V2KX-3GP 2
TypeC1 C 3802 M UX_TYPEC_RXN1
[8] PCH_DPC_N3 D P3N A UXN D PB_AUXN [8] M UX_TYPEC_RXN2 T YPEC_CON_RXN2
M UX_TYPEC_RXP1 30
M UX_TYPEC_RXN1 31 R X1P 14 D PEQ0_A1 T YPEC_CON_RXN1
M UX_TYPEC_RXP2 40 R X1N D PEQ0/A1 2 D PEQ1
M UX_TYPEC_RXN2 39 R X2P D PEQ1
R X2N 11 S SEQ0_A0
M UX_TYPEC_TXP1 33 S SEQ0/A0 3 S SEQ1
M UX_TYPEC_TXN1 34 T X1P S SEQ1 R 3835 1 2 0R0402-PAD
M UX_TYPEC_TXP2 37 T X1N R 3837 1 2 0R0402-PAD
M UX_TYPEC_TXN2 36 T X2P 21 I 2C_CLK_PD_MUX 0R2J-2-GP TypeC
2 1 R 3814
USB HOST T X2N F LIP/SCL I 2C_CLK_PD [37]
R 3838 1 2 0R0402-PAD
[16] USB30_RX_CPU_P4 C 3805 1TypeC
2 SCD1U16V2KX-3GP U SB30_RX_CPU_P4_C 5 22 I 2C_DATA_PD_MUX 0R2J-2-GP TypeC
2 1 R 3816
SCD1U16V2KX-3GP U SB30_RX_CPU_N4_C 4 S SRXP C TL0/SDA 23 C PU_DP_HPD I 2C_DATA_PD [37]
[16] USB30_RX_CPU_N4 C 3806 1TypeC
2 0R2J-2-GP 2 TypeC 1 R 3849
C PU_DP_HPD_R [8,37,57]
S SRXN C TL1/HPDIN
C 3803 1TypeC
2 SCD1U16V2KX-3GP U SB30_TX_CPU_P4_C 8 T YPEC_CON_TXP2
[16] USB30_TX_CPU_P4 S STXP
C 3804 1TypeC
2 SCD1U16V2KX-3GP U SB30_TX_CPU_N4_C 7 41
[16] USB30_TX_CPU_N4 S STXN G ND
M UX_TYPEC_TXP2C 3861 1TypeC
2 SCD1U16V2KX-3GP M UX_TYPEC_TXP2_C
TUSB546-DCIRNQR-GP
3 D3V_MUX M UX_TYPEC_TXN2C 3862 1TypeC
2 SCD1U16V2KX-3GP M UX_TYPEC_TXN2_C
T YPEC_CON_TXN2
TypeC D PB_AUXN_C
R 3801 1 2 100KR2J-1-GP
R3802 1 2 100KR2J-1-GP D PB_AUXP_C

TypeC Vince,20161026
R 3839 1 2 0R0402-PAD
3 D3V_S5 3 D3V_MUX
3 D3V_MUX 3 D3V_MUX 3 D3V_MUX 3 D3V_MUX 3 D3V_MUX
3 D3V_MUX
3D3V_MUX
L 3801
1 TypeC 2 E D3806
1
1
C C
1
R 3842 3874 R 3847 R 3871 R 3852 R 3845 T YPEC_CON_TXP1 1 1 0 T YPEC_CON_TXP1

DY R 3840 TypeCR1KR2J-1-GP DY DY DY DY BLM15AX221SN1D-GP C 3820 C 3817 C 3818 C 3816 C 3819
1
1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP C 3815
DY
1
1KR2J-1-GP
TypeC TypeC TypeC TypeC TypeC TypeC T YPEC_CON_TXN1 2 9 T YPEC_CON_TXN1
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
3 8
TypeC
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
2
2
EQ0 E Q1 I 2CEN D PEQ1 D PEQ0_A1 S SEQ1 S SEQ0_A0
2
2
T YPEC_CON_RXP1 4 7 T YPEC_CON_RXP1
1
1
T YPEC_CON_RXN1 YPEC_CON_RXN1
2
2
R 3843 R 3873 R 3870 R 3872 R 3846 5 6 T
TypeC 1KR2J-1-GP R 3841 TypeC DY 1KR2J-1-GP 1KR2J-1-GP
TypeC TypeC 1KR2J-1-GP R 3844TypeC TypeC1KR2J-1-GP
20KR2F-L-GP 20KR2F-L-GP
L05ESDL5V0NA-4-GP
2
2
1
1
Vince,20170721 Vince,20170721 E D3802
T YPEC_CON_RXN2 1 1 0 T YPEC_CON_RXN2
T YPEC_CON_RXP2 2 9 T YPEC_CON_RXP2
3 TypeC 8
V CCPD_VBUS V CCPD_VBUS T YPEC_CON_TXN2 4 7 T YPEC_CON_TXN2

V CCPD_VBUS
Vince,20160922 T YPEC_CON_TXP2 5 6 T YPEC_CON_TXP2
U SB1
A1 B1 L05ESDL5V0NA-4-GP
T YPEC_CON_TXP1 A2 G ND G ND B2 T YPEC_CON_TXP2
T YPEC_CON_TXN1 A3 S STXP1 S STXP2 B3 T YPEC_CON_TXN2
S STXN1 S STXN2
1
C 3821 A4 B4
A5 V BUS#A4 V BUS#B4 B5
SCD1U25V2KX-GP
TypeC [37] U SBC1_CC1_CONN TOP_MUX_P A6 C C1 C C2 B6 B OT_MUX_P U SBC1_CC2_CONN [37]

D P1 D P2
2
T OP_MUX_N A7 B7 B OT_MUX_N
U SBC_DPAUX1 A8 D N1 D N2 B8 U SBC_DPAUX2
A9 R FU1 R FU2 B9
T YPEC_CON_RXN2 A10 V BUS#A9 V BUS#B9 B10 T YPEC_CON_RXN1
T YPEC_CON_RXP2 A11 S SRXN2 S SRXN1 B11 T YPEC_CON_RXP1
S SRXP2 S SRXP1
1
B A12 B12 B
G ND G ND
1
R 3831
R 3830 TypeC 2MR2F-GP
2MR2F-GP TypeC
TypeC
2
13
C HASSIS#13
2
16 14
17 G ROUNDC HASSIS#14 15
G ROUNDC HASSIS#21 22
C HASSIS#22
3 D3V_MUX E D3801
U 3802 SKT-USB34-21-GP-U E D3805
2 U SBC1_CC1_CONN
13 18 T OP_MUX_P_L 2 B OT_MUX_P
V CC O UTA0+ 17 T OP_MUX_N_L 3
O UTA0- 20 3
TypeC
1 O UTA1+ 19
TypeC 1 U SBC1_CC2_CONN
[16] USB_CPU_PP3 2 I NA+ O UTA1- 8 B OT_MUX_P_L B OT_MUX_N
1
[16] USB_CPU_PN3 M UX_INB_N 3 I NA- O UTB0+ 9 B OT_MUX_N_L
R 3854 1 2 0R2J-2-GP
TypeC
[24] TypeC_SMBCLK 1 2 0R2J-2-GP M UX_INB_P 4 I NB+ O UTB0- 6
R 3853 TypeC
[24] TypeC_SMBDA I NB- O UTB1+ 7 AZ5315-02F-GP
Vince,20170517 O UTB1-
AZ5315-02F-GP
1 2 0R2J-2-GP M UX_SAI 14
TypeC 16 M UX_ENA_L
[37] CCG4_FLIP# R 3855 TypeC R 3859 1 2
TypeC 0R2J-2-GP D OCK_USB_EN_A [37]
R 3856 1 2 0R2J-2-GP M UX_SBI 12 S AI E NA 10 M UX_ENB_L R 3860 1 2 0R2J-2-GP
TypeC S BI E NB TypeC D OCK_USB_EN_B [37]
1 M UX_SAO 15
R 3857
1
TypeC2 2R2F-GP
M UX_SBO 11 S AO 5
3D3V_MUX
R 3858 TypeC2 2R2F-GP
S BO G ND 21 E D3803
G ND
Vince,20161028 E D3804
2 U SBC_DPAUX1
T OP_MUX_P
1
TypeC TS3DS10224RUKR-GP 2
C3865 3 TypeC
3 TypeC
2
1 U SBC_DPAUX2
SCD1U16V2KX-3GP
1 T OP_MUX_N
Vince,20161004
Vince,20160929 AZ5315-02F-GP AZ5315-02F-GP
A A
R 3862 1 DY 2 0R2J-2-GP R 3863 1 DY 2 0R2J-2-GP
E L3801
TOP_MUX_P_L 1 2 T OP_MUX_P B OT_MUX_P_L 4 3 B OT_MUX_P <Core Design>
TOP_MUX_N_L 4
TypeC 3 T OP_MUX_N B OT_MUX_N_L 1
TypeC 2 B OT_MUX_N
E L3802
COIL-90OHM-100MHZ-5-GP 2 1F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
R 3861 1 DY 2 0R2J-2-GP R 3864 1 DY 2 0R2J-2-GP Title
( Reserved)
Size
A 2
Document Number
S tarlord KBL-R
1
Sheet 38 o f
Rev
A 00
106
5 4 3 2 1
D D
C C
B B
A A
<Core Design>
itle
T Title
( Reserved)
A 2
5 4 3 2 1
5 4 3 2 1
SSID = Power Plane & Sequence P ower Good 3 D3V_S0
1
R 4005
R 4011 1KR2J-1-GP
[51] 1 D2V_VTT_PWRGD 1 2
2
ROSA Run Power
0R0402-PAD
D 4002 R UNPWROK [17,24]
change common part PN:074.05027.0093, 20170110 R SMRST_PWRGD# R 4002
K A
1 2
V R_EN [46]
C 4001 DY
1 2 RB751V-40H-GP 0R0402-PAD
R 40101 2 3 D3V_S5 + 3VALW_EC
0R2J-2-GP 5 V_S5 SC470P50V2KX-3GP
C 40021 2 [#543016] Optional, Added for addition system robustness
D
5 V_S5 U 4001 D
3 D3V_S5 SC470P50V2KX-3GP
4 12 3 V5V_CT1 5 V_S0 R 4032
1
U 4003 R 4031
1 5 V BIAS C T1 10 3 V5V_CT2 100KR2J-1-GP 100KR2J-1-GP
[17,27,51,54] S IO_SLP_S3# A V CC C T2
R 4012 DY
LP_S0_U 2 1 13
[17,24,60,91] SIO_SLP_S0# 1 DY 2S
0R2J-2-GP B 2 V IN1#1 V OUT1#13 14
DY 3 D3V_S0
3 V5V_S0_ON V IN1#2 V OUT1#14
2
3
1
4
G ND Y 6 8 C 4005 R SMRST_PWRGD#
U74LVC1G08G-AL5-R-GP-U 3 D3V_S5 7 V IN2#6 V OUT2#8 9 SC10U6D3V3MX-DL-GP
V IN2#7 V OUT2#9
2
[52] 1 D0V_S5_PWRGD R 4029 1 2
5 V_S0_ON
1
3 0R0402-PAD
3 D3V_S0_ON 5 O N1 11 C 4004 R 4030 1 2
O N2 G ND [24,54] 1 D8V_S5_PWROK
15 SC10U6D3V3MX-DL-GP 0R0402-PAD
For modern standby T HERMAL_PAD
2
[17,45,52,54] 3 V_5V_POK R 4033 1 DY 2
0R2J-2-GP
TPS22976DPUR-GP NON DS3: PH 3V_5V_POK to 3D3V_AUX_S5 at page17
R 4013 R 4014
3 V5V_S0_ON 1 2
0R2J-2-GP
5 V_S0_ON 3 V5V_S0_ON1 2
0R2J-2-GP
3 D3V_S0_ON
5V_S0 VCCIO and VCCSTG
5V_S0 Comsumption change common part PN:074.05027.0093, 20170302
1
1
C 4010 C 4011 Peak current 5A
DY SCD22U10V2KX-1GP DY SCD22U10V2KX-1GP
3D3V_S0
2
2
3D3V_S0 Comsumption 1 D0V_S5 + VCCIO_SIP + VCCIO
Peak current 2.5A 5 V_S5
SC1U10V2KX-1GP
1
C 4006
C
4032
D 4001
1
SC10U6D3V3MX-GP
2 1 R 4045 2
2
[45] 1 3
3 V_5V_EN P URE_HW_SHUTDOWN# [26]
2
U 4002 0R1206-PAD
+ VCCSTG
LBAS16LT1G-GP
1
C 1 8 C
2 I N#1 O UT#8 7
R 4006 N#2
1 R 4042 2
20KR2F-L-GP 9 I O UT#7 6 0R0402-PAD
N#9 O UT#6
SCD1U16V2KX-3GP
C 4008
I
R 4017
1
3
4 V BIAS
2
1 2V CCSTG_EN_R 5 C 4007 DY
[17,27,51,54] S IO_SLP_S3# O N G ND
1
R 4009 1 2 10KR2J-3-GP 0R0402-PAD
SCD1U16V2KX-3DLGP
A LWON [24]
2
SC1U10V2KX-1GP
C 4033
G5027RD1D-GP-U
SC10U6D3V3MX-GP
C 4009
2
1
DY
1
2
D VT1 0210
2
modify at DVT1 power sequence 20150203
20150116 2032
Vince,20161012
EOPIO and EDRAM Vince,20161027
+V_EDRAM_VR
Imax = 6 A
Voltage = 1.0 V ± 50 mV
Imax = 3.2 A V1.8S Vince,20161012
Rds on = 4.65mohm TRISE = 240 us
B
+V_EOPIO_VR
Voltage = 1.0 V ± 50 mV
B
Imax = 2.8 A
TRISE = 240 us
Vince,20161012
Vince,20161012 Vince,20161012
MANAGEMENT RAIL POWER GENERATION VCCST, VCCSTG, and VCCPLL can remain powered during S4 and S5 power states for board VR optimization.
+ V1.00U_CPU
+ VCCST_CPU
VCCST R 4036 1 2
0R0402-PAD
+ VCCSFR
R 4038 1 2
0.04 A
0R0402-PAD
Vince,20161031 change common part PN:074.05027.0093, 20170110
1 D0V_S5
5 V_S5
1
SC1U10V2KX-1GP
SC10U6D3V3MX-GP
C4031
C4013
1
+ V1.00U_CPU
DY
2
U 4006
2
A 1 8 A
2 I N#1 O UT#8 7
9 I N#2 O UT#7 6
I N#9 O UT#6
R 4024
1
3 C 4012
1 2 V CCSTU_EN_R 4 V BIAS 5 SC10U6D3V3MX-GP
[17,54] S IO_SLP_S4# O N G ND <Core Design>
2
0R0402-PAD
1
G5027RD1D-GP-U
SC1U10V2KX-1GP
C4034
DY
2
Title
P ower Plane Enable

Size
A 2
Document Number

S tarlord KBL-R
1
Sheet 40 o f
Rev
A 00
106
5 4 3 2 1
Main Func = Power Plane & Sequence
3D3V_S5 3D3V_S5_PCH
D R4101 D
1 2
0R0805-PAD Reserve by NON DS3 function 20150413
Vince,20161031
C C
DS3
B B
<Core Design>
A
Title
Connected_Standby(1/2)+DS3
A4
Starlord KBL-R A 00
5 4 3 2 1
5 4 3 2 1
Main Func = DIMM1

Main Func = DIMM2
D D
C C
B B
A <Core Design> A
Wistron Corporation
TTitle
itle
Connected_Standby(2/2)
A3
Starlord KBL-R A 00
WWW.AliSaler.Com
5 4 3 2
1
42 of 106
5 4 3 2 1
SSID = ADT Input 5 V_S5
2
3 D3V_S5
1
P R4302
15KR2F-GP P R4303
20170623 Reserve
2
10KR2J-3-GP
P Q3802_1 3 D3V_S5
1
1 P Q4302
1
PMBS3904-1-GP
2
2
P D4302 P R4314
P SID_DISABLE#_R_C
1
P R4309 LBAV99LT1G-1-GP
100KR2J-1-GP P R4304 1 2 0R2J-2-GP
2K2R2J-2-GP
Layout Note:
P Q4301
3
PSID Layout width > 25mil P D4309
2
G
D P R4305 D C_IN_OK A DY K D
P S_ID_R 1 2 P S_ID_R2 D P S_ID_R1 1 2 BAT54TM-GP
P S_ID [24]
D C_IN_OK_R
P D4310
2 0140815 david P R4317 S 33R2J-2-GP
0R0603-PAD-1-GP-U PJA138KA-GP P D_VBUS_P_CTRL1
A DY K
1
BAT54TM-GP
E L4304
1
1 2 P D4303 P R4329 DY
J GND L30ESD24VC3-2-GP 1MR2J-1-GP
0R5J-5-GP
2
Pin Definition: TBD E L4303
3
1 2 P R4306
1 DY 2
D CIN1 0R5J-5-GP
9 60ohm@100MHz 33R2J-2-GP
+ SDC_IN
1 DCR=0.02 ohm
Max current = 6000mA
2 1 A FTP4301
3 1 A FTP4302 + DC_IN A D+
4 P U4301 TypeC P U4302
5 E L4301 1 S D8 8 D S 1
SC10U25V3MX-GP
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
240KR3-GP
P C4305
P C4303
P C4304
P C4306
6 + DC_IN_C 1 2 2 S D7 7 D S 2
1
7 0R5J-5-GP P C4302 3 S D6 6 D S 3
SC10U25V3MX-GP
SCD1U25V2KX-GP
SC1U50V3KX-GP
E C4302
P R4307
P R4316
P R4318
20KR2J-L2-GP
100KR2J-1-GP
E C4301
1
8 SCD1U50V3KX-GP 4 D5 5 4
P
G D G
C4301
1
P D4301 DY DY
10 P6AF24A-R1-00001-GP SI7121DN-T1-GE3-GP
1
P R4311
2
2
1
ACES-CON8-13-GP-U2 SI7121DN-T1-GE3-GP 100KR2F-L1-GP

Vince,20161110
2
P R4312 NON_TypeC
470KR2F-GP
TypeC
47KR2F-GP
P Q4305
E L4302
2
1
R2
1 2 P R4326 P Q4304 2 Id=-9.6A P D4305
P R4308
2
J GND C A D_OFF_L 1
JGND 0R5J-5-GP
1 2 0R2J-2-GP A C_DIS_R B R 1
1
R
3 A D_OFF_R Qg=-25nC D C_IN_OK A
NON_TypeC
K
2016/01/07 mofiy [24] A C_DIS Rdson=18~30mohm A COK_IN_M [17,44]
2
E
R2 LTA024EUB-FS8-GP RB751V-40H-GP
P R4315
18K7R2F-GP
2
A C_IN#_G P D4307 LMUN5212T1G-GP
1
A DY K R 4303 V CCPD_VBUS
NON_TypeC
If=0.3A + SDC_IN_SW_R1 1 2 +SDC_IN_SW
1
BAT54TM-GP P R4333
C 1KR2F-3-GP PD_VBUS_C_CTRL1 = 1 (Consumer Path OFF) C
PD_VBUS_C_CTRL1 = 0/Z (Consumer Path ON) 10KR2F-2-GP

1
1
2
P R4313 P R4343 2 0150520_ EC097
71K5R2F-1-GP 200KR2F-L-GP
TypeC
DC_IN_OK G
PQ4306
3 D3V_S5
TypeC P Q4313 + SDC_IN
2
2
I E_DELAY_G 3 4 V CCPD_VBUS
PD_VBUS_C_CTRL1_A
ote:ZZ.27002.F7C01
D
K
2 P BAT_PRES# U SB_ADT
TypeC5 TypeC TypeC
S P D4308
P U4307 DY BAT54TM-GP I E_DELAY_S 1 6 P U4303 P U4304
SC100P50V2JN-3GP
+ SDC_IN
1
2N7002K-2-GP TypeC 1 S D8 8 D S 1
680KR2J-GP
1 6 P C4315 2N7002KDW-1-GP P D_VBUS_C_CTRL1_A 2 S D7 7 D S 2
N C#1 V CC TypeC
A
D C_IN_OK
1
2 5 SC100P50V2JN-3GP 3 S D6 6 D 3
A DY N C#5 S
P R4336
2
D C_IN_OK#
2
3 4 P C4314 4 G D5 5 D 4 P R4320
G ND Y TypeC TypeC G
P C4310
P R4344 240KR2F-L-GP
3 D3V_S5 V CC3PD 680KR2J-GP SI7121DN-T1-GE3-GP SI7121DN-T1-GE3-GP
TypeC TypeC
1
SN74AUP1G04DRYR-GP
SC1U25V2KX-2-GP
2
U SB_ADT_SW
AFTP4303 1 +DC_IN_C U SB_TYPEC_R U SB_ADT
240KR2F-L-GP
47KR2F-GP
V CCPD_VBUS
1
PS_ID_R
10KR2F-2-GP
1
AFTP4304
20170622 Reserve
2
1
AFTP4305 1 +DC_IN_C P R4335
P R4337
P R4321
1
1
100KR2J-1-GP TypeC
P R4322
2
TypeC TypeC P R4319
P Q4311 100KR2F-L1-GP + SDC_IN_SW_R1 TypeC
TypeC
2
U 4302 4 3 TypeC 12K4R2F-GP

P Q4307 P Q4308
1
2
P R4327
ote:ZZ.27002.F7C01
P Q4310
2
AC_IN#_G 5 1 D C_IN_OK V BUS_PRODECT# 5TypeC 2 4 3 U SB_TYPEC_SW U SB_ADT_SW_R 3 4
S ENSE O UT D C_IN_OK [24]
1
2 V CC3PD 4 3
ote:ZZ.27002.F7C01
ote:ZZ.27002.F7C01
IC_DELAY 4 V DD 3 6 1 P D_VBUS_C_CTRL1_A 5TypeC 2 D C_IN_OK_R 2
C D TypeC V SS TypeC5
ote:ZZ.27002.F7C01
D C_IN_OK 5TypeC 2
Vince,20170519
N
2N7002KDW-1-GP 6 1 1 6 U SB_ADT_R1
C CG4_OVP_TRIP_P1 U SB_TYPEC_DIS
100KR2F-L1-GP
1
6 1
N
1
PC4307 TypeC P R4342 2N7002KDW-1-GP 2N7002KDW-1-GP P D4306
P R4332
SC100P50V2JN-3GP
1
SC1KP50V2KX-1DLGP 100KR2F-L1-GP VBUS overvoltage 2N7002KDW-1-GP TypeCK
P C4311
A
TypeC
TypeC output indicator (active LOW)
2
P D_VBUS_C_CTRL1_R COK_IN_M [17,44]
1
P Q4312 A
Vince,20161004
2
2
G RB751V-40H-GP TypeC
[37] P D_VBUS_C_CTRL1
2
100R2512J-1-GP
2
D P D_VBUS_C_CTRL1_R
TypeC P R4338 P D_VBUS_DISCHG [37]
2K2R2J-2-GP
1
R4328
B
TypeC If=0.3A P B
1
S P R4323 TypeC
1
VBUS_C_CTRL = 1 (Consumer Path ON) P R4325 TypeC 100KR2F-L1-GP
1
100KR2F-L1-GP 2N7002K-2-GP V CCPD_VBUS
VBUS_C_CTRL = 0/Z (Consumer Path OFF) TypeC U SB30_VCCB
2
P U4305 P U4306
2
8 D S 1 T YPEC_5V_SW 1 S D 8
7 D S 2 2 S D 7
6 D S 3 3 S D 6
240KR2F-L-GP
5 D D 5
G G
2
SSID = M-BAT Input
SI7625DN-T1-GE3-GP SI7625DN-T1-GE3-GP
4
SCD1U25V2KX-GP
2
P R4330
TypeC TypeC
P C4312
TypeC
PD_VBUS_DISCHG = 1 (VBUS Discharging)
1
Placement: Close to Batt Connector PD_VBUS_DISCHG = 0/Z (VBUS not discharging)
1
Vince,20161013
BT+
Batt Connecter TypeC
PBAT_CHG_SMBDAT
PBAT_CHG_SMBCLK
T YPEC_5V_SW_R
PD_VBUS_P_CTRL1 = 1 (Provider Path ON) P R4339
PBAT_PRES#
K
1
DY DY 64K9R2F-1-GP
PD_VBUS_P_CTRL1 = 0/Z (Provider Path OFF)
1
EC4308 EC4307 P D4304

SCD1U50V3KX-GP SCD1U25V2KX-GP DY SMF18A-GP TypeC
P Q4309
2
P R4341
A
2
P R4310 T YPEC_5V_L 4 3 T YPEC_5V
3
B ATT1 1KR2J-1-GP 0R0402-PAD-1-GP
ote:ZZ.27002.F7C01
1 N P1 D 4304 D 4305 D 4306 1 2 P D_VBUS_P_CTRL1_R 5TypeC 2 C CG4_OVP_TRIP_P1_G 1 TypeC2
[37] P D_VBUS_P_CTRL1 C CG4_OVP_TRIP_P1 [37]
2
LBAV99LT1G-1-GP LBAV99LT1G-1-GP LBAV99LT1G-1-GP TypeC T YPEC_5V_L 6 1
R N4302
1
4 5 3
VBUS overvoltage
N
P BAT_SMBCLK1 4
2
3 6
[24,44] PBAT_CHG_SMBCLK Vince,20161004 P R4324 2N7002KDW-1-GP P R4340 P C4313
output indicator (active LOW)
1
2 7 P BAT_SMBDAT1 5 100KR2F-L1-GP
[24,44] PBAT_CHG_SMBDAT 1 8 P BAT_PRES1# 6 TypeC DY
Id=115mA
100KR2F-L1-GP
SCD1U25V2KX-GP
[24] PBAT_PRES# TypeC
1
1 R 4301 2 S YS_PRES1# 7
2
SRN100J-4-GP 0R0402-PAD 8
9
Vince,20161013 10 N P2
+ 3VALW_EC
A ETY-CON10-28-GP-U A
EC4309 E C4310 E C4306

1
1 A FTP4306
1
SC10P50V2JN-4GP
SC10P50V2JN-4GP
SC10P50V2JN-4GP
DY DY DY 1
A FTP4307
<Core Design>
A FTP4308
2
P BAT_PRES1# 1 A FTP4309 Taipei Hsien 221, Taiwan, R.O.C.
P BAT_SMBDAT1 1 A FTP4310
P BAT_SMBCLK1 1 A FTP4311 Title
B T+ 1 A FTP4312
B T+ 1
B T+ 1
A
A
FTP4313
FTP4314 Size Document Number
D CIN Rev
S YS_PRES1# 1 A FTP4315 A 2
5 4 3 2 1
5 4 3 2 1
Main Func = Charger
SDC_IN CBATOUT
+ D
R4402
D01R3721F-GP-U
P
1 2
D D
1
G4402 G4403
GAP-CLOSE-PW
P R-6-GP GAP-CLOSE-PW
P R-6-GP
2
Vince,20161011
G_1
G_2
R4414
1P
1P
R4444 2R2F-GP
P
0R0402-PAD-1-GP
P CBATOUT HARGER_SRC
D G4404 C
C4402 GAP-CLOSE-PW
P R-3-GP
SCD1U25V2KX-GP
P
2
2 1 SB_ADT
1 2 G4405 U
GAP-CLOSE-PW
P R-3-GP D4409
P CBATOUT
2 1 D
G4406
TypeC
K A
C4403 C4404 GAP-CLOSE-PW
P R-3-GP W R_CHG_PHASE_1 CBATOUT RB751V-40H-GP
1
P P P D
2 1 U4403
If=0.3A
S
DY DY D4411
P
G4407 P P C4425
C2200P50V2KX-2GP
C2200P50V2KX-2GP
2
2
WR_CHG_ACP
WR_CHG_ACN
GAP-CLOSE-PW
P R-3-GP C4434 D+ E
1
8 D S 1 SC2200P50V2KX-2GP
P K A A
SB_ADT D4407 2 1 7 D S 2 RB751V-40H-GP
S
U 6 D S 3 1 SB_ADT_D1 DY
RB751VM-40TE-17-GP
P DY2
C2D2U10V2KX-GP
2
5 D G 4 U
A K CBATOUT SI7121DN-T1-GE3-GP If=0.3A
D HARGER_SRC R4442
TypeC
1
C
Vf=0.25V @ 30mA 470KR2J-L1-GP
P
U
R4410 R4403
SB_ADT_D
D4406 P
1KR2F-3-GP P
100R5F-2-GP
P
RB751VM-40TE-17-GP W R_VBAT T+
D+ 2 1 P 1 2 B
2
A A K RF request 2016/01/12 modify
SC2200P50V2KX-2GP
C4405 C4406 C4407 C4408 C4409
SC1KP50V2KX-1GP
SCD1U25V2KX-GP
SCD22U25V3KX-GP
1
Vf=0.25V @ 30mA P P P P P
S
1
1
SC1KP50V2KX-1GP
C10U25V5KX-GP
C10U25V5KX-GP
C10U25V5KX-GP
C10U25V5KX-GP
CD1U25V2KX-GP
2
2
1
DY DY
C4426
C4437
1
DD
VAC DET R4408
C4410
C4411
2
2
1 P
P
V 300KR2F-GP
P T+
C4436
Greater than 2.633 V
P
B
Less than 3.5 V
1 P
2
2
1
100KR2F-L2-GP
W R_CHG_ACDET C4435 C4415 C4433

R4471
SCD1U50V3KX-GP
25 WR_CHG_BATDRV
2
P
5
6
7
8
C U4404 P P P C
P
D
D
D
D
3VALW_EC DD
AC_IN:3.35~3.75V
S
P
AON7410-GP
31 WR_CHG_ACN
32 WR_CHG_ACP
WR_CMSRC
+ Q4415 V
30 WR_ASGATE
C4416
C10U25V5KX-GP
C10U25V5KX-GP
C10U25V5KX-GP
P
2
28 WR_OPCN
27 WR_OPCP
C4413 W R_CHG_REGN
P
1
4 3 P R4409
A
1
P
37K4R2F-1-GP
P
[24] w_ACAV_IN
COK#
5 2
G
S
S
S
P
P
h
2
C2D2U10V2KX-GP
[17,43] COK_IN_M
29
26
2
4
3
2
1
2
R4438 R4439 R4445 6 1 R4443 R4422 U4401 L4401 R4415
A
ote:ZZ.27002.F7C01
1
1
P P P P P P P P
D01R3721F-GP-U T+
N
2
2N7002KDW -1-GP B
BAT
SIN
PCN
SIP
MSRC
PCP
GATE
SGATE
W R_CHG_PHASE
1 0KR2F-2-GP
1 0KR2F-2-GP
1 00KR2F-L2-GP
1
P 1 2 1 2
DY DY DY COIL-4D7UH-33-GP
00KR2F-L-GP
00KR2F-L2-GP
C
R4447 C4414
V
Q
Q
P P
B
0R0603-PAD-1-GP-U SCD22U25V3KX-GP C4418 C4419
C
2
1
1 24 W R_CHG_BTST W R_CHG_BTST1 C4417 P P
CIN OOT P 2P
1
Vince,20161013 1 1 2
S
GAP-CLOSE-PW R-3-GP G4412 G4413 P
A B
5
6
7
8
G4408 W R_CHG_ACOK 2 23 W R_CHG_HIDRV U4405 P P
C10U25V5KX-GP
CD1U25V2KX-GP
2
2
P COK GATE P
D
D
D
D
2 1
S
P P
AON7410-GP
G
W R_CHG_SDA A U
G4409 GAP-CLOSE-PWR-6-GP 3 22 W R_CHG_PHASE
C10U25V3MX-GP
AP-CLOSE-PWR-6-GP
AP-CLOSE-PWR-6-GP
2
2
[24,43] BAT_CHG_SMBDAT P 1 2 P DA HASE P
P S P
G4410 GAP-CLOSE-PWR-6-GP W R_CHG_SCL 4 21 W R_CHG_LODRV
P 1 2 P CL GATE P
S ISL88739HRZ-T-GP-U L
W R_CHG_PROCHOT# 20 W R_CHG_REGN DD
G
S
S
S
G4419 GAP-CLOSE-PWR-3-GP 5 R4412
P 2 1 P ROCHOT# DDP P V 4D7R3F-L-GP
P
WR_CHG_SRN_1
WR_CHG_SRP_1
GAP-CLOSE-PW R-3-GP P V
4
3
2
1
[24,43] BAT_CHG_SMBCLK W R_CHG_IADP
P G4401 6 19 DD hange MLCC size to release spacing to EE placement
[24] D_IA P MON DD
Vince,20160926 A P 2 GAP-CLOSE-PW
1 R-3-GP
W R_CHG_IDCHG 7
A V
V
18 W R_CHG_VCC
1 2 C
[24] oost_mon G4414
P 2 1 P MON CIN P
b B D C4428 C4431
1
[4,24,46] _PROCHOT# Vince,20170105 [46] _SYS G4415
2 1
W R_CHG_PMON
P
8
C#8 TC
17 W R_CHG_NTC
P
P P
S
P
P
H P GAP-CLOSE-PW R-3-GP N N
C1U10V2KX-1GP
C1U10V2KX-1GP
ATGONE
R4411
1
R4437 P
2R2F-GP R4448
SC2200P50V2KX-2GP
SC2200P50V2KX-2GP
SC2200P50V2KX-2DLGP
1
1
C4423
C4424
C4430
R4401
CLIM
P P
CLIM
OMP
ROG
SON
33
SOP
0R0402-PAD-1-GP
SET
21KR2F-3-GP1
ND
4
G
P
SB_ADT
9K9R2F-L-GP
D4405 C4420
2
10 C
11 C
14 C
15 C
U
9 P
13 B
16 A
12 F
R4407 P
RB751VM-40TE-17-GP P
SCD1U25V2KX-GP
2
P W R_CHG_1
2
1
2D2R5J-1-GP 2 P K TypeCA C4421 1 2 DY
C4412 D4402 If=0.3A D+ P
SC2200P50V2KX-2GP C4422
1
P P A P
SC1U50V3KX-1-GP RB751VM-40TE-17-GP
S
DY
WR_CHG_BATPRES#
W R_CHG_REGN K A
C2200P50V2KX-2GP
2
2
P If=0.3A T+
WR_CHG_COMP
WR_CHG_PROG
D4401
WR_CHG_FSET
P B
RB751VM-40TE-17-GP
WR_CHG_ILIM
R4420 R4421 K A
1
P P If=0.3A
1
W R_CHG_SRP
P
0KR2F-2-GP
0KR2F-2-GP
P
W R_CHG_SRN
B P P B
2
CLIM
A
100R2F-L1-GP-U
R4416 1
R4423 R4424
1
P P
1
C560P50V2KX-2GP
D+
P
A
DY
00KR2F-L1-GP
DY
00KR2F-L1-GP
2150KR2F-L-GP
C4427
1
2
R4433
R4430
DY
2
P
R_2
100KR2J-1-GP
2
P
P
P
1
R4431
P
SCD022U16V2KX-3DLGP
R4449
2
1
P
1KR2F-3-GP
1
S
C4432
0R0402-PAD-1-GP
2
2
P
2
1
R4436
P
1MR2J-1-GP
Switching frequency is 350KHz DY
Q4408_E
_PROCHOT# [4,24,46]
H
2
D4404
1
P
2 P
R4455
P
L1SS355T1G-GP 0R0402-PAD-1-GP
D4403_A Q4408
K AP 1 P
PMBS3906-GP
D4403_K Q4405
P
2
P
Q4405_3
3
4462 P 3 4
R
1
R4458 Q4408_C
P Q4405_2
P Q4405_5
P
P 2 1 2 5
0R0402-PAD-1-GP
ote:ZZ.27002.F7C01
1
1 6
P
0R2J-2-GP
SC1U10V2KX-1GP
C4438
N
2
1
R4451 R4463 2N7002KDW -1-GP
2
P P
680KR2F-GP 0R2J-2-GP
CBATOUT
DY
D
P
Q4405_6
2
2
P
2
WR_CHG_ACOK
R4413
1
P
R4450
P 100KR2F-L1-GP
10KR2F-2-GP
A CHECK EE D3V_S5
3 A
1
follow custormer circuits.
2
<Core Design>
Wistron Corporation
1F,288, Sec.1, Hsin Tai W u Rd., Hsichih,
Title
Size Document Number

Charger Rev
D
Starlord KBL-R A 00
Date: Friday, December 08, 2017 Sheet 4 4 f o 106
5 4 3 2 1
WWW.AliSaler.Com
5 4 3 2 1
3 D3V_AUX_S5
SSID = PWR.Plane.Regulator_5V
1
P WR_5V 5 V_S5
P R4503
0R2J-2-GP P G4507
GAP-CLOSE-PWR-3-GP
DY
3 V_5V_POK
[17,40,52,54]
1 2
P R4530
2
0R2J-2-GP
R4504 P G4508
2 DY 1 P WR_5V_EN1_R 1P 2 P WR_5V_EN1
GAP-CLOSE-PWR-3-GP
5 V_AUX_S5
1 2
0R0402-PAD-1-GP
2
P R4515
P G4509
2
0R0402-PAD-1-GP P R4510 P G4529
D CBATOUT P WR_DCBATOUT_5V GAP-CLOSE-PWR-3-GP
1
00KR2J-1-GP
1
P G4501 DY 1 2
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP
1
1 2 P R4516
D 1 2 P WR_3D3V_EN1 D
[40] 3 V_5V_EN P G4510
2
0R0402-PAD-1-GP GAP-CLOSE-PWR-3-GP
P G4502 1 2
GAP-CLOSE-PWR-3-GP
1 2 P WR_DCBATOUT_5V P U4502
2
I N#2
P G
9 P WR_5V_PG
P C4521
Design Current=7A P G4511
GAP-CLOSE-PWR-3-GP
P G4503
P C4522 3 1 P WR_5V_BOOT
1 2 P WR_5V_BOOT_A 1
SCD1U25V2KX-1-DL-GP
2 Cyntec. 6.5*6.9*3mm 10.5A<OCP>12.6A 1 2
1
GAP-CLOSE-PWR-3-GP I N#3 B S
1
P C4523 P C4505 P C4519 DCR: 18mOhm
S
CD1U25V2KX-1-DL-GP
1 2 4 P R4502
S
C10U25V3MX-GP
C10U25V3MX-GP
C10U25V3MX-GP
I N#4 0R0603-PAD-1-GP-U Idc : 8A , Isat : 14A P G4512
2
GAP-CLOSE-PWR-3-GP
2
5 P WR_5V
P G4504 I N#5 P L4502 1 2
GAP-CLOSE-PWR-3-GP 6 P WR_5V_PH 1 2
1 2 L X#6
P WR_5V_PG 10 19 IND-2D2UH-46-GP-U1 P G4513
N C#10 L X#19 GAP-CLOSE-PWR-3-GP
1
P G4505 P C4514 P C4527 1 2
1
20
1
GAP-CLOSE-PWR-3-GP 16 L X#20
Trace used 10 mil DY P C4518 P C4515 P C4516 P C4517
DY P C4528 P C4529
S
C22U6D3V3MX-1-DL-GP
1 2 N C#16
S
DY
CD1U16V2KX-3DLGP
S
CD1U16V2KX-3DLGP
P G4527
2
S
S
SY8288CRAC-GP P G4514
C22U6D3V3MX-1-DL-GP
C22U6D3V3MX-1-DL-GP
C22U6D3V3MX-1-DL-GP
C22U6D3V3MX-1-DL-GP
C22U6D3V3MX-1-DL-GP
2
GAP-CLOSE-PWR-3-GP
2
14 P WR_5V_VOUT GAP-CLOSE-PWR-3-GP
1 2
P G4506 P WR_5V_VCC 17 O UT 1 2
GAP-CLOSE-PWR-3-GP P C4526 P R4507
V CC SC1KP50V2KX-1DLGP 1KR2F-3-GP
1 2 P WR_5V_FB
13 1 2 P WR_5V_FB_A 1 2
1
P C4524 F F
S
C2D2U10V3KX-1DLGP-U
12 P G4528 5 V_AUX_S5
E N1 GAP-CLOSE-PWR-3-GP
P WR_5V_EN1
2
11 15 P WR_5V_LDO 1 2
E N2 L DO
1
P R4513 P C4520
EN rating 25V P C4531
1
1MR2J-1-GP SC4D7U25V5KX-DL-GP
G ND
G ND
G ND
G ND
S
DY
CD1U25V2KX-1-DL-GP
EN Rising Threshold : 0.8V
2
P WR_5V_FB 20170327 DVT1
18
21
Ilimt : 8A
1
P R4551
560KR2F-GP
C C
P R4511
1KR2F-3-GP
2
1 2 P WR_5V_EN
D CBATOUT
P C4530
1
P R4512 1
SCD1U25V2KX-1-DL-GP
DY DY
200KR2F-L1-GP
2
2
SSID = PWR.Plane.Regulator_3D3V
Design Current=5A P WR_3D3V 3 D3V_S5

B D CBATOUT P WR_DCBATOUT_3D3V
P R4501 P C4506 7.5A<OCP>9A P G4519
GAP-CLOSE-PWR-3-GP
B
P G4515 0R0603-PAD-1-GP-U SCD1U25V2KX-1-DL-GP Cyntec.4.85*4.7*2.8mm 1 2

GAP-CLOSE-PWR-3-GP P WR_3D3V_BOOT 1 2 P WR_3D3V_BOOT_A 1 2
1 2 DCR: 20~25mOhm
P L4501 Idc : 6A , Isat : 10A P G4520
P WR_DCBATOUT_3D3V P U4501 COIL-1D5UH-43-GP P WR_3D3V
GAP-CLOSE-PWR-3-GP
P G4516 1 2
GAP-CLOSE-PWR-3-GP 2 6 P WR_3D3V_PH 1 2
1 2 3 I N#2 L X#6 19
4 I N#3 L X#19 20
1
5 I N#4 L X#20 P C4509 P C4525 P C4512 P G4521
1
1
P C4501 P C4502 P C4503 P C4504 P C4513
1
1
SC22U6D3V3MX-1-DL-GP
I N#5 10 P WR_3V_PG P C4510 P C4511 DY GAP-CLOSE-PWR-3-GP
P G4517
SCD1U16V2KX-3DLGP
12 N C#10 15 1 2
GAP-CLOSE-PWR-3-GP
SC10U25V3MX-GP
SC10U25V3MX-GP
SC10U25V3MX-GP
2
SCD1U25V2KX-1-DL-GP
11 E N1 N C#15
2
2
1 2 P WR_3D3V_EN 16 P WR_3D3V_LDO
2
2
E N2 N C#16
P WR_3D3V_BOOT 1 P G4522
P WR_3V_PG 9 B S 7 GAP-CLOSE-PWR-3-GP
P G4518 1 2
GAP-CLOSE-PWR-3-GP P WR_3D3V_FB 13 P G G ND 8
1 2 14 F F G ND 18
17 O UT G ND 21
L DO G ND 3 D3V_AUX_S5 P G4523
GAP-CLOSE-PWR-3-GP
P WR_3D3V_EN1 P G4532 1 2
SY8286BRAC-GP GAP-CLOSE-PWR-3-GP
P WR_3D3V_LDO
1
P R4514 1 2
1MR2J-1-GP
P G4524
P C4532 GAP-CLOSE-PWR-3-GP
1
P C4507 1 2
SCD1U25V2KX-1-DL-GP
DY SC4D7U25V5KX-DL-GP
2
P R4509 Trace used 10 mil

2
1KR2F-3-GP P G4530
1 2 GAP-CLOSE-PWR-3-GP
D CBATOUT P WR_3D3V_VOUT 1 2
P C4508
1
P C4533 P R4506
SCD1U25V2KX-1-DL-GP
P R4508
DY
EN rating 25V DY SC1KP50V2KX-1DLGP
1 2 P WR_3D3V_FB2 2
1KR2F-3-GP
1
D CBATOUT EN Rising Threshold : 0.8V
200KR2F-L1-GP
P R4505
2
Ilimt : 8A 1
100KR2J-1-GP
2
3 D3V_AUX_S5 DY
A A
P G4531
GAP-CLOSE-PWR-3-GP
1
1 2
DY E C4534
SCD1U25V2KX-GP
[17,40,52,54] 3 V_5V_POK
2
<Core Design>
Title
( Reserved)
A 2
5 4 3 2 1
5 4 3 2 1
SSID = CPU_CORE
Vince,20160922
P R4611
18K2R2F-L-GP
1 2
P C4632
0 413 P/N change 78.15322.2FLDL to 78.15322.2FL 1 2
P C4602 SC1KP50V2KX-1DLGP
P R4602 8 1208_AGND
D D
1 2 P WR_VCCSA_COMP_R1 2 P WR_VCCSA_CSN_L 1 2
P WR_VCCSA_CSN [50]
1K5R2F-2-GP
2
SCD015U25V2KX-DLGP P C4648 P R4681
20160614 modify SC2200P50V2KX-2DLGPP C4606 10R2F-L-GP P R4606
P C4604 NTC-100K-11-GP-U
1
SCD01U50V2KX-1DLGP
1
1 2 P R4609
P C4603 P C4607 14K3R2F-GP
2
SC1KP50V2KX-1DLGP SC15P50V2JN-DL-GP 8 1208_AGND
P WR_VCCSA_VSN_R P WR_VCCSA_CSN_NTC
1
1 2 SCD01U50V2KX-1DLGP 1 2
8 1208_AGND
P R4605 P R4612
[7] V SSSA_SENSE 1 2 1 2 1 2
8K06R3F-AS-GP P WR_VCCSA_CSP [50]
P R4604 0R0402-PAD-1-GP 825R2F-GP P R4613 91KR2F-GP 3 D3V_S0
2
P C4605 1 2
SC1KP50V2KX-1DLGP
1
P R4608 P C4609 SC220P50V2KX-3DLGP
1
2K87R2F-1-GP 1 2 R4614
[7] V CCSA_SENSE 1 2 1 2 DY P 10KR2F-2-GP
P R4607 0R0402-PAD-1-GP P R4616 8 1208_AGND P R4670 0R0402-PAD-1-GP
P WR_VCCSA_VSP_R V R_RDY
2
1 2 1 2 1 2
1 2
0R0402-PAD-1-GP P C4608 P R4630 0R0402-PAD-1-GP V R_EN [40]
SC1KP50V2KX-1DLGP P R4671 + VCCST_CPU
P WR_VCCSA_VSP_RC 1 2 P SYS
[44] P _SYS
1
0R0402-PAD-1-GP
P R4682
20KR2J-L2-GP
DY
75R2F-2-GP
100R2F-L1-GP-U
P
P
R4622
R4623
1
P C4610
2
SCD1U25V2KX-1-DL-GP
P R4617 0R0402-PAD-1-GP + VCCST_CPU + VCCSTG Check +VCCST_CPU or +VCCSTG
2
[7] 1 2
V CC_SENSE
45D3R2F-L-GP
1
P
R4621
DY
1
P C4611 [#543016]
SC1KP50V2KX-1DLGP
1
C P R4618 0R0402-PAD-1-GP P R4619 C
[7] V SS_SENSE
1 2 1 2 P R4624 P R4669
1K54R2F-GP 1KR2F-3-GP
V R_SVID_CLK [7] DY DY 75R2F-2-GP
P WR_VCCGT_VSN_R 1 2
V R_SVID_ALERT# [7]
2
P C4612 SC2200P50V2KX-2DLGP P G4601 V R_SVID_DATA [7]
GAP-CLOSE-PWR-3-GP
[50]
P WR_VCCSA_PWM
[47,48,50]
P WR_VCORE_DRVON
2 1 P R4668
1
1 2
PR4665
PR4667
H _PROCHOT# [4,24,44]
P R4625 100R2F-L1-GP-U
37D4R2F-GP
PR4666 0R0402-PAD-1-GP
WR_VCORE_VR_RDY
8 1208_AGND
WR_VCCSA_CSP1B
P WR_VCCSA_COMP
1
WR_VCCSA_IOUT
P R4626
P WR_VCCGT_VSN
P WR_VCCGT_VSP
P WR_VCCSA_VSN
P WR_VCCSA_VSP
P WR_VCCSA_ILIM
49D9R2F-GP
10R2F-L-GP
2
WR_VCORE_EN
1KR2F-3-GP P C46131 2 SC470P50V2KX-3DLGP
P WR_VCCGT_FB_R
1
P R4627
1 2 1 2
P WR_VCCGT_CSP [48]
1
P C4614 P R4628 8K06R3F-AS-GP

2
SC470P50V2KX-3DLGP P R4632
1 2 105KR2F-1-GP
8 1208_AGND
P R4629
2
2
30K1R2F-L-GP 8 1208_AGND
1 2 P WR_VCORE_CSNNTC
P
P
P
P
P WR_VCORE_VRHOT#
P WR_VCORE_ALERT#
1
P WR_VCORE_SCLK
8 1208_AGND
2
P WR_VCORE_SDIO
49
48
47
46
45
44
43
42
41
40
39
38
37
P R4631 14KR2F-GP
4K75R2F-1-GP 1 2 P U4601 P R4633
1
1
P C4615 P C4647 P C4634 P C4616 NTC-100K-11-GP-U
P SYS
V SP_1B
C OMP_1B
I LIM_1B
C SN_1B
V SN_1B
C SP_1B
I OUT_1B
V R_RDY
P WR_VCCGT_ILIM_R
G ND
V SN_2PH
V SP_2PH
EN
1
P C4617 SC470P50V2KX-3DLGP SC2200P50V2KX-2DLGP SCD015U25V2KX-DLGP
2
SC10P50V2JN-4DLGP SCD015U25V2KX-DLGP
2
2
P WR_VCCGT_COMP_R P R4680
2
P WR_VCCGT_CSN_L
1
P R4634 P C4618 8 1208_AGND 1 2

P WR_VCCGT_CSN [48]
1
1 2 SC2200P50V2KX-2DLGP P WR_VCCGT_IOUT 1 36 10R2F-L-GP
P WR_VCCGT_DIFFOUT 2 I OUT_2PH P WM_1B 35 1 2
D IFFOUT_2PH D RVON
2
P R4638 NTC-220K-GP-U P WR_VCCGT_FB 3 34 P R4635

P R4637 200KR2F-L-GP P WR_VCCGT_COMP 4 F B_2PH S CLK 33 51K1R2F-GP
1 2 2 1 1 P R4639 2 1 2 P WR_VCCGT_ILIM 5 C OMP_2PH A LERT# 32
[47] PWR_VCORE_CSPA P WR_VCCGT_CSCOMP I LIM_2PH S DIO
P R4640 6 31
P WR_VCCGT_CSSUM C SCOMP_2PH V R_HOT# P WR_VCORE_IOUT P R4636
1
75KR3F-GP P C4620 11K5R2F-GP 7 30 P C4633 P C4601 8 1208_AGND

75KR2F-GP SC470P50V2KX-3DLGP P C4621 P WR_VCCGT_CSREF 8 C SSUM_2PH I OUT_1A 29 P WR_VCORE_CSP_1A 1 2 1 2 P WR_VCORE_COMP_R 1 2
SC330P50V2KX-3-DL-GP 9 C SREF_2PH C SP_1A 28 SCD015U25V2KX-DLGP
C SP2_2PH C SN_1A
2
P R4679 10 27 P WR_VCORE_ILIM SC1KP50V2KX-1DLGP 20160614 modify 2K15R2F-1-GP

1 11 C SP1_2PH I LIM_1A 26 P WR_VCORE_COMP
U42 2 1 2 P C4619
R OSC_COREGT
[47] PWR_VCORE_CSPB T SENSE_2PH C OMP_1A P WR_VCORE_VSN
12 25 1 2P WR_VCORE_VSN_R
A DDR_VBOOT
B SC150P50V2JN-3DLGP 8 1208_AGND B
T SENSE_1PH
I CCMAX_2PH
V RMP V SN_1A
R OSC_SAUS
75KR3F-GP P C4622
I CCMAX_1A
I CCMAX_1B
P WM1_2PH
P WM2_2PH
P WR_VCORE_VRMP
[47] PWR_VCORE_CSNB P R4677 2 U42 1 10R2F-L-GP 5 V_S5 SC3300P50V2KX-1DLGP P R4645 0R0402-PAD-1-GP
P WM_1A
V SP_1A
1 2 1 2
V SSGT_SENSE [7]
P R4644
V CC
1
1
[47] PWR_VCORE_CSNA P R4646 2 1 10R2F-L-GP P C4623 P C4641 P C4625
SCD047U25V2KX-4-GPU42SCD047U25V2KX-4-GP R4676 820R2F-GP SC1KP50V2KX-1DLGP
U22 P1KR2F-3-GP NCP81218MNTXG-GP P R4647 P R4648 0R0402-PAD-1-GP
P WR_VCORE_VCC_R 13
14
P WR_VCORE_ROSC_SAUS 15
16
17
18
19
20
21
22
23
24
2
2
1 2 1 2
P WR_VCCGT_CSP2 V CCGT_SENSE [7]
2
1
P WR_VCORE_ROSC_COREGT 4K75R2F-1-GP
P C4646 P WR_VCCGT_CSP1 P WR_VCORE_VSP 1 2P WR_VCORE_VSP_RC1 2 P WR_VCORE_VSP_R
SCD01U50V2KX-1DLGP P WR_VCCGT_TSENSE P R4649
P R4650
2
2K49R2F-GP P C4627
D CBATOUT P WR_VCORE_TSENSE SC1KP50V2KX-1DLGP 1 2 P WR_VCORE_NTC
P R4651 8 1208_AGND P WR_VCCGT_PWMA [48]
1 2 P R4601 P WR_VCORE_ADDR_BOOT
[47] PWR_VCORE_CSPA P WR_VCCSA_ICCMAX 100R2F-L1-GP-U
2
1 2 1KR2F-3-GP
P WR_VCORE_ICCMAX
1
4K87R2F-GP P C4628 P R4652 P R4653
P R4678 P WR_VCCGT_ICCMAX SCD1U25V2KX-1-DL-GP 21K5R2F-GP NTC-100K-11-GP-U
1
[47] PWR_VCORE_CSPB 1 U42 2 P C4629
2
SCD01U50V2KX-1DLGP
2
4K87R2F-GP
P R4655
2
1
P WR_VCCGT_NTC 1 2 P R4662 P R4658 P R4660
51K1R2F-GP
97K6R2F-GP
19K1R2F-GP
P R4663
8 1208_AGND 35K7R2F-GP 8 1208_AGND
1K54R2F-GP
2
U22 15W U42 15W 5 V_S5
2
1
P R4656 P C4630 P R4657

NTC-100K-11-GP-U P R4661 SCD1U25V2KX-1-DL-GP 2D2R2F-GP P R4664 P R4659
19K6R2F-GP 1 2 24KR2F-GP 24KR2F-GP
PR4640 11.5K (64.11525.6DL) 20.5K (64.20525.6DL)
For NCP81218MNTXG-GP Vboot
2
PR4679 DY 71.5K (64.71525.55L)

2
2
1
1
PR4677 DY 10 (64.10R05.6DL) P C4631

SC1U10V2KX-1DLGP 8 1208_AGND
2
PR4678 DY 4.87K (64.48715.6DL)

P WR_VCORE_PWM2 [47]
8 1208_AGND
PC4641 DY 0.047u (78.47322.2FL) 8 1208_AGND8 1208_AGND 8 1208_AGND
P WR_VCORE_PWM1 [47]
PR4676 1K (64.10015.6DL) DY
A A
PR4662 51.1K (64.51125.6DL) 100K (64.10035.6DL)
PR4658 97.6K (64.97625.6DL) 97.6K (64.97625.6DL)

20170208
PR4635 51.1K (64.51125.6DL) 51.1K (64.51125.6DL) <Core Design>
PR4628 105K (64.10535.6DLLS) 105K (64.10535.6DLLS) W istron Corporation

PR4632 30.1K (64.30125.6DL) 26.1K (64.26125.6DL)
Title
N CP81208MN_CPU_VCORE(1/3)
Size
A 2
Document Number
S tarlord KBL-R
1
Sheet 46 o f
Rev
A 00
105
5 4 3 2 1
Main Func = CPU_CORE

Vince,20161020
D CBATOUT_VCORE
1020 EMI add
D CBATOUT_VCORE D CBATOUT D CBATOUT_VCORE1 D CBATOUT
For acoustic noice
S CD1U25V2KX-1-DL-GP
P G4701 1 2 GAP-CLOSE-PWR-3-GP P G4705 1 2 GAP-CLOSE-PWR-3-GP
S C10U25V5KX-DL-GP
S C10U25V5KX-DL-GP
S C10U25V5KX-DL-GP
S C10U25V5KX-DL-GP
D CBATOUT
SCD1U25V2KX-GP E C4701
1
P C4702 P C4703 P C4704 P C4705 P C4710
DY
1
2
D P T4704 P T4703 D
ST33U25VDM-5-GP ST33U25VDM-5-GP
2
P G4704 1 2 GAP-CLOSE-PWR-3-GP PG4722 1 2 G AP-CLOSE-PWR-3-GP
Vince,20160922 EVT1_20160901
P R4701
1 2 P WR_VCORE_BOOT_RC1
P WR_VCORE_BOOT1
3D9R3-GP
1
5 V_S5 P C4706
SCD22U25V3KX-DL-GP
P R4702
2
25
26
27
28
29
30
33
35
2D2R2F-GP
1
2 1 P WR_VCORE_VCC1 P U4701
0.15uH,
T HWN
IN
IN
IN
IN
IN
IN
B OOT
G H
1
P C4708 DCR=0.66mohm,
V
V
V
V
V
V
SC1U10V2KX-1DLGP V CC_CORE
6 Idc=36A, Isat=45A
V CC P WR_VCORE_PHASED1
2
34
7 P HASED 32 P L4701
V CCD P HASEF
1
P C4707
SC2D2U10V3KX-1DLGP-U 12 P WR_VCORE_SW1 1 2
5 V SW#12 13
C GND V SW#13
2
14
V SW#14 15 COIL-D15UH-2-GP
4 V SW#15 16
[46] PWR_VCORE_PWM1 P WM V SW#16
1
P R4704 17 P T4702
P WR_VCORE_DISB#1 2 V SW#17 18 SE330U2VDM-4-GP
1 2
[46,48,50] PWR_VCORE_DRVON D ISB# V SW#18
2
0R0402-PAD-1-GP 36
Z CD_EN P G4707 P G4708
1
5 V_S5
3 R4703
G
DY P2D2R5F-2-GP
AP-CLOSE-PWR-3-GP
AP-CLOSE-PWR-3-GP
S MOD#
1
11 G L#10
G L#11
GND
GND
GND
GND
GND
GND
GND
GND
9 G L#8
10 G L#9
C C
2
P
P
P
P
P
P
P
P
NCP81382MNTXG-3-GP P WR_VCORE_SNUB1
8
19
20
21
22
23
24
31
37
330uF/2V,
1
C4709
DYPSC2200P50V2KX-2DLGP ESR=9mohm,
P WR_VCORE_GL1 Ripple current=3000mA
2
Confirm with EE:
22uF/0805 total 32pcs (DY 5 pcs)
[46] P WR_VCORE_CSPA
[46] P WR_VCORE_CSNA
D CBATOUT_VCORE1
EVT1_20160810
S C10U25V5KX-DL-GP
S C10U25V5KX-DL-GP
S C10U25V5KX-DL-GP
S C10U25V5KX-DL-GP
S C10U25V5KX-DL-GP
P C4725 P C4724 P C4723 P C4729 P C4726 P C4730
1
1
U42
U42 U42 U42 U42 U42
2
2
B B
P R4711
1 2 P WR_VCORE_BOOT_RC2
U42
P WR_VCORE_BOOT2
3D9R3-GP
U42P C4722
1
5 V_S5 TDC=42A
SCD22U25V3KX-DL-GP
P R4712 Iomax=64A
OCP>80A
2
2D2R2F-GP
25
26
27
28
29
30
33
35
1
2 1 P WR_VCORE_VCC2 P U4702
U42 0.15uH,
T HWN
V IN
V IN
V IN
V IN
V IN
V IN
B OOT
GH
1
SC1U10V2KX-1DLGP U42 Idc=36A, Isat=45A
V CC_CORE
6
V CC
2
34 P WR_VCORE_PHASED2
7 P HASED 32 P L4702
V CCD P HASEF
1
P C4721
U42
SC2D2U10V3KX-1DLGP-U V SW#12
12 P WR_VCORE_SW2 1 U42 2
5 13
C GND V SW#13
2
14
U42 V
V
SW#14
SW#15
15 COIL-D15UH-2-GP
4 16
P WM V SW#16
1
[46] P WR_VCORE_PWM2 P R4714 17 T4705
1 2 P WR_VCORE_DISB#2 2
D ISB#
V
V
SW#17
SW#18
18 U42P SE330U2VDM-4-GP
2
2
[46,48,50] P WR_VCORE_DRVON
2
36
U42 0R0402-PAD-1-GP
Z CD_EN
1
P G4712 P G4711
5 V_S5
3 EVT1_20160829
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
R4713
S MOD# DY P2D2R5F-2-GP
1
1
G L#10
G L#11
P GND
P GND
P GND
P GND
P GND
P GND
P GND
P GND
G L#8
G L#9
NCP81382MNTXG-3-GP P WR_VCORE_SNUB2
330uF/2V,
8
9
10
11
19
20
21
22
23
24
31
37
A A
ESR=9mohm,
1
C4727
P WR_VCORE_GL2
DYPSC2200P50V2KX-2DLGP Ripple current=3000mA
2
<Core Design>
[46] P WR_VCORE_CSPB 2 1F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
[46] P WR_VCORE_CSNB
N CP81382MN_CPU_VCORE(2/3)
A 2 S tarlord KBL-R A 00
5 4 3 2 1
5 4 3 2 1
Vince,20160929
Vince,20160922
Vince,20160929 Vince,20161020
D D
D CBATOUT
1020 EMI add
S C10U25V5KX-DL-GP
S C10U25V5KX-DL-GP
S C10U25V5KX-DL-GP
S C10U25V5KX-DL-GP
S C10U25V5KX-DL-GP
E C4801
P C4802 P C4803 P C4804 P C4805 P C4806 P C4811
1
DY
SCD1U25V2KX-GP
2
2
P R4802
1 2
P WR_VCCGT_BOOTA
3D9R3-GP P W R_VCCGT_BOOTA_RC
5 V_S5
1
C P C4809 C
SCD22U25V3KX-DL-GP
P R4803
2
2D2R2F-GP TDC=18A
25
26
27
28
29
30
33
35
1
2 1 P W R_VCCGT_VCCA P U4801
Iomax=31A
0.15uH,
VIN
VIN
VIN
VIN
VIN
VIN
GH
THWN
BOOT
OCP>46.5A
1
SC1U10V2KX-1DLGP
6
Idc=36A, Isat=45A + VCCGT
VCC
2
34 P W R_VCCGT_PHASEDA
PHASED P L4801
7 32
VCCD PHASEF
1
P C4807
12 P W R_VCCGT_SWA 1 2
SC2D2U10V3KX-1DLGP-U VSW#12
5 13 COIL-D15UH-2-GP
CGND VSW#13
2
14
VSW#14 15
4 VSW#15 16
[46] P W R_VCCGT_PWMA P R4808 PWM VSW#16 17
1 2 P W R_VCCGT_DISB#_A 2 VSW#17 18
DISB# VSW#18
2
[46,47,50] P W R_VCORE_DRVON P T4801
1
0R0402-PAD-1-GP 36
ZCD_EN
1
P G4808 P G4809
S
5 V_S5
T330U2D5VBM-1-GP
GAP-CLOSE-PWR-3-GP
G
3 P R4804
AP-CLOSE-PWR-3-GP
SMOD#
2
2D2R5F-2-GP
DY
GL#10
GL#11
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
GL#8
GL#9
2
NCP81382MNTXG-3-GP
10
11
19
20
21
22
23
24
31
37
8
9
P W R_VCCGT_SNUB_1
B B
1
P W R_VCCGT_GL1
P C4810 330uF/2.5V,
DY SC2200P50V2KX-2GP ESR=9mohm,
2
Ripple current=3073mA
Confirm with EE:
22uF/0805 total 35pcs (DY 5 pcs)
[46] P W R_VCCGT_CSP
[46] P W R_VCCGT_CSN
<Core Design>
A A
Wistron Corporation
Title
NCP81382MN_CPU_VCCGT(3/3)
A3 S tarlord KBL-R A00
1
48 of 105
5 4 3 2 1
D D
C C
(Blanking)
B B
<Core Design>
A
Title
NCP81210MN_CPU_VCCGTUS
A4 Starlord KBL-R A 00
5 4 3 2 1
5 4 3 2 1
Vince,20160922
D D
Vince,20161020
D CBATOUT_+VCCSA
D CBATOUT
P G5001
2 1
GAP-CLOSE-PWR-3-GP
P G5002
E C5001
20160614 modify to 84.07410.A37 for COST P C5029 P C5027 P C5002 2 1
1
GAP-CLOSE-PWR-3-GP
DY
5
6
7
8
SC10U25V5KX-DL-GP
SC10U25V5KX-DL-GP
SCD1U25V2KX-1-DL-GP
P R5013
SCD1U25V2KX-GP
2
2
D
D
D
D
1 2 P W R_VCCSA_BST_RC P U5002
AON7410-GP
2D2R3-1-U-GP TDC=4A
65BOM charger
P WR_VCCSA_BST
Iomax=4.5A
OCP>6.75A
1
P C5008
G
S
S
S
SCD22U25V3KX-DL-GP 0.47uH,
4
3
2
1
DCR=3.5~4.1mohm,
2
#543977 Intel PDG Rev0.91
P U5001
Idc=18A, Isat=20A + VCCSA +VCCSA(ICCMAX.=5A)
C P L5001 C
1 8 P W R_VCCSA_DRVH
BST DRVH P W R_VCCSA_SW 1 2
2 7
PWM SW
[46] P W R_VCCSA_PW M 3 6
EN GND
[46,47,48] P W R_VCORE_DRVON 5 V_S5 4 5
VCC DRVL IND-D47UH-22-GP-U
1
9
GND
1
P C5001 P R5014
DY 2D2R5F-2-GP
5
6
7
8
2
NCP81253MNTBG-1-GP
2
D
D
D
D
P U5003
2
P G5021 P G5022
PWR_VCCSA_SNUB
AON7410-GP
GAP-CLOSE-PWR-3-GP
G
65BOM charger
AP-CLOSE-PWR-3-GP
1
1
G
S
S
S
4
3
2
1
P W R_VCCSA_DRVL
1
P
DYSC2200P50V2KX-2DLGP
C5031
2
B B
Confirm with EE:

[46] P W R_VCCSA_CSP 22uF/0805 total 20pcs (DY 5 pcs)
[46] P W R_VCCSA_CSN
A <Core Design> A
Wistron Corporation
Title
NCP81253MN_CPU_VCCSA
1
50 of 105
5 4 3 2 1
SSID = PWR.Plane.Regulator_1p2v
1 D2V_PWR 1 D2V_S3
P G5102
1 2
GAP-CLOSE-PWR-3-GP
D CBATOUT
P WR_DCBATOUT_1D2V
P G5110 P G5111
1 2 1 2
P G5104
D 1 2 P G5106 D
GAP-CLOSE-PWR-3-GP 1 2
GAP-CLOSE-PWR-3-GP
P G5101
1 2
GAP-CLOSE-PWR-3-GP P G5112
1 2
P G5107 GAP-CLOSE-PWR-3-GP
1 2
GAP-CLOSE-PWR-3-GP
P G5109
P G5103 1 2
1 2 GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
P G5108 P G5114
1 2 1 2
SY8288RAC for 1D2V

P G5115
1 2
P WR_DCBATOUT_1D2V GAP-CLOSE-PWR-3-GP
Vince,20161014
P C5106 P C5108 P C5107
1
DY
Design Current=7A
S
CD01U50V2KX-1DLGP
S
S
C10U25V5KX-DL-GP
C10U25V5KX-DL-GP
10.5A<OCP>12.6A
2
1
P C5113
P
WR_1D2V_LDO_P5
SC2D2U10V3KX-1DLGP-U P C5117
SCD1U25V2KX-1-DL-GP 1 D2V_PWR
P L5101
G AP-CLOSE-PWR-3-GP
P R5107 0R0402-PAD-1-GP P WR_1D2V_BOOT 1 2 PPWR_1D2V_BOOT_R
WR_1D2V_BOOT_R 1 2 1 2
1 2 P WR_1D2V_PGOOD
[40] 1D2V_VTT_PWRGD P R5101 COIL-1UH-73-GP
P U5101 0R0603-PAD-1-GP-U
1
1 2 P WR_1D2V_EN P WR_1D2V_PHASE
1
[54] PWR_2D5V_PG 17 6 P G5113 P C5103 P C5101
P C5105
1
P R5105 0R0402-PAD-1-GP V CC L X#6 19 P C5104 P C5102
L X#19
S
20
CD1U16V2KX-3DLGP
C22U6D3V3MX-1-DL-GP
C22U6D3V3MX-1-DL-GP
C22U6D3V3MX-1-DL-GP
C22U6D3V3MX-1-DL-GP
C C
L X#20
2
1
P C5138 P R5127 2
2
DY 1MR2J-1-GP 3 I N#2 10 P WR_1D2V_PGOOD
S
CD1U16V2KX-3DLGP
4 I N#3 N C#10 12
DY 5 I N#4 N C#12
2
16 P WR_1D2V_LDO_P5
I N#5 N C#16
1
2
P WR_1D2V_BOOT 1 P WR_1D2V_VFB_R
9 BS P R5103
11 P G 7 10KR2F-2-GP
1
P R5106
1 2P WR_1D2V_IMAX 13 E N G ND 8 P C5112
DY0R2J-2-GP PWR_1D2V_VFB 14 I LMT G ND 18 SC330P50V2KX-3-DL-GP
R1
2
15 F B G ND
2
21
OCP setting B YP G ND
High 12A SY8288RAC-GP Vo=0.6x(1+R1/R2)

Float 8A =0.6x(1+100/100)
P R5102 =1.2V
Low 6A P WR_1D2V_BYP 1 2
3 D3V_S0
R2
1
0R0402-PAD-1-GP P R5104
1
P C5110 10KR2F-2-GP
SC1U10V2KX-1DLGP
2
2
D DR_VREF_S3
B B
Vince,20170103
1
P C5116
SCD1U16V2KX-3DLGP
2
1 D2V_PWR
[17,27,40,54] S IO_SLP_S3# P R5126 1 DY 2 0R2J-2-GP P C5115

SC10U6D3V3MX-DL-GP
1
P C5118
P R5125 SCD1U16V2KX-3DLGP
Peak Current = 1470mA
1 2 P WR_0D6V_S3EN
[5] S M_PGCNTL_R
2
2
0R0402-PAD-1-GP
11
P R5114 P U5102
1 2 P WR_0D6V_S5EN 0 D6V_PWR 0 D6V_PWR 0 D6V_S0
G ND
[54] P WR_2D5V_PG P G5121

0R0402-PAD-1-GP 6 5 1 2
7 V TTREF V TTSEN 4
S 3 P GND GAP-CLOSE-PWR-3-GP
8 3
G ND V TT
1
P R5118 9 2 P C5114
1 2 P WR_0D6V_VCNTL 10 S 5 V IN 1 P G5120
5 V_S5
SC22U6D3V3MX-1-GP
V CNTL V REF 1 2
0R0402-PAD-1-GP
2
1
P C5111 GAP-CLOSE-PWR-3-GP
1
P C5119 P C5120
Vince,20161014
SC1U10V2KX-1DLGP
APL5338XAI-TRG-GP
DY DY
SCD1U16V2KX-3DLGP
SCD1U16V2KX-3DLGP
2
2nd source:
74.02997.B79
2 014.03.28 EE modify
A A
<Core Design>
Title
( Reserved)
A 2
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Plane.Regulator_1D0V
1 D0V_PW R 1 D0V_S5
P G5211
GAP-CLOSE-PW R-3-GP
1 2
P W R_DCBATOUT_1D0V P G5204
D D CBATOUT D
GAP-CLOSE-PW R-3-GP
1 2
P G5214
P G5216
GAP-CLOSE-PWR-3-GP
1 2 GAP-CLOSE-PW R-3-GP
1 2
P G5210
AOZ2262 for 1D0V

P G5201
GAP-CLOSE-PWR-3-GP
1 2
P G5212
P G5208
GAP-CLOSE-PWR-3-GP
1 2
P G5215
GAP-CLOSE-PW R-3-GP
1 2
5 V_S5 P G5209
Design Current : 9A GAP-CLOSE-PW R-3-GP
1 2
11.25A<OCP>13.5A P G5213
1
GAP-CLOSE-PW R-3-GP
P C5202
MAG. 7*7*3 1 2
SC1U10V2KX-1DLGP DCR: 9m~10mOhm
Idc : 11 A , Isat : 22A P G5206
2
C GAP-CLOSE-PW R-3-GP C
1 2
P L5201
P U5201 1 D0V_PW R
IND-1UH-94-GP-U P G5207
P W R_DCBATOUT_1D0V 21 18 P W R_1D0V_PH 1 2 P C5203 P C5205 P C5201 P C5206 P C5208 GAP-CLOSE-PW R-3-GP
VCC LX#18 1 2
S
17
CD1U25V2KX-1-DL-GP
LX#17
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
S
16
C22U6D3V3MX-1-GP
C22U6D3V3MX-1-GP
LX#16
11
LX#11
1
7 10
IN#7 LX#10
2
8 P C5204 SCD1U25V2KX-1-DL-GP
IN#8 P W R_1D0V_BT 1 2
PC5214
PC5216
PC5209
PC5210
PC5211
9 20 P G5223
IN#9 BST
2
P R5201 P W R_1D0V_FB
GAP-CLOSE-PWR-6-GP DY DY
88K7R2F-GP 5
FB
1
1
1 2 P W R_1D0V_TON 6
TON
DY DY P W R_1D0V_PG 1 4
PGOOD AGND
2
2
SCD1U50V3KX-DL-GP
SC10U25V5KX-DL-GP
SC10U25V5KX-DL-GP
SC10U25V5KX-DL-GP
SC10U25V5KX-DL-GP
P W R_1D0V_FB_A
P W R_1D0V_EN 2 19
EN PGND 14
P W R_1D0V_PFM 3 PGND 13
PFM# PGND 12
PGND
1
P W R_1D0V_SS 22 15 P C5212
SS PGND P R5202
R1 SC220P50V2KX-3DLGP
1
P R5203 P C5213 2K55R2F-GP
2
AOZ2262QI-10-GP-U
1
100KR2F-L1-GP
SCD01U50V2KX-1DLGP
2
2
B B
1
3 D3V_S5 P R5204
10KR2F-2-GP R2 Vo=0.8x(1+R1/R2)
=0.8x(1+2.55/10)
=1.004V
2
1
P R5208
DY 100KR2J-1-GP
P R5209
2
1 2 P W R_1D0V_PG
[40] 1 D0V_S5_PW RGD
0R0402-PAD-1-GP
Vince,20161031 P W R_1D0V_EN
1
P C5215
SC1KP50V2KX-1DLGP
PR5210
1 2
[17,40,45,54] 3V_5V_POK
2
0R0402-PAD-1-GP
<Core Design>
A A
Wistron Corporation
Title
(Reserved)
A3
S tarlord KBL-R A00
1
52 of 106
A B C D E
4 4
3 3
2 2
<Core Design>
1 1
Wistron Corporation
TTitle
itle
(Reserved)
A3
S tarlord KBL-R A00
A B C D E
5 4 3 2 1
SSID = 1D5V
APL5930 for 2D5V P W R_2D5V

P G5408
2 D5V_S3
GAP-CLOSE-PWR-3-GP
1 2 3 D3V_S5
S-1339D15-M5001 for 1D5V_S0
P G5409
GAP-CLOSE-PWR-3-GP
3 D3V_S5
1 2
SC1U10V2KX-1DLGP
3 D3V_S5
P
1
5 V_S5
C5408
D D
2
P C5414
Design Current = 16mA
SC10U6D3V3MX-DL-GP
SC1U10V2KX-1DLGP
PC5410
1
1
Design current = 700mA P U5402 1 D5V_PW R
1 D5V_S0
P R5410 P G5404
1 5 1 2
10KR2J-3-GP VIN VOUT
2
P W R_2D5V 2
P U5403 1 2P W R_1D5V_EN VSS
3 4
[17,27,40,51] S IO_SLP_S3# ON/OFF NC#4
2
GAP-CLOSE-PWR-3-GP
5 P R5405
VIN#5
SC1U10V2KX-1DLGP
0R0402-PAD-1-GP
P
6 4 P C5407
C5409
VCNTL VOUT#4 S-1339D15-M5001-GP
7 3 DY
S
[51] P W R_2D5V_PG POK VOUT#3
CD1U16V2KX-3DLGP
1 2 P W R_2D5V_EN 8 2 P W R_2D5V_FB
[17,40] S IO_SLP_S4# EN FB
2
9 1
P R5417 0R0402-PAD-1-GP VIN#9 GND
47KR2J-2-GP
1
1
29K4R2F-GP
P C5411DY
P R5409
P C5427 APL5930KAI-TRG-GP P R5419
SC10U6D3V3MX-GP
SC68P50V2JN-1GP
PC5413
P C5412
SCD1U16V2KX-3DLGP
2
R1 SC10U6D3V3MX-GP
2
DY
2
2
1
C C
R2 P R5420
Vout=0.8V*(R1+R2)/R2 13K7R2F-GP
2
APL5930 for 1D8V_S5
Vince,20161027 5 V_S5 3 D3V_S5
1 D8V_PW R + V1.8A
P G5405
B P C5401 P C5403 B
GAP-CLOSE-PWR-3-GP
1 2
SC10U6D3V3MX-DL-GP
SC1U10V2KX-1DLGP
Design Current = 770mA

1
1
P G5406
1 D8V_PW R GAP-CLOSE-PWR-3-GP
2
2
1 2
P U5401
5 P G5407
P R5408 6 VIN#5 4 GAP-CLOSE-PWR-3-GP
1 2 P W R_1D8V_POK 7 VCNTL VOUT#4 3 1 2
[24,40] 1 D8V_S5_PW ROK P W R_1D8V_EN POK VOUT#3
8 2
0R0402-PAD-1-GP 9 EN FB 1
P R5406 VIN#9 GND
1 2 P R5403 P C5405
[17,40,45,52] 3 V_5V_POK
1
1
DY APL5930KAI-TRG-GP
SC10U6D3V3MX-GP
16K5R2F-2-GP
SC68P50V2JN-1GP
PC5402
0R0402-PAD-1-GP P R5401 DY DY
Vince,20161031 47KR2J-2-GP P C5406 R1
2
2
1 .8V_RUN_FB
SC4700P50V2KX-1GP
2
2
1
P R5404
A R2 13K3R2F-L1-GP
Vince,20161027 <Core Design>
A
Vout=0.8V*(R1+R2)/R2 Wistron Corporation

2

Title
(Reserved)
A3
S tarlord KBL-R A00
1
54 of 106
5 4 3 2 1
SSID = LCD
CAMERA POWER
D 5501 Hi:2.0V
L CD1
Panel Conn. [8] E DP_VDD_EN 1 Lo:0.8V
LCDVDD Layout 80 mil
3 D3V_S0
3 D3V_S0
Add 0603 0ohm , 20141118 3 D3V_CAMERA_S0
43 3
U 5501 R 5513 1 2 0R3J-0-U-GP
41 Backup , 20141114 2
DY
[24] L CD_VCC_TEST_EN L VDS_VDD_EN_R
D
D CBATOUT_LCD 1 5 D
1 2 E N V IN#5
F 5502
BAT54C-11-GP L CDVDD 3 G ND 4 1 2
2 V OUT V IN#4
3 E C5502
POLYSW-1D1A6V-9-GP-U
1
4 RT9724GB-GP C 5502
CD1U25V2KX-GP
S
5 C 5503
SC4D7U6D3V3KX-GP
C4D7U6D3V3KX-GP
S
6
L CDVDD
2
1
1
7 C 5508 C 5505
8 C 5507
S
C1U10V2KX-1GP
Add 0ohm , 20141118
S
C4D7U6D3V3KX-GP
9 SCD1U16V2KX-3DLGP
2
10
11
12 E DP_AUX C 55101 2 SCD1U16V2KX-3DLGP
13 E DP_AUX# E DP_AUX_DP [8]
C 55111 2 SCD1U16V2KX-3DLGP
14 E DP_AUX_DN [8]
15
16
E DP_TX3#
E DP_TX3
E DP_TX3_DN [8]DY INVERTER POWER
[8]DY
17 E DP_TX3_DP
18 E DP_TX2#
Add 1206 0ohm , 20141118
[8]DY R 5502
19 E DP_TX2 E DP_TX2_DN D CBATOUT D CBATOUT_LCD
[8]DY
0R2J-2-GP
20 E DP_TX2_DP 1 DY 2 R 5514
21 E DP_TX1# C 55011 2 SCD1U16V2KX-3DLGP 2 1
22 E DP_TX1 E DP_TX1_DN [8] DY
C 55041 2 SCD1U16V2KX-3DLGP D 5502
23 E DP_TX1_DP [8]
0R6J-L-GP
24 E DP_TX0# C 55061 2 SCD1U16V2KX-3DLGP 1
25 E DP_TX0 E DP_TX0_DN [8] L _BKLT_CTRL [8]
C 55091 2 SCD1U16V2KX-3DLGP F 5503
26 E DP_TX0_DP [8] B KLT_CTRL 3 1 2
27 E DP_HPD_CONN
28 2 L CD_TST POLYSW-1D1A24V-GP-U C 5514 C 5518
L CD_TST_C
1
29 C 5512 5513
S
C
C2D2U35V3KX-GP
C2D2U35V3KX-GP
30 L CD_BRIGHTNESS
S
CD1U50V3KX-GP
C1KP50V2KX-1GP
31 B LON_OUT_C R 5503 BAT54C-11-GP
D BC_EN_R
2
32 1 2
33 0R0402-PAD D BC_PANEL_EN [20]
34 R N5503
35 D MIC_CLK_C 1 4
D MIC_DATA_C D MIC_CLK [27]
36 2 3
D MIC_DATA [27]
37
38 SRN33J-5-GP-U E C5503 E C5504
1
39 Starload height limite change to 0603 package
40
S
C22P50V2JN-4GP
C22P50V2JN-4GP
C C
R5504,R5505 merge to RN5503 E MI DVT1 0210 2015/09/24 modify
2
42
44
2015/10/06 modify SENSOR POWER
3 D3V_S0 3 D3V_SEN_S0
IPEX-CON40-3-GP Vince,20170202
R 5501
1 2 R 5516 1 DY 2 0R3J-0-U-GP
0R0402-PAD
R N5501 D 5503 Add 0603 0ohm , 20141118

L CD_TST_C 1 8 F 5504
B LON_OUT_C 2 7 B LON_OUT L CD_TST [24]
1 P ANEL_BKEN_EC_C
1 R 5515 2 1 2
E DP_HPD_CONN P ANEL_BKEN_EC [24]
M IC_GND 3 6
L CD_BRIGHTNESS 4 5 B KLT_CTRL E DP_HPD [8] B LON_OUT 3 0R0402-PAD
1
R 5512 POLYSW-1D1A6V-9-GP-U
SRN100J-4-GP 2 L _BKLT_EN_C 1 E C5505DY 5515
DY 2 0R2J-2-GP L _BKLT_EN [8,24]
SC33P50V2JN-3GP
C
SC4D7U6D3V3KX-GP
Power Pin Count : 7
2
Vince,20170202 BAT54C-11-GP
GND Pin Count : 9
HSYNC
L CD_BRIGHTNESS
1
2
R N5502
8
7
B
E
KLT_CTRL
DP_HPD Vince,20161202 TOUCH PANEL POWER
LON_OUT
1
3 6 B E C5501
4 5 L VDS_VDD_EN_R
DY SC6D8P50V2DN-GP
2
SRN100KJ-5-GP
Remove HSYNC schematic
201511276 5 V_S0 T PAN_VDD
B B
F 5501
1 2
U SB_CAMERA_N POLYSW-1D1A6V-9-GP-U
U SB_CPU_PN4 [16]
R 5507 1 DY 2
0R3J-0-U-GP
1
3 4 C 5516 C 5520 C 5517
SCD1U50V3KX-GP
SC10U6D3V3MX-GP
DY
SC4D7U6D3V3KX-GP
2 1
2
TCBD1 E L5501
33
NP1 D CBATOUT_CAMERA
1 IR CAMERA Power
2 D CBATOUT_CAMERA D CBATOUT
3 3 D3V_SEN_S0 U SB_CAMERA_P
U SB_CPU_PP4 [16]
4 Starload height limite change to 0603 package
5 R 5520
6 0R3J-0-U-GP 2015/09/30 modify
3 D3V_CAMERA_S0
7 1 2
8 S ENSOR_I2C_SDA [20,70]
9 S ENSOR_I2C_SCL [20,70]
G SEN_INT1 [20]
2
10 C 5534
G SEN_INT2 [20]
11 C 5542 SC1KP50V2KX-1GP
G YRO_INT [70]
12 SCD1U50V3KX-GP
G YRO_DRDY [20]
1
13 USB_PN7_TPNL
U SB_CAMERA_P U SB_CPU_PN7 [16]
14
15 U SB_CAMERA_N
16
17 D MIC_CLK_C COIL-90OHM-100MHZ-5-GP
18 D MIC_DATA_C 3 4
19
M IC_GND
20 2 1
A 21 A
R 5540
22 I R_CAMERA_DET#_R 1 2 E L5502
23 I R_CAM_DET# [20]
0R0402-PAD
24 U SB_PP7_TPNL
U SB_CPU_PP7 [16]
25
26
T PAN_VDD <Core Design>
27
28
29
30
31
USB_PP7_TPNL
USB_PN7_TPNL
Touch Panel Vince,20161025 W istron Corporation
32 Taipei Hsien 221, Taiwan, R.O.C.
T OUCH_REPORT_SW [24]
NP2
34 Title
Vince,20161107 L CD&CAM&DMC&Touch
JAE-CON32-2-GP-U Size Document Number Rev
A 2
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
<Core Design>
itle
T Title
C RT
WWW.AliSaler.Com
5 4 3 2
Size
A 2
Document Number
S tarlord KBL-R
1
Sheet 56 o f
Rev
A 00
106
5 4 3 2 1
3 D3V_S0
vince 20170516 EMI request
SSID = HDMI
2
260mA
C 5717 C 5701
C 5703 change common part PN:71.08201.G03, 20170110
S C100P50V2JN-3DLGP
S CD1U16V2KX-3DLGP
S C10U6D3V3MX-DL-GP
1
1
1 D5V_S0 1 D5V_VDD
C 5714 1 2 H DMI_CLK#_R R 5701
SCD1U16V2KX-3DLGP
[8] H DMI_CLK# C 5709 1 2 SCD1U16V2KX-3DLGP
H DMI_CLK_R 1 2
[8] H DMI_CLK 0R0603-PAD
D C 5707 1 2 H DMI_DATA2_R D
SCD1U16V2KX-3DLGP
[8] H DMI_DATA2 C 5710 1 2 SCD1U16V2KX-3DLGP
H DMI_DATA2#_R U 5701
[8] H DMI_DATA2# Exchange 0603 0ohm , 20141118
11 21 H DMI_CLK#_R_C
VDD33 OUT_CKN H DMI_CLK_R_C
22
1 D5V_VDD OUT_CKP
C 5715 1 2 H DMI_DATA1#_R 25 H DMI_DATA2#_R_C
SCD1U16V2KX-3DLGP OUT_D0P
[8] H DMI_DATA1# C 5712 1 2 SCD1U16V2KX-3DLGP
H DMI_DATA1_R 40 24 H DMI_DATA2_R_C
[8] H DMI_DATA1 VDD15 OUT_D0N H
27 DMI_DATA1#_R_C
OUT_D1P
2
1 2 H DMI_DATA0_R H
C 5702
C 5705
C 5711 19 26 DMI_DATA1_R_C
SC10U6D3V3MX-DL-GP
SCD1U16V2KX-3DLGP
SC100P50V2JN-3DLGP
[8] H DMI_DATA0 1 2 H DMI_DATA0#_R VDD15 OUT_D1N H
C 5706
C 5704
C 5716
C 5708 SCD1U16V2KX-3DLGP DY 30 DMI_DATA0#_R_C
SCD1U16V2KX-3DLGP
SCD1U16V2KX-3DLGP
SCD1U16V2KX-3DLGP
[8] H DMI_DATA0# OUT_D2P H
20 29 DMI_DATA0_R_C
VDD15 OUT_D2N
1
31
VDD15 D DC_CLK_HDMI
32
SCL_SNK D DC_DATA_HDMI
33
H DMI_DATA2#_R SDA_SNK H PD_HDMI_CON
6 28
H DMI_DATA2_R IN_D0P HPD_SNK
7
H DMI_CLK_R_C H DMI_DATA2#_R_C H DMI_DATA0#_R_C H DMI_DATA1_R_C H DMI_DATA1#_R IN_D0N
4 38
H DMI_DATA1_R IN_D1P SCL_SRC C PU_DP1_CTRL_CLK [8]
5 39 C PU_DP1_CTRL_DATA [8]
H DMI_DATA0#_R IN_D1N SDA_SRC
1 3
IN_D2P HPD_SRC C PU_DP1_HPD [8]
2
1
H DMI_DATA0_R 2
IN_D2N
R 5704 vince 20170516 EMI request I2C_CTL_EN
8
180R2J-1-GP 180R2J-1-GP 180R2J-1-GP 180R2J-1-GP H DMI_CLK_R 9
R 5705 R 5702 R 5703 H DMI_CLK#_R IN_CKP P RE
10 16
IN_CKN PRE
1
2
H DMI_CLK#_R_C H DMI_DATA2_R_C H DMI_DATA0_R_C H DMI_DATA1#_R_C D CIN_EN 13
D DCBUF DCIN_EN/SCL_CTL
14 36
DDCBUF/SDA_CTL PD#
C change to 180 for HDMI signal quality 2016/01/05 EQ 17
EQ/I2C_ADDR
C
C FG 23
CFG
35
Change to 4.12k GND
20170327 18 41
5 V_S0 REXT GND
R EXT 12
NC#12
1
5 V_S0 5 V_S5 5 V_HDMI_R_S5 5 V_HDMI_S5 15
F 5701 R 5710 NC#15
37
R 5715 I SET NC#37
POLYSW -1D1A6V-9-GP-U 4D3KR2F-GP 34
NC#34
3
1 2 1 2
D 5701 0R0603-PAD HDMI CONN
2
LBAW 56LT1G-GP 1 DY 2 PS8201ATQFN40GTR2-A0-GP
R 5716 0R3J-0-U-GP vince 20170315
X01 0227
2
For DIODE in case of leakage from HDMI1

5 V_HDMI_S5
H DMI1
D DC_DATA_PH2
D DC_CLK_PH1
18 15 D DC_CLK_HDMI
+5V_POWER SCL D DC_DATA_HDMI
Remove DUMMY-HDMI , 20141118 SDA
16
1
3 D3V_S0 H DMI_DATA0_R_C 7
3 D3V_S0 C 5713 H DMI_DATA0#_R_C 9 TMDS_DATA0+ 13
EQ 2 R 5411 1 H DMI_DATA1_R_C 4 TMDS_DATA0- CEC 17
SCD1U16V2KX-3DLGP TMDS_DATA1+ DDC/CEC_GROUNG
2
2 R 5415 1 H DMI_DATA1#_R_C H PD_HDMI_CON
4K7R2J-2-GP
DY P RE
H DMI_DATA2_R_C
6
TMDS_DATA1- HOT_PLUG_DETECT
19
4K7R2J-2-GP
DY 1
TMDS_DATA2+
1
1
2 R 5412 1 H DMI_DATA2#_R_C 3 14
2 R 5416 1 TMDS_DATA2- RESERVED#14
B
R 5707 R 5706 4K7R2J-2-GP
DY B
2K2R2J-2-GP 2K2R2J-2-GP 4K7R2J-2-GP
DY 8
5 TMDS_DATA0_SHIELD
2 TMDS_DATA1_SHIELD
TMDS_DATA2_SHIELD
2
2
3 D3V_S0 20
3 D3V_S0 11 GND 21
D DC_DATA_HDMI I SET 2 R 5413 1 H DMI_CLK_R_C 10 TMDS_CLOCK_SHIELD GND 22
D DC_CLK_HDMI 2 R 5417 1 H DMI_CLK#_R_C TMDS_CLOCK+ HDMI GND
4K7R2J-2-GP
DY D DCBUF
4K7R2J-2-GP
12
TMDS_CLOCK- (A_Type) GND
23
2 R 5414 1
2 R 5418 1
4K7R2J-2-GP
DY Vince,20161101 SKT-HDMI23-167-GP-U
4K7R2J-2-GP
DY
20170622 Type-c HPD close window

RTC_AUX_S5 3 D3V_S0
R 5419
C PU_DP_HPD_R [8,37,38] D CIN_EN 2 DY 1
1
4K7R2J-2-GP
R5721
Q 5704
100KR2J-1-GP
4 3 3 D3V_S0
R 5722
2
CPU_DP_HPD_R 5 2 H PD_HDMI_CON_C 1 2 H PD_HDMI_CON 2 R 5420 1

N ote:ZZ.27002.F7C01
C FG
A <Core Design> A
R5723 0R0402-PAD 4K7R2J-2-GP
1 2 HDMI_EC_DET#_C 6 1
[24] HDMI_EC_DET#
0R0402-PAD
2N7002KDW-1-GP Wistron Corporation
Title
HDMI
A3
S tarlord KBL-R A00
5 4 3 2 1
5 4 3 2 1
D D
C
(Blanking) C
B B
A <Core Design> A
Wistron Corporation
TTitle
itle
(Reserved)
A3
S tarlord KBL-R A00
WWW.AliSaler.Com
5 4 3 2
1
58 of 106
5 4 3 2 1
D D
C
(Blanking) C
B B
A <Core Design> A
Wistron Corporation
TTitle
itle
(Reserved)
A3
S tarlord KBL-R A00
5 4 3 2 1
5 4 3 2 1
SSID = HDD
R 6002
[16] H DD_DEVSLP 1 2 H DD_DEVSLP_R
0R0402-PAD
SATA HDD Connector Reserved for M15 EE Implementation.
H DD1
R 6001 22 21
1 2 F FS_INT2_Q_R 1 N P1
E [70] F FS_INT2_Q E
0R0402-PAD
2
3
4 Layout Note:
5 V_HDD_SIP 5
6 Place near HDD1
7 1A
8 U 6001
9 5 V_HDD_SIP
10 S ATA_TXP0_R 1 10 S ATA_TXP0_R
S ATA_TXN0_R L INE_1 N C#10 S ATA_TXN0_R
11 2 9
L INE_2 N C#9
12 3 8
H DD_DEVSLP_R S ATA_RXN0_R G NDDY G ND S ATA_RXN0_R
13 4 7
S ATA_RXP0_R L INE_3 N C#7 S ATA_RXP0_R
HDD 14 5 6
S ATA_TXP0_R L INE_4 N C#6
2
[16] S ATA_TX_CPU_P0 SCD01U50V2KX-1GP 1 2 C 6001 15 HDD C 6004
SCD01U50V2KX-1GP 1 2 C 6003 S ATA_TXN0_R 16 SC1U10V2KX-1DLGP 6002
[16] S ATA_TX_CPU_N0 HDD 17
HDD HDDC AZ1045-04F-R7G-GP
SCD1U16V2KX-3DLGP
S ATA_RXN0_R
1
[16] S ATA_RX_CPU_N0 SCD01U50V2KX-1GP 1
HDD22 C 6006 18
SCD01U50V2KX-1GP 1 C 6005 S ATA_RXP0_R 19
[16] S ATA_RX_CPU_P0
HDD 20 N P2
24 23 S wap based on the swap report.
FOX-CON20-1-GP-U1
Close to HDD1
Modify at 20150922
SC1U10V2KX-1DLGP
5 V_S0 5 V_HDD 5 V_HDD_SIP

D R 6006 R 6003 D
1 2 1 2
0R0603-PAD 0R0603-PAD
R 6007
C 6009
0R2J-2-GP
DY U 6002
1 DY 2
[18] HDD_EN_PCH
2
1 8
2 V IN V OUT#8 7
1 2 H DD_EN 3 V IN V OUT#7 6 H DD_CT
[17,24,40,91] SIO_SLP_S0# DY 4 EN DY CT 5
R 6005 V BIAS G ND
SCD1U16V2KX-3GP
1
0R2J-2-GP 9
C6007
G ND
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
C 6008
C6010
DY
1
DY
2
APE8937GN2-GP-U
DY
2
2
Add HDD power switch schematic(reserve) by Win10 feature ,DVT1 20150204
C C
Main Func = ODD

B B
A A
<Core Design>
Title
S ATA IF_HDD/ODD
Size
A 2
Document Number
S tarlord KBL-R
1
Sheet 60 o f
Rev
A 00
106
5 4 3 2 1
Main Func = WLAN
D D
C C
B B
A <Core Design> A
Wistron Corporation
TTitle
itle
NGFF_WLAN CONN
A3
S tarlord KBL-R A00
5 4 3 2 1
A B C D E
4 4
3
(Blanking) 3
2 2
<Core Design>
1
Wistron Corporation 1
Title
Reserved
A4
Starlord KBL-R A 00
WWW.AliSaler.Com
A B C
D
Sheet 62
E
of 106
5 4 3 2 1
SSD = M.2 Vince,20160929
3 D3V_S0 3 D3V_SSD
R 6302 1 2
R 6307 1
0R0603-PAD
2
Vince,20161028
Vince,20161103
0R0603-PAD
1
D C 6305 C 6304 C 6306 C 6308 C 6307 C 6317 C 6318 D
3 D3V_SSD
SSD M.2 CONN
2
SC33P50V2JN-3GP
SC33P50V2JN-3GP
SCD047U25V2KX-GP
SCD047U25V2KX-GP
SCD1U16V2KX-3GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SSD SSD SSD SSD SSD SSD SSD
2
3 D3V_SSD S SD1
PCIE : 1 ; SATA : 0
SSDR 6306
NP2 NP1
NP2 NP1 100KR2J-1-GP
76 77
76 77
74 75
3_3VAUX GND
1
72 73
3_3VAUX GND
70 71
3_3VAUX GND S SD_PEDET R 6310 2 1
68
SUSCLK_32KHZ PEDET(OC_PCIE/GND_SATA)
69 SSD M 2_SSD_PEDET [16]
58 67 0R2J-2-GP
M SATA_RST# NC#58 NC#67
56 57
NC#56 GND
Vince,20161028 54
52
PEWAKE#/NC#54 REFCLKP
55
53
M SATA_CLK_CPU [18]
[18] C LK_PCIE_NVME_REQ# 1 R 6308 2 M SATA_RST# CLKREQ#/NC#52 REFCLKN M SATA_CLK_CPU# [18]
[17,66,91] P LT_RST#
50
PERST#/NC#50 GND
51
S ATA_TX_CPU_P12_C 1
SSD 2C
0R0402-PAD 48 49 6302 SCD22U10V2KX-1GP S ATA_TX_CPU_P12 [16]
NC#48 PERP0/SATA_A+
1
46 47 S ATA_TX_CPU_N12_C 1 2C 6303 SCD22U10V2KX-1GP

NC#46 PERN0/SATA_A- S ATA_TX_CPU_N12 [16]
E D6305
Layout Note: 44
NC#44 GND
45 SSD Vince,20161007
PESD5V0U1BL-GP-U1 DY 42
NC#42 PETP0/SATA_B-
43 S ATA_RX_CPU_N12 [16]
Need close to SSD1 conn R 6301 40
NC#40 PETN0/SATA_B+
41 S ATA_RX_CPU_P12 [16]
1 2 M SATA_DEVSLP_R 38 39 SSD 2C
[16] S SD_DEVSLP DEVSLP GND
2
0R0402-PAD 36 37 P CIE_TX_CPU_P11_C 1 6311 SCD22U10V2KX-1GP

NC#36 PERP1 P CIE_TX_CPU_P11 [16]
34 35 P CIE_TX_CPU_N11_C 1 2C 6312 SCD22U10V2KX-1GP
3 D3V_SSD NC#34 PERN1 P CIE_TX_CPU_N11 [16]
32
NC#32 GND
33 SSD
30 31 P CIE_RX_CPU_P11 [16]
NC#30 PETP1
28 29 P CIE_RX_CPU_N11 [16]
NC#28 PETN1
26 27 SSD 2C
1
3 D3V_SSD NC#26 GND P CIE_TX_CPU_P10_C 1

C
R 6303
24 25 6315 SCD22U10V2KX-1GP P CIE_TX_CPU_P10 [16]
C
NC#24 PERP2 P CIE_TX_CPU_N10_C 1 2C 6316 SCD22U10V2KX-1GP
DY 10KR2J-3-GP
22
NC#22 PERN2
23 P CIE_TX_CPU_N10 [16]
20
18
NC#20 GND
21
19
SSD Vince,20161007
3_3VAUX PETN2 P CIE_RX_CPU_N10 [16]
16 17
2
3_3VAUX PETP2 P CIE_RX_CPU_P10 [16]

S SD_DEVSLP
14
3_3VAUX GND
15
P CIE_TX_CPU_P9_C 1
SSD 2C
12 13 6313 SCD22U10V2KX-1GP P CIE_TX_CPU_P9 [16]
3 D3V_SSD 1 A FTP6304 AFTE14P-GP 3 D3V_SSD 3_3VAUX PERP3 P CIE_TX_CPU_N9_C 1 2C 6314 SCD22U10V2KX-1GP
10 11
1
DAS/DSS# PERN3 P CIE_TX_CPU_N9 [16]

M SATA_DEVSLP_R 1
R 6304
A FTP6302 AFTE14P-GP 8
NC#8 SSD GND
9 SSD Vince,20161007
DY 10KR2J-3-GP S SD_PEDET 1 A FTP6303 AFTE14P-GP
6
NC#6 PETN3
7 P CIE_RX_CPU_N9 [16]
4 5 P CIE_RX_CPU_P9 [16]
3_3VAUX PETP3
2 3
3_3VAUX GND 1
2
NGFF_KEY_M 75P GND
U 6304 U 6303 SKT-MINI67P-15-GP
P CIE_TX_CPU_P10_C 6 5 P CIE_TX_CPU_P10_C P CIE_TX_CPU_P9_C 6 5 P CIE_TX_CPU_P9_C

U 6301
P CIE_TX_CPU_N10_C 7 4 P CIE_TX_CPU_N10_C P CIE_TX_CPU_N9_C 7 4 P CIE_TX_CPU_N9_C
P CIE_RX_CPU_N10 9 2 P CIE_RX_CPU_N10 P CIE_RX_CPU_N9 9 2 P CIE_RX_CPU_N9 S ATA_TX_CPU_P12_C 6 5 S ATA_TX_CPU_P12_C

SSD SSD
P CIE_RX_CPU_P10 10 1 P CIE_RX_CPU_P10 P CIE_RX_CPU_P9 10 1 P CIE_RX_CPU_P9 S ATA_TX_CPU_N12_C 7 4 S ATA_TX_CPU_N12_C
3 3 SSD
8 8 S ATA_RX_CPU_N12 9 2 S ATA_RX_CPU_N12
Vince,20161011 Vince,20161011
B S ATA_RX_CPU_P12 10 1 S ATA_RX_CPU_P12 B
AZ1043-04F-R7G-GP AZ1043-04F-R7G-GP 3
8
Vince,20161011
AZ1043-04F-R7G-GP
U 6302
P CIE_TX_CPU_P11_C 6 5 P CIE_TX_CPU_P11_C
P CIE_TX_CPU_N11_C 7 4 P CIE_TX_CPU_N11_C
P CIE_RX_CPU_P11 9
SSD 2 P CIE_RX_CPU_P11
P CIE_RX_CPU_N11 10 1 P CIE_RX_CPU_N11
3
8
AZ1043-04F-R7G-GP
A <Core Design> A
Wistron Corporation
Title
(Reserved)
A3
S tarlord KBL-R A00
5 4 3 2 1
5 4 3 2 1
SSID = Power BTN
D Battery LED1 (AMBER_LED) D
Low actived from KBC GPIO

5 V_S5
Q 6402
R 6403 R2 E
1 2 C HG_AMBER_LED_R# B R 6401
[24] C HG_AMBER_LED# C A MBER_LED_BAT 2 1
R1
0R0402-PAD B AT_AMBER [65] AMBER
499R2F-2-GP
1
LDTA144VLT1G-GP
1
E D6401
DYE C6401 PESD5V0S1BB-GP-U
SC220P50V2KX-3GP DY
2
5 V_S5
Q 6401
C R 6404 R2 E C
1 2 B ATT_W HITE_LED_R# B R 6402
[24] B ATT_W HITE_LED# 0R0402-PAD
R1
C W HITE_LED_BAT 2 1 B AT_W HITE [65]
330R2J-3-GP
WHITE
1
LDTA144VLT1G-GP
1
E D6402
DYE C6402 PESD5V0S1BB-GP-U
SC220P50V2KX-3GP DY
2
Battery LED2 (WHITE_LED)
Low actived from KBC GPIO
B B
Vince, 20170116
SATA LED Q 6403

S (Vth:1.1V)
[16] S ATA_LED#
D B ATT_W HITE_LED_R#
G HWHDLED
[24] M ASK_SATA_LED#
PJA138KA-GP
1D8V_S0
R 6120
1 2 M ASK_SATA_LED#
HWHDLED
10KR2J-3-GP
Add SATA LED solution by customer request 2016/02/03

A <Core Design> A
Wistron Corporation
Title
LED Board&Power Button

A3
Starlord KBL-R A 00
1
64 of 106
5 4 3 2 1
SSID = KB
Vince,20161103 K SO10 C65161 2 SC100P50V2JN-3GP
SI0 C65051 SC100P50V2JN-3GP SO11
E DY
C65151 SC100P50V2JN-3GP
Keyboard
K E DY 2 K E DY 2
K SI3 C65061 2 SC100P50V2JN-3GP K SO9 C65181 2 SC100P50V2JN-3GP
K SI1
E DY
C65071 2 SC100P50V2JN-3GP K SO14
E DY
C65141 2 SC100P50V2JN-3GP
Vince,20170208 K SI5
E DY
C65081 2 SC100P50V2JN-3GP K SO13
E DY
C65171 2 SC100P50V2JN-3GP
K SI2
E DY
C65091 2 SC100P50V2JN-3GP K SO15
E DY
C65191 2 SC100P50V2JN-3GP
SI4
E DY SO16
E DY
K BBL1 K E C65101
DY 2 SC100P50V2JN-3GP K E C65201
DY 2 SC100P50V2JN-3GP
5 K SI6 C65111 2 SC100P50V2JN-3GP K SO12 C65131 2 SC100P50V2JN-3GP
[24] K SI[0..7] 1 K SI7
E DY
C65121 2 SC100P50V2JN-3GP K SO0
E DY
C65241 2 SC100P50V2JN-3GP
K B1 + 5V_KB_BL E DY K SO2
E DY
C65231 2 SC100P50V2JN-3GP
K B_LED_DET_C 2 K SO1
E DY
C65261 2 SC100P50V2JN-3GP
[24] K SO[0..16] 31 3 K SO3
E DY
C65221 2 SC100P50V2JN-3GP
K B_BL_CTRL# 4 K SO8
E DY
C65251 2 SC100P50V2JN-3GP
C AP_LED SO6
E DY
1 6 E C65301DY 2 SC100P50V2JN-3GP K E C65271
DY 2 SC100P50V2JN-3GP
K SO7 C65281 2 SC100P50V2JN-3GP
2 ACES-CON4-90-GP-U K SO4
E DY
C65211 2 SC100P50V2JN-3GP
SO5
E DY
D A FTP6538 1 3 K E C65291
DY 2 SC100P50V2JN-3GP D
C AP_LED 4
C AP_LED
A FTP6523 1 K SO10 5 EMI request
A FTP6522 1 K SO11 6
A FTP6504 1 K SO9 7
A FTP6521 1 K SO14 8
A FTP6520
A FTP6524
1
1
K SO13
K SO15
9
10
Main Func = TPAD
A FTP6539 1 K SO16 11
A FTP6519 1 K SO12 12 L ED1
A FTP6507 1 K SO0 13 5 TP_VDD Discharge Circuit
A FTP6513 1 K SO2 14 1 3 D3V_S5 3 D3V_S0 T P_VDD
A FTP6511 1 K SO1 15 NON TP_WAKE
A FTP6518 1 K SO3 16 [64] 2 T P_VDD
B AT_AMBER
A FTP6516 1 K SO8 17 [64] 3 R 6502
1 2
B AT_WHITE
A FTP6517 1 K SO6 18 4 0R3J-0-U-GP
A FTP6515 1 K SO7 19 6 Q 6502 Q 6502_D
1
A FTP6514 1 K SO4 20 DMG3415U-GP
A FTP6510 1 K SO5 21 ACES-CON4-66-GP R 6514 TP_WAKE R 6503
A FTP6512 1 K SI0 22 S D 1 2
TP_WAKE 100R3J-4-GP
K SI3 23 Q 6503
A FTP6509 1 C 6502 TP_WAKE
A FTP6501 1 K SI1 24 SCD1U16V2KX-3DLGP 0R3J-0-U-GP T P_ON#_GATE G
2
1
A FTP6506 1 K SI5 25
A FTP6508 1 K SI2 26 D Q 6205_Q
TP_WAKE TP_WAKE TP_WAKE
G
A FTP6505 1 K SI4 27 Add 0ohm , 20141118
T P_ON#_GATE
2
A FTP6503 1 K SI6 28 [24] T P_EN# 1 2 S
A FTP6502 1 K SI7 29
[20] 30 R 6504
K B_DET# 2N7002K-2-GP
20KR2F-L-GP
32
PTWO-CON30-18-GP
C T P_VDD C
GPIO_TPAD: TBD
(Touch pad wake# for S3 wake up @ PCH GPIO??)
2
1
R N6501
SRN10KJ-5-GP
Vince,20161201 ACES-CON8-66-GP
3
4
T P_VDD
R N6502 9
SRN33J-5-GP-U 1
2 3 T PCLK_C
PS2 [24] C LK_TP_SIO
[24] D AT_TP_SIO 1 4 T PDATA_C I 2C0_SDA_R 2
I 2C0_SCL_R
1
3
[20] I 2C0_SCL_TCH_PAD 0R2J-2-GP1 2
NON TP_WAKE R 6505I 2C0_SCL_R C 6503 4
0R2J-2-GP1 2
NON TP_WAKE R 6506I 2C0_SDA_R 5
SCD1U16V2KX-3DLGP
I2C [20] I 2C0_SDA_TCH_PAD [4,24]T P_WAKE_KBC#
2
[24] P TP_DIS#_R 6
T PDATA_C 7
T PCLK_C 8
A FTP225 1 1 0
SC33P50V2JN-3GP
SC33P50V2JN-3GP
SC33P50V2JN-3GP
EC6502
EC6503
EC6504
1
1
T P1
E C6501
SC33P50V2JN-3GP DY DY DY DY Vince,20161102
2
5V_S0 + 5V_KB_BL
F6501
1 KBBL 2
1
POLYSW-1D1A6V-9-GP-U C hange pindefine DVT1 0210 1330
1 2
KBBLC 6501
DY SCD1U16V2KX-3DLGP Pin number Pin name
2
B R6501 0R3J-0-U-GP Need to check if it is Active High or Active Low B
and check if there is PH on TPAD side. 1 VDD

5 V_S0 2 DAT(I2C)
X02 0415 3 CLK(I2C)
KB Backlight Power Consumption: 285mA max. T P_VDD T P_VDD 4 GND
2
5 ATTN
R 6510
K B_BL_CTRL# 0R0402-PAD 6 GPIO
1
2
1
R 6511 7 DAT(PS2)
1
R N6503 10KR2J-3-GP
SRN2K2J-1-GPTP_WAKE 8 CLK(PS2)
D
2
Q 6501 R 6507 Q 6204_G T P_WAKE_KBC#
3
4
DMN3404L-7-1-GP 1 K B_LED_DET_C
G
KBBL [19] K B_LED_BL_DET KBBL 2
[24] KB_LED_PWM Q 6504
1
51KR2J-1-GP
I 2C0_SCL_TCH_PAD I 2C0_SCL_R P_VDD
1
1 6 T 1 A FTP6531
ote:ZZ.27002.F7C01
N
S
T PCLK_C 1
DY R 6509 KBBL R 6508 DY C 6504 PDATA_C
A FTP6532
S CD1U16V2KX-3GP
100KR2J-1-GP 100KR2J-1-GP 2 5 T 1 FTP6533

TP_WAKE A
2
I 2C0_SCL_R 1 A FTP6534
2
3 4 I 2C0_SDA_R I 2C0_SDA_R 1 A FTP6535

2
T P_WAKE_KBC# 1 A FTP6536
P TP_DIS#_R 1 A FTP6537
2N7002KDW-1-GP
I 2C0_SDA_TCH_PAD
+ 5V_KB_BL 1
A FTP6529
KB_BL_CTRL# 1
A FTP6530
CAP LED Control

A LOW actived from KBC GPIO A
<Core Design>
5 V_S5
R 6512
Q 6505
R2
E
1 2 C AP_LED_R# B
[24] CAP_LED#_R Taipei Hsien 221, Taiwan, R.O.C.
R1
C C AP_LED_Q 1 2 C AP_LED
R 6513 1KR2J-1-GP Title
0R0402-PAD
LDTA144VLT1G-GP
K ey Board&Touch Pad
A 2
5 4 3 2 1
5 4 3 2 1
SSID = IO Connector
IOBD1
51
53
1 Change choke Height just for Starload
Cutomer remove IO board USB3.0 2015/09/23 modify
2
3
4
D 5 D
6
7
8
P CIE_RX_CPU_P6 [16] Vince,20170105
P CIE_RX_CPU_N6 [16] COIL-90OHM-100MHZ-5-GP
9 U SB_CPU_PP2_C 4 3 U SB_CPU_PP2 [16]
10
11 P CIE_TX_WLAN_N6 [16] U SB_CPU_PN2_C 1 2
P CIE_TX_WLAN_P6 [16] WLAN U SB_CPU_PN2 [16]
12
13 E L6601
14 P EG_CLK1_CPU# [18]
15 P EG_CLK1_CPU [18]
16 U SB_CPU_PN6_C
17 U SB_CPU_PP6_C Vince,20161025
18
19 U SB_CPU_PN2_C
20 U SB_CPU_PP2_C USB3.0 port3
21
22 U SB_CPU_PN5_C
23 U SB_CPU_PP5_C Card Reader
24
25
26
27
Vince,20161025 COIL-90OHM-100MHZ-5-GP
28 U SB_CPU_PP5_C 4 3
5 V_S5 U SB_CPU_PP5 [16]
29
30 U SB_CPU_PN5_C 1 2 U SB_CPU_PN5 [16]
31
32 E L6602
33
C 34
Vince,20161025 C
+ RTC_VCC
35
36 3 D3V_S0
37
38
39
40
41 V OL_UP# [24]
42 V OL_DOW N# [24]
43
44 P LT_RST# [17,63,91]
C LK_PCIE_WLAN_REQ# [18] E L6603
45 K BC_PW RBTN# [24]
46 U SB_CPU_PN6_C 1 2
W IFI_RF_EN [15] U SB_CPU_PN6 [16]
47
48 B LUETOOTH_EN [20] U SB_CPU_PP6_C 4 3
U SB_OC1# [16] U SB_CPU_PP6 [16]
49
50 U SB_EN# [24,35]
54
52
IPEX-CON50-1-GP
EMI Reserve , 20141118
B G PU1 K BC_PW RBTN# P LT_RST# W IFI_RF_EN B
1
A1 B1 DY DY DY
C6601
C6602
C6603
SC33P50V2JN-3GP
SC33P50V2JN-3GP
SC33P50V2JN-3GP
A2 A1 B1 B2
[18] C LK_PCIE_PEG_REQ# A2 B2 d GPU_RXP_C_CPU_TXP2 [16]
2
A3 B3
A3 B3 d GPU_RXN_C_CPU_TXN2 [16]
E
A4 B4
[16] d GPU_RXP_C_CPU_TXP0 A5 A4 B4 B5
[16] d GPU_RXN_C_CPU_TXN0 A6 A5 B5 B6
d GPU_RXP_C_CPU_TXP3 [16]
A6 B6 d GPU_RXN_C_CPU_TXN3 [16]
A7 B7 G PU2
[16] d GPU_RXP_C_CPU_TXP1 A8 A7 B7 B8
[16] d GPU_RXN_C_CPU_TXN1 A9 A8 B8 B9 C LK_PCIE_VGA [18] A1 C1
A9 B9 C LK_PCIE_VGA# [18] D CBATOUT A1 C1
A10 B10 A2 C2
A10 B10 A3 A2 C2 C3
C1 D1 A4 A3 C3 C4
[20] G C6_FB_EN C2 C1 OPS D1 D2 P LT_RST# [17,63,91] A5 A4 C4 C5
[24] O VER_CURRENT_P8# C9 C2 D2 D9 A6 A5 C5 C6
C9 D9 D GPU_PW ROK [19,24] A6 C6
C10 D10 D GPU_HOLD_RST# [20]
[20] D GPU_PW R_EN C10 D10 B1 D1
E1 F1 B2 B1 D1 D2
E1 F1 3 D3V_AUX_S5 B2 D2
E2 F2 B3 D3
[16] CPU_RXP_C_dGPU_TXP0 E2 F2 B3 D3
E3 F3 B4 D4
[16] CPU_RXN_C_dGPU_TXN0 E3 F3 B4 D4
E4 F4 C PU_RXP_C_dGPU_TXP2 [16] B5 D5
E5 E4 F4 F5 B6 B5 D5 D6
[16] CPU_RXP_C_dGPU_TXP1
E6 E5 F5 F6
C PU_RXN_C_dGPU_TXN2 [16] B6 OPS D6
[16] CPU_RXN_C_dGPU_TXN1 E6 F6
E7 F7 C PU_RXP_C_dGPU_TXP3 [16] 3 D3V_S0 P1 N1
E8 E7 F7 F8 P2 P1 N1 Wistron Confidential document, Anyone can not
[18,24,26] SML1_SMBCLK E8 F8 C PU_RXN_C_dGPU_TXN3 [16] P2 Duplicate, Modify, Forward or any other purpose
E9 F9 P3 NP1
[18,24,26] SML1_SMBDATA E10 E9 F9 F10 P4 P3 NP1 NP2 application without get Wistron permission
E10 F10 G PU_EVENT# [20] 5 V_S0 P4 NP2 NP3
A NP3 <Core Design> A
NP1 N1
NP2 NP1 N1
NP2
NP3
NP3
UNI-CONN28-6R-GP-U
Wistron Corporation
UNI-CONN48-6R-GP-U2 Taipei Hsien 221, Taiwan, R.O.C.
Title
IO Board Connector
A3
Starlord KBL-R A 00
1
66 of 106
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
TTitle
itle
Reserved
A3
S tarlord KBL-R A00
5 4 3 2 1
5 4 3 2 1
SSID = Debug
D D
Debug Connector
DB1
R6801 15
R6807 2 1 ESPI_CLK_C 2 1ESPI_ALERT#_ESPI 1
[18,24] ESPI_CLK DEBUG 0R2J-2-GP [18,24] ESPI_ALERT# DY 0R2J-2-GP
ESPI_CLK_C 2
3
[18,24] ESPI_IO[3..0] [18,24] ESPI_RESET# 4
ESPI_IO3 R6803 2 1 ESPI_IO3_C 5
ESPI_IO2 R6804 2
DEBUG
1 0R2J-2-GP ESPI_IO2_C
[18,24] ESPI_CS#
ESPI_IO3_C 6
ESPI_IO1 R6805 2
DEBUG
1 0R2J-2-GP ESPI_IO1_C ESPI_IO2_C 7
DEBUG
ESPI_IO0 R6806 2
DEBUG
1 0R2J-2-GP ESPI_IO0_C 3D3V_S0 ESPI_IO1_C 8
DEBUG 0R2J-2-GP ESPI_IO0_C 9
R6802 2
DEBUG 10R2J-2-GP 1D8V_ESPI 10
R6808 2 1 HOST_DEBUG_TX_CON 11
C
[24] HOST_DEBUG_TX DEBUG
0R2J-2-GP 12
C
R6809 2 1 UART_2_CTXD_DRXD_CON 13
[20] UART_2_CTXD_DRXD
R6810 2
DEBUG
0R2J-2-GP
1 UART_2_CRXD_DTXD_CON 14
[20] UART_2_CRXD_DTXD DEBUG
0R2J-2-GP 16
ACES-CON14-5-GP
Vince,20170106
B B
<Core Design>
A
Title
Dubug connector
A4
Starlord KBL-R A 00
WWW.AliSaler.Com 5 4 3
2
Sheet 68
1
of 106
5 4 3 2 1
D D
C C
B B
A <Core Design> A
Wistron Corporation
TTitle
itle
Reserved
A3
S tarlord KBL-R A00
5 4 3 2 1
5 4 3 2 1
Main Func = Hall Sensor
LID sensoe combine G

3 D3V_S5 3 D3V_S5
2
R 7001 R 7011
DY DY 3 D3V_S5 G YRO_INT_P11 1
DY 2
G YRO_INT [55]
D G MR1 0R2J-2-GP R 7002 D
1
R 7003
1 4 1 2
[24] K B_CLOSE#_2 O UT2 O UT1 L ID_CL_SIO# [24] [20] G YRO_INT_C
2 3 0R0402-PAD
G ND V DD
1
C 7002
1
HGDEDM013A-GP SCD1U16V2KX-3DLGP
2
C 7001
DY
S
CD047U16V2KX-1-GP
D 7001
G YRO_INT_P11 1
DY 3
F FS_INT2 [20]
I NT2_SELECT 2
BAT54A-7-F-2-GP
R 7008
1 2
0R0402-PAD
C C
Note:
- no via, trace, under the sensor (keep out area around 2mm)
- stay away from the screw hole or metal shield soldering joints
3D3V_S0 3 D3V_GSEN2 - design PCB pad based on our sensor LGA pad size (add 0.1mm)
C7004 - solder stencil opening to 90% of the PCB pad size
R 7004 near pin9
1 2
0R0402-PAD
11uA
Free Fall Sensor + G Sensor - mount the sensor near the center of mass of the NB as possible as you can
1
C 7003 C 7004
SC10U6D3V3MX-GP
SCD1U16V2KX-3DLGP
2
3 D3V_GSEN2
U 7001
R 7006
Please help to close with U6602
9 2 G SENSOR_CS 1 2
V DD CS 5 3 D3V_S0
10 R ES
V DD_IO 12 G SEN2_INT1 10KR2J-3-GP
I NT1 G SEN2_INT2
1
11
I NT2 R 7018
S ENSOR_I2C_SCL_2G 1 100KR2J-1-GP
S ENSOR_I2C_SDA_2G 4 S CL/SPC 6
R 7005 1 2 10KR2J-3-GP 3 S DA/SDI/SDO G ND 7
3D3V_GSEN2 DY S DO/SA0 G ND
2
8 F ALL_INT2
R 7007 1 2 G SENSOR_SDO G ND
0R0402-PAD
LNG2DMTR-GP
1
B B
Q 7001
2N7002KDW-1-GP
ote:ZZ.27002.F7C01
N
6
G SEN2_INT1_C R 70091 2 G SEN2_INT1
[20] GSEN2_INT1_C
0R0402-PAD
G SEN2_INT2_C R 70101 2 G SEN2_INT2
[20] GSEN2_INT2_C
0R0402-PAD
I NT2_SELECT
F FS_INT2_Q [60]
R 70121 2 Note:
[18] FFS_INT1
I NT2_SELECT
0R0402-PAD (1) Keep all signals are the same trace width. (included VDD, GND).
R 70131 2
0R0402-PAD
(2) No VIA under IC bottom.
R N7001
2 3 S ENSOR_I2C_SCL_2G
[20,55] SENSOR_I2C_SCL 1 4 S ENSOR_I2C_SDA_2G
[20,55] SENSOR_I2C_SDA
SRN0J-6-GP
A A
<Core Design>
Title
( Reserved)
Size
A 2
Document Number

S tarlord KBL-R
1
Sheet 70 o f
Rev
A 00
106
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
TTitle
itle
Size
RESERVED
Document Number Rev
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A <Core Design> A
Wistron Corporation
TTitle
itle
USB3.0 PORT
A3
S tarlord KBL-R A00
WWW.AliSaler.Com
5 4 3 2
1
72 of 106
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
TTitle
itle
Reserved
A3
S tarlord KBL-R A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
TTitle
itle
Reserved
A3
S tarlord KBL-R A00
WWW.AliSaler.Com
5 4 3 2
1
74 of 106
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
TTitle
itle
Reserved
A3
S tarlord KBL-R A00
5 4 3 2 1
5 4 3 2 1
Main Func = dGPU
D D
C C
B B
A A
<Core Design>
T Title
itle
G PU(1/5)PEG
WWW.AliSaler.Com
A 2
5 4 3 2 1
5 4 3 2 1
Main Func = dGPU
D D
C C
B B
A A
<Core Design>
itle
T Title
G PU(2/5)DIGITALOUT
A 2
5 4 3 2 1
5 4 3 2 1
Main Func = dGPU
D D
C C
B B
A A
<Core Design>
itleT
Title
WWW.AliSaler.Com
G PU(3/5)VRAMI/F
1 A
S tarlord KBL-R
Monday, August 28, 2017
0A0
Date: Sheet 78 f o 106
5 4 3 2 1
5 4 3 2 1
Main Func = dGPU
D D
C C
B B
A A
<Core Design>
Wistron Corporation
T Title
itle
GPU(4/5)GPIO/STRAP
C ustom
Starlord KBL-R
Monday, August 28, 2017
A 00
Date: Sheet 79 o f 106
5 4 3 2 1
5 4 3 2 1
Main Func = dGPU
D D
C C
B B
A A
<Core Design>
Wistron Corporation
TTitle
itle
GPU(5/5)PWR/GND
WWW.AliSaler.Com
5 4 3 2
Size
C ustom
Date:
Document Number
Starlord KBL-R
Monday, August 28, 2017 Sheet
1
80 of
Rev
106
A00
5 4 3 2 1
Main Func = dGPU
D D
C C
B B
<Core Design>
A A
Wistron Corporation
TTitle
itle
GPU-VRAM1,2 (1/4)
A3
Starlord KBL-R A 00
5 4 3 2 1
5 4 3 2 1
Main Func = dGPU
D D
C C
B B
<Core Design>
A A
Wistron Corporation
TTitle
itle
GPU-VRAM3,4 (2/4)
A3
Starlord KBL-R A 00
WWW.AliSaler.Com
5 4 3 2
1
82 of 106
5 4 3 2 1
Main Func = dGPU
D D
C C
B B
A <Core Design> A
Wistron Corporation
TTitle
itle
GPU-VRAM5,6 (3/4)
A3
Starlord KBL-R A 00
5 4 3 2 1
5 4 3 2 1
Main Func = dGPU
D D
C C
B B
<Core Design>
A A
Wistron Corporation
TTitle
itle
GPU-VRAM7,8 (4/4)
A3
Starlord KBL-R A 00
WWW.AliSaler.Com
5 4 3 2
1
84 of 106
5 4 3 2 1
Main Func = dGFX_CORE
D D
C C
B B
A A
<Core Design>
itle
T Title
G PU CORE
A 2
5 4 3 2 1
5 4 3 2 1
Main Func = dGPU
D D
C C
B B
A A
<Core Design>
itle
T Title
G PU Discrete Power
WWW.AliSaler.Com
5 4 3 2
Size
A 2
Document Number
S tarlord KBL-R
1
Sheet 86 o f
Rev
A 00
106
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
TTitle
itle
Reserved
A3
S tarlord KBL-R A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
TTitle
itle
Reserved
A3
S tarlord KBL-R A00
WWW.AliSaler.Com
5 4 3 2
1
88 of 106
5 4 3 2 1
SSID = UnusedParts
34.4YW18.001 ZZ.00PAD.7F1 ZZ.00PAD.7G1

H2 H4 H3 H6
S PR3 S PR4 S PR2
HOLE335R178-GP HOLE335R178-GP H5 HOLE335R229-GP HOLE335R229-GP
SPRING-171-GP SPRING-7-GP SPRING-171-GP HOLE335R229-GP
D D
1
1
1
S PR1
SPRING-171-GP
H7 H8 H9 H 10
1
HOLE335R178-GP HOLE335R178-GP HOLE335R178-GP HOLE335R178-GP H S1 STFSR158R113H62-GP STFSR158R113H62-GP
STF217R115H101-2-GP H S2 OPS H S3
OPS
1
NP1
NP1
SSID = EMI
1
D CBATOUT
Mind the voltage rating of the caps.
C C
A UD_AGND 5 V_S5 5 V_S0 1 D2V_S3

E C8906 E C8907 E C8908
1
SC1U50V3KX-GP
EC8905
SC2200P50V2KX-2GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
DY DY DY
E C8901 E C8902 E C8903 E C8904
2
2
1
SC1KP50V2KX-1GP
SCD1U25V2KX-GP
E
E
E C8914 E C8915 E C8916 E C8917
C8918
C8919
1
1
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
S
DY DY DY DY DY DY
CD1U25V2KX-GP
CD1U25V2KX-GP
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
2
Vince,20161111
2
E C8930 E C8931 E C8932 E C8939 E C8940 E C8941 E C8942 E C8943 E C8944 E C8945
1
1
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
DY DY DY DY DY DY DY DY DY DY Change to 0.1uF at 20150427 for EMI
2
2
3 D3V_S0 3 D3V_S5 + DC_IN
E C8952 E C8951 E C8955 E C8947 E C8949 E C8950 E C8953 E C8954 E C8946 E C8948 E C8909 E C8910 E C8911 E C8912 E C8913
1
1
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
S
SSID = RF DY DY DY
CD1U25V2KX-GP
CD1U25V2KX-GP
CD1U25V2KX-GP
CD1U25V2KX-GP
CD1U25V2KX-GP
DY DY DY DY DY DY DY DY DY DY
2
2
B B
1 D2V_S3
D CBATOUT
E C8920 E C8921 E C8922 E C8923 E C8924 E C8925 D CBATOUT
1
1
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
2
E C8926
1
1
1
SC1U50V3KX-GP
SC1U50V3KX-GP
SC1U50V3KX-GP
EC8927
EC8928
EC8929
SC2D2U10V2KX-GP
DY
2
2
Change to 0.1uF at 20150427 for EMI
1D2V_S3
Remove EC8931,EC8932,EC8926,EC8930for placement RF request 2016/01/12 modify

A <Core Design> A
1
EC8933DY EC8934DY EC8935DY EC8936 EC8937 E C8938

Wistron Corporation
SC2200P50V2KX-2GP
SC2200P50V2KX-2GP
SC2200P50V2KX-2GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
2

TTitle
itle
UNUSED PARTS/EMI Capacitors

A3
Change to 0.1uF at 20150427 for EMI Starlord KBL-R A 00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
TTitle
itle
Reserved
A3
S tarlord KBL-R A00
WWW.AliSaler.Com
5 4 3 2
1
90 of 106
5 4 3 2 1
SSID = TPM
Vince,20160922 3 D3V_S5 3 D3V_TPM
R 9101
1 2
Vince,20161123 DY
0R2J-2-GP
1
D 3 D3V_S0 C 9105 C 9101 C 9104 C 9102 D
TPM
R 9102
C4D7U6D3V3KX-GP
C2200P50V2KX-2GP
C2200P50V2KX-2GP
CD1U16V2KX-3DLGP
S
S
TPM TPM TPM
2
1 DY 2
0R2J-2-GP
3 D3V_S5_PCH
R 9103
1 TPM 2
0R2J-2-GP
3 D3V_TPM
2 0150613 modify
Vince,20160929
3 D3V_TPM R 91401TPM 2 10KR2J-3-GP
2
R 9138
Vince,20160929
0R2J-L-GP 2 1 R 9130 S PI_CS2#_R_TPM2 Q 9102 3 D3V_TPM
[18] S PI_CS2#_R S PI_SO_ROM TPM S PI_SO_ROM_TPM2 Q 9104 DY 0R2J-L-GP
R 91341 2 33R2J-2-GP DMP2130L-7-GP
[18,25] S PI_SO_ROM
S PI_SI_ROM R 91391 TPM 2 33R2J-2-GP S PI_SI_ROM_TPM2 SSM3K15AMFV-GP-U
[18,25] S PI_SI_ROM
S PI_CLK_ROM TPM S PI_CLK_ROM_TPM2
1
R 91321 2 33R2J-2-GP
[18,25] S PI_CLK_ROM TPM S DY D T PM_GPIO2 S
T PM_GPIO2 D
3D3V_TPM
D
1
EV Reseved for modern stanby DY
G
R 9131DY
S PI_IRQ#_TPM2
G
R9119 1DY 2 10KR2J-3-GP 10KR2J-3-GP
S PI_IRQ#_TPM2 [18]
G
R 9142
2 1 S PI_CS2#_R Q 9102.G 1 R 9129 2 S PI_CS2#_R
[17,24,40,60] S IO_SLP_S0# DY
2
0R2J-L-GP DY
100R2F-L1-GP-U
Vince DVT2,20170511
C U 9104 3 D3V_S0 C
3 D3V_TPM + UZ12_TPM 8 29 T PM_GPIO0 R 91411 TPM 2

V DD S DA/GPIO0 30 10KR2J-3-GP
R 9147 1 2 0R2J-L-GP T PM_VDD14 14 G PIO1/SCL 3 T PM_GPIO2 R 91201 2
3 D3V_S5 3 D3V_TPM_1
TPM 0R2J-L-GP T PM_VDD22 22 V HIO G PX/GPIO2 6 DY
R 9149 1 TPM 2
HIO
10KR2J-3-GP
R 9143 V G PIO3/BADD 13 T PM_GPIO4 R 91331 2S PI_CS2#_R
1 2 R 9144 1 2 0R2J-L-GP T PM_VSB 1 C LKRUN#/GPIO4/SINT# DY
TPM TPM V SB 12
0R2J-L-GP
0R2J-L-GP R ESERVED#12
SC4D7U6D3V3KX-GP
SCD1U16V2KX-3GP
1
1
C9106
C9113
S PI_SO_ROM_TPM2 24 2
S PI_SI_ROM_TPM2 21 L AD0/MISO
TPM N C#2 7
TPM TPM 18 L AD1/MOSI N C#7
2
S PI_IRQ#_TPM2 10
15 L AD2/SPI_IRQ# N C#10 11
L AD3 N C#11 25
3D3V_S0 R 9136 1 P LT_RST#_Q_TPM2 17 N C#25 26
R9145
[17,63,66] P LT_RST#
0R2J-L-GP
TPM2 S PI_CLK_ROM_TPM2 19 L RESET#/SPI_RST#/SRESET# N C#26 31
1 2 0R2J-L-GP S PI_CS2#_R_TPM2 20 L CLK/SCLK N C#31
TPM S ERIRQ_TPM 27 L FRAME#/SCS#
3D3V_S5 28 S ERIRQ 9
L PCPD# G ND 16
R9146 + UZ12_TPM G ND
1
1 23
DY 2 R 9148 4 G ND 32
0R2J-L-GP
10KR2J-3-GP 5 PP G ND 33
TPM T EST G ND
1
TPM C 9114
2
SC4D7U6D3V3KX-GP NPCT650VB2YX-GP
2
B B
A A
<Core Design>
Title
T PM2.0
A 2
5 4 3 2 1
5 4 3 2 1
D D
C (Blanking) C
B B
<Core Design>
A
Title
(Reserved)Finger Print
A4
Starlord KBL-R A 00
WWW.AliSaler.Com
5 4 3
2
Sheet 92
1
of 106
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
TTitle
itle
(Reserved)
A3
S tarlord KBL-R A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
TTitle
itle
(Reserved)
A3
S tarlord KBL-R A00
WWW.AliSaler.Com
5 4 3 2
1
94 of 106
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
TTitle
itle
(Reserved)
A3
S tarlord KBL-R A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
TTitle
itle
(Reserved)
A3
S tarlord KBL-R A00
WWW.AliSaler.Com
5 4 3 2
1
96 of 106
5 4 3 2 1
D D
C C
(Blanking)
B B
<Core Design>
A A
Wistron Corporation
TTitle
itle
LVDS_Switch
A3
Starlord KBL-R A 00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
<Core Design>
A A
Wistron Corporation
TTitle
itle
CRT_Switch
A3
Starlord KBL-R A 00
WWW.AliSaler.Com
5 4 3 2
1
98 of 106
5 4 3 2 1
Main Func = Debug
D D
C C
B B
A A
<Core Design>
itle
T Title
C PU_XDP;PCH_XDP
A 2
5 4 3 2 1
5 4 3 2 1
CLK Block Diagram
Intel CPU
D Haswell/Broadwell ULT D
M_A_DIMA_CLK_DDR0
CK0 SA_CLK0
M_A_DIMA_CLK_DDR#0
CK0# SA_CLK#0
DDR3L DIMM1
M_A_DIMA_CLK_DDR1
CK1 SA_CLK1
M_A_DIMA_CLK_DDR#1
CK1# SA_CLK#1 CLK_PCIE_WLAN_P3
CLKOUT_PCIE_P2 REFCLKP0
WLAN
CLKOUT_PCIE_N2
CLK_PCIE_WLAN_N3
REFCLKN0 NGFF
LAN
CLK_PCIE_LAN_P4
RTL8106E/RTL8111G
CLKOUT_PCIE_P3 REFCLK_P
FBA_CLK0P CLK_PCIE_LAN_N4
CK CLKOUT_PCIE_N3 REFCLK_N
VGA
C C
VRAM1 FBA_CLK0N
CK#
N15V-GM-S-A2
GB2-64 (23x23) LANXIN
CKXTAL1
FBA_CLK0P
CLK_PCIE_VGA#
CK ‧ FBA_CLK0 PEX_REFCLK# CLKOUT_PCIE_N4
FBA_CLK0N
VRAM2 CK# ‧ FBA_CLK0# X3001
25MHz
CLK_PCIE_VGA
PEX_REFCLK CLKOUT_PCIE_P4
LANXOUT
CKXTAL2
FBA_CLK1P
CK 27MHZ_IN
XTAL_IN
VRAM3 CK#
FBA_CLK1N
X7601
27MHz
FBA_CLK1P
CK FBA_CLK1
VRAM4 FBA_CLK1N ‧
FBA_CLK1# XTAL_OUT
27MHZ_OUT Audio
‧
CK#
RN2102
Realtek
HDA_BCLK/I2S0_SCLK
HDA_BITCLK HDA_CODEC_BITCLK
BITCLK ALC3223
B SRN33J-5-GP-U B
RTC_X1
RTCX1
X1901
R5815
0R2J-2-GP
SUSCLK_NGFF
SUS_CLK NGFF
32.768KHz
RTC_X2
RTCX2
XTAL24_IN KBC
XTAL24_IN NPCE285P
SUS_CLK_PCH R1710 SUS_CLK R2441 SUS_CLK_KBC
X1801 SUSCLK/GPIO62 ‧ GPIO0/EXTCLK/F_SDIO3
0R2J-2-GP 0R2J-2-GP
24MHz CLK_PCI_KBC_R R1805 CLK_PCI_KBC
CLKOUT_LPC_1 LCLK/GPIOF5
0R2J-2-GP
XTAL24_OUT
CLKOUT_LPC_0 CLK_PCI_LPC_R CLK_PCI_LPC
XTAL24_OUT
R1804
0R2J-2-GP
LPC
CLKOUT_ITPXDP#
CLKOUT_ITPXDP_P
Test Point
A A
<Core Design>
itle
T Title
C LK Block Diagram
WWW.AliSaler.Com
5 4 3 2
Size
A 2
Document Number
S tarlord KBL-R
1
Sheet 100 o f
Rev
A 00
106
5 4 3 2 1
Change notes -
DATE VERSON DATE Page Modify List OWNER
D D
C C
B B
<Core Design>
A A
Wistron Corporation
TTitle
itle
Change History
A3
S tarlord KBL-R A00
5 4 3 2 1
5 4 3 2 1
SKL-U/Y Timing Diagram for G3 to S0/M0 [Non Deep Sx Platform] T ulip Skylake POWER UP SEQUENCE DIAGRAM (Deep Sx Platform)
For DDR4 power sequence 3D3V_S5 5V_S5 1D05V_S5
Red: Power Rail IN IN
Orange: Output from KBC 74LVC1G07GW VCCSTU_EN SLG59M1470VTR +V1.00U_CPU

A Out EN Out
Light Blue: Output from CPU
2D5V_S3 Page40 Page40
PWR_DCBATOUT_1D35V
1D2V_S3 DC SI7121DN-T1-GE3-GP
Vin
a Battery
BT+ Page44
EN 1D35_S3 4
DCBATOUT OUT
Page43
CH035H-40PT0-GP SY8206DQNC
0D6V_S0 Page44
Power Good
1D35V_VTT_PWRGD
AC +DC_IN
SI7121DN-T1-GE3-GP VIN
a Adapter in
Page43 3D3V_S5 5V_S5
Page43
EN1 5V_S5
IN 5V_S0
AD+ EN Out
TPS51225RUKR
DC/DC G5016KD1U 3D3V_S0
EN2 (3.3V/5V) 3D3V_S5 Page40
D Charger D
3D3V_S5
BQ24770RUYR Page45 PGOOD
3V_5V_POK IN 1D5V_S0
EN Out
ACOK Page44 3D3V_AUX_KBC
d TLV70215DBVR
Page40
IO_SLP_S4#
IO_SLP_S3#
b PWR_CHG_ACOK
PM_SLP_S4# S5
3V_5V_EN
e 3 1D35V_S3
R2446 4
S
SWITCH
PR4475 Page24 APL5338XAI
Page45
Page40 3 4 S3 0D675V_S0
Page51
c SLP_S4# SLP_S3#
ALWON PIO71
G
DPWROK
KBC_PWRBTN#
PSL_IN2#
The DSW rails must be stable for at least
1 10 ms before DSW_PWROK is asserted to PCH. H_VR_ENABLE
GPIO66
VR_EN 7
DSW_PWROK
KBC_DPWROK 3D3V_S5
ACAV_IN b CI_OVRD_IN PIO20

G
PM_PWRBTN# Skylake-U MCP
V PWRBTN#
2 4 PM_SLP_S3#
j
RSMRST_PWRGD# BD
T KBC ALL_SYS_PWRGD and VR_RDY assert,
AND Gate
Vcc
elay 10ms
PM_SLP_S0#
MEC1404 delay 10ms; PCH_PWROK assert.
U74LVC1G08G-AL5 Y
RSMRST#_KBC: Delay 10 ms after receive 8 PCH_PWROK
5
RSMRST_PWRGD# and PM_SLP_SUS#. APWROK 6
AND
VCCSTG_EN
RSMRST#_KBC k
PIO36
G PIO93
G PCH_PWROK PCH_PWROK SLP_S0# 1D0V_S5 5V_S5
PM_SUSWARN#
PIO02
G SUSWARN# PROCPWRGD VIN VDD
ALL_SYS_PWRGD l EN +VCCIO
6 PIO26
G 9 VOUT
PM_SUSACK#
GPIO81 SUSACK#
SLG59M1470VTR
m AND
It is recommended that SYS_PWROK be asserted after RSMRST#_KBC Page40
RSMRST#
both PWROK assertion and processor core VR PWRGD assertion. 11 PCI_PLTRST#
k PLTRST#
PM_SLP_S4#
PIO44
G
3
elay 100ms
PM_SLP_S3#
PIO01
G
4 6
H_VCCST_PWRGD ALL_SYS_PWRGD
Level Shifter
D
C 10 SYS_PWROK
74LVC1G07GW Page17
C
PIO77
G SYS_PWROK
EXT_PWR_GATE#
PIO05
i G SIO_SLP_SUS# 1D35V_VTT_PWRGD
SLP_SUS# EXT_PWR_GATE#
g 5
g 1D0V_S5_PWRGD ALL_SYS_PWRGD
Page24 5
3D3V_S5
ALL_SYS_PWRGD assert,
delay 100ms; SYS_PWROK assert.
SVID Transanctions g 1D8V_S5_PWROK 6
f
VIN
PCH_ALW_ON 3D3V_S5_PCH 6 ALL_SYS_PWRGD

VR_ON IMVP8
EN SW PWR_VCORE_VR_RDY
VR_READY CPU SVID Rails
SY6288C10CAC 7 SA/Core/GT
Page41
1D8V_S5_PWROK
g 0R 0402
IO_SLP_SUS#
3V_5V_POK RSMRST_PWRGD#
PWR_DCBATOUT_1D0V e 0R 0402 j
1D0V_S5_PWRGD
S
i 0R 0402
Page40
VIN
EN
LX
1D0V_S5 h
SY8208DQNC 1D0V_S5_PWRGD 3D3V_S5 5V_S5
PGOOD
i
Page52
Vin VCNTL
Vout
1D8V_S5 f
1D0V_S5
e
3V_5V_POK
EN APL5930KAI 1D8V_S5_PWROK
PGOOD
R1103 VCCPRIM_CORE
Page54
Page11
R1734 +VCCMPHYGTAON_1P0_LS_SIP
Page17
[dGPU] N16x Power-Up/Down Sequence

B B
[DG-07158-001_v03]
a b c d e f g h i j k l m
1 2 3a 4 4a 4b 5 6 7 8 9 10 11 12
A A
<Core Des ign>
1F, 88, Sec.1,2 Hs in Tai Wu Rd., Hs ichih,
Taipei Hs ien 221, Taiwan, R.O.C.
itle
Title T
Size Docum ent Num ber

P ower Sequence Rev
0 A
S
tarlord KBL-R 00A
Date: Monday, Augus t 28, 2017 Sheet 102 f o
106
5 4 3 2 1
WWW.AliSaler.Com
5 4 3 2 1
DCBATOUT
Adapter TBD VR_EN VR_EN VR_EN 3D3V_VGA_S0 1D35V_VGA_EN
EN EN PWR_2D5V_PG EN
AOZ1268QI SY8288RAC-GP NCP81208MNTXG NCP81210MNTWG
EN
NCP81382MNTXG
EN EN
TypeC Adapter RT8812AGQW SY8288RAC
Charger NCP81382MNTXG NCP81382MNTXG
BQ24780SRUYR 1D0V_S5
D D
Battery BT+ 1D2V_S3 1D2V_S3 VCC_CORE +VCCGT

+V_VCCGTUS_VR +VCCSA_VR VGA_CORE 1D35V_VGA_S0
VCCPRIM_CORE
EN(S5) PWR_2D5V_PG
APL5338XAI-TRG EN(S3) SM_PGCNTL
0D6V_S0
PWR_3D3V_EN1
PWR_5V_EN1
EN
SY8286BRAC
EN
SY8288CRAC
3D3V_AUX_S5
5V_S5 3D3V_S5
5V_AUX_S5 5V_PWR_2
USB_PWR_EN# PM_SLP_S3# PM_SLP_S3# 1D05V_VGA_EN 3V_5V_POK SIO_SLP_S4# PM_SLP_S3# SIO_SLP_S3#
USB_CHG_EN
C EN C
EN EN EN EN
G5016KD1U EN EN EN
USB30_VCCA SY6288DAAC x 2 RT8068AZQWID APL5930KAI APL5930KAI S-1339D15-M5001 M5938ARD1U
3D3V_S0
USB30_VCCB 5V_S0
USB20_VCCC +V1.8A 2D5V_S3 1D5V_S0
SIO_SLP_S0#
1D05V_VGA_S0 VCCIO
EN
TPS22965DSGR
DGPU_PWR_EN
EN
5V_HDD
RT9724GB G5016KD1U
Power Shape
LCDVDD 3D3V_VGA_S0 Regulator LDO Switch
B B
A A
<Core Design>
itle
T Title
P ower Block Diagram
A 2
5 4 3 2 1
A B C D E
PCH SMBus Block Diagram

3D3V_S5_PCH
3D3V_S0
KBC SMBus Block Diagram
‧ TP_VDD
‧
3D3V_S0 SRN10KJ-5-GP
‧
SRN2K2J-1-GP SMBus Address:0xA0/0xA1
‧
DIMM 1 SRN10KJ-5-GP
TouchPad Conn.
SMBCLK MEM_SMBCLK
1
‧ ‧PCH_SMBCLK SCL 1
SMBDATA MEM_SMBDATA
‧ ‧ PCH_SMBDATA SDA
PS2_DAT0 DAT_TP_SIO DAT_TP_SIO TPDATA
‧
PS2_CLK0 CLK_TP_SIO CLK_TP_SIO TPCLK
‧
2N7002SPT SMBus Address:0xA0/0xA1
3D3V_AUX_KBC
PCH_SMBCLK
DIMM 2
SCL ‧
PCH_SMBDATA
SDA
3D3V_S5_PCH
3D3V_S5_PCH SRN4K7J-8-GP
‧
‧
SMB01_CLK18
SRN33J-7-GP Battery Conn.
3D3V_S0 ‧‧SMBCLK1 PBAT_SMBCLK1 CLK_SMB
SRN2K2J-1-GP SMB01_DATA18 SMBDA1 PBAT_SMBDAT1 DAT_SMB SMBus address:16
SRN2K2J-1-GP ‧ ‧
‧
CYPD2122 HPA02224RGRR
SML0CLK SML0_CLK
MEM_SMBCLK
SML0DATA SML0_DATA ‧
MEM_SMBDATA
‧
SMSC SCL
SDA SMBus address:0X13H/0X12H
SMBus Address:0x08 2N7002SPT MEC1404
2 2
GPIO73/SCL2
GPIO74/SDA2
PCH 3D3V_S0 SMBus Address:

3D3V_S5_PCH 0x94/0x95/0x96/0x97
‧
SRN2K2J-8-GP
3D3V_S0
SRN2K2J-8-GP
SML1CLK ‧ ‧SML1_SMBCLK ‧ THM_SML1_CLK SCL Thermal

SML1DATA ‧ ‧ SML1_SMBDATA ‧ THM_SML1_DATA SDL
NCT7718W
SMBus Address:0x82/0x83 SMBus Address:0x98/0x99
2N7002SPT
3D3V_VGA_S0
‧SRN4K7J-8-GP
3D3V_VGA_S0
3 ‧
dGPU 3
SMB_CLK_VGA I2CS_SCL
‧
SMB_DATA_VGA I2CS_SDA
‧
SMBus Address:0x9E/0x9C
5V_S0
0R2J-2-GP
‧ DY
SRN2K2J-1-GP CMP_VOUT1 CMP_VOUT1

‧ H_PROCHOT_EC
HDMI Level Shifter GPIO166/CMP_VREF1/UART_CLK LCD_TST_EN LCD_TST_EN
‧ ‧
0R2J-2-GP
DDPB_CTRLCLK CPU_DP1_CTRL_CLK DDC_CLK_HDMI
‧
HDMI CONN
LCD_TST
DDPB_CTRLDATA CPU_DP1_CTRL_DATA DDC_DATA_HDMI
‧
SMBus Address:0x80h/0x81h
4 4
<Core Design>
itle
T Title
S MBUS Block Diagram

A 2 S tarlord KBL-R A 00
A B C D E
A B C D E
Thermal Block Diagram Audio Block Diagram

1 1
3D3V_S5_PCH 3D3V_S0 SPKR_L+

PAGE28 D+ NCT7718_DXP SPKR_L-
PCH MMBT3904-3-GP
SPKR_R-
SPKR_R+ SPEAKER
SC2200P50V2KX-2GP
D-
Thermal NCT7718_DXN Place near CPU
NCT7718 PWM CORE Codec
GPP_C6/SMML1DATA ‧ ‧‧ 2N7002 ‧ SDA
THM_SML1_DATA ALC3253
GPP_C7/SML1CLK ‧‧ ‧ ‧ SCL
THM_SML1_CLK MMBT3904-3-GP AUD_HP1_JACK_L HP MIC
SML1_SMBDATA
Put under CPU(T8 HW shutdown)

SML1_SMBCLK
T8 AUD_HP1_JACK_R
THERM_SYS_SHDN# 2N7002 D
PURE_HW_SHUTDOWN# SLEEVE COMBO
T_CRIT# EN
3V/5V RING2
2 PAGE18 S G RESET_OUT# 2
3D3V_S5_KBC
PAGE24
GPIO012 Digital
KBC GPIO013 GPIO0/DMIC_DATA
DMIC_DATA_R R2714
0R2J-2-GP
DMIC_DATA
MIC
SMSC1404 CMP_VOUT0
KBC T8 HW shutdown GPIO1/DMIC_CLK
DMIC_CLK_R R2716
0R2J-2-GP
DMIC_CLK
GPIO124 27K
CMP_VIN0_R
GPIO020
SCD1U16V2KX-3GP
SC100P50V2JN-3GP
GPIO56 GPIO050
NTC100K
FAN1_PWM
FAN_TACH1
GND GND GND
3 3
TACH
FAN
FAN_VCC1
VIN
5V
4 4
<Core Design>
itle
TTitle
Size
T hermal/Audio Block Diagram
Document Number Rev
C ustom
Starlord KBL-R A 00
A B C D E
5 4 3 2 1
D D
C C
B B
<Core Design>
Wistron Corporation
A Taipei Hsien 221, Taiwan, R.O.C. A
Title
SIP connector
A
Starlord KBL-R A00
5 4 3 2 1

Dell Inspiron 5379 5579 7773 16888-1 Starlord ROR-L A00

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Dell Inspiron 5379 5579 7773 16888-1 Starlord ROR-L A00

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5 4 3 2 1

Starlord KBL_Refresh Schematics

A DY : None Installed <Core Design> A

UMA: UMA only installed Wistron Corporation

OPS: DISCRTE OPTIMUS installed TTitle

Project code: 4PD0CF010001(SL13_R) C HARGER

PCB P/N: 16888

VRAM(GDDR5) *4 NVDIA Intel CPU

USB2.0/I2C MUX 0D675V_S0

7mm HDD SATA L DO-V1D5V

Thermal KBC & USB2.0/I2C MUX) INPUTS OUTPUTS

Fan Control TPM Flash ROM MIC_IN/GND

SSID = CPU #544669 CRB Rev0.52

Add resistor by NON DS3 function

(#543016) PROCHOT# Routing Guidelines

M1,2,3,4,5: <3 inches

SKYLAKE_ULT M _A_DQ32 AY39 SKYLAKE_ULT AN45

M _A_DQS_DN[7:0] [12] M _B_DQS_DN0 M _B_DQS_DN[7:0] [13]

M _B_DQS_DP0 M _B_DQS_DP[7:0] [13]

Main Func = CPU

PCH strap pin: 2016/01/11 modify

[BDW Only]PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)

DISPLAY PORT PRESENCE STRAP

For U22 & U42

SVID CLOCK #544669

E55 SKYLAKE_ULT C47

(#543016) eDP_RCOMP Guideline C PU_DP2_HPD R 804 1 2 0R2J-2-GP C PU_DP_HPD_R [37,38,57]

(#543016) DDI Disabling and Termination Guidelines 3 D3V_S0

PU to 3.3 V with 2.2-k

Main Func = CPU

2015/10/16 modify (Power team request)

S CD1U25V2KX-L-GP S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP

S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP

IccMax current-10ms max[A] = 67 A

S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP S C22U6D3V3MX-1-GP

22U 0603 x13 (5 DY)

Main Func = CPU

PCH DERIVED RAILS UNSLICED GT VCCIO

C1176 near N15

C1124 C1125 C1126 C1101 C1127

2 1F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

RF request 2016/01/12 modify

M _A_DQS_DP0 M _A_DQS_DP[7:0] [5]

By layou modify 20150916 3 D3V_S0

[5] 144 8 1 D2V_S3

150 D Q17 62 M _B_DQ17 [5]

Layout note: closed to Dimm 3 D3V_S0

2 R 1306 1 10KR2F-2-GP S A1_CHB_DIM0 E C1303

RF request 2016/01/12 modify

Main Func = PCH

1 USB3.0 Port2 (Debug Port/IOBD)

2 USB3.0 Port3 (IOBD)

#545659 (SKL_PCH_U_Y_EDS Rev0.7)

Friday, December 08, 2017

Main Func = PCH

R1709,R1723,R1703,R1724 merge to RN1704

R 1730 #544669 (CRB): 330k.

[ #543016 Rev0.7] SYSTEM POWER MANAGEMENT

R 1739 1 2 10KR2J-3-GP M E_SUS_PWR_ACK_R

AOZ Power switch, P/N: 074.01334.0093 H _VCCST_PWRGD 1 R 1713 2 P CH_PLTRST#

DS3 BOM Option DY DY DY

E MI DVT1 0210 R 1737

Reserve by NON DS3 function 20150413