Semiconductor Intellectual Property (“IP”)

for Digital & Analog Designs

Rob A. Rutenbar
Professor, Electrical & Computer Engineering
rutenbar@ece.cmu.edu
© R.A. Rutenbar 2004
Intellectual Property

ƒ “IP” is any product of the human intellect that is unique, novel,

and unobvious (and has some value in the marketplace).
ƒ An idea or invention
ƒ Expression or literary creation
ƒ Business method, or industrial process, or chemical formula
ƒ Computer program / algorithm

ƒ Semiconductor IP
ƒ Stuff that let’s us design large chips faster, from pre-existing blocks
ƒ What are these blocks? How hard are they to design and use?

© R.A. Rutenbar 2004 Slide 2

You Already Know Two Important Kinds of IP
ƒ Chips on boards ƒ Software binaries or source code

© R.A. Rutenbar 2004 Slide 3

Semiconductor IP Targets “Systems On Chip”

ƒ Lots of big, separate blocks on a modern “SoC”

ƒ I don’t want to design them all by myself – I want to just buy some of them

Random
CPU Logic Memory
Core

Datapath
(for arithmetic)

© R.A. Rutenbar 2004 Slide 4

Typical IP Components for Digital Chips

ƒ Small stuff ƒ Big stuff –called “cores”

ƒ Logic gates ƒ CPUs

ƒ Gates, flip flops, adders, muxs, etc ƒ 8-bit to 32-bit
ƒ Can build arbitrary logic from these ƒ Small & simple, or big & complex

ƒ Memories, register files ƒ Digital signal processors (DSPs)

ƒ For large storage, beyond a few ƒ For voice, video, image, telecom
flip flops, you need these apps, more efficient than a CPU

ƒ Datapaths ƒ Single-purpose cores

ƒ For complex arithmetic beyond ƒ MPEG engine, MP3 engine, ethernet
simple ADD or MULTIPLY network processor, etc

© R.A. Rutenbar 2004 Slide 5

Real Example

ƒ They really do
look like this...

[Courtesy Neolinear, Inc.]

© R.A. Rutenbar 2004 Slide 6
Automotive SoC Example

ƒ Look at blocks
Memories

Random
control
logic

CPU core

Analog interface
to external world
[Courtesy Neolinear, Inc.]
© R.A. Rutenbar 2004 Slide 7
Non-Memory Blocks Are Made Out of Gates

ƒ Called “standard cells” – you buy a “library” of them

ƒ Standard cell = 1 gate or flip flop
ƒ Arranged in rows on surface of the chip
Random
CPU Logic Memory
Core

Datapath

Cells

Wiring

© R.A. Rutenbar 2004 Slide 8

Bigger SoC Example: Network Chip

DSP
CPU Core
Mem
Logic

Analog
Mem Memory
Frontend
Courtesy Frank Op’t Eynde, Alcatel
© R.A. Rutenbar 2004 Slide 9
How Complex – How Big – Do These Get?
ƒ How many “equivalent” gates? ƒ Example: IBM network switch
ƒ 10 -20 million ƒ Every big colored block is a memory,
background is several million gates
ƒ How many “placed” objects?
ƒ 1 – 5 million
ƒ (i.e., 4X – 5X more “equiv gates”)

ƒ How about memories?

ƒ > 100 memories not uncommon
ƒ Kbits – Mbits per memory

ƒ IO pins
ƒ 200 – 800 common

Courtesy Juergen Koehl, IBM

© R.A. Rutenbar 2004 Slide 10
What Do You Actually Get In A “Cell Library”?
ƒ You get gates and flip flops and small arithmetic blocks

NOT NAND2, 3 NOR2, 3 FULL ADD D FF

+ Q Q’
D

ƒ What you also get…

ƒ The timing and power info for each different gate or flip flop--for simulation
ƒ Electrical circuit and mask-level layouts to use to do the real silicon

© R.A. Rutenbar 2004 Slide 11

How Big is a Std Cell Library--How Many Cells?
ƒ Often, pretty big
ƒ Big enough to get all necessary logic functions, IO variants, with different
electrical properties (eg, speed vs power)

Logic Electrical
functions variations
Fanin &
=~500-1000
(speed,
X fanout
variants
X power,
D Q etc) cells

ƒ Suggested way think about a standard cell

ƒ Inside the cell: messy silicon/electrical stuff
ƒ Outside the cell: a box with pins
ƒ Cell hides these messy silicon details

© R.A. Rutenbar 2004 Slide 12

Logic Æ Circuit Æ Layout Abstractions
A complex library Transistor circuit Mask shapes for layout
gate (AOI221) Vdd
a b c d e
a

b c

d e
out
b d
a
c e

Vss

a b c d e a b c d e a b c d e
VDD Power Rail

Placed in rows

VSS Power Rail

cell cell cell
on surface of chip;
wires go over the
cell cell cell cell top of the cell rows

© R.A. Rutenbar 2004 Slide 13

How Does Overall Design Happen?

Verilog Gates + Mask

code wires shapes
Digital
High-Level Logic Layout
Descrip Synthesis Synthesis
Language

IP Library Support
(cells, memories, cores, etc)

ƒ Thru a sequence of CAD tools, that use these various

libraries, IP blocks, etc. Overall sequence is called a “flow”

© R.A. Rutenbar 2004 Slide 14

Flavors of Semiconductor IP: Hard vs Soft
ƒ Hard IP = a fixed mask layout for ƒ Soft IP = a synthesizable version
the block you want to use of block, eg, a Verilog program

for(i=…)
x=x^y

CPU Core Logic Synthesis

Layout Synthesis

© R.A. Rutenbar 2004 Slide 15

Example: CPU vs Memory Cores

ƒ People often buy CPUs as hard IP cores

ƒ Just get the layout, drop it in your chip as a block, and run with it

ƒ But memory blocks are not like this. They’re usually soft
ƒ You don’t buy a layout.
ƒ You buy a program that “makes” the memory layout. Called a “generator”

ƒ Why? Too many different memory variations for hard IP

ƒ You want to specify how many words, how many bits/word, how fast, how
much power consumed, what shape the memory block should be, etc etc
ƒ Easier to provide this flexibility in software that builds the memory structure

© R.A. Rutenbar 2004 Slide 16

You Already Know a Version of This Tradeoff
ƒ Software
ƒ Hard IP = Executable Binary
ƒ You get the binary file
ƒ You can run it, cannot change it
ƒ Soft IP = Source code
ƒ You get the source itself
ƒ You can change it as you like
ƒ You get to compile it
© R.A. Rutenbar 2004
ƒ Semiconductor IP
ƒ Hard IP = mask layout
ƒ Cannot change it
ƒ Only works in a specific
semiconductor mfg process
ƒ Min flexibility, max “ease of use”
ƒ Soft IP = Synthesizable version
ƒ Can change it, can move it to any
mfg process for chips you want
ƒ Lots more work – you have to
synthesize it, make sure its correct
Slide 17
Hidden Side Effects With Hard IP
ƒ Related to fact that the
manufacturing process for chips
is very complicated OK
ƒ Problem: Mfg steps on one part
of chip can affect other parts

ƒ Typical example for hard IP

ƒ You buy a layout for a CPU core
ƒ Vendor guarantees the
performance – eg, the speed…
ƒ …but only if you do not put any
No!
wires over the top of the block(!)

© R.A. Rutenbar 2004 Slide 18

Why? Many Layers of Metal Wiring on Chip
ƒ 10 layers in a modern microproc ƒ Unfortunately, stuff “over there”
affects stuff “over here” on chip

Cu thickness
distribution
(different chip)

Cross-sectional view of Cu thickness

IBM G5 processor wiring histogram
done in copper technology
[Courtesy IBM]

© R.A. Rutenbar 2004 Slide 19

Example of Chip Mfg Interaction: CMP

ƒ Chemical Mechanical Polishing – used to make each metal

wiring layer “flat” so you can put the next metal layer on chip

Thickness depends on
how much metal wire
is in the neighborhood.
Thickness changes electrical
behavior of these local wires
Final Post-CMP Cu Thickness (M4)

Duane Boning, MIT

© R.A. Rutenbar 2004 Slide 20
Consequences for IP

ƒ As technology “scales” and gives us smaller transistors, it also

makes these across-the-chip manufacturing effects worse
ƒ Hard to be perfect fabricating things that are ~100-1000 atoms across

ƒ So – how does this impact semiconductor IP?

ƒ Many people think hard IP will soon be dead

ƒ You cannot guarantee its performance if it depends on what other stuff you
choose to put on the chip
ƒ If you cannot change it – remember, it’s a fixed layout – then you have no
hope of correcting these problems inside the IP block
ƒ So, maybe the future is all about soft IP. This is a big debate today.

© R.A. Rutenbar 2004 Slide 21

Another Aside: IP is Big Bucks Business

ƒ World’s biggest supplier of

CPU cores (ARM microproc)
for SoC applications

ƒ World’s biggest supplier of

standard cell libraries and
memory blocks for chips

© R.A. Rutenbar 2004 Slide 22

What About the IP for the Analog Side…?
Mixed-Signal SoC Design

Digital Side

Analog Side
[Courtesy Neolinear, Inc.]

© R.A. Rutenbar 2004 Slide 23

Why This Matters: Many “Mixed-Signal” SoCs
Telecom Automotive
Mixed-Signal Chips

% % Digital Chips with

Analog Content
Consumer Medical

75%
Computers
& Networks

30%
12%

2000 2003 2006

[Source: IBS 2003]
© R.A. Rutenbar 2004 Slide 24
Lots of Digital “Support” Functions Are Analog

ƒ Some obvious, some not

Wireless
connectivity IO pads use
Is analog analog to control
RF signal shape
Front-
end
Modem frontend
also analog MODEM

Clock Network
Synch Interface
Clock synch is Physical LAN layer
an analog problem (Ether, Firewire, ..)
is all analog

© R.A. Rutenbar 2004 Slide 25

Problem: Analog “Std Cell” Libs Don’t Work…

ƒ Why: too many continuous specifications for analog cells

−
11/4 11/4 160/12

10 independent
= =
10pF

+
In- In+

performance
54µA 23µA 3/52
42/3 42/3

¿10pF

3/3 3/3 specifications

3/4 3/4

Spec=LOW
Spec=HIGH
X variants = ~ 1000 variants
for ALL
combinations
for just this cell

ƒ Can’t just build a practical-size, universal analog library

© R.A. Rutenbar 2004 Slide 26

Analog IP: What Are People Actually Doing?

ƒ Device-level IP
ƒ Generators for individual devices
ƒ Mix of Hard IP & Soft IP

ƒ Cell-level IP
ƒ Synthesizable building blocks
ƒ Soft IP

ƒ System-level IP
ƒ Larger blocks for
useful chip functions
ƒ Mix: can be Hard IP, can be Soft IP

© R.A. Rutenbar 2004 Slide 27

Analog Device-Level IP
ƒ Individual analog devices a lot more difficult, more “fussy”
ƒ Need to deal with very precise electrical quantities, or be very big to handle
large currents or voltages at the physical interfaces
ƒ Making generators for these devices – soft IP – is most common

2 Digital Devices 1 Analog Device

Courtesy Neolinear, Inc

© R.A. Rutenbar 2004 Slide 28
Real SoC-- Analog vs Digital Devices Example

digital
A small
CPU core

analog

1 FET A few
capacitors
[Courtesy Neolinear, Inc.]
© R.A. Rutenbar 2004 Slide 29
Analog IP: Same Sort of Hard vs Soft Issues

ƒ But made worse by the fact that analog circuits are much
more sensitive to the mfg process than digital circuits
ƒ So, they’re much harder to design, and to “retarget” to a new mfg process

ƒ Most analog IP today is hard IP

ƒ Buy a layout for something like an Ethernet or Bluetooth interface

ƒ Synthesis tools for soft IP are just emerging commercially

ƒ Took about another 10-15 years to figure out how to do this for analog

© R.A. Rutenbar 2004 Slide 30

From Analog Synthesis Æ Analog IP
ƒ From Neolinear synthesis tools -- CMU startup company
Unsized commercial 0.6um proprietary
diff-amp cell CMOS fab
Circuit
Synthesis W=83
L=6

Physical
Synthesis

© R.A. Rutenbar 2004 Slide 31

From Analog Synthesis Æ Analog IP
ƒ Ex: from commercial version of flow, at SRC member company
Unsized commercial 0.6um proprietary
diff-amp cell CMOS fab
Circuit
Synthesis

Physical
Synthesis
TSMC 0.35um
CMOS fab

Circuit Physical
Synthesis Synthesis

W=83 78% less area; 42% less power

Resized ckt L=6

© R.A. Rutenbar 2004 Slide 32

With Synthesis, You Can Create Soft Libraries
Sample & hold Opamp (CMFB) Opamp (2stage) Diff. Opamp Gain Stage

Charge Pump Divider D FF

ƒ Examples from NeoIP
soft analog IP library
of basic blocks

Comparator VCO (Diff. Ring) Bandgap VRef Bandgap IRef Freq Detector

© R.A. Rutenbar 2004 Slide 33

Aside: Analog Side is Also an Interesting Biz

ƒ Biggest mixed-signal
chip CAD company

ƒ Biggest analog
synthesis tools player

© R.A. Rutenbar 2004 Slide 34

Summary
ƒ Semiconductor IP is a critical part of how we design big chips
ƒ Nobody has time to build every block they want from scratch
ƒ Want to be able to buy or generate the blocks we need

ƒ Digital IP
ƒ Standard cell libraries, CPU cores, memory block generators are common
ƒ Soft vs hard IP is the big distinction. Unclear what tomorrow will look like

ƒ Analog IP
ƒ Not nearly so mature, mostly hard IP today
ƒ Emerging tools to handle soft IP, still a research issue

ƒ Still a big, active research area, for both digital & analog

© R.A. Rutenbar 2004 Slide 35