-Ques: Explain Channel length Modulation and Body Effect.

Channel Length Modulation:

Reverse- biased p-n junction forms a depletion region between n and p with no carriers. The
current
between drain and source terminals is constant and independent of applied voltage over the
terminals. The effective length of channel is actually modulated by applied Vds , when Vds is
increased, depletion region at drain junction increases reducing length of effective channel.
Leff = L- Ld
Width of depletion Ld increases with reverse bias. Thus Ids increases with Vds , even in
saturation because shorter Leff gives more current.
Body Effect:
When in a NMOS device, substrate voltage lowers than 0 V, then electrons will need more
positive gate energy to get attracted towards channel because substrate potential is acting
against gain potential thus Vt increases. This effect is known as body effect. The threshold
voltage Vt is not constant with respect to voltage difference between substrate and source of
MOS transistor.

Ques 2. Define a long-channel device. Briefly explain the benefits of a long-channel device
over a short-channel one.
a. A long-channel device is a device with a large enough channel length, i.e.
larger than the sum of the source and drain widths, that the edge effects
can be neglected.
b. Advantages of a long-channel device
i. Longer time till current saturation
ii. Lesser carrier scattering
iii. Lesser subthreshold conduction
iv. Constant threshold voltage
v. No chance of drain induced barrier lowering

Ques 3. Mention four approach to control crosstalk(2 marks)

Ques 4.

Ques 5.

Ques 6.

Ques 7. List and briefly explain the leakage sources in a MOSFET

Ques 8. What is the effect of short channel on Vt (Threshold Voltage)? [1
Mark]
Ques 9. a) Explain the variation of MOS capacitance values with gate voltage assuming the
body to
be n-type and the frequency to be high.
b) Also, comment on any 2 factors which result in a S-type or an F-type chip.
Ques 10. Explain how changes in tox, width, power supply voltage and temperature will
affect the delay and leakage.
Ques 11. Why polysilicon material is used to make gates instead of metals?
QUes 12. State whether True/False with proper reasoning. (2x1=2)
(a) PMOS and NMOS provide the same current for the same set of features.
(b) Tungsten is used instead of copper in the fabrication process

Ques 13. Describe the relation between then oxide thickness track between devices to the
speed of a NMOS and PMOS transistor.
Ques 14. What is DIBL? What is its impact on the performance of a device?
Ques 15.

Ques 16. given the resistivity of Cu.

1. Calculate the sheet resistance of a 0.25 um thick Cu wire.
2. Calculate the total resistance of this wire if its 0.5mm long and 0.3um wide.
3. There are two such wires 0.5mm long adjacent to each other. Capacitance to
ground = 0.2 fF/um, Capacitance with adjacent wire = 0.3 fF/um.
Calculate contamination delay and propagation delay of the path.

Ques 17. Why was aluminium used for making interconnects earlier ? Why copper is used now
and why we were not able to use it earlier ? What has changed ?

Ques 18.
Ques 19.

Ques 20
21. Explain accumulation, depletion and inversion region in MOS capacitor and why bend
bending occurs.
22 Explain threshold voltage w.r.t a MOS capacitor
23Explain and draw C-V characteristics of MOS capacitor and also give ides about low and high
frequency
24

25
26.

27.

28.

29.

30.
31.

32.
32.

33.
34.Explain the functioning of the following Latches:
a)TSPC
b)C2MOS
35)

36) Does the body effect of a process limit the number of transistors that can be placed in series
in a CMOS gate at low frequencies. [1Mark]

37) what is slack? [1Mark]

38) An nMOS transistor has a threshold voltage of 0.4 V and a supply voltage of VDD = 1.2 V. A
circuit designer is evaluating a proposal to reduce Vt by 100 mV to obtain faster transistors. a)
By what factor would the saturation current increase (at Vgs = Vds = VDD) if the transistor were
ideal? b) By what factor would the subthreshold leakage current increase at room temperature
at Vgs = 0? Assume n = 1.4. c) By what factor would the subthreshold leakage current increase
at 120 °C? Assume the threshold voltage is independent of temperature. [4Mark]

39 Draw MOSFET capacitance model

40 explain various delays in MOSFET.

41

42

43.List the methods to reduce the diffusion capacitance of the gate.

44.Explain the MOS gate capacitance model in detail( i.e capacitance on gate drain source and
body in cutoff,linear and saturation region). Also plot the capacitance vs vg plot .
45.What is short channel effect? What is DIBL?
46.Why there is overlap between gate and source or gate and drain?

47.Explain the formation of a channel in the MOS capacitor and how capacitance varies along
with it?

48.How does MOSFETs act and how the terminal acts?

49

50

51
Explain briefly what is latch up and how can u prevent it.

52
Answer the following:-
a) What is the effect of forward and reverse body bias on Vt? Explain.
b) When does tunneling happen? In 65nm technologies, tunneling is very critical. Then
how are we able to make 7nm technologies?
c) What is the effect of stacking on static power?

53
given the resistivity of Cu.
1. Calculate the sheet resistance of a 0.25 um thick Cu wire.
2. Calculate the total resistance of this wire if its 0.5mm long and 0.3um wide.
3. There are two such wires 0.5mm long adjacent to each other. Capacitance to
ground = 0.2 fF/um, Capacitance with adjacent wire = 0.3 fF/um.
Calculate contamination delay and propagation delay of the path

54
Explain Latch up in CMOS and write methods to prevent Latch Up and also
explain why strapping is essential in CMOS?

55
Q 56)
(a)

(b)

57.
ANSWER
58)

59)

60)
61?61

61) Mobility and Threshold increases or decreases with Temperature ? Defend your
answer.
62)

63)
64)

65)

66.
67.

68.

69.What is subthreshold slope ?How does subthreshold slope helps in leakage variation?

67.

68.
69.

70

71) what is Latch-up ? And what measures you can take to prevent it?
72)
73) Despite of the fact that on decreasing width of oxide layer of mosfet, gate tunneling
increases, why we intend to decrease the oxide width? What is the other alternative of achieving
the same characteristic without further reducing the oxide thickness?

74.
75.
76.

a.What is the surface potential?

b.What is the gate voltage ?
c.In which region is MOS working?
d.What is the voltage across the oxide?

77.A 90 nm long transistor has a gate oxide thickness of 16 Å. What is its gate capacitance per micron
of width?

78.
why Id Vs Vds curve is linear for short channel compare to long channel?

79.
What is Metal Oxide Semiconductor. Draw the band diagram and explain the
Region of operation of MOS capacitor?
80

81

82

83

84
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86

87

88

89
90
91

92

93
90
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92

93

94
95.

96.
97.

98.

99.
100.

101.

102
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104