1.

Implement logic using cmos gates

2.

3. Design a complex CMOS gate: (D+A.(B+C))'

4. Implement Half Adder circuit using static CMOS
5. Realize the following logic function F = NOT ( NOT( A OR B ) OR NOT( A AND B ) )
using static CMOS and pseudo-NMOS
6.
7. Draw CMOS version of the circuit to realize the following boolean expression :
bar(AD+BC).
8. In domino Logic, output with high noise derives the static gate. What are these
parameters for high noise? Describe their effects.
9.

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Why nMOS is used in the pulldown network and pMOS pullup network in the
CMOS technology?

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20)

21) Implement cmos circuit for logic : (A+BC)D’

22)
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Implement A.(B+C)+D.E.F whole bar with the same delay as a balanced inverter.

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55. Give reasons for the following:

(a) As compared to static CMOS, power dissipation in dynamic logic is higher. [1]
(b) The logical effort is lower in dynamic logic as compared to static CMOS [1]

Ans
(a) The power dissipation in dynamic logic is higher due to clock activity. In case we
have
constant inputs, the output will get toggled continuously with the clock. This increases
the
activity factor of our circuit and hence the power consumption.
(b) Static CMOS has both PDNs and PUNs whereas dynamic logic has either of two which
reduces the input capacitance and decreases the effort required by the inputs to drive
the
circuit.

56.
(a) Draw circuit diagram for AOI321 using PTL logic [2.5]
(b) Redraw the circuit drawn above without using inverted inputs. [2.5]
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63. Explain the impact of process variation in brief.
What is process compensation? Explain the effect of forward body bias and
reverse body bias effect.
What command is used for SS corner in eldo.
Ans: Process variation is naturally occurring variation in attributes of transistor
(length, width, oxide thickness). Process variation happens when processes fail to
follow a precise pattern. Threshold voltage of device changes and performance
modulates accordingly. If pmos is good it threshold voltage increase from vdd/2 and
if nmos is good threshold voltage will be lesser than vdd/2.

Bringing all the corners in the desired rhombus or meeting the desired specification
with the help of reverse body bias and forward body bias is called process
compensation.
By applying reverse body bias, threshold voltage will increase and device becomes
slower, means FF will come in new power specification and SS will not be affected.
On applying forward body bias, the threshold voltage of device will decrease and
device will become faster hence SS will shift and lie in desired specifications.
In eldo, the command for SS corner is :
.include /modelfile_65nm/minXminP.cir

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