Quantum

Computing
Internet
Autonomous
Vehicles
Hardware

SEPTEMBER 2021 www.computer.org

 IEEE COMPUTER SOCIETY JOBS BOARD

Evolving Career
Opportunities
Need Your Skills
Explore new options—upload your resume today

Changes in the marketplace shift demands for vital skills

www.computer.org/jobs and talent. The IEEE Computer Society Jobs Board is a
valuable resource tool to keep job seekers up to date on
the dynamic career opportunities offered by employers.
Take advantage of these special resources for job seekers:

JOB ALERTS TEMPLATES WEBINARS

CAREER RESUMES VIEWED

ADVICE BY TOP EMPLOYERS

No matter what your career level, the IEEE Computer

Society Jobs Board keeps you connected to
workplace trends and exciting career prospects.
 IEEE COMPUTER SOCIETY computer.org

STAFF
Editor Publications Portfolio Managers
Cathy Martin Carrie Clark, Kimberly Sperka

Publications Operations Project Specialist Publisher

Christine Anthony Robin Baldwin

Production & Design Artist Senior Advertising Coordinator

Carmen Flores-Garvey Debbie Sims

Circulation: ComputingEdge (ISSN 2469-7087) is published monthly by the IEEE Computer Society. IEEE Headquarters, Three Park Avenue, 17th
Floor, New York, NY 10016-5997; IEEE Computer Society Publications Office, 10662 Los Vaqueros Circle, Los Alamitos, CA 90720; voice +1 714 821 8380;
fax +1 714 821 4010; IEEE Computer Society Headquarters, 2001 L Street NW, Suite 700, Washington, DC 20036.
Postmaster: Send address changes to ComputingEdge-IEEE Membership Processing Dept., 445 Hoes Lane, Piscataway, NJ 08855. Periodicals Postage
Paid at New York, New York, and at additional mailing offices. Printed in USA.
Editorial: Unless otherwise stated, bylined articles, as well as product and service descriptions, reflect the author’s or firm’s opinion. Inclusion in
ComputingEdge does not necessarily constitute endorsement by the IEEE or the Computer Society. All submissions are subject to editing for style,
clarity, and space.
Reuse Rights and Reprint Permissions: Educational or personal use of this material is permitted without fee, provided such use: 1) is not made for
profit; 2) includes this notice and a full citation to the original work on the first page of the copy; and 3) does not imply IEEE endorsement of any third-
party products or services. Authors and their companies are permitted to post the accepted version of IEEE-copyrighted material on their own Web
servers without permission, provided that the IEEE copyright notice and a full citation to the original work appear on the first screen of the posted copy.
An accepted manuscript is a version which has been revised by the author to incorporate review suggestions, but not the published version with copy-
editing, proofreading, and formatting added by IEEE. For more information, please go to: http://www.ieee.org/publications_standards/publications
/rights/paperversionpolicy.html. Permission to reprint/republish this material for commercial, advertising, or promotional purposes or for creating new
collective works for resale or redistribution must be obtained from IEEE by writing to the IEEE Intellectual Property Rights Office, 445 Hoes Lane,
Piscataway, NJ 08854-4141 or pubs-permissions@ieee.org. Copyright © 2021 IEEE. All rights reserved.
Abstracting and Library Use: Abstracting is permitted with credit to the source. Libraries are permitted to photocopy for private use of patrons,
provided the per-copy fee indicated in the code at the bottom of the first page is paid through the Copyright Clearance Center, 222 Rosewood Drive,
Danvers, MA 01923.
Unsubscribe: If you no longer wish to receive this ComputingEdge mailing, please email IEEE Computer Society Customer Service at help@
computer.org and type “unsubscribe ComputingEdge” in your subject line.
IEEE prohibits discrimination, harassment, and bullying. For more information, visit www.ieee.org/web/aboutus/whatis/policies/p9-26.html.

IEEE Computer Society Magazine Editors in Chief

Computer IEEE Intelligent Systems IEEE Pervasive Computing

Jeff Voas, NIST V.S. Subrahmanian, Marc Langheinrich, Università
Northwestern University della Svizzera italiana
Computing in Science
& Engineering IEEE Internet Computing IEEE Security & Privacy
Lorena A. Barba, George George Pallis, University Sean Peisert, Lawrence
Washington University of Cyprus Berkeley National
Laboratory and University
IEEE Annals of the History IEEE Micro of California, Davis
of Computing Lizy Kurian John, University
Gerardo Con Diaz, University of Texas at Austin IEEE Software
of California, Davis Ipek Ozkaya, Software
IEEE MultiMedia Engineering Institute
IEEE Computer Graphics Shu-Ching Chen, Florida
and Applications International University IT Professional
Torsten Möller, Irena Bojanova, NIST
Universität Wien

2469-7087/21 © 2021 IEEE Published by the IEEE Computer Society September 2021 1
 SEPTEMBER 2021 � VOLUME 7 � NUMBER 9

Long-distance
The distances between connectivity and the
quantum computers diversity of qubits
within a quantum farm are expected.
are relatively short.
The distances Qubits are most likely
Distance and Heterogeneity

between qubits within to be homogeneous. Step 3:

Silicon Qubit Printed Circuit a quantum computer Interconnecting
MCM Chip Board
are extremely short. Multiple
Qubits are Geographically
homogeneous. Step 2: Distributed
Interconnecting Quantum Farms
Multiple Quantum
Computers Within
Step 1: the Same Quantum
ng Interconnecting Farm
ss RF Wiring HarnessQuantum
Multiple
Processors Within
ds a Single Quantum
Ribbon Bonds

8 14 34
mps Computer
Coplanar Waveguide
ier Transition to MCM

Time

Quantum The Rise of The 5G

Access the Quantum Revolution:
Internet Expectations
Versus Reality
 Quantum Computing
8 Quantum Access
ERIK DEBENEDICTIS

14 The Rise of the Quantum Internet

MARCELLO CALEFFI, DARYUS CHANDRA, DANIELE CUOMO, SHIMA
HASSANPOUR, AND ANGELA SARA CACCIAPUOTI

Internet
20 Principles and Elements of Governance of Digital
Public Services
VIRGILIO ALMEIDA, FERNANDO FILGUEIRAS, AND FRANCISCO GAETANI

25 The Rising Threat of Launchpad Attacks

MARKUS JAKOBSSON

Autonomous Vehicles
31 Right Code
GERARD J. HOLZMANN

34 The 5G Revolution: Expectations Versus Reality

NURA JABAGI, ANDREW PARK, AND JAN KIETZMANN

Hardware
42 High-Level Synthesis-Based Approach for Accelerating
Scientific Codes on FPGAs
RAMSHANKAR VENKATAKRISHNAN, ASHISH MISRA, AND
VOLODYMYR KINDRATENKO

47 Recent Advances in Compute-in-Memory Support

for SRAM Using Monolithic 3-D Integration
ZHIXIAO ZHANG, XIN SI, SRIVATSA SRINIVASA, AKSHAY KRISHNA
RAMANATHAN, AND MENG-FAN CHANG

Departments
4 Magazine Roundup
7 Editor’s Note: Moving Quantum Computing Forward
60 Conference Calendar

Subscribe to ComputingEdge for free at

www.computer.org/computingedge.
 Magazine Roundup
T he IEEE Computer Society’s lineup of 12 peer-reviewed technical magazines covers cutting-edge topics
ranging from software design and computer graphics to Internet computing and security, from scien-
tific applications and machine intelligence to visualization and microchip design. Here are highlights from
recent issues.
eCloud: A Vision for
the Evolution of the Edge-
Cloud Continuum
The authors of this article from the
May 2021 issue of Computer pres-
ent a holistic vision for the edge-
cloud ecosystem, with the intent
of spurring the creation of next-
generation technologies for futur-
istic applications that operate at
computational-perception speeds
to convert sensed data to action-
able knowledge.
Jupyter: Thinking and
Storytelling With Code
and Data
Project Jupyter is an open-source
project for interactive comput-
ing that is widely used in data sci-
ence, machine learning, and sci-
entific computing. The authors of
this article from the March/April
2021 issue of Computing in Science
& Engineering argue that even
though Jupyter helps users per-
form complex technical work, Jupy-
ter itself solves problems that are
4 September 2021
fundamentally human in nature;
Jupyter helps humans think and
tell stories with code and data. The
authors illustrate this by describ-
ing three dimensions of Jupyter: (1)
interactive computing, (2) compu-
tational narratives, and (3) the idea
that Jupyter is more than software.
They illustrate the impact of these
dimensions on a community of prac-
tice in earth and climate science.
The Computer Programs of
Charles Babbage
The mathematician and inven-
tor Charles Babbage drafted 26
code fragments between 1836
and 1840 for his unfinished “Ana-
lytical Engine.” The programs were
embedded implicitly in tables rep-
resenting execution traces. In this
article from the January–March
2021 issue of IEEE Annals of the
History of Computing, the authors
explore the programming architec-
ture of Babbage’s mechanical com-
puter, that is, its structure from
the point of view of a programmer,
based on those 26 coding exam-
ples preserved in the Babbage
Papers Archive.
Published by the IEEE Computer Society
Caricature Expression
Extrapolation Based on
Kendall Shape Space Theory
In this article from the May/June
2021 issue of IEEE Computer
Graphics and Applications, the
authors propose a novel expres-
sion extrapolation method for
caricature facial expressions
based on the Kendall shape
space, in which the key idea is
to introduce a representation
for the 3D expression model to
remove rigid transformations,
such as translation, scaling, and
rotation, from the Kendall shape
space. Built on the proposed rep-
resentation, the 2D caricature
expression extrapolation pro-
cess can be controlled by the 3D
model reconstructed from the
input 2D caricature image and
the exaggerated expressions
of the caricature images gener-
ated based on the extrapolated
expression of a 3D model that is
robust to facial poses in the Ken-
dall shape space; this 3D model
can be calculated with tools
such as exponential mapping in
Riemannian space.
2469-7087/21 © 2021 IEEE

Optimal Finite-Horizon
Perturbation Policy for
Inference of Gene
Regulatory Networks
A major goal of systems biology is
to model accurately the complex
dynamical behavior of gene regu-
latory networks (GRNs). Despite
several advancements that have
been made in inference of GRNs,
two main issues continue to make
the problem challenging: (1) non-
identifiability of parameters and
(2) limited amounts of data. Thus, it
becomes necessary to experimen-
tally perturb or excite the system
into different states. This perturba-
tion process disrupts the expres-
sion of genes from active to inac-
tive, or vice versa, at each time
point. Another issue is the partial
observability of the gene states,
which must be inferred indirectly
from noisy gene expression mea-
surements. In this article from the
January/February 2021 issue of IEEE
Intelligent Systems, the latter issue
is accounted for by employing the
partially observed Boolean dynami-
cal system signal model for the data
and applying optimal state estima-
tion. Then, the optimal finite-hori-
zon perturbation policy is derived
to achieve the highest possible
expected performance for the
maximum a posteriori estimator
under a small perturbation cost.
www.computer.org/computingedge
AI-Driven Provisioning in the
5G Core
Network slicing enables com-
munication service providers to
partition physical infrastructure
into logically independent net-
works. Network slices must be
provisioned to meet the service-
level objectives (SLOs) of dispa-
rate offerings. Network orches-
trators must customize service
placement and scaling to achieve
the SLO of each network slice. In
this article from the March/April
2021 issue of IEEE Internet Com-
puting, the authors discuss the
challenges encountered by net-
work orchestrators in allocating
resources to disparate 5G net-
work slices. They propose the use
of artificial intelligence to make
core placement and scaling deci-
sions that meet the requirements
of network slices deployed on
shared infrastructure.
Klessydra-T: Designing
Vector Coprocessors
for Multithreaded Edge-
Computing Cores
Computation-intensive kernels,
such as convolutions, matrix multi-
plication, and Fourier transform, are
fundamental to edge-computing
AI, signal processing, and crypto-
graphic applications. Interleaved-
multithreading (IMT) processor
cores are interesting to pursue
energy efficiency and low hard-
ware cost for edge computing,
yet they need hardware acceler-
ation schemes to run heavy com-
putational workloads. Following
a vector approach to accelerate
computations, this article from
the March/April 2021 issue of IEEE
Micro explores possible alterna-
tives to implement vector copro-
cessing units in RISC-V cores,
showing the synergy between IMT
and data-level parallelism in the
target workloads.
Feature-Guided Spatial
Attention Upsampling
for Real-Time Stereo
Matching Network
In this article from the January–
March 2021 issue of IEEE MultiMe-
dia, the authors propose an end-
to-end real-time stereo matching
network (RTSMNet). RTSMNet
consists of three modules. The
global and local feature extrac-
tion (GLFE) module captures the
hierarchical context information
and generates the coarse cost
volume. The initial disparity esti-
mation module is a compact 3D
convolution architecture aim-
ing to produce the low-resolution
5
MAGAZINE ROUNDUP
(LR) disparity map rapidly. The
feature-guided spatial attention
upsampling module takes the LR
disparity map and the shared fea-
tures from the GLFE module as
guidance, first estimates resid-
ual disparity values and then an
attention mechanism is devel-
oped to generate context-aware
adaptive kernels for each upsam-
pled pixel.
The Road to Ubiquitous
Personal Fabrication:
Modeling-Free Instead of
Increasingly Simple
The authors of this article from
the January–March 2021 issue of
IEEE Pervasive Computing argue
that to achieve similar outreach
and impact as personal comput-
ing, personal fabrication research
may have to venture beyond ever-
simpler interfaces for creation,
toward lowest-effort workflows
for remixing. The authors sur-
veyed novice-friendly digital fab-
rication (DF) workflows from the
perspective of HCI. Through this
survey, they found two distinct
approaches for this challenge: (1)
simplifying expert modeling tools
and (2) enriching tools not involv-
ing primitive-based modeling with
powerful customization. They
argue that to be able to include
the majority of the population
in DF, research should embrace
omission of workflow steps, shift-
ing toward automation, remixing,
and templates, instead of model-
ing from the ground up.
6 ComputingEdge
A Systems Approach Toward
Addressing Anonymous
Abuses: Technical and
Policy Considerations
Can we prevent the abuses of anon-
ymous communication networks
without affecting their ability to
enhance privacy and evade censor-
ship? The authors of this article
from the March/April 2021 issue
of IEEE Security & Privacy evaluate
approaches for balancing the need
for anonymity with the desire to
mitigate anonymous abuses.
Automatic Recovery of
Missing Issue Type Labels
Agile software organizations
em­
power developers to make
appropriate decisions rather than
enforce adherence to a process,
resulting in incomplete and noisy
data in software archives. Since
software analytics techniques
are trained using this data, auto-
mated techniques are required to
recover it. Read more in this arti-
cle from the May/June 2021 issue
of IEEE Software.
Technology-Enhanced
Educational Escape Rooms:
A Road Map
Educational escape rooms have
emerged as a new type of teach-
ing practice with the promise
of enhancing students’ learning
through highly engaging experi-
ences. The rapid rise of educa-
tional escape rooms has led to
a misalignment between educa-
tors’ needs for being able to imple-
ment this novel teaching prac-
tice and the availability of tools
to ease the process. Moreover,
this lack of support is preventing
teachers and students from tak-
ing full advantage of the potential
of educational escape rooms. This
article from the March/April 2021
issue of IT Professional provides
a road map of the most urgent
issues to be addressed to bridge
the aforementioned gap: easing
the creation of digital puzzles, aid-
ing in the logistical aspects of con-
ducting an educational escape
room, harnessing learning ana-
lytics, fostering remote collabo-
ration, and integrating artificial
intelligence to adapt the experi-
ence to each team.
Join the IEEE
Computer
Society
computer.org/join
September 2021
 Editor’s Note
Moving Quantum
Computing Forward
I n the past few years, quantum
computing has gone from theo-
retical science to promising tech-
nology with many real-world appli-
cations. Quantum computing is
being used to make transporta-
tion and scientific discovery more
efficient, and myriad other use
cases are on the horizon. How-
ever, a lot of work remains before
quantum computing can reach its
full potential. Two articles from
Computer focus on what it will
take to further develop and lever-
age quantum computing.
“Quantum Access” pres-
ents a vision for giving students,
researchers, and start-up compa-
nies access to quantum hardware,
allowing more people to contrib-
ute to the advancement of quan-
tum computing. “The Rise of the
Quantum Internet” details the
2469-7087/21 © 2021 IEEE
challenges involved in designing a
quantum network infrastructure,
such as reformulating information
transmission and interconnecting
quantum processors.
Digital literacy and effective
use of the Internet are essen-
tial skills. IEEE Internet Comput-
ing’s “Principles and Elements of
Governance of Digital Public Ser-
vices” examines the government’s
role in expanding digital literacy
and Internet access. IEEE Secu-
rity & Privacy’s “The Rising Threat
of Launchpad Attacks” provides
background on online social engi-
neering and gives advice on how
to protect against such attacks.
Autonomous vehicles are
becoming more prevalent in our
society. In IEEE Software’s “Right
Code,” the author asserts that self-
checking code and requirements
Published by the IEEE Computer Society
testing can improve reliability in
autonomous vehicle software. In
IT Professional’s “The 5G Revolu-
tion: Expectations Versus Real-
ity,” the authors predict that 5G’s
ultra-low latency will help enable
fully autonomous vehicles.
This ComputingEdge issue
concludes with two articles on
hardware for high-performance
computing (HPC). “High-Level
Synthesis-Based Approach for
Accelerating Scientific Codes on
FPGAs,” from Computing in Sci-
ence & Engineering, describes
design platforms for HPC on FPGA
hardware. “Recent Advances in
Compute-in-Memory Support for
SRAM Using Monolithic 3-D Inte-
gration,” from IEEE Micro, explores
an approach for improving hard-
ware performance for data-inten-
sive applications.
September 2021 7
 EDITOR: Erik P. DeBenedictis, Zettaflops, LLC, erikdebenedictis@gmail.com
DEPARTMENT: REBOOTING COMPUTING
Quantum Access
Erik DeBenedictis, Zettaflops, LLC
Quantum computers are available via the Internet for students and small-scale
research. What if similar access could be extended to quantum hardware?
I
took a class on integrated circuit design when
I was a student in 1981. The class project was for
each student to design and test a CMOS circuit.
I designed a CMOS arbiter, a circuit used to reliably
detect which of two input signals arrives first. The chip
was fabricated as part of a multiproject wafer during
the first run of ARPA’s (now DARPA’s) MOS Imple-
mentation Service (MOSIS) and delivered to me as a
chip bonded into a package—like a simplified version
of the one shown in Figure 1—and I tested it with an
oscilloscope.
However, the version shown in Figure 1 is a quan-
tum module built by a professional research team1
out of components created by governmental and
commercial fabricators (fabs) that could become
the quantum equivalent of my 1981 CMOS chip. The
central gray box in Figure 1 contains qubits bonded
on top of a somewhat larger classical electronics
chip. Unlike my 1981 chip, some of the leads in Figure
1 carry microwave signals, and the module operates
at millikelvins. Although the module in Figure 1 is not
a complete quantum computer, its structure and the
process of creating it would give students hands-on
experience or support experimental research proj-
ects within the bounds of the module’s external
interfaces.
Quantum technology is roughly as mature as
CMOS was in 1981, making it feasible to offer students
and small research groups access to quantum hard-
ware prototyping. This concept has been discussed
Digital Object Identifier 10.1109/MC.2020.3011079
Date of current version: 5 October 2020
8 September 2021 Published by the IEEE Computer Society 
This article originally
appeared in
vol. 53, no. 10, 2020
in an IEEE Quantum Initiative working group, and I’m
writing about it here as a noncommercial concept
that IEEE Members could champion in the public
interest.
A BRIEF HISTORY OF
INTEGRATED CIRCUITS
Integrated circuits were originally designed by cut-
ting plastic such as Rubylith and handcrafting what
were essentially photographic negatives. The meth-
od’s scale-up limitations are obvious. At some point,
companies started writing their own computer-aided
design (CAD) software, which codified design rules
such as the minimum dimensions of wires or tran-
sistors and the various spacings between them. The
design processes were proprietary because they
gave the electronics manufacturer that sold the chips
a competitive advantage in speed, density, and reli-
ability. Proprietary design processes preserved this
competitive advantage but meant that the employ-
ees had to be trained on the job.
To make the semiconductor industry scalable,
universities championed relaxed “least common
denominator” design rules that were independent of
any specific process.2 Process-independent design
rules would work on proprietary fab lines, thus fore-
shadowing the emergence of a separate CAD industry,
semiconductor foundries, and a systematic way to
train the workforce that has engineered all of the chips
in use today.
ARPA’s MOSIS made chip design widely accessible.
The main idea was that students from many universi-
ties would create chip designs using generic design
rules as class projects or for theses. Student designs
2469-7087/21 © 2021 IEEE
 Silicon Qubit
MCM Chip
dc Wiring
Harness
Wire Bonds
Microbumps
Metal Carrier
FIGURE 1. A hybrid classical-quantum module.1 The small square indicated contains two qubits, and the larger square below it
contains single-flux quantum logic. The test fixture carries both dc and microwave signals. RF: radio frequency; MCM: mul-
tichip module.
are typically so small that the overhead of commercial
contracting is burdensome; therefore, many student
designs could be combined into a single fab run. The
MOSIS operational model is one in which the layout
from multiple student projects would be combined by
the MOSIS operator into a single set of masks and then
manufactured by any foundry that could support the
generic design rules.
MOSIS is in operation today (https://mosis.com)
and the main chip fab option available to students. But
it is also a practical option for start-ups and, in fact,
any researcher who wants to create a handful of small
chips to test a hardware idea.
QUANTUM ACCESS
Quantum computer systems are now accessible
via the Internet for quantum software training and
small-scale research. Extending access to quantum
hardware could follow and then extend the semicon-
ductor MOSIS paradigm. The IEEE Quantum Initiative
is using the name quantum access for a potential non-
profit service that
www.computer.org/computingedge
Printed Circuit
Board
RF Wiring Harness
Ribbon Bonds
Coplanar Waveguide
Transition to MCM
›› fabricates quantum components like those
shown in Figure 1, using unique quantum fea-
tures such as cryogenic packaging, microwave
signals, qubits, and control electronics, extend-
ing the suite of available features over time as
discussed later in this article
›› at the operational level, the operator would
contract with fabs, design tool suppliers, and
companies that can perform certain assembly
activities, essentially aggregating funds from
small users to create a fab run that is compatible
with standard industrial processes
›› organizes, but does not create, educational
materials, process design kits (PDKs), and
generic intellectual property (IP) that enables
users to get up to speed quickly.
The quantum access user would be a student,
researcher, or start-up company that wants to try out
a hardware idea in quantum information technology.
Student interest would start by taking classes, perhaps
those specifically developed for quantum access. All
9
REBOOTING COMPUTING

TABLE 1. The quantum access user classes.

Segment Objectives Typical interaction Technology and IP

Students Hands-on experience to University uses educational
augment classwork materials that highlight the use of
quantum access; submits simple
components from the class project
for fab
Educational modules where indicated; a
standard PDK and generic IP from others;
little interest in commercializing the IP
students create

University Foundry for trying out Fab using standard processes with May modify the PDK or create a new
research novel ideas for a thesis new designs; researcher may go on one; interest in IP for publication or
or for faculty research site commercialization through university
projects licensing

Commercial users Prototyping hardware Fab using standard processes with May modify the PDK; the design may be
concepts, R&D new designs; employees may go on commercially sensitive and must be kept
missions, and derivative site from other user; new IP will be owned by
technology the user

Government Prototyping Requests from government research Standard or government-supplied PDKs;

agencies nonstandard technology programs; researchers may go on the latter could be released commercially
site as well as government program over time; government IP may be sensitive
administrators

Government Exploring high-risk or Fab request directly from a Standard or government-supplied PDKs;
research labs niche technology that government entity government may create a fab; government
may not be destined for IP may be sensitive but may not be
commercialization intended for commercialization

(Original table courtesy of Synopsys; modified by the author.)

users would then require access to a capital-intensive cryogenic). This would enable the user (or the user’s
fab and help construct a “test harness,” that is, a university or employer) to place an order for commer-
simple system, to test an idea. Table 1 summarizes the cially available equipment and have some assurance
different user classes. that the purchased parts would work together and
To try out the idea quickly and at low cost, quan- also work with the custom parts created by quantum
tum access would also curate information about access’s foundries. Unlike the situation I experienced
the design of standard components, called IP, which in 1981, it may be possible for a cryogenic test sys-
tem to be constructed on a centralized location and
accessed via the Internet.
UNLIKE THE SITUATION I Quantum access should anticipate that a few
EXPERIENCED IN 1981, IT MAY BE projects will become unusually successful and provide
POSSIBLE FOR A CRYOGENIC TEST a path to volume manufacturing. Thus, start-ups, the
SYSTEM TO BE CONSTRUCTED ON government, and government labs would have a role
A CENTRALIZED LOCATION AND that eventually outgrows the quantum access model;
ACCESSED VIA THE INTERNET. these are listed near the bottom of Table 1.

users could include with no modification and hence
with less effort or risk of error. For example, users with
ideas for a new microwave amplifier can prototype
their innovative amplifier circuit but use open source,
tested designs for filters, drivers, and so on.
Quantum access would also be a source of reliable
information about physical test apparatus (including
QUANTUM ACCESS
MATURATION PROCESS
It didn’t occur to me in 1981 to ask which semiconduc-
tor process would be used for my CMOS MOSIS chip.
I was simply glad there was one option instead of no
options. Quantum access could start out similarly by
supporting a single quantum-system type (for exam-
ple, a qubit type) and expand the number of types over

10 ComputingEdge September 2021


time. As an example of where this might go, the semi-
conductor MOSIS service currently supports 20 semi-
conductor processes from two foundries.
QUBITS
Superconducting qubits (transmons) seem to have
reached the maturity level necessary for quantum
access to be viable. Transmons are physically large and
do not require many mask layers, making current designs
mature enough for general production. Although
research on superconducting qubits continues, the
quantum industry is growing and expected to special-
ize as it matures, so some students and new corporate
or university entrants may want to avoid well-trodden
areas, such as making their own qubits. Instead, they
might use generic qubits for research projects in other
areas under the assumption that their results would
be combined with the latest qubits prior to production.
Even though specific plans are yet to be deter-
mined, ion traps may be the second qubit type
offered. Experimental ion traps used for quantum
computer-type applications are manufactured by gov-
ernment labs. Some of these labs fabricate for other
parties, although foundry access will need to mature
before ion traps will be viable in quantum access.
CLASSICAL CONTROL SYSTEMS
Transmon systems are almost universally controlled
by room-temperature lab equipment interfacing via
electronics at various temperature stages. The elec-
tronics may be passive, transistor, or Josephson junc-
tion (JJ) based.
Just as I tested my CMOS chip in 1981 using an
oscilloscope, the idea is that quantum access would
engage with test equipment and cryogenic equip-
ment manufacturers from the start. Although quan-
tum technology is not ready for formal standards,
researchers need information on signal flow through
cryogenic stages and what to expect from test equip-
ment. Test equipment and cryogenics will inevitably
evolve; therefore, these manufacturers are expected
to be interested in feedback from users.
As quantum technologies mature, there is the
belief that room-temperature lab equipment will be
supplemented by electronics close to the qubits for
reasons of signal latency, bandwidth, and thermal
backflow. Broadly speaking, the two leading options
www.computer.org/computingedge
REBOOTING COMPUTING
are cryo CMOS and superconducting electronics
based on classical JJs.
For example, Intel and Microsoft fund quantum
control electronics using existing CMOS processes
of a modest linewidth (for example, 28 nm) and that
are in commercial use for the Internet of Things
and other timely business opportunities. 3,4 Many
room-temperature semiconductor processes work
at cryogenic temperatures, although some work bet-
ter than others. It is expected that, over time, special
cryo CMOS processes will be developed for quantum
information, further differentiating quantum access
from MOSIS. Lincoln Labs, SeeQC, Skywater, and
others use JJ-based control circuitry,1,5 which has
different properties in terms of density, heat dissipa-
tion, and so forth.
Unlike the simple fab processes used by transmon
EXPERIMENTAL ION TRAPS USED
FOR QUANTUM COMPUTER-TYPE
APPLICATIONS ARE MANUFACTURED
BY GOVERNMENT LABS.
qubits, classical control systems will have roughly the
same process complexity (for example, the number of
layers) as that of today’s CMOS, implying an expensive
fab. JJ processes are destined to be equally complex
but are still under development, including through
government R&D funding. When it is time to support
ion traps, quantum access would need to embrace a
different fab process, electronics with different oper-
ating voltages, optical (laser) signaling, and optical
components.
DESIGN TOOLS AND IP
Integrated circuits have not been designed directly by
humans for decades, but rather by electronic design
automation (EDA) software that synthesizes circuits,
translates them into physical layouts, and then simu-
lates their performance. Thus, new quantum-relevant
design principles will need to be embedded into design
tools. It will be essential that industry fosters the devel-
opment of quantum-specific design tools and dissem-
inates to the quantum workforce the knowledge for
how to use them.
11
REBOOTING COMPUTING
The idea is that quantum access would work with
EDA companies to ensure that students and other
users have the most advanced and compatible tools
available from industry to produce designs for quan-
tum access. Quantum access would also serve as a
repository for open access hardware designs, subject
to limitations on the distribution of this information
due to proprietary or government restrictions.
EDUCATIONAL MATERIALS
Although quantum access is not expected to dis-
tribute educational materials directly, it may end up
with a central role in making educational materials
effective. Future quantum engineering students
will need to take classes on the design of qubits and
various forms of control electronics. These classes
would teach best practices and have a role in defin-
ing the terminology, circuits, and so forth that stu-
dents bring to the workforce after they gradu-
ate. The developers of educational materials could
coordinate with quantum access to ensure that stu-
dents do homework assignments and class proj-
ects in ways that are not just generally correct but
compatible with the specific methods and customs
used in industry.
If experience with the semiconductor MOSIS
activity decades ago recurs, quantum access could
influence the development of an industrial quantum
infrastructure and, possibly, standards in the quantum
engineering domain.
I t seems natural that the quantum industry will
develop commercial infrastructure similar to the
existing semiconductor industry, including fabs, fab-
less design houses, design tool vendors, and IP sup-
pliers, all of which would be coordinated by standards.
Yet, the industry can and should partner with noncom-
mercial organizations, such as IEEE, the Quantum Eco-
nomic Development Consortium, universities, and, we
suggest here, a new quantum access entity.
Building a fab costs a lot of money, yet the quan-
tum access concept does not involve building fabs.
Instead, it organizes people to cooperate toward the
common goal of educating students and supporting
early-stage research, both of which are imperative and
worthwhile goals. This article describes a worthwhile
goal in the hope that readers will lend support.
12 ComputingEdge
ACKNOWLEDGMENTS
Although references made to my 1981 MOSIS project
are entirely my responsibility, quantum access is the
topic in a semiformal IEEE Quantum Initiative work-
ing group. The ideas herein are due to approximately a
dozen people in that group. Individuals from Raytheon,
Baylor University, Syracuse University, the Massachu-
setts Institute of Technology, and Synopsys assisted
with preparing this article.
REFERENCES
1. R. Das et al., “Cryogenic qubit integration for quantum
computing,” in Proc. 2018 IEEE 68th Electronic Compo-
nents and Technology Conf. (ECTC), pp. 504–514. doi: 10
.1109/ECTC.2018.00080.
2. C. Mead and L. Conway, Introduction to VLSI Systems,
vol. 1080. Reading, MA: Addison-Wesley, 1980.
3. B. Patra et al., “A scalable Cryo-CMOS 2-to-20GHz
digitally intensive controller for 4 × 32 frequency
multiplexed spin qubits/transmons in 22nm FinFET
technology for quantum computers,” in Proc. 2020 Int.
Solid-State Circuits Conf., pp. 304–306. doi: 10.1109
/ISSCC19947.2020.9063109.
4. S. J. Pauka et al., A cryogenic interface for controlling
many qubits. 2019. [Online]. Available: arXiv:1912.01299
5. R. McDermott et al., “Quantum–classical interface
based on single flux quantum digital logic,” Quantum
Sci. Technol., vol. 3, no. 2, p. 024004, 2018. doi: 10.1088
/2058-9565/aaa3a0.
ERIK DEBENEDICTIS is the principal of Zettaflops, LLC,
editor-in-chief of IEEE Transactions on Quantum Engineer-
ing, and a volunteer supporting the IEEE Computer Society,
Council on Superconductivity, Rebooting Computing, and
Quantum Initiative. Contact him at erikdebenedictis@gmail
.com.
F O LLOW US
@ s e cu rit y p riv a c y
September 2021
PURPOSE: The IEEE Computer Society is the world’s largest
association of computing professionals and is the leading provider
of technical information in the field.
MEMBERSHIP: Members receive the monthly magazine
Computer, discounts, and opportunities to serve (all activities
are led by volunteer members). Membership is open to all IEEE
members, affiliate society members, and others interested in the
computer field.
COMPUTER SOCIETY WEBSITE: www.computer.org
OMBUDSMAN: Direct unresolved complaints to
ombudsman@computer.org.
CHAPTERS: Regular and student chapters worldwide provide the
opportunity to interact with colleagues, hear technical experts,
and serve the local professional community.
AVAILABLE INFORMATION: To check membership status, report
an address change, or obtain more information on any of the
following, email Customer Service at help@computer.org or call
+1 714 821 8380 (international) or our toll-free number,
+1 800 272 6657 (US):
• Membership applications
• Publications catalog
• Draft standards and order forms
• Technical committee list
• Technical committee application
• Chapter start-up procedures
• Student scholarship information
• Volunteer leaders/staff directory
• IEEE senior member grade application (requires 10 years
practice and significant performance in five of those 10)
PUBLICATIONS AND ACTIVITIES
Computer: The flagship publication of the IEEE Computer Society,
Computer publishes peer-reviewed technical content that covers
all aspects of computer science, computer engineering,
technology, and applications.
Periodicals: The society publishes 12 magazines and 17 journals.
Refer to membership application or request information as noted
above.
Conference Proceedings & Books: Conference Publishing
Services publishes more than 275 titles every year.
Standards Working Groups: More than 150 groups produce IEEE
standards used throughout the world.
Technical Committees: TCs provide professional interaction in
more than 30 technical areas and directly influence computer
engineering conferences and publications.
Conferences/Education: The society holds about 200 conferences
each year and sponsors many educational activities, including
computing science accreditation.
Certifications: The society offers three software developer
credentials. For more information, visit
www.computer.org/certification.
BOARD OF GOVERNORS MEETING
TBD
revised 25 May 2021
EXECUTIVE COMMITTEE
President: Forrest Shull
President-Elect: William D. Gropp
Past President: Leila De Floriani
First VP: Riccardo Mariani; Second VP: Fabrizio Lombardi
Secretary: Ramalatha Marimuthu; Treasurer: David Lomet
VP, Membership & Geographic Activities: Andre Oboler
VP, Professional & Educational Activities: Hironori Washizaki
VP, Publications: M. Brian Blake
VP, Standards Activities: Riccardo Mariani
VP, Technical & Conference Activities: Grace Lewis
2021–2022 IEEE Division VIII Director: Christina M. Schober
2020-2021 IEEE Division V Director: Thomas M. Conte
2021 IEEE Division V Director-Elect: Cecilia Metra
BOARD OF GOVERNORS
Term Expiring 2021: M. Brian Blake, Fred Douglis,
Carlos E. Jimenez-Gomez, Ramalatha Marimuthu,
Erik Jan Marinissen, Kunio Uchiyama
Term Expiring 2022: Nils Aschenbruck,
Ernesto Cuadros‐Vargas, David S. Ebert, Grace Lewis,
Hironori Washizaki, Stefano Zanero
Term Expiring 2023: Jyotika Athavale, Terry Benzel,
Takako Hashimoto, Irene Pazos Viana, Annette Reilly,
Deborah Silver
EXECUTIVE STAFF
Executive Director: Melissa A. Russell
Director, Governance & Associate Executive Director:
Anne Marie Kelly
Director, Conference Operations: Silvia Ceballos
Director, Finance & Accounting: Sunny Hwang
Director, Information Technology & Services: Sumit Kacker
Director, Marketing & Sales: Michelle Tubb
Director, Membership & Education: Eric Berkowitz
COMPUTER SOCIETY OFFICES
Washington, D.C.: 2001 L St., Ste. 700, Washington, D.C.
20036-4928; Phone: +1 202 371 0101; Fax: +1 202 728 9614;
Email: help@computer.org
Los Alamitos: 10662 Los Vaqueros Cir., Los Alamitos, CA 90720;
Phone: +1 714 821 8380; Email: help@computer.org
MEMBERSHIP & PUBLICATION ORDERS
Phone: +1 800 678 4333; Fax: +1 714 821 4641;
Email: help@computer.org
IEEE BOARD OF DIRECTORS
President: Susan K. “Kathy” Land
President-Elect: K.J. Ray Liu
Past President: Toshio Fukuda
Secretary: Kathleen A. Kramer
Treasurer: Mary Ellen Randall
Director & President, IEEE-USA: Katherine J. Duncan Director
& President, Standards Association: James Matthews Director
& VP, Educational Activities: Stephen Phillips Director & VP,
Membership & Geographic Activities:
Maike Luiken
Director & VP, Publication Services & Products: Lawrence Hall
Director & VP, Technical Activities: Roger U. Fujii
 EDITOR: Erik P. DeBenedictis, Zettaflops, LLC, erikdebenedictis@gmail.com

This article originally

appeared in
DEPARTMENT: REBOOTING COMPUTING
vol. 53, no. 6, 2020

The Rise of the Quantum Internet

Marcello Caleffi, Daryus Chandra, Daniele Cuomo, Shima Hassanpour, and
Angela Sara Cacciapuoti, University of Naples Federico II

The Internet just turned 50: five decades that shaped the world we live in. But what
comes next, the so-called Quantum Internet, will be even more revolutionary, likely in
ways we can’t imagine yet.

O
n 29 October 1969, the first successful mes-
sage was exchanged over the Arpanet, the
predecessor to what we now know as the
Internet. In the five decades since, the Internet has
revolutionized communications to the extent that its
impact on our lives is not only technological but rather
has affected almost every facet of business and life-
style, throughout the structure of society.
The Internet itself evolved amazingly during these
decades, from a network comprising a few static nodes
in the early days to a leviathan interconnecting half of
the world’s population through billions of devices. Yet
the fundamental underlying assumption—the Inter-
net’s primary purpose of transmitting messages that
can be successfully encoded in a sequence of classical
bits—has been unchanged since the beginning.
The advent of the engineering phase of quantum
technologies is challenging the Internet’s fundamen-
tal assumption because quantum devices require—as
communication primitives—the ability to transmit
quantum information. Hence, research groups
throughout the world, and ours as well, are investing
their efforts to design and engineer the Quantum
Internet.1–6 But there’s still a long way to go and no
guarantee of getting there very soon.
THE QUANTUM REVOLUTION
Quantum technology advances have successfully
enticed tech giants, such as IBM, Google, and Intel,
Digital Object Identifier 10.1109/MC.2020.2984871
Date of current version: 4 June 2020
to participate in the so-called quantum race. Several
start-up companies also have been founded to join
in this monumental endeavor. A very significant mile-
stone was achieved at the end of 2019 by a group of
researchers at Google, which announced quantum
supremacy by solving a classically intractable prob-
lem with its quantum processor7,8 (see “The Quantum
Supremacy”).
Immense interest in the future of quantum tech-
nologies is not only displayed by industry but also
by governments around the world. To mention some
initiatives, in April 2017, the European Commission
launched a 10-year, €1 billion flagship project to accel-
erate European quantum technologies research.9
Meanwhile, across the Atlantic, in September 2018, the
U.S. House of Representatives unanimously approved
the establishment of a National Quantum Initiative
funded with US$1.25 billion over 10 years.10
Within this context of a real quantum revolution,
the ultimate vision is to build a quantum network infra-
structure—also known as the Quantum Internet—to
interconnect remote quantum devices so that quan-
tum communications among them are enabled.2,3 The
reason behind this vision is that the Quantum Internet
is capable of supporting functionalities with no direct
counterpart in the classical Internet—ranging from
secure communication5 to blind computing 11 through
distributed quantum computing 1,2—as recently over-
viewed by the Internet Engineering Task Force.12
Although it is too early to tell when and how this
quantum network will be deployed, our goal here is
to describe how the Quantum Internet differs from
the current Internet. For this, we introduce the very

14 September 2021 Published by the IEEE Computer Society  2469-7087/21 © 2021 IEEE
 basic idea of the Quantum Internet and its underlying
foundation, and we highlight the necessary steps as
well as the novel challenges we will face on our journey
toward the Quantum Internet design and deployment.
THE QUANTUM INTERNET
The Quantum Internet is a network enabling quantum
communications among remote quantum devices.
What sets it apart from the classical Internet is the
ability to transmit quantum bits (qubits), which dif-
fer fundamentally from classical bits, and create dis-
tributed, entangled quantum states with no classical
equivalent.3
Specifically, the Quantum Internet is governed by
the laws of quantum mechanics. Hence, phenomena
with no counterpart in classical networks, such as
entanglement, the impossibility to safely read and
copy the quantum information impose terrific con-
straints for the network design. That means most
techniques adopted within the classical Internet can-
not be reused here.2
Just consider how important storing information
for long periods at network nodes is to classical Inter-
net functionalities. This cannot be taken for granted
in the Quantum Internet because the phenomenon
known as decoherence rapidly corrupts quantum
information, making it challenging to rely on quantum
memories.
Another constraint that makes things harder is
the no-cloning theorem. Indeed, the classical Inter-
net operates by extensively duplicating information
among the different components of a network node
and among different nodes. In the Quantum Internet,
the no-cloning theorem forbids copying an unknown
qubit. Hence, the commonly used methods for keep-
ing the integrity of information, for example, retrans-
mission of the same information, are now forbidden.
Finally, quantum states cannot be read without
affecting their states. Any attempt to measure a qubit
www.computer.org/computingedge
THE QUANTUM
SUPREMACY
T he term quantum supremacy was coined by
J. Preskill in 2011S1 to describe the moment
when a programmable quantum device would solve
a problem that cannot be solved by classical com-
puters, regardless of the usefulness of the problem.
REFERENCE
S1. J. Preskill, “Quantum computing and the
entanglement frontier,” in Proc. 25th Solvay
Conf. Physics, Oct. 2011.
THE DIRECT TRANSMISSION OF
QUBITS SO FAR APPEARS LIMITED
TO RELATIVELY SHORT DISTANCES
IN THE CONTEXT OF SPECIFIC
APPLICATIONS THAT CAN TOLERATE
LOW-TRANSMISSION SUCCESS RATES.
makes its state collapse into a classical bit value—0
or 1. For this particular reason, and for the no-cloning
theorem as well, the direct transmission of qubits so
far appears limited to relatively short distances in
the context of specific applications that can tolerate
low-transmission success rates.
It becomes evident that a paradigm shift is required.
Indeed, the very concept of information transmission has
to be rethought and reformulated for Quantum Inter-
net design. Thankfully, quantum mechanics provides us
an amazing tool for transmitting quantum information,
the quantum teleportation process, astonishingly,
without the physical transfer of the qubit.
15
REBOOTING COMPUTING

Sender
Original
Quantum State Entanglement”), in 1993 Bennett
et al.13 showed that it is possible to
Classical instantaneously transfer the quan-
Communication tum state encoded in a qubit at a
certain sender to a qubit stored at
a certain receiver without, surpris-
EPR Pair ingly, the physical transfer of the
qubit at the sender.3 This quantum
Receiver communication protocol, already
experimentally verified, is known
as quantum teleportation.
In a nutshell, the teleportation
process, portrayed in Figure 1 for a
Two-Qubit Operations One-Qubit Operations Measurement single qubit, requires 1) the genera-
tion and distribution of a maximally
FIGURE 1. A general schematic of quantum teleportation protocol, where the entangled pair of qubits (referred
standard bra-ket notation |· is adopted for describing quantum states. Notice in the to as an EPR pair) between the
figure that after quantum teleportation, the original qubit and the entanglement are source and destination, and 2)
destroyed. As weird as it seems, quantum teleportation fully obeys the fundamen- a classical transmission to send
tal principles of quantum mechanics. Therefore, the cost of transmitting quantum two classical bits. Consequently, a
information can be exchanged with entanglement and classical communications. classical link for sending classical
Because the entanglement is always destroyed after every single teleportation, information and a quantum link for
it constitutes the primary consumable resource in the Quantum Internet, which entanglement generation and dis-
means it needs to be generated continuously. tribution need to be established in
advance.
Moreover, each teleportation
process destroys the entanglement-pair member at
the source. A successive teleporting requires the
INTRODUCING generation and distribution of a new entangled pair
ENTANGLEMENT between source and destination. This, in turn, implies

E
ntanglement is one of the most distinguishing
quantum phenomena with no counterpart in
the classical world, in which the quantum states of
two or more particles become inextricably linked
even if they are separated by a great distance. The
entanglement of quantum particles demonstrates
a relationship between their fundamental proper-
ties that cannot happen arbitrarily. When a mea-
surement is performed on one of the particles, the
other particle will be instantly influenced.
BEYOND DIRECT QUBIT
TRANSMISSION
By using a unique feature of quantum mechan-
ics, known as entanglement (see “Introducing
radically new challenges from a network design per-
spective, completely changing the classical concepts
of network connectivity and throughput. Indeed, the
connectivity between two quantum nodes is strictly
determined by the availability of a shared entangled
pair, and it inherently varies in time as a consequence
of the depletion of the entanglement-pair member at
the source.
The challenges are not limited to the above-
mentioned ones. In fact, long-distance entanglement
distribution still constitutes a key issue due to the
decay of the entanglement distribution rate as a func-
tion of the distance.1,3 And because qubits cannot be
copied due to the no-cloning theorem, classical signal
amplification techniques cannot be employed. In this
context, quantum teleportation relies on intermediate
nodes, known as quantum repeaters, that are capable

16 ComputingEdge September 2021

 REBOOTING COMPUTING

Quantum Device 1 Quantum Repeater Quantum Device 2

(4) Local (2) Bell-State (4) Local

Operation (3) Classical Measurement (3) Classical Operation
Communication Communication

(a) (1) EPR Pair (1) EPR Pair

Quantum Device 1 Quantum Repeater Quantum Device 2

Classical Link Classical Link

(b) Entangled Qubits Over a Longer Link

FIGURE 2. The entanglement swapping portrait. (a) Each quantum device shares an EPR pair with an intermediate node, the
quantum repeater. The repeater performs Bell-state measurement on the two qubits in its possession, which results in the col-
lapse of their quantum states into classical bits. The repeater sends the classical bits obtained from the measurement opera-
tion to the quantum devices. Finally, based on the received bits, the quantum devices perform local operations to complete the
swapping process. (b) The result is that the entanglement between the quantum devices is created over a longer distance.

of entangling distant nodes—without physically send-

ing an entangled qubit through the entire distance—
by swapping the entanglement generated through REALIZING THE QUBIT
shorter links,14 as illustrated in Figure 2.
It is evident that the design of the Quantum Inter-
net constitutes a breakthrough from an engineering
perspective. Each network functionality must be
C urrently, there exist multiple technolo-
gies for realizing a qubit (quantum dots,
transmons, ion traps, photons, and so forth),
redesigned and reengineered with a solid integra- with each technology characterized by different
tion of classical and quantum communications pros and cons. This hardware heterogeneity will
impose its own additional challenges to create
resources.15 In this regard, the classical resources
an integrated Quantum Internet ecosystem.
for transmitting classical bits will likely be provided
by integrating such classical networks as the current
Internet with the Quantum Internet. 2

P aving a journey toward the Quantum Internet is

indeed not a straightforward task. Historically,
predictions about technological developments prove
themselves true hardly or in ways the predictor didn’t
expect at all. Hence, there will definitely be twists
and turns in the design of the Quantum Internet, with
uncertainty on when and how this goal will be accom-
plished (see “Realizing the Qubit”).
However, we may envision roughly three subse-
quent necessary steps, whose complexity scales
as a function of the time and the level of platform
heterogeneity, as portrayed in Figure 3. The very
first step involves interconnecting multiple quan-
tum processors within a single quantum computer.
The qubits are likely to be homogeneous among the

www.computer.org/computingedge 17
REBOOTING COMPUTING

Long-distance The second step involves

The distances between connectivity and the
quantum computers
interconnecting multiple quan-
diversity of qubits
within a quantum farm are expected.tum computers within the same
are relatively short. farm. At this stage, the hardware
The distances Qubits are most likely
Distance and Heterogeneity

between qubits within to be homogeneous.

a quantum computer
are extremely short.
Qubits are
homogeneous.
Interconnecting
Multiple Quantum
Computers Within
Step 1: the Same Quantum
Interconnecting
Farm
Multiple Quantum
Processors Within
a Single Quantum
Computer
Time
FIGURE 3. The necessary steps toward the envisioned Quantum Internet. We
hypothesize that the complexity scales proportional to the distance of connectivity
and level of platform heterogeneity among quantum farms.
different processors, although heterogeneity may
arise within due to different hardware technolo-
gies underlying memory and computational units.
The link for connecting the qubits is very short, and
the network topology is fixed so that only a simple
addressing and routing protocol is required. Timing
and synchronization need to be carefully designed.
Network functionalities that are unavailable in clas-
sical networks must be designed and implemented.
For instance, quantum decoherence must be care-
fully accounted for within the network design so
that it can be used to represent a key metric for the
network functionalities. Local operations among
qubits within a single processor must be comple-
mented by remote operations—operations among
qubits placed at different processors. The tradeoff
between qubits devoted to computation and entan-
gled qubits devoted to communication represents
a key issue with no counterpart in the classical
network design. The very concept of distributed
quantum algorithm design must explicitly take such
a tradeoff and the delay induced by remote opera-
tions into consideration.
Step 3: heterogeneity among the different
Interconnecting quantum computers may arise.
Multiple
Geographically Such heterogeneity must be con-
Step 2:
Distributed sidered in network functionalities.
Quantum Farms
The entanglement distribution
benefits from the controlled farm
environment and relatively short
distances. Delay imposed by
classical communication times
is slightly longer compared to
interprocessor wiring. Hence,
this requires more sophisticated
timing and synchronization. The
network topology is more com-
plex, and it may vary in time as the
number of nodes in the network
changes. This, in turn, induces
dynamics at the network boot-
strap/functioning, which requires
more sophisticated strategies for
routing and access as well as for mitigating quantum
errors. Finally, the balance between local and remote
operations—between computational and communi-
cation qubits—becomes even more intricate.
The final long-term step involves interconnect-
ing multiple geographically distributed quantum
farms. One of the key challenges is the heterogeneity
among different quantum farms, which may be oper-
ated by different companies. This requires significant
efforts in terms of network standardization. Further-
more, the heterogeneity among quantum links, for
example, optical, free space, or satellite, will arise.
The delays induced by the distances will introduce
severe challenges on the entanglement generation
and distribution. The increasing number of quantum
devices to be wired and the heterogeneity of the
environments hosting the quantum computers must
be taken into account.
One of the judicious questions raised from this
discussion is when will we see the Quantum Inter-
net? There is no definite answer to this question.
However, we firmly believe this is a goal that requires
a collaborative effort and a multidisciplinary

18 ComputingEdge September 2021


approach between academics and industry. The
required competences and skills are many and
diverse, and each is interconnected with and vital
to the others.
REFERENCES
1. M. Caleffi, A. S. Cacciapuoti, and G. Bianchi, “Quantum
Internet: From communication to distributed comput-
ing!” in Proc. 5th ACM Int. Conf. Nanoscale Computing
and Communication, 2018, pp. 1–4. doi: 10.1145/3233188
.3233224.
2. A. S. Cacciapuoti, M. Caleffi, F. Tafuri, F. S. Cataliotti,
S. Gherardini, and G. Bianchi, “Quantum Internet:
Networking challenges in distributed quantum
computing,” IEEE Netw., vol. 34, no. 1, pp. 137–143, Jan.
2020. doi: 10.1109/MNET.001.1900092.
3. A. S. Cacciapuoti, M. Caleffi, R. Van Meter, and L.
Hanzo, “When entanglement meets classical com-
munications: Quantum teleportation for the Quantum
Internet,” IEEE Trans. Commun., to be published.
4. S. Pirandola and S. L. Braunstein, “Physics: Unite to
build a quantum internet,” Nature, vol. 532, no. 7598,
pp. 169–171, 2016. doi: 10.1038/532169a.
5. S. Wehner, D. Elkouss, and R. Hanson, “Quantum
Internet: A vision for the road ahead,” Sci., vol. 362,
no. 6412, p. eaam9288, 2018. doi: 10.1126/science
.aam9288.
6. D. Castelvecchi, “The quantum internet has arrived
(and it hasn’t),” Nature, vol. 554, no. 7692, Feb. 2018.
doi: 10.1038/d41586-018-01835-3.
7. F. Arute et al., “Quantum supremacy using a program-
mable superconducting processor,” Nature, vol. 574,
no. 7779, pp. 505–510, 2019. doi: 10.1038/s41586-019
-1666-5.
8. E. P. Debenedictis, “Beyond quantum supremacy,”
Computer, vol. 53, no. 2, pp. 91–94, Feb. 2020. doi:
10.1109/MC.2019.2958446.
9. E. Gibney, “Europe’s billion-euro quantum project takes
shape,” Nature News, vol. 545, no. 7652, p. 16, 2017. doi:
10.1038/545016a.
10. E. Gibney, “Quantum gold rush: The private funding
pouring into quantum start-ups,” Nature, vol. 574,
no. 7776, pp. 22–24, 2019. doi: 10.1038/d41586-019
-02935-4.
11. A. Broadbent, J. Fitzsimons, and E. Kashefi, “Univer-
sal blind quantum computation,” in Proc. IEEE 50th
Annu. Symp. Foundations Computer Science, 2009,
www.computer.org/computingedge
REBOOTING COMPUTING
pp. 517–526.
12. C. Wang, A. Rahman, and R. Li, “Applications and
use cases for the Quantum Internet,” Internet-Draft
Draft-Wang-Qirg-Quantum-Internet-Use-Cases-04,
Internet Engineering Task Force, Fremont, CA, Mar.
2020. Work in Progress.
13. C. H. Bennett, G. Brassard, C. Crépeau, R. Jozsa,
A. Peres, and W. K. Wootters, “Teleporting an
unknown quantum state via dual classical and
Einstein-Podolsky-Rosen channels,” Phys. Rev. Lett.,
vol. 70, no. 13, pp. 1895–1899, 1993. doi: 10.1103
/PhysRevLett.70.1895.
14. R. Van Meter, Quantum Networking. Hoboken, NJ:
Wiley-ISTE, Apr. 2014.
15. W. Kozlowski, S. Wehner, R. V. Meter, B. Rijsman,
A. S. Cacciapuoti, and M. Caleffi, “Architectural
principles for a Quantum Internet,” Internet-Draft
Draft-Irtf-Qirg-Principles-03, Internet Engineering Task
Force, Fremont, CA, Mar. 2020. Work in Progress.
MARCELLO CALEFFI is the codirector of the FLY: Future
Communications Laboratory, University of Naples Federico II,
Italy. He is also with the Laboratorio Nazionale di Comunica-
zioni Multimediali, National Inter-University Consortium for
Telecommunications, Naples, Italy. Contact him at marcello
.caleffi@unina.it.
DARYUS CHANDRA is with the www.QuantumInternet.it
Research Group, FLY: Future Communications Laboratory,
University of Naples Federico II, Italy. Contact him at daryus
.chandra@unina.it.
DANIELE CUOMO is with the www.QuantumInternet.it
Research Group, FLY: Future Communications Laboratory,
University of Naples Federico II, Italy. Contact him at daniele
.cuomo@unina.it.
SHIMA HASSANPOUR is with the www.QuantumInternet.
it Research Group, FLY: Future Communications Laboratory,
University of Naples Federico II, Italy. Contact her at shima
.hassanpour@unina.it.
ANGELA SARA CACCIAPUOTI is the codirector of the FLY:
Future Communications Laboratory, University of Naples
Federico II, Italy. Contact her at angelasara.cacciapuoti
@unina.it.
19
 EDITOR: Virgilio Almeida, virgilio@dcc.ufmg.br
This article originally
appeared in
DEPARTMENT: INTERNET GOVERNANCE
vol. 23, no. 6, 2019

Principles and Elements

of Governance of Digital
Public Services
Virgilio Almeida, Harvard University
Fernando Filgueiras, National School of Public Administration, Brazil
Francisco Gaetani, Getulio Vargas Foundation

Digital technologies can be valuable tools to create better public services that benefit society
as a whole. Governance is the way to align digital public services with the interests of society.
In this article, we discuss principles and elements of governance of digital public services.

D
igital technologies, especially algorithms,
Internet, artificial intelligence, voice inter-
face technologies and IoT, are transforming
the world, modifying how we communicate, live, and
work. In many countries, better and more efficient
public services are being demanded by society, due to
economic pressures, ageing populations, new forms of
social services, and digital transformation initiatives.1
Digital technologies can be valuable tools to create
better public services that benefit society as a whole
and in particular the most vulnerable groups. Mecha-
nisms and procedures are needed to assure that digiti-
zation of public services meets society's needs and is
not adopted because of the technological fads pushed
by the technology industry.
Thus, a natural question that arises is: How can we
use digital technologies to improve public services?
Governance is the answer. Governance is the way to
align digital public services with the interests of soci-
ety. A governance framework for digital public services
should be able to oversight the process of procure-
ment, development, delivery, and evaluation of digital
public services. In this article, we discuss principles
and elements of governance of digital public services.
Digital public services are usually developed
Digital Object Identifier 10.1109/MIC.2019.2936928
Date of current version 17 January 2020.
and operated in a decentralized way and distributed
over different parts of the public administration. The
governance ecosystem of digital public services has
many players with very different legal statuses, which
depend on the formal organization of government
as well as on the informal power structure, based on
political interests. Common principles could be the
element that will put together different interests in
government to create digital public services that are
inclusive, effective, and legitimate.
A set of high-level principles could be useful to
shape the governance structure of digital public
services. Principles should be formulated by a multi-
stakeholder group, involving different sectors of gov-
ernment, civil society, and businesses. For example, an
overarching principle to guide the digitization of public
services could be one that emphasizes the inclusive
nature of public services in a simple statement, such
as: Assure that digital public services leave no one
behind.10 Good governance must also adhere to gen-
eral principles such as transparency, accountability,
openness, fairness, and responsiveness, to ensure
that digital public services meet the legitimate expec-
tations and needs of citizens.
There are elements that we consider important
for the governance of digital public services. They can
be applied to the governance framework, depending
on the stage of digitization of the public services. The
elements that follow provide practical support for the

20 September 2021 Published by the IEEE Computer Society  2469-7087/21 © 2021 IEEE

development of a framework for governance of digital
public services.
ELEMENT #1: HAVE
COPRODUCTION GUIDELINES
One of the central elements for governance of digital
public services is the capacity with which algorithms
can promote public services’ coproduction and cus-
tomization. Coproduction of public services is the
involvement of users with the provision of services,
in which deliveries will be the result of the relation-
ship between the users of the service and the organi-
zation that provides it.2 Coproduction occurs through
the long-term involvement of users and professionals
that provide services. The active role of citizens in the
production of public services increases customization
and improves service delivery and avoids technocratic
governance.3 Additionally, the involvement of users
and civil society in the production process can con-
tribute to include an accountability perspective to the
public service algorithms.
Digitization of public services involves redesigning
process—from service demand to delivery—so as to
ensure that public services’ bureaucratic paper pro-
cesses are not simply transposed to digital processes.
Coproduction is necessary so that public services
can expand their delivery capacity and anticipate or
predict the needs of citizens.4 In addition, coproduc-
tion promotes services that are need-based holism.
The coproduction element allows for more resilient
and responsive governments, which may be able to
respond to different problems in real time.
Thus, public service digitization strategies should
consider coproduction as a necessary condition for
the increase of efficiency. Associated with algorithms
that can be used to collect and analyze user data, digi-
tization should aim to promote increasingly custom-
ized and anticipated public services. Algorithms can
collect data and anticipate future individual lives.5
They can be augmented with the use of machine-
learning tools in order to promote changes based on
knowledge about citizen behavior. That way digital
public services can predict, nudge, and drive citizens’
behavior.6 Individual citizens, understood as users of
public services, are coproducers and data sources
that can be analyzed by the use of machine learning
algorithms to customize public services.
www.computer.org/computingedge
INTERNET GOVERNANCE
ELEMENT #2: HAVE INCLUSIVE
AND EQUITABLE POLICIES
Public services result in rights and benefits for citi-
zens. Governments should provide public services in
an inclusive perspective by law and to reach social
justice. Assuming that digital public services are not
only the shift from interaction between the citizen
and the bureaucracy to the interaction between the
citizen and the computer, they must contain an inclu-
sion perspective.
The main factors that promote citizens' exclusion
derive from digital divide. The interaction between
man and computer requires individual skills to access
its economic, political, and social dimensions. Digital
divide refers to the growing gap between nonprivi-
leged portions of society and increasingly digitized
and Internet-based organizations. Internet access
is a structural condition of digital divide. The other
condition refers to the different level of knowledge
between people who have access to information
technology and those who do not. Digital literacy is
the individual's ability to use information and com-
munication technologies to find, evaluate, create, and
communicate information, requiring both cognitive
and technical skills.7
Digital public services have the potential to pro-
mote coproduction and customization through algo-
rithms and machine learning. However, algorithms can
produce exclusion by simply ignoring portions of soci-
ety that are not users of digital public services. Rural
populations, illiterates, and residents of areas without
Internet access may be summarily excluded by digital
services that they cannot access.
The governance of digital public services should
create mechanisms to expand digital literacy and
Internet access infrastructure as essential points for
promoting digital inclusion and allowing citizens’ inter-
action with online services.
ELEMENT #3: COMPLY WITH DATA
PROTECTION REGULATION
Digital public services must follow standards and reg-
ulation for data protection. Risks related to cyberse-
curity issues or even misuse of data by governments
can break users' trust in digital public services. Reg-
ulatory standards are needed where data may be
misused—for various purposes such as commercial,
21
INTERNET GOVERNANCE
political, or social—or where systems are subject to
cybersecurity issues.
Protecting citizens' privacy is key to building trust
in the institutional functioning of digital public ser-
vices.8 To this end, regulatory authorities need to be
created, or strengthened if they exist, to constitute a
set of standards that are enough to delimit the appli-
cability of protection, the scope of regulation and the
penalties, which should apply to different companies.
Personal data processing must be regulated from end
to end in order to avoid problems of misuse and inse-
curity. At the same time, regulation of data protection
must be dynamic in order to meet the challenges of
organizations going through digital transformation.
Compliance with data protection regulation should
result in governments’ provision of a set of standards
for citizens’ action, as well as channels for them to
communicate with the regulatory authority for pri-
vacy protection.9 Initiatives such as the General Data
Protection Regulation (GDPR) of the European Union
are recommended in order to exercise extra-territorial
regulation, and to define authority and principles
within the scope of personal data protection.
ELEMENT #4: DEVELOP DIGITAL
AND DATA-RELATED SKILLS
Lacking digital expertise in its workforce can lead to
serious consequences for governments’ provision
of digital public services. Human resources’ recruit-
ment and retention are on-going challenges for gov-
ernments, which are in short supply of qualified per-
sonnel, due to uncompetitive rates of pay and unclear
career progression rules.
The use of digital technologies in governments
transforms the government workforce. Algorithms
gradually replace street-level bureaucrats with
street-level algorithms.12 Algorithms gradually replace
people and make discretionary decisions about rights
and benefits. The result of the use of digital tech-
nologies is the reduction of the size of the workforce,
suppression of clerk activities, adoption of big data
practices, redefinition of the profile of civil servants,
introduction of artificial intelligence and others. Public
service work shifts to the back office, requiring new
skills from public servants.13
Human resources’ policies in the public sector
have faced radical changes. OECD's reports 9 on
22 ComputingEdge
the subject have emphasized the importance of
handling strategically the processes through which
governments are going through. Public servants
should develop technology skills and develop more
proactive and analytical skills that can support
a profile of greater service experimentation and
innovation.14
Digital public services impact governments and
their management tools. In this case, the process
of digital transformation of public services depends
on building skills that enable the transformation and
proper use of digital tools for governments. These skills
are related to dynamic learning ability in organizations
so that they can learn from mistakes and successful
experiences.
ELEMENT #5: HAVE
PROCUREMENT GUIDELINES
The quality of public expenditure is directly related to
procurement processes—a key public management
policy. Procurement governance has been deeply
impacted by the acceleration of the path of techno-
logical transformations. The current context has no
precedent in terms of speed, volume, and value. Pro-
curement policy is central to providing infrastructure
for government digital technologies.
On one side of the table—the government—there
are political appointees, high-level officials, middle
managers, public lawyers, and contractors. On the
other side of the table, you find marketing people from
the big tech companies, such as Amazon, Microsoft,
Google, Facebook, and Apple—all globally connected
and on the frontier of digital innovation. This formal
procurement policy relationship creates an informa-
tion asymmetry that impacts the technology infra-
structure available to governments.
The digital capacity deficit in the public sector is
not usually trivial nor easily solvable. Third parties can
play an important role in reducing informational asym-
metries. Universities, think-tanks, and consultants
should be called upon to support the decision-making
process despite the unfairness of the default nego-
tiation. It is not only a matter of resources—human,
financial, technological—but of governance arrange-
ments. Together they can establish guidelines to
guide government procurement of infrastructure,
making the most of available technology.
September 2021

ELEMENT #6: DEVELOP
ALGORITHMIC DECISION-
MAKING POLICIES
A working definition of decision-making algorithms
is given by European Commission20: ”A software sys-
tem—including its testing, training, and input data
as well as associated governance processes—that,
autonomously or with human involvement, takes deci-
sions or applies measures relating to social or physical
systems on the basis of personal or nonpersonal data,
with impacts either at the individual or collective level.“
Decision-making algorithms in public services have
been used in many areas such as education, healthcare,
transportation, security, and judicial system. Examples
of government applications include risk-assessment
algorithms that estimate the likelihood of recidivism for
criminals and customer service chatbots used by local
governments to answer questions from their constitu-
ents. The use of algorithms has the potential to improve
the quality of decision-making.17,19 They have possibil-
ity to increase speed, reduce cost, improve accuracy,
support new types of applications, and extend the
reach of public services, depending on the availability
of communication infrastructure. Although algorith-
mic decision-making can improve efficiency of public
services, it also faces some challenges, such as errors,
biases, discrimination, and other undesirable behavior
patterns. Its impact needs to be monitored. As algorith-
mic decision-making is used in an ever-growing number
of public service applications, it is necessary to protect
citizens against negative side effects of algorithmic
decisions. As pointed out by Brauneis and Goodman,16
“In the public sector, the opacity of algorithmic deci-
sion making is particularly problematic, both because
governmental decisions may be especially weighty
and because democratically elected governments
have special duties of accountability.” It is clear that
governance bodies should provide government-wide
oversight of services that rely on algorithmic deci-
sions. Governance mechanisms and measures need
to be specified to achieve transparency accountabil-
ity and fairness in digital public services.
In order to minimize risks and negative conse-
quences of automated decision-making in public
services, governments have to create governance
frameworks to deal with the development and use of
this kind of technology. Frontrunner countries in this
www.computer.org/computingedge
INTERNET GOVERNANCE
area have already proposed and developed governance
frameworks, policies, and principles for guiding the
use of algorithmic decision-making.17–19 One example
proposed by Copeland15 is: ”Every algorithm used by a
public sector organization should be accompanied with
a description of its function, objectives, and intended
impact, made available to those who use it.” Before
decision-making algorithms and artificial intelligence
technologies are deployed in large scale in government,
a key question should be answered by public administra-
tors17: Who should be responsible for governing, audit-
ing, and assuring algorithmic decision-making systems?
CONCLUSION
The rapid evolution of digital technologies requires
flexible and adaptive governance framework for dig-
ital public services. Flexible governance approaches
should support multistakeholder dialogues and part-
nerships with other government organizations, indus-
try, and civil society in order to create sustainable,
inclusive, and principle-based solutions for digital pub-
lic services.11 The process of digital transformation of
public services is underway in several countries. Gov-
ernance frameworks, with their principles and ele-
ments, is key in the digital transformation of public
services and should be created. In this article, we pre-
sented a number of principles and elements that point
in the direction of adaptive governance models.
REFERENCES
1. P. Dunleavy, H. Margetts, S. Bastow, and J. Tinkler.
Digital Era Governance: IT Corporations, the State, and
E-Government. Oxford, U.K.: Oxford Univ. Press, 2007.
2. D. Linders, “From e-government to we-government:
Defining a typology for citizen coproduction in the age
of social media,” Government Inf. Quart., vol. 23, no. 6,
pp. 446–454, 2012.
3. M. Janssen and G. Kuk, “The challenges and limits
of big data algorithms in technocratic governance,”
Government Inf. Quart., vol. 33, no. 3, pp. 371–377, 2016.
4. T. Bovaird, “Beyond engagement and participation-user
and community co-production of public services,”
Public Admin. Rev., vol. 67, pp. 846–860, 2007.
5. A. Meijer, “Co-production in an information age: Individual
and community engagement supported by new media,”
VOLUNTAS, vol. 23, no. 4, pp. 1156–1172, 2012.
6. H. Margetts and P. Dunleavy, “The second wave of
23
INTERNET GOVERNANCE
digital-era governance: A quasi-paradigm for govern-
ment on the Web,” Philos. Trans. Roy. Soc. A, Math.,
Phys. Eng. Sci., vol. 371, no. 1987, pp. 1–17, 2013.
7. International Telecommunication Union (ITU), “Uni-
versal service fund and digital inclusion for all,” 2013.
[Online]. Available: https://www.itu.int/en/ITU-D
/Digital-Inclusion/Documents/USF_final-en.pdf
8. The Royal Society and the British Academy, “Data
management and use: Governance in the 21st Century,”
The Royal Society and the British Academy, London, U.K.,
2017. [Online]. Available: https://royalsociety.org/~/media
/policy/projects/ data-governance/data-management
-governance.pdf
9. OECD, “Strengthening digital government,” OECD
Going Digital Policy Note, OECD, Paris, Italy. [Online].
Available: www.oecd.org/going-digital/strengthening
-digital-government.pdf
10. A. Young-Powell, “The challenge to ensure digital pub-
lic services leave no one behind,” The Guardian, Mar. 5,
2019. [Online]. Available: https://www.theguardian
.com/society/2019/mar/05/challenge-ensure-digital
-public-services-leave-no-one-behind
11. I. Linkov, B. Trump, K. Poinsatte-Jones, and M. Florin,
“Governance strategies for a sustainable digital world,”
J. Sustain., vol. 10, no. 2, p. 440, 2018.
12. A. Alkhatib and M. Bernstein, “Street-level algorithms:
A theory at the gaps between policy and decisions,”
in Proc. CHI Conf. Human Factors Comput. Syst. Proc.,
2019, Paper no. 530.
13. OECD, Building on Basics. Paris, Italy: OECD Publish-
ing, 2015.
14. OECD, “HR and Leadership strategies for building innova-
tive public sector organisations,” Paris, Italy. [Online].
Available: https://oecd-opsi.org/wp-content
/uploads/2019/03/HR-and-Leadership-Catalyst-for
-Innovation-Capabilities.pdf
15. E. Copeland, “10 principles for public sector use of
algorithmic decision making,” Nesta Blog, Feb. 20, 2018.
[Online]. Available: www.nesta.org.uk/blog/10-principles
-for-public-sector-use-of-algorithmic-decision-making/
16. R. Brauneis and E. Goodman, “Algorithmic Transpar-
ency for the Smart City” (August 2, 2017). 20 Yale J. of
Law & Tech. 103 (2018); GWU Law School Public Law
Research Paper; GWU Legal Studies Research Paper.
17. The Centre for Data Ethics and Innovation (CDEI),
“Review into bias in algorithmic decision-making,” Jul.
2019, U.K. [Online]. Available: www.gov.uk/cdei
24 ComputingEdge
18. C. Castelluccia and D. Le Métayer, “Understanding
algorithmic decision-making: Opportunities and
challenges,” Study, Panel Future Sci. Technol., Eur.
Parliamentary Res. Service, Mar. 2019.
19. S. Chignard and S. Penicaud, “With great power comes
great responsibility: Keeping public sector algorithms
accountable,” RightsCon, 2019, Tunis, Tunisia. [Online].
Available: rightscon2019.sched.com/event/Pvg5/with
-great-power-comes-great-responsibility-keeping
-public-sector-algorithms-accountable
20. European Commission (procured by) State-of-the-Art
Report | Algorithmic decision-making, delivered by
Optimity Advisors, Dec. 2018. [Online]. Available:
https://www.algoaware.eu/state-of-the-art-report/
VIRGILIO A. F. ALMEIDA is a Faculty Associate at the Berk-
man Klein Center for Internet and Society, Harvard Univer-
sity and an Emeritus Professor in the Computer Science
Department, Federal University of Minas Gerais, Brazil. His
research interests include cyber policies and governance,
large-scale distributed systems, the Internet, and social
computing. He received the Ph.D. degree in computer sci-
ence from Vanderbilt University. Contact him at virgilio
@dcc.ufmg.br or valmeida@cyber.harvard.edu.
FERNANDO FILGUEIRAS is the Director of Research and
Graduate Studies, National School of Public Administration,
Brazil. He is an Associate Professor at the Department of
Political Science, Federal University of Minas Gerais. He
is a researcher of the Digital Democracy Institute and a
researcher at the Institute of Advanced Studies, University of
São Paulo. His research interests include digital governance,
digital public policy and accountability. He received the
Ph.D. degree in political science from Rio de Janeiro Univer-
sity Research Institute. Contact him at fernando.filgueiras
@enap.gov.br or fernandofilgueiras@hotmail.com.
FRANCISCO GAETANI is Professor of Public Management of
the Getulio Vargas Foundation. He was the Deputy Minister
for Planning, Budget and Management, Brazilian Federal
Government. He was the Deputy Minister for the Environ-
ment, Brazilian Federal Government. His research interests
include governance, public management. He received the
Ph.D. degree in political science from London School of
Economics and Political Science. Contact him at francisco
.gaetani@fgv.br or fgaetani@gmail.com.
September 2021
 EDITORS: Heather Richter Lipford, richter@uncc.edu
Jessica Staddon, jessica.staddon@gmail.com
DEPARTMENT:
SOCIOTECHNICAL SECURITY AND PRIVACY
The Rising Threat of
Launchpad Attacks
Markus Jakobsson, ZapFraud Inc.
H
uman failure is the weakest link in many,
if not most, security systems. As a result,
criminals are increasingly relying on social
engineering as a way to circumvent security controls.
To improve their yield, criminals constantly experiment
with methods aimed at making their attacks harder to
detect—both to security systems and to the end users
behind them. Naturally, an attack that successfully
evades detection by both human and machine has the
potential to make criminals very wealthy. Therefore,
once discovered and successfully tested, such attacks
exhibit dramatic growth and are commonly copied and
tweaked by other criminals spotting an opportunity
when they see it. What we term the launchpad attack
is the newest example of such an attack. This attack
is also commonly referred to as a business email com-
promise (BEC) that uses account takeover. Although
it was virtually unheard of just a few years ago, 44%
of organizations have now experienced this type of
attack according to a recent industry report.1
In a launchpad attack, a first user—the launchpad
user—is compromised by the criminal. This typically
means that the criminal gains access to this user’s
email account, enabling the criminal to review all
emails sent and received and identify valuable con-
tacts based on their affiliations and the conversations
between the launchpad user and these contacts.
Based on this, the criminal selects one or more target
victims—the valuable contacts—and sends them
messages that, based on the scanned emails, will most
likely be both credible (to the victim) and profitable (to
the criminal).
Digital Object Identifier 10.1109/MSEC.2019.2922865
Date of publication: 3 September 2019
2469-7087/21 © 2021 IEEE Published by the IEEE Computer Society September 2021
This article originally
appeared in
vol. 17, no. 5, 2019
In one common version of the launchpad attack,
the criminal compromises an email account of a per-
son whose job involves financial transactions—for
example, a person who invoices clients of a contract-
ing company. Based on the emails this launchpad user
has sent and received, the criminal determines where
invoices are sent and sends additional invoices—or
just a request for a change of bank accounts—to
these unfortunate targets. These emails are typically
sent from the compromised account of the launchpad
user, making them instantly trustworthy to the target
due to the already established trust relationship.
However, the criminal knows that a slightly suspicious
target user may respond to the email from the launch-
pad user to ask for a confirmation before updating the
bank account information to be used to pay invoices.
These are messages that the criminal wants to receive
but that he or she does not want the launchpad user to
get to see. Therefore, criminals often set up selective
forwarding and deletion rules (e.g., based on an email
thread or a subject line).
WHY ARE LAUNCHPAD ATTACKS
SO SUCCESSFUL?
There are two principal reasons why launchpad
attacks are as successful as they are. First of all, the
deceptive emails sent to the target users are rarely
blocked by automated email filters. For one thing,
these emails are not sent from users that have been
reported as being abusive, as a spammer or a phisher
might have been. See “A Brief History of Online Social
Engineering: The Early Years” for a short history of
Internet attacks. The emails are also not sent from
unknown users with display names that are decep-
tively similar to users the target user has a trust rela-
tionship with (an otherwise common deception
25
SOCIOTECHNICAL SECURITY AND PRIVACY
A BRIEF HISTORY OF ONLINE SOCIAL ENGINEERING:
THE EARLY YEARS
H uman history is rife with examples of decep-
tion, and it should not surprise anybody that
the rapid expansion of the Internet in the 1990s was
followed by an almost equally rapid rise of abuse. Some
of this abuse targeted computers in what is commonly
referred to as hacking, but most of it targeted humans
in what is referred to as social engineering. In a social
engineering attack, a victim is tricked to perform an
action that is undesirable to him or her but that ben-
efits an attacker. See Stajano and WilsonS1 for a good
overview of general techniques.
Phishing is the perhaps the best-known example of
social engineering. Phishing started in the 1990s when
online criminals attempted to steal Internet access time
from America Online (AOL) users by posing as an AOL
staff member and asking for the login credentials of the
victims. Ten years later, with the popularization of online
payments and online banking in the early 2000s, phish-
ers were given a new and much more profitable target,
and the threat grew accordingly.
In these financial phishing attacks, phishers typically
used email spoofing to impersonate large financial insti-
tutions and request for the recipients of these emails to
log in to their bank using a URL in the phishing email that
led to a phishing website. At first, there were no techni-
cal countermeasures in place to block the spoofed
strategy). Therefore, common solutions to detect tra-
ditional BEC attacks also do not apply. Moreover, while
the emails are deceptive, they are not spoofed. There-
fore, Domain-Based Message Authentication, Report-
ing, and Conformance (DMARC)2 does not detect
them. For more about DMARC, see “A Brief History of
Online Social Engineering: The Recent Years.”
Launchpad attacks are also so successful because
the deceptive emails are sent either from users with
whom the target users have a trust relationship
(namely, the launchpad user) or from strangers with-
out an abusive history known to the system.
Furthermore, considering the content of the decep-
tive emails, this also does not cause the messages
to be blocked. Typically, the deceptive messages are
26 ComputingEdge
emails or the phishing websites. Therefore, the principal
line of defense became awareness, with financial institu-
tions and security specialists asking people to be on the
lookout for poorly spelled emails and be careful not to
click on links in emails.
The first type of advice soon became rather useless,
as phishers made an effort to have their phishing emails
carefully proofread. The second was never very helpful
given that most legitimate companies would at times
send emails with links inside, in effect training their users
that clicking was safe. Although more carefully designed
awareness campaigns have been shown to have positive
effects,S2 these effects are likely to be of a much lesser
magnitude for targeted attacks, such as emails appear-
ing to come from known parties.
REFERENCES
S1. F. Stajano and P. Wilso, “Understanding scam
victims: Seven principles for systems security,”
Commun. ACM, vol. 54, no. 3, pp. 70–75, 2011. doi:
10.1145/1897852.1897872.
S2. S. Sheng, M. Holbrook, P. Kumaraguru, L. F. Cranor,
and J. Downs, “Who falls for phish? A demographic
analysis of phishing susceptibility and effectiveness
of interventions,” in Proc. SIGCHI Conf. Human Fac-
tors Computing Systems, 2010, pp. 373–382.
highly similar to legitimate messages, and they do not
contain keywords indicative of spam (such as Viagra),
nor do they contain high-volume URLs associated with
malicious behavior (such as a phishing URL). In other
words, today’s email filters simply do not block these
deceptive messages. Otherwise, based on their cur-
rent detection strategies, they would also have blocked
countless benevolent messages. Finally, it is known
that some security technologies adapt the rules based
on the actions of the recipient, thereby becoming less
likely to block emails of the types a recipient responds
to.3 This unfortunately weakens the protections of the
most vulnerable users. The problem is not that tradi-
tional security controls are flawed. Rather, they simply
do not address launchpad attacks.
September 2021

A BRIEF HISTORY OF ONLINE SOCIAL ENGINEERING:
THE RECENT YEARS
P hishing remained a substantial problem until the
deployment of Domain-Based Message Authenti-
cation, Reporting, and Conformance (DMARC)2 in 2012.
DMARC is a security control that combines digital
signatures with whitelists of approved servers to make
email spoofing detectable. With DMARC’s adoption still
being incomplete, spoofing is sometimes still possible.
The probably most famous examples—whether of
spoofing or phishing—relate to attacks associated with
the 2016 U.S. presidential election. S3 Despite a small
number of prominent spoofing attacks, DMARC has
been hugely successful, forcing many online criminals
to consider alternative approaches.
One prominent alternative has been Nigerian scams,
which gained prominence in the late 1990s and started
to be seen as a serious problem in the early 2000s.S4 Ini-
tially, Nigerian scams were directed mostly at consum-
ers and were not very sophisticated.S5 However, as the
scammers realized that their yield could be improved by
making their messages more plausible, various targeting
techniques were developed, with contexts ranging from
romanceS6 and rental scamsS7 to reshipping muleS8 and
Craigslist scams.S9
In approximately 2015, Nigerian scammers realized
that even greater profits could be reaped by modify-
ing their techniques and targeting companies. As a
result, business email compromise (BEC) was seeing a
meteoric rise in popularity. BEC is an attack in which a
criminal poses as a colleague of a victim, such as a chief
executive officer at a company, and requests sensitive
information or funds transfers. This has been a very suc-
cessfulS10 form of attack given that most people want to
help their colleagues and are prone to agree to requests
made by their bosses. Instead of spoofing emails, the
BEC attackers commonly use free webmail accounts
with strategically selected usernames (i.e., those match-
ing the impersonated person). In the past few years,
security controls that detect such impersonation have
Turning now to the human recipients of the decep-
tive emails, we note that the contents are not unex-
pected (e.g., nobody is claiming that an unknown rela-
tive of the target user has died and that the target user
www.computer.org/computingedge
SOCIOTECHNICAL SECURITY AND PRIVACY
been developed and deployed, again forcing criminals to
consider where to go next, thereby propelling the growth
of launchpad attacks.
REFERENCES
S3. B. Krebs, “Russian ‘Dukes’ of hackers pounce on
Trump win,” Krebs on Security, Nov. 16, 2016. [On-
line]. Available: https://krebsonsecurity.com/2016/11
/russian-dukes-of-hackers-pounce-on-trump-win/
S4. J. Buchanan and A. J. Grant, “Investigating and
prosecuting Nigerian fraud,” United States Attor-
neys’ Bulletin, vol. 49, no. 6, pp. 39–47, 2001.
S5. C. Herley, “Why do Nigerian scammers say they
are from Nigeria?” Microsoft Research, June 2012.
[Online]. Available: https://www.microsoft.com
/en-us/research/wp-content/uploads/2016/02
/WhyFromNigeria.pdf
S6. A. Rege, “What’s love got to do with it? Exploring
online dating scams and identity fraud,” Int. J. Cyber
Criminology, vol. 3, no. 2, pp. 494–512, July–Dec. 2009.
S7. Y. Park, D. McCoy, and E. Shi, “Understanding craig-
slist rental scams,” in Financial Cryptography and
Data Security—20th Int. Conf., FC 2016, Revised
Selected Papers, vol. 9603 LNCS. Berlin: Springer
Verlag, 2016, pp. 3–21. doi: 10.1007/978-3-662
-54970-4_1.
S8 S. Hao et al., “Drops for stuff: An analysis of reship-
ping mule scams,” in Proc. 22nd ACM SIGSAC Conf.
Computer and Communications Security, 2015, pp.
1081–1092.
S9. Y. Park ,J. Jones, D. McCoy, E. Shi, and M. Jako-
bsson, “Scambaiter: Understanding targeted Nige-
rian scams on Craigslist,” in Proc. Annual Network
and Distributed System Security Symp. (NDSS), San
Diego, California, 2014. [Online]. Available: https:
//dblp.org/rec/bib/conf/ndss/ParkJMSJ14
S10. Federal Bureau of Investigation, “Business e-mail
compromise: The 12 billion dollar scam,” Internet
Crime Complaint Center, July 12, 2018. [Online]. Avail-
able: https://www.ic3.gov/media/2018/180712.aspx
has inherited vast fortunes). Instead, the email mes-
sages are mostly business as usual and sometimes
even expected. This logical fit is made possible by
the criminal’s use of detailed contextual information
27
SOCIOTECHNICAL SECURITY AND PRIVACY
for the targeting of the intended victims, in terms of
crafting the deceptive messages and what accounts
these are sent from. Indeed, it has been shown4 that
the success rate of deceptive emails can be increased
from single-digit percentages to more than 70% by
using contextual information for targeting.
THE BUILDING BLOCKS TO DETECT
LAUNCHPAD ATTACKS
To understand the attack and how to counter it, it is
not sufficient to understand how existing countermea-
sures are circumvented, whether these are computa-
tional or psychological. It is critical to also understand
the behavior of a successful attacker. Launchpad
attacks always start with information collection. At the
EVERY TIME A USER CLICKS ON AN
ARTIFACT REFERENCE TO LOAD
THE CORRESPONDING ARTIFACT,
THE SYSTEM CHARACTERIZES THE
REQUESTER IN TERMS OF THREE
DIMENSIONS: DEVICE, ENVIRONMENT,
AND AUTOMATION.
heart of the problem is that traditional security controls
do not identify from where (i.e., what locations or what
computers) actions are initiated and, therefore, do not
detect when an attacker rummages through the mail-
box of a launchpad user to identify suitable target vic-
tims or when the attacker remotely sends emails from
the launchpad user’s account. We describe an approach
that addresses this problem, based on tracking the
access to artifacts. By artifacts, we mean attachments
(such as invoices and purchase orders) and URLs. For
concreteness, we focus on attachments here.
Step 1: Replace Artifacts With Links
The security system scans incoming and outgo-
ing emails of protected users, detects artifacts in
these emails, and replaces them with references to
cloud-hosted copies of the artifacts. In this way, the
messages in the mailbox of a protected user will not
have artifacts but instead will have links to cloud-hosted
copies of these. For the same reason, an email from a
protected user in the mailbox of its recipient will also
28 ComputingEdge
not have artifacts. The system can to a very large extent
maintain the visual appearance of the modified emails
(e.g., by replacing an attached document with a hyper-
linked image that appears like the thumbprint of the
attached document). When a user interacts with a ref-
erence to a removed artifact (e.g., by double-clicking
on the thumbprint representing the artifact), a request
is made for the cloud-hosted artifact. However, before
this is served, the system characterizes the requester.
Step 2: Characterize Requesters
Every time a user clicks on an artifact reference to
load the corresponding artifact, the system charac-
terizes the requester in terms of three dimensions:
device, environment, and automation. The device
identifier corresponds to a stored state (e.g., using
HTML cookies or flash cookies) and user agent infor-
mation (e.g., information relating to the operating
system, screen size, and application name and ver-
sion). The stored state of a given device may change
over time, but it typically does not undergo dramatic
changes. The environmental identifier corresponds to
information about the requester’s geographical and
service context, such as his or her geolocation, server
name, and carrier or Internet provider. Like the device
identifier, the environmental identifier may change—
but typically not in a dramatic manner and rarely at
the same time as the device identifier undergoes dra-
matic changes. A third identifier indicates the extent
to which automation was used for accessing an arti-
fact or sending an email. This can be determined from
script and application programming interface indi-
cations in the headers or from the timing of multiple
requests. Most email users never use automation.
Some (such as e-commerce email servers) always use
it. Very few email users switch back and forth.
A given user is associated with a profile, which cor-
responds to one or more sets of identifiers described
previously. As a new user is observed by the system, it
has no profile, but as the user request artifacts, the sys-
tem gradually builds a profile. An attacker is detected
and classified based on the types of mismatch that
result from his or her artifact access requests.
PUTTING EVERYTHING TOGETHER
The functionality of the system is perhaps best
described using an example. The transmission of an
September 2021
 SOCIOTECHNICAL SECURITY AND PRIVACY

Cloud Storage
email from sender S to recipient R
?
is described in Figure 1. At step 1, R =
a filter replaces artifact A with ref-
X = A
erence X and reports to the cloud
storage that A and X are associ-
(Step 2) A
ated with R. When a user asso- X
ciated with recipient R initiates A
a request for the artifact corre-
X
sponding to X, the cloud storage Sender S Recipient R
A X
characterizes the requestor (step R
2). If the characterization iden- Email Modified
(Step 1) Email
tifies a likely attack, the system
takes a security action. Otherwise,
it transmits artifact A to R. FIGURE 1. The transmission of an email with artifact A.
We will now consider an
attacker that corrupts a user to
use his or her account as a launch- Device ID Environmental ID Automation ID
pad in the attack against another Legit User Good Match Good Match Good Match
user. Let us start by assuming
Legit User, New Device Poor Match Good Match Good Match
that the launchpad victim is a
protected user. To collect intel- Phisher Poor Match Poor Match

ligence from the launchpad user, Remote Access Trojan Poor Match
the attacker accesses one or more Automated Forwarding Poor Match Poor Match Poor Match
attachments. Depending on the
manner in which the attacker has FIGURE 2. The extent to which the three types of identifiers—device, environmen-
gained access to the launchpad tal, and automation—would typically be matched in a variety of scenarios.
user’s account, the profile match-
ing generates different results, as
shown in Figure 2. Green corresponds to a likely good the attacker’s computer. Therefore, the device match
match, while red corresponds to a likely poor match. will be poor. Moreover, the attacker is also likely to
(For the white fields, the match depends on the level of be associated with a different environment, making
sophistication of the attacker.) that match poor as well. If the attacker uses a script
Consider the various cases shown in Figure 2. The to request and render attachments, this will show
legitimate user is expected to have a very high degree up as an anomaly related to automation. The same
of match. A legitimate user on a new device would kinds of mismatches will also be observed—without
naturally have new device identifiers and would trig- any interaction between the attacker and the cloud
ger a verification. A phisher gaining access to a user’s server—when the attacker uses the launchpad user’s
account after having stolen the user’s password would email account to send email to intended targets. In
typically be very easily distinguished from a legitimate other words, indicators similar to those that can be
user. A remote access Trojan could be more difficult observed when a user makes artifact requests will also
to detect, as it involves a compromised device of the be automatically encoded in the headers of the emails
legitimate user. An automated forwarding rule, on the that this user sends.
other hand, is very easy to detect.
If we assume that the attacker has stolen the Step 3: Reacting to an Attack
launchpad user’s password (e.g., the attacker is a For each artifact request, the system computes a risk
phisher), then the attacker will not access the email score that depends on the three types of identifiers
account from the launchpad user’s computer but from and on the profile of the legitimate user. The score also

www.computer.org/computingedge 29
SOCIOTECHNICAL SECURITY AND PRIVACY
depends on the number of artifacts requested from
this party, the pattern of requests (such as the inter-
arrival times of the requests and whether they appear
to correspond to a particular search term), and the his-
torical request patterns associated with the profile.
If the risk score is low, access is permitted, and the
requested artifact is transmitted to the requester. If
the risk score is intermediate, the system may request
additional authentication, such as two-factor authen-
tication, before transmitting the requested artifact to
the requester. Finally, if the risk score is high, the sys-
tem may respond with a synthetic artifact, that is, a
modification of the original artifact or an automati-
cally generated replacement. Moreover, the system
may notify affected users. Any email sent by an identi-
fied attacker from the launchpad account to contacts
of the launchpad user may be blocked or augmented
with a warning.
T he approach we have described, as with all secu-
rity controls, is not a silver bullet. The degree of
protection provided depends on the type of attack
used to compromise the launchpad accounts as well
as the sophistication of the attacker. That said, we
believe this approach can curb the rise of launchpad
IEEE COMPUTER SOCIETY
Call for Papers
30 ComputingEdge
attacks and help consumers and enterprises protect
themselves.
REFERENCES
1. Osterman Research, “Best practices for protecting
against phishing, ransomware and email fraud,” Black
Diamond, WA, White paper, 2018.
2. M. Moorehead, “How to explain DMARC in plain English,”
Return Path, July 20, 2015. [Online]. Available: https://blog
.returnpath.com/how-to-explain-dmarc-in-plain-english/
3. M. Jakobsson and T.-F. Yen, “How vulnerable are we to
scams?” Black Hat, 2015. [Online]. Available: https:
//www.blackhat.com/docs/us-15/materials/us-15
-Jakobsson-How-Vulnerable-Are-We-To-Scams-wp.pdf
4. T. N. Jagatic, N. A. Johnson, M. Jakobsson, and F.
Menczer, “Social phishing,” Commun. ACM, vol. 50, no.
10, pp. 94–100, 2007. doi: 10.1145/1290958.1290968.
MARKUS JAKOBSSON is the chief of security and data ana-
lytics at Amber Solutions. He is the founder of ZapFraud Inc.
His research interests include security, privacy, and abuse.
Jakobsson received a Ph.D. in computer science from the
University of California, San Diego. Contact him at us.expert
.witness@gmail.com.
Write for the IEEE Computer
Society’s authoritative
computing publications
and conferences.
GET PUBLISHED
www.computer.org/cfp
September 2021
 EDITOR: Gerard J. Holzmann, Nimble Research, gholzmann@acm.org
DEPARTMENT: RELIABLE CODE
Right Code
Gerard J. Holzmann
T
hese days, when you see the headline “How Safe
Are Airplanes?” the text more likely refers to the
spread of disease than the likelihood of a crash.
With steady safety improvements over at least the last
five decades, airplane crashes have become exceed-
ingly uncommon, and they are rarely caused by flaws
in the design of the airplane itself. The most common
remaining causes are the usual suspects of human
error, extreme weather events, and mechanical failure.
That perception of safety for air travel may have
changed with the recent crashes of two new Boeing
airplanes. The 737 MAX was introduced as a relatively
small upgrade in a long line of successful airplane
designs that, in this case, was primarily meant to
improve fuel efficiency.1 The cause—or, rather, the
causes—of the two crashes has been sufficiently
fleshed out by now, for instance, in the detailed con-
gressional report that was released in September
2020, “The Design, Development, and Certification
of the Boeing 737 MAX.”2 As the title of this report
indicates, the failures cannot be attributed to a single
mistake, but were found to have been caused by a
sequence of shortcuts and errors combined with a
lack of meaningful oversight by the U.S. Federal Avia-
tion Administration.
SOFTWARE PROCESS
The lack of rigor in the vetting of new or revised designs
has led to a series of problems, including in the develop-
ment of the CST-100 Starliner system, Boeing’s design
for a reusable crewed spacecraft. A serious test failure
of the Starliner craft in December 20193 was found in a
review by a NASA panel to have been caused by multi-
ple software bugs. The panel concluded, among many
other findings, that NASA should “go beyond merely
correcting the cause of the anomalies” and “scrutinize
Boeing’s entire software testing processes.”
Digital Object Identifier 10.1109/MS.2020.3028759
Date of current version: 22 December 2020
2469-7087/21 © 2021 IEEE Published by the IEEE Computer Society September 2021
This article originally
appeared in
vol. 38, no. 1, 2021
In a review like this, it is always tempting to try to
come up with a single remedy that should fix all prob-
lems. The NASA study team that is investigating the
issues may be leaning in that direction as well, with
a recommendation that all software from NASA con-
tractors would need to comply with a new restriction
on the cyclomatic complexity of functions.4 The cyclo-
matic complexity metric, which was popular for a while
in the 1980s, measures the number of independent
paths through the control flow graph of a function.
Would it not be great if one could indeed demonstrate
the existence of a correlation between cyclomatic
complexity and the postrelease fault density of func-
tions? Quite a few researchers have tried to look for
such an effect, but, alas, most have found that there is
no such correlation. So, is there no hope?
BUILDING RELIABLE SYSTEMS
In most disciplines, system reliability is achieved
through the judicious use of redundancy. Virtually all
spacecraft, for instance, have multiple ways of com-
municating with Earth, using independent transmit-
ters and receivers. Some spacecraft, such as the Cas-
sini spacecraft that orbited Saturn, are designed with
two separate main engines and two sets of thrusters
to avoid single points of failure that could end a mis-
sion prematurely.
To make data transmissions over noisy transmis-
sion channels more reliable, we can add redundant
information in the form of error-correcting codes so
that small bursts of errors are recoverable. The big
question is, of course, how we could do something
similar in software design. The answer is not to
merely duplicate a code base and then run it on two
computers. This may protect against hardware faults,
but it cannot do the same for the software. If there is
a bug in the code, the same bug will obviously affect
both executions, which then provides no protection
at all. This is also the scenario that led to the failure
of the maiden flight of the Ariane 5 launch system in
31
RELIABLE CODE
June 1996. 5 The same software was running on both
the main CPU and backup CPU, which meant that
a single floating-point exception error could crash
both, causing the costly loss of the vehicle.
Another method for using redundancy in the design
of software systems, called N-version programming,
was popular for a while, but it also failed to deliver the
promised increase in reliability. The thought was to
have multiple independent teams write software in
parallel and compare the results of the executions
of all systems to detect inconsistencies caused by
bugs. As Knight and Leveson 6 pointed out in the
late 1980s, all teams working on the design still
begin from a common set of requirements and are
likely to make similar types of mistakes. Splitting a
team into N subteams can also lead to an increase
in cost and loss of productivity as well as create
tension among them. That is, how does one avoid
cross contamination of key findings during develop-
ment, for example, if one team discovers significant
omissions in the design requirements all teams
work from?
SELF-CHECKING CODE
Although all of this sounds discouraging, there is, in
fact, an effective technique for using redundancy to
improve system reliability, although we often do not
think of it in quite that way. The method is to increase
the use of assertions throughout a code base. As many
software developers will tell you, these assertions are
redundant and can safely be removed after testing. Do
they help to improve reliability? The sobering news, at
least for those developers, is that it can be shown that
the number of assertions that are retained in the code
after testing correlates strongly with postrelease fault
density. More assertions means fewer faults. It is as
simple as that. This was first shown in a study done by
Microsoft researchers, who studied postrelease faults
in the Office suite of tools and compared it with the
assertion density of the failing code.7
For the mission code that is developed at NASA/
Jet Propulsion Laboratory, we require that the aver-
age assertion density for each module is 2% or more.
This means that 2% of the code performs self-checks
at key steps in the computations performed to make
sure that integrity is maintained, even in anomalous
execution scenarios. The use of assertions thus
32 ComputingEdge
provides a form of software redundancy that can
indeed make a system more reliable.
WHAT ABOUT TESTING?
I have not mentioned testing in the discussion of reli-
ability so far. Some say that, since the cyclomatic com-
plexity metric measures the number of paths in the
control-flow graph of a function, this gives the num-
ber of tests that are required to test all of those paths.
Fewer required tests should, then, make it possible to
test code more rigorously. This ignores, though, the
fact that most of the complexity in a program execution
does not originate in the structure of the control-flow
graph but in the data that are processed. A single path
in the control-flow graph can be executed in an astro-
nomical number of different ways, which means that a
single test of each path in the control-flow graph has
little chance of revealing all of the bugs that may hide
on that path.
A function with a lower cyclomatic complex-
ity does not necessarily require fewer tests to vet
thoroughly. All code is written to satisfy some set of
requirements and provide a desired functionality. We
can spread that functionality across multiple modules
and functions to create a large assembly of intercon-
nected and mutually dependent small functions, but
that will rarely be the right way to structure the code,
and neither will it be able to simplify testing.
REQUIREMENTS TESTING
To put it most succinctly: tests should not be derived
from the structure of a control-flow graph but from
the requirements that prompted the creation of the
code. To check if a requirement is met, the tester or
developer should define a suite of tests that can eval-
uate the adequacy of the code to handle a range of
cases, including expected cases, boundary cases, and
even cases that outright violate the design assump-
tions. If, after running that suite of tests for all require-
ments, it turns out that parts of the code base were
not reached, this indicates a flaw in either the require-
ments or in the code. The most common situation is
that the requirements are found to be incomplete
and fail to cover things that the code must be able to
handle. It can, however, also be that the code itself is
redundant and that parts of it serve no legitimate pur-
pose to satisfy the requirements.
September 2021

Code coverage metrics serve to check the ade-
quacy of a test suite for a specific set of requirements.
Adding test cases to an existing test suite that serve
only to improve the coverage metric, without actually
testing anything, is common practice, but it cannot
improve a system’s reliability.
REFERENCES
1. M. R. Jacobson. “What’s wrong with Boeing?” Defense
One. https://www.defenseone.com/ideas/2019/11
/whats-wrong-boeing/161245/ (accessed Oct. 14, 2020).
2. “Boeing 737 MAX investigation,” U.S House of Repre-
sentatives, Washington, D.C. Accessed: Oct. 14, 2020.
[Online]. Available: https://transportation.house.gov
/committee-activity/boeing-737-max-investigation
3. J. Roulette. “Boeing’s botched Starliner test flirted with
‘catastrophic’ failure: NASA panel.” Reuters. https:
//www.reuters.com/article/us-space-exploration
-boeing/boeings-botched-starliner-test-flirted-with
-catastrophic-failure-nasa-panel-idUSKBN20106A
(accessed Oct. 14, 2020).
ADVERTISER INFORMATION
Advertising Coordinator
Debbie Sims
Email: dsims@computer.org
Phone: +1 714-816-2138 | Fax: +1 714-821-4010
Advertising Sales Contacts
Mid-Atlantic US:
Dawn Scoda
Email: dscoda@computer.org
Phone: +1 732-772-0160
Cell: +1 732-685-6068 | Fax: +1 732-772-0164
Southwest US, California:
Mike Hughes
Email: mikehughes@computer.org
Cell: +1 805-208-5882
Northeast, Europe, the Middle East and Africa:
David Schissler
Email: d.schissler@computer.org
Phone: +1 508-394-4026
www.computer.org/computingedge
RELIABLE CODE
4. T. J. McCabe, “A complexity measure,” IEEE Trans.
Softw. Eng., vol. 2, no. 4, pp. 308–320, Dec. 1976. doi:
10.1109/TSE.1976.233837.
5. J. L. Lions, “Ariane 5: Flight 501 failure,” 1996. [Online].
Available: http://sunnyday.mit.edu/nasa-class/Ariane5
-report.html
6. J. C. Knight and N. G. Leveson, “An experimental evalua-
tion of the assumption of independence in multi-version
programming,” IEEE Trans. Softw. Eng., vol. SE-12, no. 1,
pp. 96–109, 1986. doi: 10.1109/TSE.1986.6312924.
7. G. Kudrjavets, N. Nagappan, and T. Ball, “Assessing the
relationship between software assertions and faults:
an empirical investigation,” in Proc. 17th Int. Symp.
Softw. Rel. Eng. (ISSRE), Nov. 2006, pp. 204–212. doi:
10.1109/ISSRE.2006.14.
GERARD J. HOLZMANN is a consultant and
researcher at Nimble Research, Monrovia,
California, USA. Further information about
him can be found at http://spinroot.com
/gerard. Contact him at gholzmann@acm.org.
Central US, Northwest US, Southeast US, Asia/Pacific:
Eric Kincaid
Email: e.kincaid@computer.org
Phone: +1 214-553-8513 | Fax: +1 888-886-8599
Cell: +1 214-673-3742
Midwest US:
Dave Jones
Email: djones@computer.org
Phone: +1 708-442-5633 Fax: +1 888-886-8599
Cell: +1 708-624-9901
Jobs Board (West Coast and Asia), Classified Line Ads
Heather Bounadies
Email: hbuonadies@computer.org
Phone: +1 623-233-6575
Jobs Board (East Coast and Europe), SE Radio Podcast
Marie Thompson
Email: marie.thompson@computer.org
Phone: +1 714-813-5094
33
 DEPARTMENT: IT TRENDS This article originally
appeared in

vol. 22, no. 6, 2020

The 5G Revolution:
Expectations Versus Reality
Nura Jabagi, Concordia University
Andrew Park, Simon Fraser University
Jan Kietzmann, University of Victoria

In response to claims that 5G will “change the world,” 5G mobile communications systems
have drawn considerable attention, from consumers and practitioners, to policymakers and
academics. Amid mass-marketing campaigns and public posturing by early 5G pioneers
in the telecom industry, cutting through the hype to understand the actual implications
of this new technology is difficult. This article examines the differences between 5G
and earlier generations of wireless technology while debunking some of the myths and
misconceptions surrounding this new technology. It further discusses 5G’s potential
business applications, as well as the opportunities and challenges IT professionals and
general managers may face in incorporating 5G within their business operations.

A
fter years of hype surrounding the
lightning-fast speeds promised by this new
generation of mobile network technology, 5G
was finally introduced to the market in 2019. Yet, like
many new technologies, such as artificial intelligence
(AI) and blockchain, 5G has been labeled both as hype
and hope. On the one hand, the arrival of 5G has been
compared to past paradigm shifting technologies,
such as electricity and automobiles. Such bold claims
have bolstered expectations that 5G will usher in a
new era of similarly innovative applications, such as
fully immersive entertainment, autonomous vehicles,
and the Massive Internet of Things (MIoT`).1–3 Adding
to the hype, 5G is predicted to contribute an astound-
ing $13.2 trillion to the global economy by 2035.2,4
On the other hand, various industry experts and
academics have argued that the current hype sur-
rounding 5G is premature, particularly given the costs
associated with its implementation and the limited
range of viable use cases available in the short-term. 5
Digital Object Identifier 10.1109/MITP.2020.2972139
Date of current version 6 November 2020.
A key feature of 5G is that it utilizes millimeter-wave
technology to tap into the very high end of the wire-
less spectrum, where large amounts of bandwidth
remain unused. While millimeter-wave signals enable
faster network speeds, they are less reliable at long
distances and are more susceptible to blockage.6
Whereas a 4G tower can offer a range as far as 30
miles, a 5G tower can, on average, only offer a range of
less than half a mile.7 As a result, 5G networks require
a greater number of access points than 4G networks,
meaning that substantial investments are required
in entirely new infrastructures and technologies to
truly harness the revolutionary use cases, such as
self-driving cars and robotic telesurgery, envisioned
by 5G proponents.3,8 Beyond these costs, first- and
early-movers must navigate a plethora of technical,
organizational, regulatory, and social challenges in
deploying 5G technology. 2,9,10
In light of the differing viewpoints concerning 5G
technology, this article aims to provide managers
with a clear understanding of 5G, its benefits and
potential applications, while also debunking some
of the myths and misconceptions surrounding this
emergent technology. To better contextualize the 5G

34 September 2021 Published by the IEEE Computer Society  2469-7087/21 © 2021 IEEE

FIGURE 1. Evolution of wireless communication systems from first (1G) to fifth (5G) generation.
revolution, we begin with a brief timeline of the previ-
ous generations of mobile technology leading up to
the development of 5G. Next, we compare 5G with its
predecessors across its generation-defining features:
speed, bandwidth, and latency. We then review the use
cases and business opportunities that are enabled by
5G's enhanced capabilities, as well as the challenges
IT professionals and general managers are likely to
face in deciding whether and which 5G technologies
to incorporate within their business operations and
revenue models.
FIVE GENERATIONS OF
WIRELESS TECHNOLOGY
Since the arrival of the first-generation network in the
early 1980s, four subsequent generations of wireless
communication systems have been introduced. With
a new mobile generation emerging every decade, each
new generation has brought improved performance
and a wider range of capabilities compared to its pre-
decessor. The evolution from 1G to today's nascent 5G
technology is illustrated in Figure 1.
While the first mobile network generation (1G) was
strictly analog and only allowed voice calls, 2G was a
digital network and the first to provide data services
for mobile devices, including SMS and multimedia
www.computer.org/computingedge
IT TRENDS
messages.11 As pioneering technologies, both 1G and
2G networks improved the accessibility of voice com-
munications across much larger population bases.
Moreover, by enabling messaging services and offer-
ing incrementally faster speeds, 2G prompted the
mass-adoption of mobile phones on a scale never
before seen. From 2G to 4G, each successive mobile
network generation has focused on increasing speed
and efficiency to improve mobile experiences for
end-users.
Drawing on digital broadband technologies, 3G and
4G mobile networks offered advanced mobile data ser-
vices and introduced the mobile internet respectively.
While 3G gave rise to new services such as mobile TV,
video conferencing, and voice over IP (VOIP) services
like Skype, 4G enabled improved user experiences to
these services through its increased speeds, ability to
handle far greater data loads, and reductions in net-
work latency. Consequently, 4G allowed for near real
time, intensive data exchange between end-users and
ushered in an “anytime, anywhere, in anyway era” for
mobile network use.11,12
Over the last decade, faster and more responsive
data transfer capabilities have led innovators to
envision a range of new and revolutionary applica-
tions, such as the tactile internet, fully autonomous
35
IT TRENDS
vehicle fleets, and next-generation industrialization
including configurable factories and mobile robots.
Yet, despite massive performance improvements over
previous generations, today's 4G networks still lack
adequate throughput capacity, as well as sufficiently
low network latency to power these ambitious future
applications.13 Fortunately, a new generation of net-
work technology has arrived.
5G TECHNOLOGY: WHAT IS IT AND
HOW IS IT DIFFERENT?
Whereas the evolutions from 2G and 3G to 4G focused
on increasing data throughput and data transfer
speeds, as well as expanding mobile service areas
to support connectivity between users, today's
fifth-generation wireless technology offers more than
an incremental performance improvement over its
predecessor.5 Rather, 5G is an expansion of mobile
networking into new regulatory and technological
paradigms where 5G technologies are not only being
designed to enable interactions between users, but
also to support advanced user-to-machine interactions
and, most importantly, machine-to-machine interac-
tions.3,6 To support such ubiquitous connectivity, 5G
brings three new features to the table: unprecedented
levels of speed; significant reductions in latency; and
greatly expanded system capacity, allowing for the
simultaneous connections of many more devices.
Very High Data-transfer Speeds
The multigigabit speeds of 5G are due to more effi-
cient encoding and the use of high frequency
millimeter-waves not utilized by 4G networks.7 With
peak data rates expected to reach 20 Gbps, 5G tech-
nology promises to bring speeds 600 times faster than
the 4G LTE (i.e., Long Term Evolution, a network stan-
dard that offers slightly faster connection than a basic
4G connection) speeds seen in today's mobile phones.2
To put things into perspective, 5G users will be able
to download an entire movie of 2–3 gigabytes (GB) of
data in less time than it would have taken a 4G user
to download a 30-megabyte (MB) application. While
the current speeds attained by 4G are often sufficient
for the typical mobile user,5 5G's higher speeds bring
the potential for improved augmented reality (AR) and
virtual reality (VR) experiences when combined with
5G's very low latency. Moreover, 5G's gigabit speeds
36 ComputingEdge
will open the door to a wide range of new industrial
applications and opportunities to improve efficien-
cies within existing applications. For instance, experts
in the manufacturing industry envision putting video
cameras and sensors throughout factories to allow
for the real-time monitoring of product quality. Simi-
larly, if we imagine a world where wireless speeds can
exceed wired speeds, industries such as energy and
mining can “cut the cord” and move to more flexible
and autonomous operations in order to increase pro-
ductivity and reduce costs.14
Ultra-Low Latency
While telecommunications carriers and marketers
have focused their 5G messaging on high data speeds,
most technical experts argue that the true benefits of
5G derive from its reduced latency.10,13 As compared
with its predecessors, 5G has significantly lower net-
work latency, which allows it to deliver more instanta-
neous, real-time data. Where high latency connections
common today can cause web pages to load slowly,
and can affect user experiences in applications that
require real-time data exchange, the reduced latency
offered by 5G is expected to enable improved multi-
person video conferencing and gaming, as well as AR
and VR. Moreover, 5G's very low latency will be partic-
ularly important for a range of cutting-edge technol-
ogies and applications that require high responsive-
ness, such as fully autonomous vehicles and robotic
surgery. It is in these applications where the benefits
of 5G's reduced latency become apparent, by allow-
ing real-time remote control at scale and across dis-
tances, as well as across devices and services. With an
actual latency of around 50 ms, 4G networks are inca-
pable of providing autonomous vehicles with reflexes
comparable to the 2 ms decision-making speeds of
humans.15 In this context, the ultra-low latency of a 5G
network would allow for mobile technology to be used
more safely in autonomous vehicles.
Massive System Capacity
4G allowed for the introduction of more high-
bandwidth applications through improvements in
data transmissions speeds and network latency com-
pared to 3G. As such, 4G device penetration rates
increased between 2006 and 2016, as evidenced by
a 4000-fold increase in global data traffic.6 With 4G
September 2021

close to reaching the technical limits of how much
data it can transfer across blocks of the wireless
spectrum, 3 a new wireless technology is needed if
we are to continue our upward trajectory of improve-
ment of current mobile applications and the intro-
duction of new ones. 5G continues this momentum
through another one of its features: an expansion in
bandwidth which promises to significantly reduce
network congestion. Specifically, by relying on dif-
ferent radio frequencies from the ones used today by
4G, 5G is set to expand into a much broader range of
the wireless spectrum, allowing for greater network
capacity as well as increased flexibility and scalabil-
ity of new applications. Most notably, 5G is expected
to provide a 100-fold increase in traffic capacity as
compared to 4G, while supporting up to 1 million
connected devices per 0.38 square miles, as com-
pared to around 2000 connected devices with 4G. 2,6
Though enhanced bandwidth and connection density
will certainly benefit consumer end-users, the true
benefit of 5G's massive capacity and connectivity
improvements lie in its ability to create a truly inter-
connected world.
HOW WILL 5G BE USED?
A common misconception, particularly among the
general public, is that 5G will only really impact the
telecommunications industry. As we have begun to
demonstrate, this is only part of the story. Rather, 5G
is a General Purpose Technology (GPT) that, through
continuous improvements over time, will come to be
widely adopted and offer a vast range of uses and
technological complementarities. Through their pro-
liferation across multiple industries, GPTs are innova-
tion catalysts that lead to transformational, and often
disruptive, changes that reach beyond industries, to
impact entire economies and societies.4
In building on earlier mobile technologies, 5G is
expected to bring about new classes of advanced
applications, promote business innovation, and drive
economic growth.4 Though a universal set of speci-
fications defining 5G is still under development, 5G
technology is being purpose-built to support three
classes of services: enhanced mobile broadband
(eMBB); the Massive Internet of Things (MIoT); and
mission-critical services (MCS).2 We now briefly dis-
cuss select potential use cases within each of these
www.computer.org/computingedge
IT TRENDS
service classes. In doing so, we highlight the key 5G
capabilities supporting these service classes.
Enhanced Mobile Broadband
As the first commercial application of 5G, eMBB is
centered on driving efficiencies at the core network
level to pave the way for greater data consumption
through a lower cost-per-bit for data and enhanced
user experiences.3 The increased use of broadband
applications on mobile networks will be driven by 5G's
improved speeds, latency, and bandwidth, as well as
the promise of ubiquitous coverage and energy effi-
ciency to address the high-power consumption rates
that have hindered 4G-driven technologies.2,3 Envi-
sioned eMBB applications include: improved outdoor
wireless broadband; ultrahigh definition or UHD (4K
and 8K) broadcast and mobile streaming; 3D multi-
player gaming; and virtual meetings with 360° video
and even real-time language translation. 5G is also
expected to enable a range of new VR/AR applica-
tions, including: virtual dressing rooms; augmented
reality for physical therapy; and fully immersive enter-
tainment experiences in 100 000 seat venues using
5G-backed hotspots that are characterized by very
high user-density and traffic capacity but that have
low mobility requirements. eMBB use cases are those
most likely to have near-term economic and social
impacts as eMBB applications are mostly likely to be
incremental improvements of existing 4G use cases.4
MASSIVE INTERNET OF THINGS
Although the introduction of 4G made IoT possi-
ble, device-to-device applications have generally
remained limited due to the inability of these networks
to reliably handle simultaneous connections. With its
high connection density, 5G technology is set to spur
the evolution from today's Machine Type Commu-
nication (MTC) paradigm towards Massive Machine
Type Communication (mMTC), a paradigm more com-
monly known as the Massive Internet of Things (MIot).
Enabled by inexpensive, long-life modules with con-
stant connectivity, MIoT applications are being devel-
oped across a wide array of industries with use cases
including: in-store beacon technology to support
proximity marketing and connected shopping expe-
riences (e.g., iBeacon); precision agriculture; smart
metering in the utilities sector; and remote industrial
37
IT TRENDS
monitoring. On a broader scale, mMTC has the poten-
tial to dramatically impact our daily lives via the devel-
opment of “smart cities.” Building on earlier IoT appli-
cations, MIoT use cases are likely to experience wider
consumer uptake in the near to mid-term.3,4 Given its
low power requirements, uniform coverage, capacity,
and robustness to connect up to 100 times the num-
ber of devices per unit area as compared to 4G, 5G is
expected to bring substantial economies of scale to
MIoT applications that will drive adoption across all
sectors. Through their widescale proliferation, experts
predict that MIoT use cases will showcase the truly
transformative impact of 5G.4
Mission Critical Services
Mission-critical services refer to applications that
require high reliability and ultra-low latency in data
transfer. Otherwise known as ultra-reliable and
low-latency communications, examples of possi-
ble 5G mission-critical services include: fully autono-
mous vehicles; smart grids and the remote control of
critical infrastructures; many drone applications; and
medical applications, such as remote patient moni-
toring and telemedicine. Contrary to MIoT use cases
that are characterized by a very large number of con-
nected devices typically transmitting a relatively low
volume of nondelay-sensitive data, MCS use cases
involve the transmission large volumes of data where a
high-latency connection and/or a loss in connectivity
could have serious, potentially life-threatening, con-
sequences. With near-zero latencies and network reli-
ability of 99.999% uptime as key minimum technical
requirements,3,16 5G has the potential to enable a wide
range of MCS applications that can transform indus-
tries and entire economies. That being said, MCS have
strong security requirements, and most applications
are still considered nascent. Experts predict that while
the potential impact from 5G-enabled MCS use cases
stands to be profound, MCS growth will take longer to
gain traction than eMBB and MIoT applications.4
5G REALITY CHECK
Like many technologists, we are hopeful about 5G's
transformative potential. Nevertheless, we also
believe that much of the early hype surrounding 5G is
premature. First, it bears noting that although the four
major U.S. carriers have all recently announced some
38 ComputingEdge
form of a 5G offering, network coverage is still heav-
ily limited.5 Moreover, all 5G devices to be launched
over the next year are set to rely on existing 4G infra-
structures, a situation known as a “non-standalone”
network (NSA), until telecoms implement a stand-
alone network.7 Given that 5G phones are expected
to cost substantially more than current 4G phones
and are likely to become outdated quickly as stan-
dards coalesce and the technology is improved, 5G
smartphones (and other devices) are not expected to
become mainstream for at least a few years.
Second, because many MIoT and MCS use cases
will require a wireless spectrum range far greater than
those offered by today's 4G networks, a 5G standalone
(SA) spectrum range will likely need to be available
before many of the new capabilities of 5G will be
brought to bear.5 Relatedly, given that requirements
for 5G use cases will differ both within and across
service classes, there may be complications in allocat-
ing the appropriate network resources for each use
case, which today is achieved through the creation of
private networks or segmenting portions of the wire-
less network for groups of users.3 Although network
segmenting, or slicing, is already a common practice
in 4G, 5G slicing is expected to be significantly more
complex and challenging due to its unknown behavior
and higher data throughput. Thus, similar to the pat-
terns seen historically in the adoption of previous
mobile generations, we do not expect 5G to become
ubiquitous for at least several years.
Managerial Challenges
And Considerations
Due to the lack of real-world 5G applications currently,
Gartner has recently placed 5G services at the “Peak of
Inflated Expectations” in its 2019 Hype Cycle for Enter-
prise Networking.5 Where Gartner considers 5G to be
five to ten years away from mainstream adoption,5 a
key challenge facing business and IT managers will be
in identifying which 5G use cases present feasible and
valuable business opportunities in the near-term while
simultaneously preparing for profitable long-term use
cases. Moreover, organizations must also be aware of
the risks and challenges associated with the adoption
of 5G technologies and innovations.
To help organizations meet this challenge, we
suggest that managers make use of Iansiti and
September 2021
 IT TRENDS

Lahani's adoption framework.17

Initially developed to evaluate
another well-known GPT, namely
Blockchain, Iansiti and Lahani's
framework encourages executives
to evaluate foundational technolo-
gies along two dimensions. The
first dimension, novelty, refers to
the extent to which an application
is considered new. Where highly
novel innovations require more
effort for users to understand
what problem an innovation
solves,17 novelty plays a key role
in the adoption process through
its impact on stakeholders’ com-
mitment to change.18 The second
dimension, complexity, refers to
the amount of ecosystem coordi-
nation required to produce value FIGURE 2. 5G adoption framework based on Iansiti and Lahani.17
from the innovation. Measured
by the number and heterogeneity
of parties that are needed to collaborate, complexity of 5G to support remote collaboration through group
plays a key role in the adoption process through its web-conferencing which remains underutilized due
impacts on the structural readiness of the ecosys- to speed and bandwidth constraints of 4G networks.
17
tem. Using these two contextual dimensions, Iansiti Localization use cases are innovations that are
and Lahani generate a two-by-two matrix with four high in novelty, while being low in complexity. To the
quadrants each representing a specific stage in tech- extent that localization cases require minimal coordi-
nology development. We now apply this framework nation between end-users and ecosystem partners,
(see Figure 2) to demonstrate how IT professionals and they present attractive opportunities for managers
general managers can better inform their investment to generate immediate business value. Accordingly,
decisions in 5G technology. where such applications are relevant to their busi-
Single use cases are highly focused applications ness’ operations and revenue model, managers should
aimed at improving the performance and efficiencies consider 5G localization cases after single-use cases.
of existing solutions. Many eMBB applications fall Within this category, we argue that various VR and AR
under this category as they are use cases that offer applications designed for one or a few users are good
incremental improvements over existing 4G-enabled candidates for viable, localized use cases. For example,
services and offerings. Although single use cases are the development of AR training tools (such as those
not disruptive, and do not stand to offer far-reaching emerging to train surgeons) would require minimal
impacts, they are the least difficult to adopt because inputs from, and collaboration with, ecosystem play-
they present minimal risk. Insofar as single use cases ers. The only requirement would be for end-users to
require little coordination with third-parties, invest- purchase the product and/or devices required to use
ment costs may also be reduced. As a result, single the application.
use cases that can provide incremental performance Substitution use cases build on existing single
improvements in data transfer and connectivity are an use and localized applications to bring solutions that
ideal place for managers to start integrating 5G tech- are relatively low in novelty but that aim to replace
nology. A viable, single use case would be the adoption entire systems and business processes. Substitution

www.computer.org/computingedge 39
IT TRENDS
applications involve broad, and often public, use cases
that require a high level of coordination among ecosys-
tem participants. An example of a substitution case is
in-vehicle infotainment (IVI). Following advances in
computing power and display technologies in the early
2000s, localized use cases of in-vehicle infotainment
became possible; early IVIs included touchscreen
displays to play music and to use GPS navigation
assistance. Today, 5G offers an opportunity to extend
mature IVIs to include applications such as in-car mar-
keting, in-car 5G streaming, and AR/VR-augmented
navigation systems.19 While these applications are rel-
atively low in novelty, they require coordination across
car manufacturers, as well as a range of service provid-
ers and vendors. Moreover, IVI systems must comply
with laws and safety regulations that can differ across
markets. Given their scope and complexity, business
managers should approach substitution cases with
caution. Careful planning and strong change manage-
ment strategies are necessary when developing and
implementing substitute applications as “existing
solutions may be difficult to dislodge.”17
Transformation use cases involve applications that
are both high in novelty and complexity. Where suc-
cessful, transformation use cases have the potential
to bring about fundamental economic, political, and
social change. Smart highways are a notable example
of a transformative use case. By allowing for the inte-
gration of self-driving cars and sensors, along with
technologies such as solar panels to generate power,
dynamic digital signage, and structural maintenance
monitoring systems, smart roads can dramatically
transform the transportation sector. Despite their
potential to deliver tremendous value, transformation
use cases, such as smart highways, require extensive
coordination between a vast array of ecosystem play-
ers, such as regulators and infrastructure developers.
As such, transformation use cases will take substan-
tially longer to realize and gain market traction than
single use and localization use cases. Thus, similar to
substitution applications, we recommend that IT pro-
fessionals and general managers consider transforma-
tion use cases very carefully. Certainly, early prepara-
tion can enable forward-thinking organizations to
leverage transformation use cases to create new, and
potentially disruptive, business models. Neverthe-
less, first-movers must be prepared to weather high
40 ComputingEdge
uncertainty while orchestrating a range of ecosystem
players with potentially competing objectives and a
lack of understanding of the new technology.
CONCLUSION
As we enter into the next generation of mobile net-
works, 5G represents an important “inflection point”
from consumer to industry applications,3 where
advanced user-to-machine and machine-to-machine
interactions are set to revolutionize the way we live
and work. In the years it will take for a widescale
adoption, we will likely see more providers praise 5G
as a “silver bullet.” We urge IT professionals and gen-
eral managers to be critical of the hyped expecta-
tions and focus instead on the reality of how very high
data-transfer speeds, ultra-low latency, and massive
system capacity can actually offer opportunities for
single use cases, localization, substitution, or trans-
formation of their businesses.
REFERENCES
1. D. Rosenberg, “How 5G will change the world,” World
Economic Forum, 2018. Accessed: Jan. 15, 2020.
[Online]. Available: https://www.weforum.org/agenda
/2018/01/the-world-is-about-to-become-even-more
-interconnected-here-s-how/
2. Qualcomm Technologies, Inc., “Everything you need to
know about 5G,” 2019. Accessed: Jan. 15, 2020. [Online].
Available: https://www.qualcomm.com/invention/5g
/what-is-5g
3. S. Fulton III, “What is 5G? The business guide to
next-generation wireless technology,” ZD Net, 2019.
Accessed: Jan. 19, 2020. [Online]. Available: https:
//www.zdnet.com/article/what-is-5g-the-business
-guide-to-next-generation-wireless-technology/
4. K. Campbell, D. J. B. Flanagan, B. O’Neil, and F. Sideco,
“The 5G economy: How 5G technology will contribute
to the global economy,” IHS Econ. IHS Technol., IHS
Markit, London, U.K., 2017.
5. A. Lerner and D. Young, “Hype cycle for enterprise
networking,” Gartner Inc., Stamford, CT, USA (ID
G00377401), 2019.
6. Making 5G NR a Reality. San Diego, CA, USA: Qual-
comm Technol. Inc., 2016.
7. S. Segan, “What is 5G?” PC Mag, 2020. Accessed: Jan.
15, 2020. [Online]. Available: https://www.pcmag.com
/news/what-is-5g
September 2021
 IT TRENDS

8. K. Finley, “ The WIRED guide to 5G ,” Wired, 2019.
Accessed: Jan. 15, 2020. [Online]. Available: https:
//www.wired.com/story/wired-guide-5g/
9. S. Li, L. Da Xu, and S. Zhao, “ 5G internet of things: A
survey,” J. Ind. Inf. Integr., vol. 10, pp. 1 – 9, 2018 .
10. D. O’Halloran, “ What you need to know about 5G ,”
World Economic Forum, 2019. Accessed: Jan. 17, 2020.
[Online]. Available: https://www.weforum.org/agenda
/2019/12/what-you-need-to-know-about-5g/
11. Techworld, “A timeline of 5G development: From 1979
to Now,” Int. Data Group (IDG), 2019. Accessed: Jan. 17,
2020. [Online]. Available: https://www.techworld.com
/picture-gallery/tech-innovation/timeline-of-5g
-development-3654794/
12. E. Ezhilarasan and M. Dinakaran, “A review on mobile
technologies: 3G, 4G, and 5G ,” in Proc. IEEE Conf.
Recent Trends Challenges Comput. Models, 2017, pp.
369 –373.
13. J. Edwards, “ 5G versus 4G: How speed, latency and
application support differ,” CIO, 2019. Accessed: Jan.
17, 2020. [Online]. Available: https://www.cio.com
/article/3491393/5g-versus-4g-how-speed-latency
-and-application-support-differ.html
14. Ericsson, “A case study on automation in mining | 5G
value,” 2018 . [Online]. Available: https://www.ericsson
.com/en/reports-and-papers/consumerlab/reports
NURA JABAGI is currently a Ph.D. candidate in business
technology management with the John Molson School
of Business, Concordia University, Canada. Her research
interests include the digital economy and understanding
how technological advances coupled with macroeconomic
trends are disrupting industries, businesses, and jobs. She
is the corresponding author of this article. Contact her at
n_ jaba@jmsb.concordia.ca .
ANDREW PARK is currently a Ph.D. candidate with the Beedie
School of Business, Simon Fraser University, Vancouver, BC,
Canada. His research interests include innovation and tech-
nology management. Contact him at andrew_park@sfu.ca .
JAN KIETZMANN is an associate professor in Management
Information Systems, University of Victoria, BC, Canada.
His research interests include organizational and social
perspectives related to emerging technologies. He received
the Ph.D. degree in innovation and information systems from
London School of Economics and is an associate editor for
Business Horizons. Contact him at jkietzma@uvic.ca .

Cutting Edge
/a-case-study-on-automation-in-mining
15. M.-A. Russon, “ Will 5G be necessary for self-driving
stay
cars? ” BBC News, 2018 . Accessed: Jan. 27, 2020.
[Online]. Available: https://www.bbc.com/news on the

of Artificial Intelligence
/business-45048264
16. K. Mendis and F. Li, “Achieving ultra reliable commu-
nication in 5G networks: A dependability perspective
availability analysis in the space domain,” IEEE Com-
J a n ua ry/ f E b r ua ry 2 016

IEEE Intelligent Systems provides peer-

IEEE

mun. Lett., vol. 21, no. 9, pp. 2057–2060, Sep. 2017. Also in this issue:
aI’s 10 to Watch
real-Time Taxi Dispatching
56
68
IEEE
January/FEBruary 2016

from flu Trends to Cybersecurity 84

17. M. Iansiti and K. Lakhani, “ The truth about block- P U T T I N G A I I N T O P R A C T I C E

reviewed, cutting-edge articles on the

chain ,” Harvard Bus. Rev., vol. 95, no. 1, pp. 118 –127,
theory and applications of systems
Online BehAviOrAl AnAlysis

2017.
that perceive, reason, learn, and
18. C. Shea , S. Jacobs, D. Esserman, K. Bruce, and B.
Weiner, “Organizational readiness for implement- act intelligently.
VOLuME 31
nuMBEr 1

www.computer.org/intelligent

ing change: A psychometric assessment of a new

IS-31-01-C1 Cover-1 January 11, 2016 6:06 PM

measure,” Implementation Sci., vol. 149, no. 7, pp. 1 –15,

2014.
19. E. Pasqua , “ The leading 5G IoT use cases,” IOT Analyt- The #1 AI Magazine
ics, 2019. Accessed: Jan. 28, 2020. [Online]. Available: www.computer.org/intelligent
IEEE

https://iot-analytics.com/the-leading-5g-iot-use
-cases-2019/

www.computer.org/computingedge 41
 EDITORS: Volodymyr Kindratenko, kindr@ncsa.uiuc.edu
Anne Elster, anne.elster@gmail.com
DEPARTMENT: NOVEL ARCHITECTURES
High-Level Synthesis-Based
Approach for Accelerating Scientific
Codes on FPGAs
Ramshankar Venkatakrishnan, Ashish Misra, and Volodymyr Kindratenko,
National Center for Supercomputing Applications (NCSA), University of Illinois
T
raditionally, hardware description Languages
(HDLs), such as Verilog or VHDL, have been
used for programming Field-Programmable
Gate Arrays (FPGAs). However, this approach requires
an advanced knowledge of digital design and computer
architecture. Recently emerged high-level design
tools make it easier for the programmers to code
complex designs in C/C++. High-level synthesis (HLS)1
and OpenCL2 are the two leading high-level design
platforms that are becoming widely used for program-
ming FPGAs. Their proponents claim that these tools
require little to no knowledge of the hardware design
principles and can significantly improve developer's
productivity. In this article, we explore these two
high-level design approaches from the point of view of
a software developer. We use Xilinx Vivado HLS C/C++
ver. 2019.13 and Xilinx SDAccel OpenCL ver. 2019.14 to
implement a cross-correlation operation from scratch
and synthesize it for a Xilinx u250 Alveo FPGA board.5
The selected operation is at the core of convolutional
neural networks and is generally nontrivial to imple-
ment using a traditional HDL methodology, but is
rather simple to implement using a programming lan-
guage, such as C. We opted not to focus on the design
optimization, but rather getting a design that works
on the FPGA with the minimal time spent on its imple-
mentation. We use the Xilinx SDAccel platform that
provides support for implementing both OpenCL- and
HLS-based kernels to run on an FPGA using OpenCL
drivers on the host platform. We also took note of how
Digital Object Identifier 10.1109/MCSE.2020.2996072
Date of current version 19 June 2020.
42 September 2021 Published by the IEEE Computer Society 
This article originally
appeared in
vol. 22, no. 4, 2020
capable each tool is in terms of optimization, without
using tool-specific attributes or pragmas, as well as
how well it utilizes the available hardware. We find
that HLS tools are easy to learn and the time to design
is much shorter compared to the HDL approach.
However, a good knowledge of digital design and the
underlying FPGA architecture is still needed to deliver
a high-performance implementation.
OVERVIEW OF THE TOOLS
The OpenCL kernel was implemented using the Xilinx
SDAccel environment and the C-based HLS kernel was
implemented in Xilinx Vivado HLS, and then brought
into the SDAccel environment to integrate with the
host side of the application.
Xilinx Vivado HLS
The Vivado HLS compiler is used to convert code
written in C/C++ or SystemC into a register transfer
level (RTL) representation, which can then be synthe-
sized to run on an FPGA. From the point of view of the
end-user, the HLS compiler is similar to other language
compilers that are available for application develop-
ment. This tool is simple to learn and use, as long as the
designer has a good knowledge of C or C++. The overall
design approach consists of the following steps.
1. Compile, execute, and debug the algorithm
written in C/C++.
2. Synthesize the C/C++ algorithm into an RTL
implementation, optionally using user-guided
optimization directives.
3. Generate comprehensive reports and analyze
the design.
2469-7087/21 © 2021 IEEE

FIGURE 1. OpenCL kernel implementation.
4. Optimize the design to meet application
requirements.
5. Verify the Register Transfer Language (RTL)
implementation using a pushbutton flow.
6. Package the RTL implementation into a selec-
tion of Intellectual Property (IP) formats.
The last step is to package the RTL output files as
an IP core. There are three formats they can be packed
into depending upon the way in which the IP is going to
be used further in the design process. In our case, we
packed IP as a Vivado IP catalog format and exported
the generated .xo file into SDAccel. This .xo file, which
contains the actual kernel, will be integrated with the
OpenCL FPGA wrapper by the SDAccel tools and can
be loaded onto the FPGA from the code executed on
the host.
Xilinx SDAccel
The OpenCL-based design flow utilizes SDAccel, an
Eclipse-based integrated development environment.
We use C/C++ with OpenCL API calls for the host soft-
ware implementation, and OpenCL for hardware ker-
nel development. The host application is built through
using the standard gcc host compiler, and the FPGA
binary is built through a separate process that uses
www.computer.org/computingedge
NOVEL ARCHITECTURES
the Xilinx xocc compiler. The overall design approach
consists of the following steps.
1. Code the desired kernel in OpenCL.
2. Run software emulation to ensure functional
correctness.
3. Run hardware emulation to generate host and
kernel profiling data.
4. Optimize kernel for performance using direc-
tives and code restructuring techniques.
5. Run hardware synthesis to generate the FPGA
kernel bit file.
6. Write host code using the OpenCL API to inter-
face with the kernel executed on the FPGA.
Note that nearly the same host code can be used
to interface with the FPGA kernel regardless of the way
the kernel was produced, as long as it was imported
into SDAccel. Therefore, we use the same host code to
test both our designs.
OpenCL IMPLEMENTATION
The source code of the cross-correlation kernel
implemented in OpenCL is shown in Figure 1. The
host code writes the data required by the kernel
into a memory bank on the FPGA board. The kernel
43
NOVEL ARCHITECTURES
code then performs the computation by accessing
the data from that memory. Once the kernel execu-
tion completes and the data are written back to the
FPGA-attached memory, the host code reads the
data back from the global memory and continues pro-
cessing as needed.
The input image, filter mask, and output image are
declared as global variables in our kernel. Along with
these variables, the image and mask dimensions are
also declared as function arguments. The values for
the function arguments are written into the global
memory by the host code and are read in during kernel
execution. The design consists of four nested loops
that are responsible for moving the mask across the
image horizontally and vertically. The design uses a
stride and padding equal to 1.
Compared to a straight OpenCL code, our kernel
uses one additional line of code, __attribute__((reqd_
work_group_size(1, 1, 1))), which specifies working size
of the kernel to be just one copy.
Once the host code and kernel code are created,
the next step is to build the application. The build
target can be chosen by the programmer. The SDAc-
cel provides three such targets: software emulation,
hardware emulation, and system. Our design was com-
piled and built using the system option targeting the
Xilinx u250 Alveo FPGA board. The SDAccel generates
reports that can be used to analyze the timing, latency,
and area information of a design.
From the timing information we can, for example,
verify that the estimated frequency is same as the
target frequency. The area information can be used to
further guide the optimization of the design.
VIVADO HLS
C/C++ IMPLEMENTATION
In the HLS implementation, the hardware kernel
is created in C/C++ using the Vivado HLS tool. The
optimization and performance validation are done
in HLS. The major difference between OpenCL and
Vivado HLS C/C++ kernel implementation is the
use of HLS pragmas instead of OpenCL attributes.
These pragmas are used to declare appropriate
interfaces for scalar and vector variables (see Fig-
ure 2). The kernel acts as an accelerator in SDAc-
cel and is required to be modeled using the guide-
lines provided by SDAccel. Interfaces are modeled
44 ComputingEdge
as Advanced eXtensible Interface (AXI) memory
interfaces and scalar parameters called by the value
are mapped to an AXI4-Lite interface. When creat-
ing interfaces, it is important to specify the depth of
the AXI ports––the wrong depth size will result in a
C/RTL simulation mismatch.
Once the kernel design is complete, the C simula-
tion tool can be used to verify the design. A simple
testbench can be written to run the C simulation.
Once the functionality of the design is verified, the C
Synthesis tool is used to synthesize the design to an
RTL implementation. A top-level function is required
in the tool. The C Synthesis tools have several options
to make this simpler, such as echoing the progress of
the synthesis project to console and a GUI interface
that provides enhanced information hyperlinks in the
output messages, which provide more information on
the source of design issues and how to resolve them.
When synthesis is complete, a report for the top-level
function is generated. The report provides details
on both the performance and the area of the RTL
design and can be used to guide further performance
optimizations.
After successfully synthesizing the design, the
next step is to verify if the RTL is correct. This is done
using the C/RTL co-simulation tool. When the verifica-
tion completes, the last step in the Vivado HLS design
flow is to package the RTL output as an IP. This is done
using the Export RTL tool that packages the RTL as a
Xilinx object (.xo) file that can then be included in the
SDAccel project. Thus, when creating a new project in
the Vivado HLS, it is important to select the SDAccel
Bottom Up Flow option, which allows one to run HLS
kernels in SDAccel. A host code similar to the one used
in the OpenCL implementation can be used to run the
HLS kernel on the FPGA.
DISCUSSION
We have shown how to implement the cross-correlation
operation with the two programming frameworks. The
biggest challenge was to learn how to use the tools and
how to implement a host code using API calls for cre-
ating platforms, attributes, and contexts for executing
a kernel on the FPGA hardware. The design tools are
rather complex and the code implementation method-
ology is tailored more toward hardware designers that
software programmers.
September 2021

FIGURE 2. HLS C kernel implementation.
The kernel code very closely resembles the origi-
nal C code, with some additional directives for guid-
ing the compiler to properly implement the intended
design. However, the kernels we have implemented
were not optimized, and only basic attributes or prag-
mas were applied to enable proper functionality. Our
OpenCL implementation consists of 29 lines of kernel
code and 131 lines of host code, whereas the HLS
kernel consists of 40 lines of kernel code and 154 lines
of host code. (Our host code also included a CPU ver-
sion of the kernel for verification.) Compared with a
traditional CPU-only implementation, this is a similar
code size.
A typical compilation time to generate the com-
plete FPGA design even for such a small kernel is well
over three hours on a multicore system where multiple
cores are used by the Xilinx tools. This is, of course, a
www.computer.org/computingedge
NOVEL ARCHITECTURES
significantly longer compilation time than software
designers are used to in more common environments.
Even though we have not applied any manual
optimizations, the compilers attempt to flatten, unroll,
and pipeline loops on their own, albeit with limited suc-
cess. For example, as reported by HLS synthesis tools,
loops 3 and 4 are flattened and pipelined with a depth
of 21 cycles and a loop initiation interval of 2. The limit-
ing factor for the loop initiation interval is the fact that
the data is coming from a single memory port that can
only provide one input value on each clock cycle. Both
designs are reported to work at 300 Mhz.
The kernel could be further optimized using attri-
butes or pragmas and code restructuring. The OpenCL
approach is somewhat easier for software program-
mers who are not familiar with hardware design, but
even this approach is not entirely friendly for those
45
NOVEL ARCHITECTURES
not familiar with the hardware design terminology.
The application developer needs to be able to read
hardware synthesis reports and correlate the informa-
tion from these reports with their design. The tools
produce a substantial amount of reports in each phase
of the code compilation process, and each of these
reports contains information instrumental in guiding
the kernel optimization. These reports are oriented
toward hardware designers.
Can software developers without knowledge of
hardware design principles use these platforms to
develop codes for FPGAs? Yes, but they will have to
learn a lot in the process. The Vivado HLS approach is
quite involved with all the verification steps, IP genera-
tion, integration with SDAccel project, etc., whereas
OpenCL is easier for software developers. However,
even a naïve implementation, which is what we have
done here, is relatively involved and time-consuming
regardless of the framework used. And of course, any
performance optimizations will require an understand-
ing of the specific FPGA board's architecture. For
example, efficient utilization of the available memory
bandwidth on the u250 Alveo FPGA board requires
distributing data across four DDR memory banks as
well as defining global pointers as 512-bit data types
to sustain the maximum data bandwidth between the
kernel and DDR memory. This requires changes to the
host and kernel code to specify which bank is to be
used for which data buffer as well as splitting data into
several buffers. Software developers are almost never
concerned with such issues.
ACKNOWLEDGMENTS
This work was supported by the National Science
Foundation’s Major Research Instrumentation pro-
gram under Grant 1725729, as well as the University of
Illinois at Urbana-Champaign.
REFERENCES
1. G. Martin and G. Smith, “ High-level synthesis: Past,
present, and future,” IEEE Des. Test Comput., vol. 26, no.
4, pp. 18 –25, Jul./Aug. 2009, doi: 10.1109/MDT.2009.83.
2. J. Stone, D. Gohara , and G. Shi, “OpenCL: A parallel
programming standard for heterogeneous computing
systems,” Comput. Sci. Eng., vol. 12, no. 3, pp. 66 –72,
May/Jun. 2010, doi:10.1109/MCSE.2010.69.
3. Vivado design suite user guide: High-level synthesis,
46 ComputingEdge
UG902 (v2019.1) July 12, 2019. [Online]. Available:
https://www.xilinx.com/support/documentation
/sw_manuals/xilinx2019_1/ug902-vivado-high-level
-synthesis.pdf
4. SDAccel development environment: Release notes,
installation, and licensing guide, UG1238 (v2019.1) July
26, 2019. [Online]. Available: https://www.xilinx.com
/support/documentation/sw_manuals/xilinx2019_1
/ug1238-sdx-rnil.pdf
5. Getting started with alveo data center accelerator
cards, UG1301 (v1.4) December 18, 2019. [Online]. Avail-
able: https://www.xilinx.com/support/documentation
/boards_and_kits/accelerator-cards/1_4/ug1301
-getting-started-guide-alveo-accelerator-cards.pdf
RAMSHANKAR VENKATAKRISHNAN is a Research Pro-
grammer at the National Center for Supercomputing Appli-
cations. He received the master’s degree from University of
Illinois at Chicago in 2015. Contact him at rvenka21@illinois
.edu.
ASHISH MISRA is a Postdoctoral Research Associate at
the National Center for Supercomputing Applications. He
received the master’s and Ph.D. degrees from Birla Institute
of Technology and Science, India, in 2008 and 2017, respec-
tively. Contact him at ashishm@illinois.edu.
VOLODYMYR KINDRATENKO is a Senior Research Scientist
at the National Center for Supercomputing Applications. He
received the Specialist degree from the Vynnychenko State
Pedagogical University, Kirovograd, Ukraine, in 1993 and the
D.Sc. degree from the University of Antwerp, Belgium, in
1997. Contact him at kindrtnk@illinois.edu.
WWW.COMPUTER.ORG/COMPUTINGEDGE
September 2021
 DEPARTMENT: EXPERT OPINION This article originally
appeared in

Recent Advances in Compute-in-

Memory Support for SRAM Using
vol. 39, no. 6, 2019

Monolithic 3-D Integration

Zhixiao Zhang, National Tsing Hua University, Fuzhou University
Xin Si, National Tsing Hua University
Srivatsa Srinivasa and Akshay Krishna Ramanathan, Pennsylvania State University
Meng-Fan Chang, National Tsing Hua University

Computing-in-memory (CiM) is a popular design alternative to overcome the von Neumann

bottleneck and improve the performance of artificial intelligence computing applications.
Monolithic three-dimensional (M3D) technology is a promising solution to extend Moore’s
law through the development of CiM for data-intensive applications. In this article, we
first discuss the motivation and challenges associated with two-dimensional CiM designs,
and then examine the possibilities presented by emerging M3D technologies. Finally, we
review recent advances and trends in the implementation of CiM using M3D technology.

A
clear differentiation between logic, memory,
and process information in conventional von
Neumann computing schemes necessitates
the frequent movement of data between the memory
and processor. Thus, much of the execution time and
energy consumption is spent in the movement of data,
a barrier referred to as the “von Neumann bottleneck”
or “memory wall.” 1,2
Computing-in-memory (CiM) is a promising
approach to deal with the memory wall problem by
executing computation tasks wherever the data
resides in order to minimize data access operations.
Among various on-chip memories, SRAM is the best
working memory due to its high speed and high endur-
ance. A number of silicon-verified SRAM-based CiM
(SRAM-CiM) devices have been reported.3–6 However,
most previous implementations have been shown to
affect the fundamental performance of the constitu-
ent memory devices (i.e., density, speed, and robust-
ness). This has prompted research into process tech-
nology aimed at advancing the integration of SRAM
within CiM devices.
Digital Object Identifier 10.1109/MM.2019.2946489
Date of current version 8 November 2019.
Many SRAM-CiMs in 2-D configurations suffer
from a large area overhead due to the need for addi-
tional transistors.3–6 This has encouraged research-
ers to develop CiM in 3-D technologies for suppressing
the overhead in density or performance of the memory
system when used for CiM.
Multilayer 3-D IC technologies can be divided into
two categories: through silicon vias (TSV)-based 3-D
(TSV-3D) and monolithic 3-D (M3D). The large dimen-
sions of TSVs7 and difficulties in establishing vertical
interconnects between layers greatly limits the den-
sity of TSV-3D devices [see Figure 1(a)]. In contrast,
sequential manufacturing can be used to fabricate
M3D devices with ultrahigh density vertical cross-layer
connections,8,9 as shown in Figure 1(b).
M3D integration has been a technology enabler
in the development of CiM-capable SRAM devices,
thanks to affinity for fine-grained vertical intercon-
nects with small parasitic load.8–14 CiM designs that
involve M3D integration cannot be implemented in
TSV-based 3-D devices, due to high pitch and large
parasitic load for vertical interconnect.
This article also reviews recent advances and
trends in the implementation of CiM using M3D IC
technology as well as the challenges researchers face
as they progress in furthering this technology.

2469-7087/21 © 2021 IEEE Published by the IEEE Computer Society September 2021 47
EXPERT OPINION
FIGURE 1. Three-dimensional ICs. Vertical interconnections
using (a) TSVs and (b) M3D vias.
FIGURE 2. (a) Conventional von Neumann architecture and
(b) CiM architecture.
BACKGROUND OF CIM AND M3D IC
Background of CiM
The primary objective of CiM is to minimize the fre-
quent movement of data in and out of the memory
system to improve energy efficiency and fully exploit
parallelism. However, the design of CiM is limited by
several challenges, which are addressed later.
48 ComputingEdge
Motivation for CiM Figure 2(a) presents a conven-
tional computing system based on the von Neumann
architecture. The bottleneck involving the movement
of data between the processor and memory has been
greatly exacerbated since the advent of data intensive
computing applications, such as artificial intelligence
(AI). Performance-centric optimization strategies
increase the complexity of logic elements by increas-
ing the gate count. Capacity-centric design strate-
gies impose considerable demands in terms of on-chip
and off-chip memory. Furthermore, dynamic energy
consumption when accessing large amounts of data,
access latency due to wire delay, and performance lim-
itations imposed by downscaling tend to hinder mem-
ory performance. This has resulted in a wide perfor-
mance gap between logic and memory systems. As
shown in Figure 2(a), the proximity of SRAM to the pro-
cessing elements in the conventional von Neumann
architecture makes it the primary performance bot-
tleneck in the execution of data-intensive workloads.
Meeting the power-performance requirements for
data-intensive workloads will require novel solutions
to bridge the ever-increasing logic-memory gap.
CiM is a promising approach to overcoming the
memory wall via parallel data processing, as shown
in Figure 2(b). The memory macros in a CiM structure
are not limited to normal read and write operations.
They can also be configured to operate as a comput-
ing engine to minimize the amount of data that needs
to be moved between the processor and discrete
memory devices. CiM has two major advantages: 1)
improve speed and area efficiency, thanks to com-
putation directly in memory (i.e., fewer accesses to
external memory); and 2) superior energy efficiency,
thanks to high data parallelism and reduced power
consumption.
The emergence of high-density nonvolatile
memory (NVM) technologies and the physical orga-
nization of bitcells within the crosspoint architecture
have enabled the development of attractive CiM solu-
tions.15,16 Unfortunately, no existing solution is able to
provide high-speed operations as well as high endur-
ance as SRAM do. Although NVM-CiM and SRAM-CiM
are used together to perform different tasks in some
applications, researchers are seeking various process
technologies that could assist in the development of
CiM solutions using SRAM.
September 2021
 EXPERT OPINION

TABLE 1. Recent development of M3D technology.

2015VLSI18 2015IEDM9 2016VLSI19 2016IEDM10 2017IEDM11 2018IEDM12 2018VLSI20

Channel SOI Epi-like Si SOI Epi-like Si Epi-like Si Epi-like Si SOI

CO2 laser CO2 laser CO2 laser

308 nm SolidPhase CO2 laser Selective
anneal anneal activation &
Anneal ELA Epitaxy(SPE) activation epitaxy
(CO2-FIR-LA) (CO2-FIR-LA) CO2 laser
(CO2-FIR-LA)
Silicide
Thermal
600° C 400° C 500–600° C 400° C 400° C 600° C 525° C
budget

Multi-channel
Device FDSOI Epi-likeSi FDSOI Multi-finEpi- Junction-
Epi-like Si NC-FinFETs
architecture MOSFET UTB-MOSFETs MOSFET likeSiFinFETs lessdevices
UTB-MOSFETs

Ion/Ioff ratio NA NA >108 >106 >106 >106 NA

Challenges in Developing 2-D CiM Researchers have
developed a number of 2-D CiM structures, includ-
ing an algorithm-dependent SRAM-CiM for binary
fully connected neural networks,3 a 10T SRAM for
multiple-bit input and binary weight CNN,4 a 6T-SRAM
CiM for multiple weight-value multiplication and aver-
aging with on-chip training,5 and a twin-8T SRAM-CiM
for multibit input and multibit weight CNN.6 Nonethe-
less, all of the above 2-D CiM solutions face a number
of challenges as follows.
the sensitivity of SRAM cells in CiM to read
disturbance.
5. Long routing: Intense transistor integration
in SRAM bitcells requires that the computing
results from CiM operations undergo long
routing to peripheral read-out circuits when
dealing with large-capacity CiM macros.
Extended routing tends to increase parasitic
capacitance, degrade operational speeds, and
boost power consumption.

1. Large area overhead: Several CiM architec- M3D Technology: Background

tures require dedicated memory cells (10T or
more) for computing operations. This greatly
increases cell area overhead (2×–3×) and limits
the density of the memory array.2)
2. Write disturbance: In 6T-SRAM CiM schemes,
multiple rows are activated simultaneously,
whereupon the bitline voltage (VBL) is pulled
down to a low level. In the event that VBL is
lower than the write trigger-point of the SRAM
cell, the data stored in the cell is susceptible to
flipping.
3. Limited signal margin: Increasing the number
of activated wordlines to improve energy effi-
ciency leads to a reduction in the signal margin
on each bitline (BL). In this situation, the CiM
requires complex small-offset readout circuits
to suppress inaccurate read operations due to
process variation.
4. Read disturbance: Regular 6T SRAM cells suf-
fer read disturbance due to process, voltage,
and temperature (PVT) variations.17 Increasing
the wordline (WL) pulse width increases
The manufacturing of M3D devices is a sequential pro-
cess, which progresses from the bottom to the top
layer. Note that each layer can be produced using dif-
ferent materials and/or different device parameters.
M3D technology provides three notable advan-
tages over 2-D devices and TSV-3D: 1) small parasitic
load and dense bandwidth, both of which are neces-
sary for vertical interconnections between layers; 2)
small area overhead to allow the stacking of transis-
tors within a given silicon footprint; and 3) highly
heterogeneous integration capability, including logic,
memory, analog, sensors, and energy harvesters.8,9
Table 1 lists recent developments in M3D tech-
nologies.9–12,18–20 They can be summarized according
to their characteristics as follows.
1. Highly heterogeneous integration of devices
without device degradation. In the paper by Wu
et al.,9 a gate-first high-k metal gate MOSFET
was fabricated with non-Al metal intercon-
nects using CO2 far-infrared laser annealing
(CO2-FIR-LA) for M3D.

www.computer.org/computingedge 49
EXPERT OPINION
FIGURE 3. Trend in subthreshold swing among recent M3D
compatible technologies.
2. Higher current driving capacity. In the paper
by Pasini et al.,19 researchers presented
high-performance FDSOI devices with record
high on-current and on–off current ratio at
low temperatures. In the paper by Hseuh et
al.,10 researchers presented a M3D scheme
that uses multi-Fin Epi like-Si UTB-MOSFETS
to achieve high driving currents.
3. Higher performance and lower power con-
sumption. In the paper by Batude et al.,18
researchers presented the M3D CoolCube,
which uses a connecting via of ultrahigh
density (exceeding 1 million/mm2) to enhance
computational performance and reduce power
consumption. In the paper by Hseuh et al.,12
researchers used NC-FinFET in the fabrica-
tion of 3-D SRAM-CiM macros, which use an
ultralow power supply (0.25 V).
4. Improved reliability. In the paper by Hseuh et
FIGURE 4. Categories of M3D integration schemes.
50 ComputingEdge
al.,11 researchers presented a multi-Fin Epi
like-Si Si FinFET-based M3D-IC with suppres-
sion of threshold voltage variation. In the paper
by Vandooren et al.,20 researchers presented
junction-less devices within a top-tier M3D to
lower the thermal budget and thereby improve
device performance and reliability.
M3D technologies can be used in the creation of
MOSFETs with high Ion/Ioff ratio (>106) to reduce current
leakage and allow low-power operations. As shown in
Figure 3, the evolution of M3D technology has opened
the door to MOSFETs with reduced subthreshold
swing (S. S.). In the paper by Hseuh et al.,12 researchers
presented a stackable 3-D NC-FinFET, which achieved
45 mV/dec (using NC-nFinFET) and NC-pFinFET: 50
mV/dec (using NC-pFinFET). Clearly, M3D technology
is a promising candidate for low-voltage operations.
Design Strategies Using M3D IC
As shown in Figure 4, circuit designs based on M3D
integration can be classified into two categories,
based on the nature of the 3-D folding (logic level
and memory level). In logic-level folding, some of the
logic blocks are moved to upper layers. This cate-
gory can be further divided into three groups, based
on the granularity of vertical interconnects per unit
area and the number of transistors associated with
logic operations. Transistor-level M3D integration
with vertical interconnects of very fine pitch allows
CMOS transistor-level stacking to create compact
cells and enable the customization of transistors in
each layer. Standard cell-level folding requires fewer
September 2021
 EXPERT OPINION

TABLE 2. Folding logics into multiple layers.

vertical interconnects and increases flexibility in
Baseline 2D 2 layers 3 layers 10 layers
standard cell placement. Block-level folding into two design design design design

layers depends on critical paths and performance Process (nm) 22 22 22 22

constraints. Low-latency vertical interconnects make Frequency

1 1 1 1
(GHz)
it easier to replace long 2-D metal routes; however, the
Num.of
use of multiple transistor types can negatively affect gates in 2D (M)
200 200 200 200
the yield and performance of layer-2. Folding logics
Metal levels 8 8 6 4
into multiple layers can also have a detrimental effect
Power (W) 17.93 13.11 11.6 7.85
on performance.
Table 2 presents results from a logic (without any
specific functionality) with 200M gate count. The
design was folded into multiple layers. The baseline
2-D chip area is 35 mm2. Under reduced power, any
increase in the number of layers and resources gradu-
ally leads to saturation, with the result that logic-level
folding provides only negligible gains while not being
cost effective.
The other circuit design category involves
memory-level folding (i.e., SRAMs folded into two lay-
ers). This approach supports bank-level, wordline-level,
and bitline-level folding to reduce area overhead and
increase data access rates. This type of M3D folding
tends to be cost effective when using only one or two
types of transistors in layer-2; however, it does not
provide computational support. Density-aware CiM
can be implemented using only a few transistors per
SRAM cell. This approach to integration enables novel
CiM design schemes by enabling direct access to the
storage nodes from layer-2, while retaining design
robustness.

Development Of CiM Techniques FIGURE 5. Development from von Neumann architecture to

Using M3D
The combination of CiM and M3D greatly reduces area
overhead, prevents write/read disturb, and reduces
routing latency. M3D based CiM is a promising solu-
tion to overcome the memory wall and improve energy
efficiency.
Features of M3D-Based CiM
The shift away from the von Neumann architecture
toward CiM has led to the development of a number of
silicon verified M3D based works,8–13 as shown in Fig-
ure 5. Early M3D works focus on the development of
processes suitable for heterogeneous integration.8–10
A variety of circuits and memory types have been
developed using M3D processes.8–13,21–23
CiM using M3D.
Rapid developments in M3D technologies have
increased the number of layers that can be stacked
vertically. This has made it possible to integrate larger
memory macros and CiM circuits in the development
of novel M3D-based CiM structures. This approach
has a number of advantages.
1. Compact cell area: Small-dimension and short
3-D vias for cross-layer vertical connections
enables the cell-level integration of multiple
transistors across layers to reduce area
overhead and parasitic load.

www.computer.org/computingedge 51
EXPERT OPINION
TABLE 3. List of recent M3D-based CiMs.
2017IEDM [11] 2018IEDM [12]
Structure
Bit cell
6T+3T SRAM Standard 6T SRAM
structure
VDDmin 0.4 V
Boolean: NAND/AND,
Function Arithmetic: Full Adder
OR/NOR, XOR/XNOR
FIGURE 6. Minimum operating voltages of recent M3D-based
SRAM and SRAM-CiM works.
2. Reduced routing overhead: Vertical memory
cells require shorter interconnects and suffer
less from parasitic load associated with the
transfer of signals. This reduces the latency
of M3D-CiM and thereby increases data
throughput.
3. Inclusion of 3-D peripheral circuits: Dense
vertical connections enable the placement of
bitlines, wordlines, and peripheral circuits in
multiple layers. This reduces parasitic capaci-
tance and routing length, which in turn reduces
power consumption and access times.24
Review of Recent M3D-Based
CiM Works
Table 3 lists recent works of M3D-based CiM. In
IEDM17,11 researchers presented an M3D 9T CiM-SRAM
52 ComputingEdge
2019VLSI [13]
6T+2T SRAM
0.25 V 0.2 V
Boolean: NAND/AND, OR/NOR, XOR/XNOR
Multi Row Multiply and Accumulate (MAC)
cell capable of Boolean operations, including nand/
and, or/nor, and xor/xnor operations. The resulting cir-
cuit proved to be highly area efficient with reduced Vth
variation, high bandwidth, and a low operating voltage
(VDD = 0.4 V). However, the need for an additional layer
for the three transistors tends to undermine the yield.
The scheme presented in IEDM1812 provides high
bandwidth, low data access time, ultralow operating
voltage (VDD = 250 mV), and a considerable reduction in
area overhead. The scheme presented in IEDM1812 pro-
vides high bandwidth, low data access time, ultralow
operating voltage (VDD = 250 mV), and a consider-
able reduction in area overhead. An NC-FinFET-based
full-adder comprising ten transistors with differential
inputs from the storage nodes in 6T SRAM is used for
near-memory computing (NMC). This scheme reduces
area overhead by 1.6× compared to previous CMOS
xnor-gate based full-adders.25 The computation speed
of NMC is lower than that of CiM; however, it is easier
to manipulate and less susceptible to PVT variations.
The advent of data-intensive workloads has been
steering research toward CiM. Most existing solutions
support computation in memory for only a small subset
of operations, with the result that the memory system
does not cater to a wide variety of applications. The
reconfigurable SRAM scheme presented in VLSI1913
uses M3D to provide multiple computation modes
and lookup table (LUT) functionality. Bitwise Boolean
computation is performed via a dedicated read port
in layer-1. Low Vth variability FinFeETs provide robust
read and write operations in layer-2. The design with
the LUT immediately above the sense amplifiers helps
September 2021
 EXPERT OPINION

to preserve the density of the memory array. Reliable

multirow activation from layer-1 enables bitwise Bool-
ean operations as well as multiply and accumulate
(MAC) functionality.

Trends in M3D-Based CiM

Figure 6 presents the minimal operating voltage (VDD-
min) of recent M3D-based SRAM and SRAM-CiM,
which achieved VDDmin of 0.5–0.2 V and 0.4–0.25 V,
respectively. Under optimal device parameters, M3D
technology enables the ultralow voltage operations
required for low-power IOT and AI edge devices.
Figure 7 presents a comparison of 2-D and M3D
technologies with various SRAM-CiM structures
in terms of area reduction. Note that standard 6T
SRAM was used as the baseline (1×). The M3D-based
SRAM-CiM enabled a 1.26×–1.51× [see Figure 7(a)] and
1.28×–1.82× [see Figure 7(b)] area overhead reduction
in SRAM cells and peripheral circuits, respectively.
The effect was more pronounced when dealing with
devices tasked with operations of greater complex- FIGURE 7. Area overhead reduction of recent M3D-based
ity. This is a clear indication that M3D can be used to SRAM-CiM works compared to 2-D SRAM-CiM works: (a) CiM
develop CiM schemes with greater functionality for AI SRAM cell and (b) peripheral circuit.
and data-intensive applications than that would other-
wise be possible using 2-D technology.
Figure 8 presents the normalized in-memory func-
tional complexity of recent M3D SRAM-CiM works,
which is based on the equivalent number of Bool-
ean operations. From simple Boolean logic to MAC
operation, we can see that the functional complexity
of M3D-based SRAM-CiM has been increasing sig-
nificantly every year. Note that the works shown here
employ only two layers in the implementation of CiM
functions. As this technology matures, it is reasonable
to expect that the functional complexity of M3D-based
SRAM-CiM will increase dramatically as the numbers
of employed layers increase in the following years. FIGURE 8. Trend of normalized functional complexity.

CONCLUSION
CiM based on M3D technology is an attractive solu-
tion for data-intensive and AI applications. In this arti-
cle, we explored the benefits of CiM based on recent
M3D technologies. We also examined the trends in
M3D-based SRAM-CiM. With improvements in VDD-
min, on–off current ratio, and yield, it is expected that
M3D-based SRAM-CiM will be able to handle func-
tions of high complexity with high energy efficiency.
ACKNOWLEDGMENT
The authors gratefully acknowledge support from TSRI,
MOST-Taiwan, and the SRC JUMP Center for Research
on Intelligent Storage and Processing-in-memory
(CRISP). This work was supported in part by the
National Science Foundation Expeditions in Comput-
ing Program: Visual Cortex on Silicon CCF 1317560.

www.computer.org/computingedge 53
EXPERT OPINION
REFERENCES
1. W. A. Wulf and Sally A. McKee, “Hitting the memory
wall: implications of the obvious,” ACM SIGARCH
Comput. Archi. News, vol. 23, no. 1, pp. 20–24, 1995.
2. W.-H. Chen, et al., “CMOS-integrated memristive
non-volatile computing-in-memory for AI edge proces-
sors,” Nature Electron., vol. 2, pp. 420–428, Sep. 2019.
3. W.-S. Khwa, et al., “A 65nm 4Kb algorithm-dependent
computing-in-memory SRAM unit-macro with 2.3ns and
55.8 TOPS/W fully parallel product-sum operation for
binary DNN edge processors,” in IEEE Int. Solid-State
Circuits Conf. Dig. Tech. Papers, Feb. 2018, pp. 496–497.
4. A. Biswas and A. P. Chandrakasan, “Conv-RAM: An
energy-efficient SRAM with embedded convolution
computation for low-power CNN-based machine
learning applications,” in IEEE Int. Solid-State Circuits
Conf. Dig. Tech. Papers, Feb. 2018, pp. 488–489.
5. S. K. Gonugondla, M. Kang, and N. Shanbhag, “A 42pJ/
Decision 3.12TOPS/W robust in-memory machine
learning classifier with on-chip training,” in IEEE Int.
Solid-State Circuits Conference Dig. Tech. Papers, Feb.
2018, pp. 490–491.
6. X. Si, et al., “A twin-8T SRAM computation-in-memory
macro for multiple-bits CNN-based machine learning,”
in IEEE Inter-Nat. Solid-State Circuits Conf. Dig. Tech.
Papers, Feb. 2019, pp. 396–397.
7. M.-F. Chang, et al., “A high layer scalability TSV-based
3D-SRAM with semi-master-slave structure and
self-timed differential-TSV for high-performance
universal-memory-capacity-platforms,” IEEE J. Solid-
State Circuits, vol. 48, no. 6, pp. 1521–1529, Jun. 2013.
8. C.-H. Shen, et al., “Monolithic 3D chip integrated with
500ns NVM, 3ps logic circuits and SRAM,” in IEEE Int.
Electron Devices Meeting Dig. Tech. Papers, Dec. 2013,
pp. 232–235.
9. T.-T. Wu, et al., “Low-cost and TSV-free monolithic
3D-IC with heterogeneous integration of logic, memory
and sensor analogy circuitry for internet of things,” in
IEEE Int. Electron Devices Meeting Dig. Tech. Papers,
Dec. 2015, pp. 25.4.1–25.4.4.
10. F.-K. Hsueh, et al., “First fully functionalized monolithic
3D+ IoT chip with 0.5 V light-electricity power manage-
ment 6.8 GHz wireless-communication VCO and
4-layer vertical ReRAM,” in IEEE Int. Electron Devices
Meeting Dig. Tech. Papers, Dec. 2016, pp. 2–3.
11. F.-K. Hsueh, et al., “TSV-free FinFET-based monolithic
3D+-IC with computing-in-memory SRAM cell for
54 ComputingEdge
intelligent IoT De-vices,” in IEEE Int. Electron Devices
Meeting Dig. Tech. Papers, Dec. 2017, pp. 12.6.1–12.6.4.
12. F.-K Hsueh, et al., “Ultra-low power 3D
NC-FinFET-based monolithic 3D+-IC with
computing-in-memory for intelligent IoT devices,” in
IEEE Int. Electron Devices Meeting Dig. Tech. Papers,
Dec. 2018, pp. 15.1.1–15.1.4.
13. S. Srinivasa, et al., “Monolithic 3D+ -IC based recon-
figurable compute-in-memory SRAM Macro,” in Proc.
Symp. VLSI Technol., Kyoto, Japan, 2019, pp. T32–T33.
14. S. Srinivasa, et al., “ROBIN: Monolithic-3D SRAM for
enhanced robustness with in-memory computation
support,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol.
66, no. 7, pp. 2533–2545, Jul. 2019.
15. C.-X. Xue, et al., “A 1Mb multibit ReRAM
computing-in-memory macro with 14.6ns parallel MAC
computing time for CNN-based AI edge processors,”
in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers,
Feb. 2019, pp. 388–390.
16. W.-H. Chen, et al., “A 65nm 1Mb nonvolatile
computing-in-memory ReRAM Macro with sub-16ns
multiply-and-accumulate for binary DNN AI edge
processors,” in IEEE Int. Solid-State Circuits Conf. Dig.
Tech. Papers, Feb. 2018, pp. 494–495.
17. M.-F. Chang, et al., “A compact-area low-VDDmin 6T
SRAM with improvement in cell stability, read-speed
and write-margin using a dual-split-control assist
scheme,” IEEE J. Solid-State Circuits, vol. 52, no. 9, pp.
2498–2514, Sep. 2017.
18. P. Batude, et al., “3DVLSI with CoolCube process:
An alternative path to scaling,” in Proc. Symp. VLSI
Technol., Kyoto, Japan, 2015, pp. T48–T49.
19. L. Pasini, et al., “High performance CMOS FDSOI
devices activated at low temperature,” in Proc. IEEE
Symp. VLSI Technol., Honolulu, HI, USA, 2016, pp. 1–2.
20. A. Vandooren, et al., “3D sequential stacked planar
devices on 300 mm wafers featuring replacement
metal gate junction-less top devices processed at
525°C with improved reliability,” in Proc. IEEE Symp.
VLSI Technol., Honolulu, HI, USA, 2018, pp. 69–70.
21. V. Deshpande, et al., “First demonstration of 3D SRAM
through 3D monolithic integration of InGaAs n-FinFETs
on FDSOI Si CMOS with inter-layer contacts,” in Proc.
Symp. VLSI Technol., Kyoto, Japan, 2017, pp. T74–T75.
22. F. Andrieu, et al., “Design technology co-optimization
of 3D-monolithic standard cells and SRAM exploiting
dynamic back-bias for ultra-low-voltage operation,” in
September 2021

Proc. IEEE Int. Electron Devices Meeting, San Francisco,
CA, USA, 2017, pp. 20.3.1–20.3.4.
23. S. Srinivasa, et al., “Compact 3-D-SRAM memory with
concur-rent row and column data access capability
using sequential monolithic 3-D integration,” IEEE
Trans. Very Large Scale Integr. (VLSI) Syst., vol. 26, no. 4,
pp. 671–683, Apr. 2018.
24. H. H. Nho, et al., “A high-speed, low-power 3D-SRAM
architecture,” in Proc. IEEE Custom Integr. Circuits
Conf., San Jose, CA, USA, 2008, pp. 201–204.
25. P. Bhattacharyya, B. Kundu, S. Ghosh, V. Kumar, and
A. Dandapat, “Performance analysis of a low-power
high-speed hybrid 1-bit full adder circuit,” IEEE Trans.
Very Large Scale Integr. (VLSI) Syst., vol. 23, no. 10, pp.
2001–2008, Oct. 2015.
26. W.-H. Chen, et al., “A dual-split-controlled 4P2N 6T
SRAM in monolithic 3D-ICs with enhanced read speed
and cell stability for IoT applications,” IEEE Electron
Device Lett., vol. 39. no. 8, pp. 1167–1170, Aug. 2018.
ZHIXIAO ZHANG is currently with Fuzhou University,
Fuzhou, China. His research interests include SRAM- and
NVM-based Computing-in-Memory design. He received
the BS degree in electrical engineering in 2006 and the MS
degree in microelectronics and solid-state electronics in
2009 from Fuzhou University. He is currently pursuing the
PhD degree in electrical engineering with the National Tsing
Hua University, Hsinchu, Taiwan.
XIN SI is currently with National Tsing Hua University, Hsin-
chu, Taiwan. His research interests include analog circuit
design, memory, and Computing-in-Memory circuit designs.
He received the BS degree in integrated circuit design and
integration system in 2016 from the University of Electronic
Science and Technology of China (UESTC), Chengdu, China,
where he is currently working toward the PhD degree with
UESTC. He is a student member of the IEEE.
SRIVATSA SRINIVASA has been with Pennsylvania State
University, State College, PA, USA, since spring 2015 and is cur-
rently working toward the PhD degree with the Electrical Engi-
neering Department. He received the BE degree in electronics
and communication engineering from VTU, Belgaum, India.
AKSHAY KRISHNA RAMANATHAN is currently working
toward the PhD degree in electrical engineering at The
www.computer.org/computingedge
EXPERT OPINION
Pennsylvania State University, University Park, PA, USA.
He received the BTech degree in electrical and electronics
engineering from SASTRA University, Thanjavur, India. He is
a student member of the IEEE.
MENG-FAN CHANG is currently a Full Professor with
National Tsing Hua University, Hsinchu, Taiwan. Before 2006,
he has worked in industry for more than ten years. From 1996
to 1997, he designed memory compilers in Mentor Graphics,
NJ, USA. From 1997 to 2001, he designed embedded SRAMs
and Flash in Design Service Division (DSD) at TSMC, Hsinchu,
Taiwan. During 2001–2006, he was a co-founder and a Direc-
tor in IPLib Company, Taiwan, where he developed embedded
SRAM and ROM compilers, flash macros, and flat-cell ROM
products. His research interests include circuit designs
for volatile and nonvolatile memory, ultralow-voltage sys-
tems, 3-D memory, circuit–device interactions, spintronics
circuits, memristor logics for neuromorphic computing,
and Computing-in-Memory for artificial intelligence. He
received the MS degree from The Pennsylvania State Uni-
versity, University Park, PA, USA, and the PhD degree from
the National Chiao Tung University, Hisnchu, Taiwan. He
is an Associate Editor for the IEEE Transactions on Very
Large Scale Integration (VLSI) Systems and the IEEE Trans-
actions on Computer-Aided Design of Integrated Circuits
and Systems. He is also a Guest Editor of the IEEE Journal
of Solid-State Circuits, the IEEE Transactions on Circuits
and Systems—II: Express Briefs, and the IEEE Journal on
Emerging and Selected Topics in Circuits and Systems. He
is also on technical program committees for ISSCC, IEDM
(Ex-Com and MT chair), DAC (Sub-Com Chair), ISCAS (Track
Co-Chair), A-SSCC, and numerous international confer-
ences. He has been a Distinguished Lecture speaker for the
IEEE Solid-State Circuits Society (SSCS) and the Circuits and
Systems Society (CASS), a technical committee member of
CASS, and the administrative committee (AdCom) member
of the IEEE Nanotechnology Council. He has also been the
Program Director of Micro-Electronics Program of Ministry
of Since and Technology (MOST) in Taiwan during 2018–2020,
Associate Executive Director for Taiwan’s National Program
of Intelligent Electronics (NPIE) and NPIE bridge program
during 2011–2018. He is the recipient of several prestigious
national-level awards in Taiwan, including the Outstanding
Research Award of MOST-Taiwan, the Outstanding Electrical
Engineering Professor Award, the Academia Sinica Junior
Research Investigators Award, and the Ta-You Wu Memorial
Award. He is a Fellow of the IEEE.
55
CAREER OPPORTUNITIES

100% ANALYTICS & BUSINESS INTELLIGENCE

BIG DATA

ONLINE
BUSINESS INFORMATION SYSTEMS
CYBERSECURITY
CYBERSECURITY MANAGEMENT

MASTER OF CYBERSECURITY POLICY

DECISION SUPPORT SYSTEMS

INFORMATION
HEALTH INFORMATION TECHNOLOGY
INNOVATION IN AI/ML
NETWORKING

TECHNOLOGY SOFTWARE DEVELOPMENT

SOFTWARE ENGINEERING

VTMIT.VT.EDU

IEEE Computer Society

Has You Covered!
WORLD-CLASS CONFERENCES —
Over 215 globally recognized conferences.
DIGITAL LIBRARY — Over 800k articles covering
world-class peer-reviewed content.
CALLS FOR PAPERS — Write and present your
ground-breaking accomplishments.
EDUCATION — Strengthen your resume with the
IEEE Computer Society Course Catalog.
ADVANCE YOUR CAREER — Search new positions
in the IEEE Computer Society Jobs Board.
NETWORK — Make connections in local Region,
Section, and Chapter activities.

Explore all of the member benefits

at www.computer.org today!

56 ComputingEdge September 2021

 Driving
Quantum
Advantage.

Quantum Advantage. It’s the advantage that comes with harnessing the
quantum universe, and applying that knowledge to computing, sensing,
communications and more. These discoveries promise to change the world
for the better.

At the Quantum Research Centre at TII, we are imagining, designing and

building the quantum technology that will be a key driver of tomorrow’s
knowledge society. Join us on the journey.

Discover more about our ground-breaking research at quantum.tii.ae

QUANTUM
ORCHESTRATION
PLATFORM
The new paradigm for
quantum control
systems, across all
qubit platforms

QUANTUM-MACHINES.CO

www.computer.org/computingedge 57
 Quantum Algorithm Design
Our software automatically synthesizes
optimized quantum circuits from high-
level functional models.

www.classiq.io

When we launched the first quantum

computer accessible on the cloud in 2016,
we were astonished when we reached
8,000 users.

Today, we’ve reached over 250,000 users.

This is the world’s largest and most
engaged quantum developer community
running over 2 billion circuits daily on a
fleet of the world’s most power quantum
computers, all on the IBM Cloud.

Our next goal is to reach the world’s 25

million developers, to empower them to
put quantum to use in solving today’s
intractable challenges.

Our strategy is to make quantum

computing as seamless and as easy to use
as today’s classical
programming frameworks.

If you’d like to learn more, please contact

hmcortes@us.ibm.com

58 ComputingEdge September 2021

 IEEE SOFTWARE

IEEE SOFTWARE
January/February 2015

March/April 2015
INTERNETWARE AND BEYOND

RELEASE ENGINEERING
Volume 32 Number 1

Volume 32 Number 2

To better understand how

companies are investing in
IEEE Software offers pioneering ideas, expert deep–tech, we surveyed more
than 200 decision-makers at
analyses, and thoughtful insights for software
large enterprises.
professionals who need to keep up with
rapid technology change. It’s the authority on Read the full report at
seeqc.com/report
translating software theory into practice.

www.computer.org/software/ Seeqc, Inc. | 150 Clearbrook Rd, Elmsford, NY 10523 | info@seeqc.com

www.computer.org/computingedge 59
 Conference Calendar
I EEE Computer Society conferences are valuable forums for learning on broad and dynamically shifting top-
ics from within the computing profession. With over 200 conferences featuring leading experts and thought
leaders, we have an event that is right for you. Questions? Contact conferences@computer.org.
OCTOBER
1 October
• ISPA (IEEE Int’l Symposium on
Parallel and Distributed Pro-
cessing with Applications),
New York, USA
2 October
• IWSC (IEEE Int’l Workshop on
Soft ware Clones), virtual
4 October
• IC2E (IEEE Int’l Conf. on Cloud
Eng.), San Francisco, USA
• ISMAR (IEEE Int’l Symposium
on Mixed and Augmented
Reality), Bari, Italy
• LCN (IEEE Conf. on Local Com-
puter Networks), Edmonton,
Canada
• MASS (IEEE Int’ l Conf. on
Mobile Ad Hoc and Smart Sys-
tems), Denver, USA
6 October
• DFT (IEEE Int’l Symposium on
Defect and Fault Tolerance in
VLSI and Nanotechnology Sys-
tems), virtual
10 October
• MODELS (ACM/IEEE Int’l Conf.
on Model Driven Eng. Languages
and Systems), Fukuoka, Japan
11 October
• ESEM (ACM/IEEE Int’l Sympo-
sium on Empirical Software
Eng. and Measurement), Bari,
Italy
60 September 2021
• ICCV (IEEE/CVF Int’l Conf. on
Computer Vision), Montreal,
Canada
12 October
• AIPR (IEEE Applied Imagery
Pattern Recognition Work-
shop), Washington, D.C., USA
13 October
• FIE (IEEE Frontiers in Educa-
tion Conf.), Lincoln, Nebraska,
USA
• WF-5G (IEEE 5G World Forum),
Montreal, Canada
16 October
• MICRO (IEEE/ACM Int’l Sym-
posium on Microarchitecture),
Athens, Greece
17 October
• ICVRV (IEEE Int’l Conf. on Vir-
tual Reality and Visualization),
Nanchang, China
18 October
• QCE (IEEE Int’l Conf. on Quan-
tum Computing and Eng.),
virtual
• SecDev (IEEE Secure Develop-
ment Conf.), Atlanta, USA
21 October
• IEEE Cloud Summit, Hemp-
stead, New York, USA
23 October
• DataCom (IEEE Int’l Conf. on
Big Data Intelligence and Com-
puting), Huizhou, China
• SAGC (Int’l Conf. on
Published by the IEEE Computer Society
Space-Air-Ground Comput-
ing), Huizhou, China
24 October
• ICCD (IEEE Int’l Conf. on Com-
puter Design), virtual
• VIS (IEEE Visualization Conf.),
New Orleans, USA
25 October
• CONISOFT (Int’l Conf. on Soft-
ware Eng. Research and Inno-
vation), virtual
• EDOC (IEEE Int’l Enterprise
Distributed Object Computing
Conf.), Gold Coast, Australia
• ISSRE (IEEE Int’l Symposium
on Software Reliability Eng.),
Wuhan, China
• LDAV (IEEE Symposium on
Large Data Analysis and Visu-
alization), New Orleans, USA
26 October
• SBAC-PAD (IEEE Int’l Sympo-
sium on Computer Architec-
ture and High-Performance
Computing), virtual
27 October
• WETICE (IEEE Int’l Conf. on
Enabling Technologies: Infra-
structure for Collaborative
Enterprises), virtual
NOVEMBER
2 November
• ICNP (IEEE Int’l Conf. on Net-
work Protocols), Dallas, USA
2469-7087/21 © 2021 IEEE
4 November
• SLIP (ACM/IEEE Int’l Workshop
on System-Level Interconnect
Prediction), virtual
6 November
• SmartCloud (IEEE Int’l Conf. on
Smart Cloud), Newark, USA
7 November
• IISWC (IEEE Int’l Symposium
on Workload Characteriza-
tion), virtual
12 November
• ICEBE (IEEE Int’ l Conf. on
e-Business Eng.), Guangzhou,
China
14 November
• SC (Int’l Conf. for High-Perfor-
mance Computing, Network-
ing, Storage, and Analysis), St.
Louis, USA
15 November
• ASE (IEEE/ACM Int’l Conf. on
Automated Sof tware Eng.),
Melbourne, Australia
• BigMM (IEEE Int’l Conf. on Mul-
timedia Big Data), Taichung,
Taiwan
16 November
• AVS S (IEEE Int’ l Conf. on
Advanced Video and Signal-
Based Surveillance), virtual
17 November
• ICMU (Int’l Conf. on Mobile
Computing and Ubiquitous
Networking), Tokyo, Japan
22 November
• ATS (IEEE Asian Test Sympo-
sium), virtual
23 November
• IMITEC (Int’l Multidisciplinary
I n f o r m a t i o n Te c h n o l o g y 9 December
and Eng. Conf.), Windhoek, • BIBM (IEEE Int’l Conf. on Bio-
Namibia informatics and Biomedicine),
24 November virtual
• SNPD (IEEE/ACIS Int’l Conf. on 12 December
Soft ware Eng., Artificial Intel- • HOST (IEEE Int’l Symposium
ligence, Networking, and Par- on Hardware-Oriented Secu-
allel/Distributed Computing), rity and Trust), Washington,
Taichung, Taiwan DC, USA
29 November 13 December
• ISM (IEEE Int’l Symposium on • PST (Int’l Conf. on Privacy,
Multimedia), virtual Security, and Trust), virtual
30 November 20 December
• ICRC (IEEE Int ’ l Conf. on • MCSoC (IEEE Int’l Sympo -
Rebooting Computing), virtual sium on Embedded Multicore/
Many-Core Systems-on-Chip),
DECEMBER Singapore
1 December
• PRDC (IEEE Pacific Rim Int’l
Symposium on Dependable
Computing), virtual
6 December
• BDCAT (IEEE Int’l Conf. on
Big Data Computing, Appli-
cations, and Technologies),
Leicester, UK
• Blockchain (IEEE Int’l Conf. on
Blockchain), virtual
• UCC (IEEE Int’l Conf. on Utility
and Cloud Computing), Leices-
ter, UK Learn more
7 December
• CSASE (Int’l Conf. on Com-
about IEEE
puter Science and Software Computer
Eng.), Duhok, Iraq Society
• ICDM (IEEE Int’l Conf. on Data
Mining), virtual
conferences
• RTSS (IEEE Real-Time Sys-
computer.org/conferences
tems Symposium), Dortmund,
Germany
IEEE COMPUTER SOCIETY ELECTION

Volunteer Leadership

Is Vital
Vote by Monday, 20 September at 12PM EDT

www.computer.org/election2021