LM833

Low Noise, Audio Dual

Operational Amplifier
The LM833 is a standard low−cost monolithic dual general−purpose
operational amplifier employing Bipolar technology with innovative
high−performance concepts for audio systems applications. With high
frequency PNP transistors, the LM833 offers low voltage noise http://onsemi.com
(4.5 nV/ Hz ), 15 MHz gain bandwidth product, 7.0 V/ms slew rate,
0.3 mV input offset voltage with 2.0 mV/°C temperature coefficient of
input offset voltage. The LM833 output stage exhibits no dead−band MARKING
crossover distortion, large output voltage swing, excellent phase and DIAGRAMS
gain margins, low open loop high frequency output impedance and 8
symmetrical source/sink AC frequency response.
PDIP−8 LM833N
For an improved performance dual/quad version, see the MC33079 AWL
N SUFFIX
family. CASE 626 YYWWG

Features 1 1

• Low Voltage Noise: 4.5 nV/ ǸHz LM833N = Device Code

A = Assembly Location
• High Gain Bandwidth Product: 15 MHz WL = Wafer Lot
• High Slew Rate: 7.0 V/ms YY = Year
WW = Work Week
• Low Input Offset Voltage: 0.3 mV G = Pb−Free Package
• Low T.C. of Input Offset Voltage: 2.0 mV/°C
• Low Distortion: 0.002%
• Excellent Frequency Stability
LM833
SOIC−8
• Dual Supply Operation D SUFFIX ALYW
G
• Pb−Free Packages are Available CASE 751
1
1
MAXIMUM RATINGS
LM833 = Device Code
Rating Symbol Value Unit A = Assembly Location
Supply Voltage (VCC to VEE) VS +36 V L = Wafer Lot
Y = Year
Input Differential Voltage Range (Note 1) VIDR 30 V W = Work Week
Input Voltage Range (Note 1) VIR ±15 V G = Pb−Free Package

Output Short Circuit Duration (Note 2) tSC Indefinite

Operating Ambient Temperature Range TA −40 to +85 °C PIN CONNECTIONS

Operating Junction Temperature TJ +150 °C

Output 1 1 8 VCC
Storage Temperature Tstg −60 to +150 °C
ESD Protection at any Pin Vesd V 2 1 7 Output 2
− Human Body Model 600
Inputs 1
− Machine Model 200
3 6
Maximum Power Dissipation (Notes 2 and 3) PD 500 mW 2 Inputs 2
Maximum ratings are those values beyond which device damage can occur. VEE 4 5
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are (Top View)
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Either or both input voltages must not exceed the magnitude of VCC or VEE. ORDERING INFORMATION
2. Power dissipation must be considered to ensure maximum junction
temperature (TJ) is not exceeded (see power dissipation performance See detailed ordering and shipping information in the package
characteristic). dimensions section on page 6 of this data sheet.
3. Maximum value at TA ≤ 85°C.

© Semiconductor Components Industries, LLC, 2005 1 Publication Order Number:

December, 2005 − Rev. 5 LM833/D
 LM833

ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, TA = 25°C, unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Input Offset Voltage (RS = 10 W, VO = 0 V) VIO − 0.3 5.0 mV
Average Temperature Coefficient of Input Offset Voltage DVIO/DT − 2.0 − mV/°C
RS = 10 W, VO = 0 V, TA = Tlow to Thigh
Input Offset Current (VCM = 0 V, VO = 0 V) IIO − 10 200 nA
Input Bias Current (VCM = 0 V, VO = 0 V) IIB − 300 1000 nA
Common Mode Input Voltage Range VICR − +14 +12 V
−12 −14 −

Large Signal Voltage Gain (RL = 2.0 kW, VO = ±10 V) AVOL 90 110 − dB
Output Voltage Swing: V
RL = 2.0 kW, VID = 1.0 V VO+ 10 13.7 −
RL = 2.0 kW, VID = 1.0 V VO− − −14.1 −10
RL = 10 kW, VID = 1.0 V VO+ 12 13.9 −
RL = 10 kW, VID = 1.0 V VO− − −14.7 −12

Common Mode Rejection (Vin = ±12 V) CMR 80 100 − dB

Power Supply Rejection (VS = 15 V to 5.0 V, −15 V to −5.0 V) PSR 80 115 − dB
Power Supply Current (VO = 0 V, Both Amplifiers) ID − 4.0 8.0 mA

AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, TA = 25°C, unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Slew Rate (Vin = −10 V to +10 V, RL = 2.0 kW, AV = +1.0) SR 5.0 7.0 − V/ms
Gain Bandwidth Product (f = 100 kHz) GBW 10 15 − MHz
Unity Gain Frequency (Open Loop) fU − 9.0 − MHz
Unity Gain Phase Margin (Open Loop) qm − 60 − °
Equivalent Input Noise Voltage (RS = 100 W, f = 1.0 kHz) en − 4.5 − nVń ǸHz
Equivalent Input Noise Current (f = 1.0 kHz) in − 0.5 − pAń ǸHz
Power Bandwidth (VO = 27 Vpp, RL = 2.0 kW, THD ≤ 1.0%) BWP − 120 − kHz
Distortion (RL = 2.0 kW, f = 20 Hz to 20 kHz, VO = 3.0 Vrms, AV = +1.0) THD − 0.002 − %
Channel Separation (f = 20 Hz to 20 kHz) CS − −120 − dB
PD , MAXIMUM POWER DISSIPATION (mW)

800 1000
IIB , INPUT BIAS CURRENT (nA)

VCC = +15 V
800 VEE = −15 V
600 VCM = 0 V
600
400
400

200
200

0 0
−50 0 50 100 150 −55 −25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C)

Figure 1. Maximum Power Dissipation Figure 2. Input Bias Current versus Temperature
versus Temperature

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 LM833

800 10
VCC
RL = ∞
I IB , INPUT BIAS CURRENT (nA)
IS
TA = 25°C

I S , SUPPLY CURRENT (mA)

8.0 TA = 25°C
600

6.0 VO
+
400 VEE
4.0

200
2.0

0 0
5.0 10 15 20 0 5.0 10 15 20
VCC, |VEE|, SUPPLY VOLTAGE (V) VCC, |VEE|, SUPPLY VOLTAGE (V)

Figure 3. Input Bias Current versus Figure 4. Supply Current versus

Supply Voltage Supply Voltage

110 110
VCC = +15 V
VEE = −15 V RL = 2.0 kW
AVOL, DC VOLTAGE GAIN (dB)

AVOL, DC VOLTAGE GAIN (dB)

RL = 2.0 kW TA = 25°C
105
100

100

90
95

90 80
−55 −25 0 25 50 75 100 125 5.0 10 15 20
TA, AMBIENT TEMPERATURE (°C) VCC, |VEE|, SUPPLY VOLTAGE (V)

Figure 5. DC Voltage Gain Figure 6. DC Voltage Gain versus

versus Temperature Supply Voltage

120 0
AVOL, OPEN LOOP VOLTAGE GAIN (dB)

20
GBW, GAIN BANDWIDTH PRODUCT (MHz)
∅ , EXCESS PHASE (DEGREES)

100
45 15
80

Phase 10
60 90

40 VCC = +15 V VCC = +15 V

VEE = −15 V Gain 135 5.0 VEE = −15 V
RL = 2.0 kW f = 100 kHz
20 TA = 25°C

0 180 0
1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M −55 −25 0 25 50 75 100 125
f, FREQUENCY (Hz) TA, AMBIENT TEMPERATURE (°C)

Figure 7. Open Loop Voltage Gain and Figure 8. Gain Bandwidth Product
Phase versus Frequency versus Temperature

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 LM833

GBW, GAIN BANDWIDTH PRODUCT (MHz)

30 10
f = 100 kHz
TA = 25°C

SR, SLEW RATE (V/ μ s)

8.0 Falling
20
Rising
6.0

10 VCC = +15 V
VEE = −15 V −
Vin + VO
4.0 RL = 2.0 kW RL
AV = +1.0

0 2.0
5.0 10 15 20 −55 −25 0 25 50 75 100 125
VCC, |VEE|, SUPPLY VOLTAGE (V) TA, AMBIENT TEMPERATURE (°C)

Figure 9. Gain Bandwidth Product versus Figure 10. Slew Rate versus Temperature
Supply Voltage

10 35
RL = 2.0k W
AV = +1.0
30

VO , OUTPUT VOLTAGE (Vpp )

8.0 TA = 25°C Falling
SR, SLEW RATE (V/ μ s)

25
6.0 Rising
20
VCC = +15 V
4.0 15 VEE = −15 V
+ VO
− RL = 2.0 kW
Vin RL 10 THD v 1.0%
2.0 TA = 25°C
5.0
0 0
5.0 10 15 20 10 100 1.0 k 10 k 1.0 M 10 M 100 k
VCC, |VEE|, SUPPLY VOLTAGE (V) f, FREQUENCY (Hz)

Figure 11. Slew Rate versus Supply Voltage Figure 12. Output Voltage versus Frequency

20 15
V sat , OUTPUT SATURATION VOLTAGE |V|

RL = 10 kW VO +
15 TA = 25°C +Vsat
VO, OUTPUT VOLTAGE (Vpp )

10
5.0
−Vsat
14
0
−5.0

−10 VCC = +15 V

VO − VEE = −15 V
−15 RL = 10 kW
−20 13
5.0 10 15 20 −55 −25 0 25 50 75 100 125
VCC, |VEE|, SUPPLY VOLTAGE (V) TA, AMBIENT TEMPERATURE (°C)

Figure 13. Maximum Output Voltage Figure 14. Output Saturation Voltage
versus Supply Voltage versus Temperature

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 LM833

PSR, POWER SUPPLY REJECTION (dB)

140 160

CMR, COMMON MODE REJECTION (dB)

VCC = +15 V DVCC DVCM −
120 VEE = −15 V − 140 ADM
TA = 25°C ADM + DVO
+ DVO
100 DVEE 120 DVCM
CMR = 20 Log × ADM
DV0
80 100
−PSR +PSR
60 80 VCC = +15 V
DVO/ADM VEE = −15 V
40 +PSR = 20 Log ( DVCC ) 60 VCM = 0 V
DVCM = ±1.5 V
20
−PSR = 20 Log ( DVDVO/AEEDM ) 40 TA = 25°C

0 20
100 1.0 k 10 k 100 k 1.0 M 10 M 100 1.0 k 10 k 100 k 1.0 M 10 M
f, FREQUENCY (Hz) f, FREQUENCY (Hz)

Figure 15. Power Supply Rejection Figure 16. Common Mode Rejection
versus Frequency versus Frequency
THD, TOTAL HARMONIC DISTORTION (%)

1.0 10

e n, INPUT NOISE VOLTAGE (nV/√ Hz )

VCC = +15 V
−
VO VEE = −15 V
+
RL RL = 2.0 kW
0.1 TA = 25°C 5.0

VCC = +15 V
VEE = −15 V
0.01 VO = 1.0 Vrms RS = 100 W
2.0 TA = 25°C

VO = 3.0 Vrms
0.001 1.0
10 100 1.0 k 10 k 100 k 10 100 1.0 k 10 k 100 k
f, FREQUENCY (Hz) f, FREQUENCY (Hz)

Figure 17. Total Harmonic Distortion Figure 18. Input Referred Noise Voltage
versus Frequency versus Frequency

2.0 100
VCC = +15 V
i n , INPUT NOISE CURRENT (pA/√ Hz )

VCC = +15 V
e n, INPUT NOISE VOLTAGE (nV/√ Hz )

VEE = −15 V VEE = −15 V

TA = 25°C Vn(total) = (inRS)2 +en2 + Ǹ
4KTRS
1.0 TA = 25°C

0.7
10
0.5
0.4

0.3

0.2 1.0
10 100 1.0 k 10 k 100 k 1.0 10 100 1.0 k 10 k 100 k 1.0 M
f, FREQUENCY (Hz) RS, SOURCE RESISTANCE (W)

Figure 19. Input Referred Noise Current Figure 20. Input Referred Noise Voltage
versus Frequency versus Source Resistance

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 LM833

VO , OUTPUT VOLTAGE (5.0 V/DIV) VCC = +15 V VCC = +15 V

VO , OUTPUT VOLTAGE (5.0 V/DIV)

VEE = −15 V VEE = −15 V
RL = 2.0 kW RL = 2.0 kW
CL = 0 pF CL = 0 pF
AV = −1.0 AV = +1.0
TA = 25°C TA = 25°C

t, TIME (2.0 ms/DIV) t, TIME (2.0 ms/DIV)

Figure 21. Inverting Amplifier Figure 22. Noninverting Amplifier Slew Rate

VCC = +15 V
VO , OUTPUT VOLTAGE (10 mV/DIV)

VEE = −15 V
RL = 2.0 kW
CL = 0 pF
AV = +1.0
TA = 25°C

t, TIME (200 ns/DIV)

Figure 23. Noninverting Amplifier Overshoot

ORDERING INFORMATION
Device Package Shipping †
LM833N PDIP−8
LM833NG PDIP−8 50 Units / Rail
(Pb−Free)

LM833D SOIC−8
LM833DG SOIC−8 98 Units / Rail
(Pb−Free)

LM833DR2 SOIC−8
LM833DR2G SOIC−8 2500 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.

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 LM833

PACKAGE DIMENSIONS

SOIC−8
D SUFFIX
CASE 751−07
ISSUE AG

NOTES:
−X− 1. DIMENSIONING AND TOLERANCING PER
A ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
8 5 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
B S 0.25 (0.010) M Y M 5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
1 PROTRUSION SHALL BE 0.127 (0.005) TOTAL
4 IN EXCESS OF THE D DIMENSION AT
−Y− K MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
G
MILLIMETERS INCHES
C N X 45 _ DIM MIN MAX MIN MAX
A 4.80 5.00 0.189 0.197
SEATING B 3.80 4.00 0.150 0.157
PLANE
C 1.35 1.75 0.053 0.069
−Z− D 0.33 0.51 0.013 0.020
0.10 (0.004) G 1.27 BSC 0.050 BSC
H M J H 0.10 0.25 0.004 0.010
D J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0_ 8_ 0 _ 8 _
0.25 (0.010) M Z Y S X S N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244

SOLDERING FOOTPRINT*

1.52
0.060

7.0 4.0
0.275 0.155

0.6 1.270
0.024 0.050

SCALE 6:1 ǒinches

mm Ǔ

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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 LM833

PACKAGE DIMENSIONS

PDIP−8
N SUFFIX
CASE 626−05
ISSUE L

NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
8 5 FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
−B− 3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
1 4
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 9.40 10.16 0.370 0.400
F B 6.10 6.60 0.240 0.260
C 3.94 4.45 0.155 0.175
NOTE 2 −A− D 0.38 0.51 0.015 0.020
L F 1.02 1.78 0.040 0.070
G 2.54 BSC 0.100 BSC
H 0.76 1.27 0.030 0.050
J 0.20 0.30 0.008 0.012
C K 2.92 3.43 0.115 0.135
L 7.62 BSC 0.300 BSC
M −−− 10 _ −−− 10_
−T− J N 0.76 1.01 0.030 0.040
SEATING N
PLANE
M
D K
H G
0.13 (0.005) M T A M B M

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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