UNIVERSITY OF LIMERICK
OLLSCOIL LUIMNIGH
COLLEGE OF INFORMATICS & ELECTRONICS
DEPARTMENT OF ELECTRONIC & COMPUTER ENGINEERING
MODULE CODE:
MODULE TITLE:
SEMESTER:
DURATION OF EXAM:
LECTURER:
INSTRUCTIONS TO CANDIDATES:
DETERMINATION OF FINAL MARK:
ED5532
Computer Systems Architecture
Spring 2004
2½ Hours
Dr. Karl Rinne
Use of a non-programmable pocket calculator is
permitted.
Exam is composed of two parts: Part A and Part B.
Both parts must be completed.
Part A is composed of 60 multiple choice questions
worth a total of 60 marks. One mark is given for each
correct answer. Do not tick any answers on the exam
paper. Write the answers on your script (for example
1d, 2a, 3c, and so on). Negative marking does not
apply to this section.
Part B: Answer two questions out of B1, B2 and B3.
Questions B1, B2 and B3 carry the same number of
marks (40 marks each). Attempt no more than two
questions from this section.
Examination: 80%
(60 marks + 80 marks=140 marks)
Lab/Assignment: 20%
(35 marks)
Total: 100%
(175 marks)
1 of 8
ED5532: Comp. Sys. Architecture Spring 2004 Dr. Karl Rinne

Part A Multiple Choice Exam Marks:

In this section each of the following questions has only one correct answer. One
mark is given for each correct answer. Negative marking does not apply. Do not Total: 60
tick any answers on the exam paper. Write the answers on your script (for
example 1d, 2a, 3c, and so on).
1) In a microprocessor, what is the main task of a) Generation of address latch signal ALE
an ALU? b) Processing arithmetic/logic operations
c) Advanced loop control
d) Address list generation
2) Which of the following buses would not be a) Address bus
commonly found in a microprocessor b) Interrupt bus
system? c) Data bus
d) Control bus
3) Which of the following functional blocks a) Instruction decoder
would not be found in a typical b) Registers
microprocessor? c) Address/data de-multiplexer
d) ALU
4) Which of the following load/retrieve a) FIFO
methods best describes a microprocessor b) LILO
stack? c) LIFO
d) Ring buffer
5) How many memory locations can be a) 16k
addressed by a microprocessor with 20 b) 64k
address lines? c) 1M
d) 16M
6) Which of the following control signals a) Refresh
would be provided to a static RAM b) DMA request
component? c) Write Enable
d) Interrupt request
7) Which of the following is typically required a) High current to blow the ROM fuses
to program EPROM cells? b) Relatively high programming voltage Vpp
c) Block write signal
d) UV light
8) Which of the following is supported by the a) Memory-mapped I/O
Intel microprocessor architecture? b) Separate memory and I/O mapping
c) I/O-mapped memory
d) Random access mapping
9) Which of the following is a disadvantage of a) Extremely slow I/O access
memory-mapped I/O? b) Larger processor instruction set
c) One set of read/write control lines
d) Blocks of address space taken by I/O
10) Which of the following is required to prevent a) Address decoding and device selection
signal contention in a system with multiple b) Wait states
memory devices connected to a data bus? c) Pull-up resistors
d) Termination
11) Which of the following is not a terminal of a a) Data input
simple tristate buffers? b) Data output
c) Latch enable
d) Output enable
12) The 27C4002 is a 4Mb EPROM device a) 8
organised as 256k x 16b. How many address b) 16
bus lines do you expect the device to have? c) 18
d) 32

2 of 8
ED5532: Comp. Sys. Architecture Spring 2004 Dr. Karl Rinne

13) In modern computer systems what type of a) Discrete logic gates

device typically carries out the address b) Discrete 3-to-8 decoders
decoding? c) Memory devices
d) Application specific IC or PLD
14) The time it takes a memory device to a) Access time
respond to valid address and chip-enable b) Set-up time
signals is called… c) Hold time
d) Acknowledge time
15) For which cycles can wait states typically be a) Memory read cycles
inserted? b) Only in memory write cycles
c) Memory and I/O read/write cycles
d) Only in memory read/write cycles
16) Interrupts can be requested by a) Address decoder
b) Tristate buffers
c) Hardware as well as software
d) Slow memory devices
17) How many bytes in a 1kB? a) 998
b) 1000
c) 1001
d) 1024
18) Which of the following techniques supports a) DMA
fast transfer of blocks of data? b) NMI
c) HDL
d) FIFO
19) Which of the following operating modes is a) Real mode
entered by Intel x86 processors after reset? b) Protected mode
c) Virtual real mode
d) RISC mode
20) Working registers in the Intel 8086 can be a) 8b registers
accessed as b) 16b registers
c) 8b as well as 16b registers
d) 32b registers
21) The Intel 80286 is a… a) 8-bit microprocessor
b) 16-bit microprocessor
c) 32-bit microprocessor
d) 64-bit microprocessor
22) For integer data which data format is used by a) Big endian
Intel x86 microprocessors? b) Medium endian
c) Floating point
d) Little endian
23) The 8086 microprocessor uses an instruction a) Determine the priority of instructions
queue in order to… b) Increase processing performance
c) Implement a super-scalar architecture
d) Avoid data inter-dependency
24) In a modern microprocessor what typically a) Processor power dissipation
limits the clock frequency the processor can b) Memory access time
be clocked at? c) Processor test equipment
d) Operating system limitations
25) Why did the 8088 have an external 8b data a) To reduce system cost
bus? b) To speed up I/O access
c) To increase data bus bandwidth
d) To be compatible with Motorola 68000
26) Assume Intel 8086 real mode: The offset is a) 0A1E6h
0C4h. The segment register contains b) 0A12E4h
0A122h. What is the resulting physical c) 0AD62h
address? d) 0A12C4h

3 of 8
ED5532: Comp. Sys. Architecture Spring 2004 Dr. Karl Rinne

27) The Intel Pentium can access its accumulator a) 8b registers AH and AL
register as b) 16b register AX
c) 32b register EAX
d) all of the above
28) What purpose does the #BHE signal serve in a) Enables access to high byte of word
an 8086 system? b) Enables access to low byte or word
c) Enables access high bus
d) Bus halt enable
29) Why does the 8086 have a multiplexed a) Increases performance
address and data bus? b) Reduces processor package cost
c) Simplifies external circuitry
d) Eases system trouble-shooting
30) The 8086 has a multiplexed address and data a) Transparent latches
bus. De-multiplexing is typically achieved b) Bus transceivers
using… c) Bus controllers
d) Clock generators
31) An 8086 bus cycle takes at least 4 clock a) 0.5MB/s
cycles to complete. If the processor is b) 1MB/s
clocked at 2MHz, what would be the c) 2MB/s
maximum data rate of the data bus? d) 4MB/s
32) Which of the following is not a feature of the a) Fully 8086 backwards compatible
Intel 80286 processor? b) 16MB addressable physical memory
c) On-chip mathematical co-processor
d) Support of real mode and protected mode
33) Protected mode in the 80286 was a) Fast 3D graphics
implemented to support… b) Multitasking operating systems
c) Cache memories
d) Internet security
34) How much physical memory can be a) 64kB
addressed by an 80386 processor in the b) 1MB
native mode? c) 16MB
d) 4GB
35) How does the 80386 perform floating-point a) Software emulation
operations in the absence of an 80387 co- b) MMX
processor? c) SIMD
d) SSE
36) Which of the following techniques was a) Reduction of instruction set
extensively used to implement the 80386? b) Micro-encoding of machine instructions
c) Hard-wired machine instructions
d) On-chip cache
37) Which of the following blocks would not be a) Bank of registers
found on a traditional RISC microprocessor? b) Instruction pipeline
c) Microcode execution unit
d) ALU
38) Super-scalar processors… a) do not have data dependency issues
b) avoid pipeline flushes
c) may execute instructions in parallel
d) directly interface to DDR memory
39) Which of the following problems is regularly a) Stack overflow due to recursion
encountered when dealing with instruction b) Register dependency
pipelines? c) Micro-encoded instructions
d) Hard-wired instructions
40) The Intel Pentium II processor is a… a) 16-bit processor
b) 32-bit processor
c) 64-bit processor
d) 128-bit processor

4 of 8
ED5532: Comp. Sys. Architecture Spring 2004 Dr. Karl Rinne

41) What is the width of the external data bus of a) 16b

a Pentium processor? b) 32b
c) 64b
d) 128b
42) How did the 80486 achieve a boost in a) 16b registers extended to 32b
performance over the 80386? b) Non-multiplexed data bus
c) Improved memory management
d) Many instructions hardwired
43) What is the result if the Pentium processor a) Slower access to data
tries to access data stored in memory, which b) General protection fault
is not aligned according to alignment rules? c) Misalignment interrupt
d) System reset
44) Under best conditions how many instructions a) 1
can a Pentium processor complete per clock b) 2
cycle? c) 4
d) 8
45) In burst mode a Pentium can transfer 256 a) 640MB/s
data bits in 5 clock cycles (2-1-1-1 burst). b) 640Mb/s
What is the theoretical data bus bandwidth if c) 25600MB/s
the processor is clocked at 100MHz? d) 25600Mb/s
46) Pentium BTB branch predictions are based a) EAX register content
on what? b) Branch repetition rate
c) Status flags
d) Past branch history
47) What does “SIMD” stand for? a) Standard interface memory device
b) Standard interface magnetic device
c) Single instruction memory dump
d) Single instruction multiple data
48) Which of the following buses would not be a) PCI bus
found in PC anymore? b) MCA bus
c) ISA bus
d) Front-side bus
49) Which of the following memory types would a) Asynchronous DRAM
support fastest sequential access? b) Synchronous DRAM
c) Synchronous DDR DRAM
d) Asynchronous EPROM
50) Which of the following may be a a) Erasable only using UV light
disadvantage of flash memory devices? b) Not erasable at all
c) Erasable through high-current pulses
d) Erasable typically only on a sector basis
51) What is the maximum continuous-write data a) 11MB/s
rate for a 32-bit PCI bus clocked at 33MHz? b) 33MB/s
c) 44MB/s
d) 132MB/s
52) Why does the AGP bus offer higher data a) Because it is used by visual devices only
rates when compared to PCI? b) Because it features DDR
c) Because it uses flash memory devices
d) Because it transmits data serially
53) Which of the following chip-set architectures a) North/South bridge architecture
is used in recent PCs? b) Hub architecture
c) East/West bridge architecture
d) VESA architecture
54) Which of the following may be a major a) Lower EMI
advantage of AGP? b) Less local video memory required
c) Less cache memory required
d) Easier to program

5 of 8
ED5532: Comp. Sys. Architecture Spring 2004 Dr. Karl Rinne

55) Which unit is used to increase the speed of a) Translation lookaside buffer
access to memory pages? b) PCI bus master
c) Instruction pipeline
d) Page directory
56) For which of the following is the Pentium a) Highly reliable systems
data bus optimised? b) DDR memory devices
c) Low cost
d) Fast cache line fills
57) Which mode of data transfer from memory a) Burst mode
to cache is used by the Pentium processor? b) DDR mode
c) Synchronous transfer mode
d) Asynchronous transfer mode
58) Which of the following statements is not a) determines which processors can be used
true. The motherboard chipset of a PC… b) determines processor clock frequency
c) determines the maximum amount of
system memory
d) determines the maximum amount of on-
chip processor cache memory
59) What is the width of MMX registers? a) 16-bit
b) 32-bit
c) 64-bit
d) 128-bit
60) Which of the following units would not be a) Level-1 cache
found within a Pentium 4 processor? b) Level-2 cache
c) MMX
d) USB Hub

6 of 8
ED5532: Comp. Sys. Architecture Spring 2004 Dr. Karl Rinne

Part B Marks:
Answer any two questions out of B1, B2 and B3 40 per
question

B1: Advanced Microprocessor Techniques Marks

B1.1 Figure 1 is an incomplete sketch illustrating the operation of a typical 8

instruction pipeline. Complete the sketch, and briefly explain the stages
(phases) of the instruction pipeline.

B1.2 Explain the primary aim of an instruction pipeline, and – using your 8
sketch – show how this aim is achieved.

B1.3 Explain briefly the function of a instruction prefetch buffer, and 8

describe how the instruction pipeline interacts with the instruction
prefetch buffer.

B1.4 Discuss the pipeline problem a conditional jump instruction is causing. 8

How has this problem been solved in Pentium processors?

B1.5 Discuss briefly how processor performance can be further improved by 8

an instruction cache memory. Briefly characterise the on-chip cache
memory of the latest Pentium 4 processors.

Stage IF Stage D Stage OF Stage E Stage WB

Instruction Stage

Instruction k Instruction k-1 Instruction k-2 Instruction k-3 Instruction k-4

n
n+1

Instruction k+1 Instruction k Instruction k-1 Instruction k-2 Instruction k-3

n+2

Instruction k+2 Instruction k+1 Instruction k Instruction k-1 Instruction k-2

n+3

Instruction k+3 Instruction k+2 Instruction k+1 Instruction k Instruction k-1

n+4

Instruction k+4 Instruction k+3 Instruction k+2 Instruction k+1 Instruction k Result k

Clock Cycle

Figure 1: Instruction Pipeline

7 of 8
ED5532: Comp. Sys. Architecture Spring 2004 Dr. Karl Rinne

B2: PC System Hardware and Interfaces Marks

B2.1 Assume your PC is equipped with the following external interfaces: 15

USB (2.0), Standard Parallel (EPP compliant supporting bi-directional
data transfer), Standard Serial RS-232-C. List and briefly explain five
advantages and five disadvantages for each of the interfaces.

B2.2 Suppose you’d like to transmit 10MB of data from a slave (e.g. a digital 12
camera) to your PC. Estimate the time required for each of the
interfaces. For USB, assume a continuous HS bulk transfer. For the EPP
parallel port, assume a constant data rate of 2MB/s. For the RS-232-C
port, assume continuous transmission at 9.6kBd (no parity, 1 stop bit).

B2.3 Assume a typical PC keyboard (102 keys) connected to the PC through 13

a PS/2 compliant interface. Sketch and explain how the keyboard
controller determines the states of the keys. Sketch and briefly discuss
how the keyboard controller transmits this information to the PC.

B3: PC Architecture and Buses Marks

B3.1 In a modern PC you would find a “Front Side Bus (FSB)”. Briefly 8
explain this bus. Assume a state-of-the-art system, and estimate the
peak data bandwidth of the FSB.

B3.2 Draw a block diagram of the north/south bridge chipset architecture. 12

Briefly explain the blocks, and point out the main buses.

B3.3 Show how expansion bus standards have evolved from first generation 12
PCs to state-of-the-art PCs. List major disadvantages for each of the
PCI bus predecessors.

B3.4 Why has PCI a multiplexed address/data bus? Explain under which 8
circumstances a 32b PCI bus clocked at 33MHz still achieves a data
bandwidth of about 132MB/s.

8 of 8