EMBEDDED SYSTEMS

BY
VARISA SASIBHUSHANARAO
ASSISTANT PROFESSOR,
DEPARTMENT
OF
ELECTRONICS AND COMMUNICATION
ENGINEERING,
RAJIV GANDHI UNIVERSITY OF KNOWLEDGE
TECHNOLOGIES - SRIKAKULAM
EMBEDDE SYSTMES

❑ Embedded system is a combination of hardware

and software that designed to do specific
function/functions.

”Controller of a Larger system”

CHARACTERISTICS

❑ Sophisticated functionality

❑ Real time operation

❑ Application dependence processor

❑ Restricted memory
❑ Low power consumption

❑ Dedicated system
❑ Low manufacturing cost
TYPES OF EMBEDDED SYSTEMS

❑ Similar to general Computing

Personal Digital Assistant, Video games, set top boxes,
ATM
❑ Control Systems
Flight control, Nuclear reactor, vehicle engines
❑ Signal processing
Radar, Sonar, DVD players
❑ Communication and networking
Cellular
BASIC STRUCTURE OF AN EMBEDDED SYSTEM
ARCHITECTURE:
IMPLEMENTING EMBEDDED SYSTEM:

HARDWARE
❑ Processing elements
❑ Peripherals
Input and output devices
Interfacing sensors and actuators
Interfacing protocols
Memory
Bus
SOFTWARE
❑ System Software
❑ Application Software
ESSENTIAL COMPONENTS OF PROCESSOR

❑ Program Flow Control Unit (CU)

❑ Execution Unit (EU)

Types of Processors
❑ General Purpose Processor (GPP)
Microprocessor
Microcontroller
Embedded Processor
Digital Signal Processor
Media Processor
❑ Application Specific System Processor (ASSP)
❑ Application Specific Instruction Processors (ASIPs)
❑ GPP core(s) or ASIP core(s) on either an Application Specific
Integrated Circuit (ASIC) or a Very Large Scale Integration (VLSI)
circuit.
EMBEDDED HARDWARE

❑ Embedded hardware is used for processing of input to

produce output in task specific fashion
MICROPROCESSOR
MICROCONTROLLERS

❑ PIC micro-controller

❑ ARM micro-controller
What is microcontroller?

❑ Microcontroller is a device which integrates a number

of components of a microprocessor system onto a
single microchip.
❑ A microcontroller combines on to the same microchip:
The CPU Core
Memory(RAM&ROM)
Parallel Digital I/O and more
COMPONENTS OF MICROCONTROLLER

❑ Timer Module
To allow the microcontroller to perform tasks for a
certain time period
❑ Serial I/O Port
To allow data to flow between the microcontroller and
other devices
❑ Analogue to Digital Converter(ADC)
To allow the microcontroller to accept analogue input
data for processing
Why Microcontroller?

❑ Low cost, Small packaging

❑ Low power consumption

❑ Programmable, Re-programmable

❑ I/O Capabilities
❑ Easy integration with circuits
❑ For applications in which cost, power and area are
critical

❑ Single purpose
Von Neumann and Harvard Architecture
Von Neumann Architecture
Harvard Architecture
CISC-COMPLEX INSTUCTION SET COMPUTER

❑ A Large number of instructions each carrying out a

different permutation of the same operation

❑ Instructions provide for complex operation

❑ Different instructions of different format
❑ Different instructions of different Length

❑ Different Addressing modes

❑ Requires multiple cycles for execution
RISC-REDUCED INSTUCTION SET COMPUTER

❑ Instructions for simple operations that can be executed

in a single cycle
❑ Each instruction is of fixed length
Facilitates Instruction pipelining
❑ Large general purpose instruction set
Can contain data or address
❑ Load-store Architecture
No memory access for data processing instructions
 PIC MICROCONTROLLER
❑ Peripheral Interface Controller

❑ PIC’s are “RISC”

❑ Have few instructions(<50)

❑ Execute 1 instruction with 1 internal clock cycle

The PIC Family Packages:

❑ PICs comes in huge variety of packages:

8pin : 12c50x(12-bit),12c67x(14-bit)
14pin : 16c5x(12-bit),16cxxx(14-bit)

28pin : 16c5x(12-bit),16cxxx(14-bit)
40 pin : 16cxxx(12-bit),17c4x(16-bit)
44-68 pin: 16cxxx(12-bit),17c4x(16-bit)
FAMILIES OF 8-BIT PIC MICROCONTROLLERS

❑ BASE LINE PIC

❑ MID-RANGE PIC
❑ ENHANCED MID-RANGE PIC

❑ PIC 18
 BASE LINE PIC

❑ Least complex PIC controller

❑ 12-bit instruction architecture
❑ Smallest and less cost PIC
❑ Available with 6 to 40 pin packaging
❑ Replaced the traditional IC’s like 555,Logic gates etc..
❑ Include the PIC10F family and proportion of the PIC12
and PIC16 families.
 MID-RANGE PIC

❑ Small Package footprints

❑ 14-bit instruction architecture
❑ Work up to 20MHz frequency
❑ Available with 8 to 64 pin packaging
❑ Available with different peripherals:
ADC,PWM,OP-AMPS and different communication
protocols like UART,SPI,12C(TWI)
❑ Includes PIC 12 and PIC 16 families
❑ Available with FLASH and OTP program memory
options
❑ The flash produces an operating voltage range of
2v-5.5v
 ENHANCED MID-RANGE PIC

❑ Enhanced version of Mid-range type core

❑ Provides additional performance

❑ Greatest Flash memory

❑ High speed at less power consumption

❑ Includes multiple peripherals and support protocols:
USART,SPI and 12C etc..
 PIC 18

❑ 16-bit instruction architecture

❑ The highest performer in the all 8-bit PIC families
❑ Available with 18-80 pin package options
❑ 10MIPS operating performance
❑ Integrated with new age protocols:
USB, CAN, IAN, Ethernet
❑ Two stage instruction pipeline
❑ Supports the connectivity of human interface
devices:
Segmented LCDs and mTOUCH sensing
PIC 8-BIT FAMILIES
MID-RANGE PIC ARCHITECTURE
 SPEED

❑ PIC’s require a clock to work

❑ May use crystal oscillators, clock oscillators or an RC
circuit.
❑ Some PIC’s have a built in 4 MHz RC clock
Not very accurate, but requires no external
components
❑ Instruction Speed = ¼ clock Speed
Tcyc = 4 *Tclk

TYPE OF PIC CONTROLLER Clock Frequency

12C50X 4MHz
12C67X 10MHz
16CXXX 20MHz
15C4X/17C7XXX 33MHz
18CXXX 40MHz
CLOCKING SCHEME
 INSTRUCTION EXECUTION

❑ Clock internally divided by 4 to generate 4

quadrate clocks

❑ Instruction cycle consist of 4Q cycles

❑ PC incremented every Q1
❑ Instruction is fetched from program and latched
into instruction register by Q4

❑ Instruction is decoded and executed in the

following Q1 to Q4
 INSTRUCTION PIPELINING

❑ Fetch takes one cycle, decode and execute takes

another cycle

❑ While execution, next instruction can be fetched

No bus conflict due to Harvard architecture
❑ If instruction changes PC extra cycle is required to
complete instruction
ALU
 STATUS REGISTER

❑ Status register contains

Arithmetic status of ALU operation
RESET status
Memory bank select bits
 MEMORY ORGANIZATION

❑ Program Memory
❑ Data Memory
❑ Access to both possible in each cycle because of
distinct buses
❑ EPROM(Erasable Programmable Read Only Memory)
One time programmable chips are EPROM chips, but
with no window
PIC’s: Any ‘C’ part: 12C50X,17C7XX etc..
 PROGRAM MEMORY

❑ FLASH
Rewritable(even by chip itself)
Much faster to develop
Finite number of writes(100K writes)
PIC’s: Any ‘F’ part: 16F84, 16F87X, 18FXXX
❑ PIC Program space is different for each chip.
❑ Mid range PIC processors have 13 bit Program Counter
❑ Width of program memory bus 14 bits
❑ Program memory space divided into 4 pages of 2K each
 STACK AND REGISTERS

❑ Mid range PIC 8- level deep 13 bit wide hardware stack

Not part of program or data memory
❑ PC is pushed onto stack when CALL instruction is
executed or interrupt occurs
❑ Register file Memory consists of two components
General Purpose register(GPR) files
Special Purpose register(SPR) files
❑ GPR: Area banked to provide greater than 96 bytes of
general purpose RAM
❑ SFR: To control the peripheral and core functions like
indirect addressing
 DATA MEMORY

PIC’s use general purpose file registers for RAM(each

register is 8 bits for all PIC’s)

❑ Programs are stored in program space so low RAM

space

❑ Memory organized into banks