University of the West Indies

Faculty of Engineering

ENGR2105
Engineering and Laboratory Design III

Laboratory #2

FPGA Programming and Simulation Using Xilinx ISE

Issued Date: February xx, 2021

Due Date: February xx, 2021

Faculty of Engineering, Mona ENGR2105 Lecturer: Lindon Falconer

Contents
1 Objectives.................................................................................................................................. 2
2 Pre Laboratory Preparation........................................................................................................ 2
3 Laboratory Activities .................................................................................................................. 2
3.1 Getting familiar with Xilinx ISE Programming and Simulation tools. .................................... 2
3.1.1 Activity - Xilinx ISE VHDL and Simulator Tutorial.......................................................... 2
3.2 Simulate four-bits Adder digital circuit ............................................................................... 3
3.2.1 Activity – Four Bits Adder VHDL Code Synthesis and Simulation .................................. 3
3.3 Create and simulate 4-bits adder and subtractor. ............................................................... 4
3.4 Implement 4-Bits Adder Subtractor using FPGA, DIP switches, LEDs, and push buttons ...... 5

1 Objectives

 To become familiar with a Xilinx ISE design software.

 To write VHDL code for implementing Digital Circuits.
 To compile and simulate VHDL code using Xilinx ISE design software.

2 Pre Laboratory Preparation

 Review VHDL programming, half-adder, full-adder and a 4-bit adder.
 Install Xilinx ISE Webpack Design Software (https://www.xilinx.com/products/design-
tools/ise-design-suite/ise-webpack.html). This software is installed and on all the computers
in the Faculty of Engineering computer laboratory. NB: Only install if you have a Core i5
processor or equivalent with a minimum of 8G RAM and over 100G free hard drive space.
 Download the following files from ENGVLE located in course ENGR2105: FourBitAdder.vhd,
full_adder.vhd, halfAdder.vhd, test_FourBitAdder.vhd.

3 Laboratory Activities
3.1 Getting familiar with Xilinx ISE Programming and Simulation tools.
In this section, the student will create a VHDL code for a simple digital circuit, synthesise it and
conduct simulation using a test bench written in VHDL and Xilinx Simulator (ISIM) application.

3.1.1 Activity - Xilinx ISE VHDL and Simulator Tutorial

1. Open file “Xilinx ISE VHDL and Simulator Tutorial V 14.7.pdf”(download from ENGVLE) and
follow the step by step tutorial.

Faculty of Engineering, Mona ENGR2105 Lecturer: Lindon Falconer

3.2 Simulate four-bits Adder digital circuit
In this section, students will simulate a four bits adder digital circuit in VHDL using a half-adder and
full-adder. The VHDL codes for a four-bit adder, full adder and half adder are provided in files
FourBitAdder.vhd, full_adder.vhd and halfAdder.vhd respectively. These files can be downloaded
from ENGVLE.

3.2.1 Activity – Four Bits Adder VHDL Code Synthesis and Simulation
1. Create a new VHDL project “FourBitAdder” using the procedure in the Xilinx ISE tutorial in
Section 3.1.
2. Copy VHDL files (FourBitAdder.vhd, full_adder.vhd, halfAdder.vhd, and
test_FourBitAdder.vhd) to the project folder.
3. Add the above VHDL files (in step 2) to the current project using “Project-> Add Source”
option from the “Project” menu.
4. Complete the VHDL code in files: FourBitAdder.vhd, full_adder.vhd, and halfAdder.vhd.
5. Synthesise the VHDL project. If errors are generated, fix the errors and resynthesise.
6. Expand the Synthesize tree, as shown in Figure 1. This will show the View RTL Schematics
and View Technology Schematics option.

Questions

1. What does “RTL Schematic” represents?

2. What does “Technology Schematic” represent?
3. Double click on “View RTL Schematic”. Place images of the entity view for FourBitAdder,
full_adder and halfAdder in your laboratory report.
4. Double click on “View Technology Schematic”. Place an image of the technology schematic
for the FourBitAdder in your laboratory report.
5. Double click on one of the “lut3” in the technology schematic.
6. What is contained in lut3?
7. What is a “lut”?
8. Simulate the “FourBitAdder” VHDL project using the procedure in the Xilinx ISE tutorial in
Section 3.1.
9. Place an image of the simulation results in your laboratory report.
10. Discuss the simulation results.

Figure 1: View RTL Schematic and View Technology Schematic

Faculty of Engineering, Mona ENGR2105 Lecturer: Lindon Falconer

3.3 Create and simulate 4-bits adder and subtractor.
In this section, students will create a VHDL code that implements a 4-bits adder and subtractor
circuit. Then synthesise the design and conduct simulation using a test bench written in VHDL and
Xilinx Simulator (ISIM) application.

1. Create a new VHDL project “FourBitAddSub” using the procedure in the Xilinx ISE tutorial in
Section 3.1.
2. Create a FourBitAddSub entity using the logic diagram in Figure 2. The signals “OP”, “NEG”
and “OVF” represent operations negative and overflow, respectively. “A” and “B” are the
four bits input, and “Sum” is the four bits results.
3. The “FourBitAddSub” VHDL module is to be implemented using a structural approach shown
in Figure 3. MUX1 and MUX2 are 2 x 1 multiplexers with select input “C”. When C = 0, the
input on “0” is selected, when C= 1, the input on “1” is selected. When input signal OP = 0,
addition is selected and when OP = 1, subtraction is selected. The OVF/NEG block generates
overflow and negative flags using the Sum, A and B signals. The block coloured in blue is the
four bits adder that you implemented in Section 3.2.
4. Write the VHDL code to implement the “FourBitAddSub” entity.
5. Copy the VHDL files that implement your four-bit adder in Section 3.2 into the folder
containing the current project.
6. Add the above VHDL files (in step 5) to the current project using “Project-> Add Source”
option from the “Project” menu.
7. Synthesise the VHDL project. If errors are generated, fix the errors and resynthesise.
8. Create a test bench using the input signals in Table 1 to simulate the “FourBitAddSub”
implementation.
9. Simulate the “FourBitAddSub” implementation.

A[0-3] Sum[0-3]

B[0-3]
Cout

OP
NEG

Cin OVF

Figure 2: Logic Diagram of 4-bits Adder/Subtractor

Faculty of Engineering, Mona ENGR2105 Lecturer: Lindon Falconer

 Four Bits Adder/Subtractor

Sum
A
A[0-3] Sum[0-3]
0
B MUX1 B[0-3]
1 Cout
Cout
C
OP

C
1
NEG
4-Bits
MUX2 Cin Adder
Cin
0 OVF OVF
NEG
A
B

Figure 2: Internal representation of Adder/Subtractor Module

A B Cin OP
0101 0010 0 0
0101 0010 0 1
0010 0110 0 0
0010 0110 0 1
1101 0111 0 0
1101 0111 0 1
Table 1: Operation to be performed in VHDL Simulation

3.4 Implement 4-Bits Adder Subtractor using FPGA, DIP switches, LEDs, and push
buttons
In this section, students will add a user constraints file (UCF) to the Xilinx VHDL project, generate a
bit file and program the Spartan 3A FPGA. The UCF will enable the mapping of VHDL entity ports to
physical pins on the FPGA on the development board.

1. To display the results from the FourBitAddSub onto LED, add the UCF file to your VHDL
project and modify it to reflect the connections shown in Figure 3 and Table 2.
2. Implement the Design and Generate Programming File for the VHDL project.
3. Connect the ElbertV2 development board to the computer USB port using the USB cable.
4. Start the ElbertV2Config programming application. Select the COM port to which the FPGA
is connected. Select the project Bit file and program the FPGA.
5. Adjust the DIP switches and press the push buttons to select the operations below, as stated
in Table 4. Take pictures of the development board showing the dip switches, pushbuttons
and LEDs.

Faculty of Engineering, Mona ENGR2105 Lecturer: Lindon Falconer

 Four Bits Adder/Subtractor
Sum
A
A[0-3] Sum[0-3]
0
B MUX1 B[0-3]
1 Cout
Cout
C
OP

C
1
NEG
4-Bits
MUX2 Cin Adder
Cin
0 OVF OVF
NEG
A
B

Figure 3: Diagram depicting connection of VHDL entity to I/O modules on the Elbert V2 development
board

Signal NET on Elbert V2 Notes

A DPSwitch[0] - DPSwitch[3] LSB on DPSwitch[0]
B DPSwitch[4] - DPSwitch[5] LSB on DPSwitch[4]
Op Switch[0] Add/Subtract
Ci Switch[1] Carry in
SUM LED[0] – LED[3] LSB on LED[0}
NEG LED[4]
Overflow LED[5]
Table 2: Connection between Entity signals and NET on FPGA Board

Faculty of Engineering, Mona ENGR2105 Lecturer: Lindon Falconer