Tutorial – 4 –

Aug, 2020
Programme : B.Tech – Semester : Interim 2021-2022
Course : Computer Architecture and Organization Code : CSE2003
Faculty : Dr. Trapti Sharma Slot/Class No. : A11
Time : 60min Max. Marks : 10

Answer all the

Questions

Q. No. Question Description Mark

s

1 A 4-way set associative cache memory unit with a capacity of 16 KB is built using a 2
block size of 8 words. The word length is 32 bits. The size of the physical address
space is 4 GB. The number of bits for the TAG field is _____.
2
A two level paging scheme uses a Translation Lookaside buffer (TLB). The effective
2
Memory access takes 170 ns and a main memory access takes 100 ns. Compute the TLB access
time(in ns) if the TLB hit ratio is 70% and there is no page fault.
3 Consider a 4-way set associative cache with 16 cache blocks (0-15). The memory
block requests are in the order-
0, 199, 5, 8, 7, 12, 121, 167, 204, 113, 55, 12, 44, 36, 85, 96, 143, 25
3
Illustrate the mapping process each memory block in the fully associative cache and
list all the even numbered blocks within in the cache memory.
Calculate the hit ratio and miss ratio.
4 3
Consider a machine with 64 MB physical memory and a 32 bit virtual
address space. If the page size is 4 KB, what is the approximate size of
the page table?

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