420
2, MARCH 2004
A Novel ZVS DC/DC Converter for
High Power Applications
Junming Zhang, Fan Zhang, Xiaogao Xie, Dezhi Jiao, and Zhaoming Qian, Senior Member, IEEE
Abstract—This paper presents a novel zero voltage switch
(ZVS) pulse-width modulation (PWM) dc/dc converter for high
power, high output voltage applications. By using two active
switches in the secondary side of a transformer, the proposed
converter achieves not only ZVS of the active switches in the entire
load ranges but also soft commutation of the output rectifier
diodes. The proposed topology has simple structure and control
strategy. Simulation results and experimental results of a 2.8 KW
200 KHz dc/dc converter are presented.
Index Terms—DAB, dc/dc converter, MOSFETs, PWM, SMPS,
ZVS, ZVZCS.
I. INTRODUCTION
F OR FURTHER improvements on efficiency, power den-
sity, electromagnetic noise and performances of switching
mode power supply (SMPS), many voltage mode soft switching
techniques have been proposed [1]–[3] to overcome the dis-
advantages in hard-switching PWM dc/dc converters. Most of
them need one or more auxiliary switches that result in both
complicated topology and complex control strategy, so that the
reliability is also deteriorated. In industry applications, the ZVS
or zero voltage/zero current switched (ZVZCS) full bridge
phase shifted dc/dc converter [4], [5], [11] is more attractive
because of its simplicity of topology and convenient control
strategy. But the interaction between the transformer’s leakage
inductance and the output rectifiers remains unresolved. The
methods used to depress the voltage stress of the rectifiers
either complicate the whole topology or increase the power
dissipation [6], [7]. The reverse recovery problem of the output
rectifier diode becomes even more serious in high output
voltage, high power applications, such as battery charger in
power substations, where the output voltage can reach as high
as 300 V.
To solve the reverse recovery problem, many techniques
have been proposed [3], [8], [9]. By shaping the current in the
secondary to a triangular waveform and clamping the reverse
voltage to the output voltage, the reverse recovery problem
is significantly improved [3], but the penalty is high current
stress for primary side switches and high conduction loss. By
replacing the output rectifier diode with MOSFETs, the dual
active bridge (DAB) topology can realize ZVS of all switches
and synchronous rectifiers at the output side [8], [9]. But
Manuscript received January 27, 2003; revised August 20, 2003. Recom-
mended by Associate Editor F. L. Luo.
The authors are with the College of Electrical Engineering, Zhejiang
University, Hangzhou 310027, China (e-mail: qian@cee.zju.edu.cn; power-
land@cee.zju.edu.cn).
Digital Object Identifier 10.1109/TPEL.2003.823248
0885-8993/04$20.00 © 2004 IEEE
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 19, NO.
Fig. 1. Topology of the proposed ZVS dc/dc converter.
circulation energy is very large, which causes high conduction
losses and high current ripple flowing through the output filter
capacitor [10], [12].
In this paper, a novel full-bridge type ZVS dc/dc converter
shown in Fig. 1 is proposed. The proposed topology achieves
soft commutation of the output rectifier diodes as well as
keeping ZVS of all active switches in the entire load ranges.
Furthermore, the circulation energy and current stress is
reduced dramatically compared to the previous topologies. The
detailed operating principle will be illustrated in Section II. The
performance of the topology is given in Section III. Section IV
will present some simulation and experimental results from a
200 kHz 2.8 kW dc/dc converter.
II. PRINCIPLE OF OPERATION
The proposed topology is shown in Fig. 1. A voltage fed full
bridge is adopted at the primary side and a full bridge type rec-
tifier with two active switches is used in the secondary side.
C1–C6 are snubber capacitors including related internal output
capacitance of the power switches. D1–D6 are anti-paralleled
body diodes of the power MOSFETs. The inductor is seri-
ally connected with the transformer T1, whose inductance in-
cludes the leakage inductance of the transformer T1. DR1–DR2
are output rectifier diodes.
The input bridge generates square-waves. The leg with two
active switches at the output bridge is phase shifted from the
input bridge. ZVS for these switches can be achieved in the
whole load range. Due to the influence of inductor , the re-
verse recovery currents of DR1 and DR2 are reduced dramati-
cally. Furthermore, the maximum reverse recovery voltage will
not exceed the output voltage. Soft commutation of those output
diodes can be achieved and no parasitic oscillation is observed.
The converter can operate either in CCM or in DCM ac-
cording to the current flowing through the inductor . The
phase shift between the input bridge and the output bridge is
and the phase lag between the input bridge and the diode
leg in secondary side is , which depends on the load condi-
tion and output voltage, as shown in Fig. 2. To simplify analysis
ZHANG et al.: NOVEL ZVS DC/DC CONVERTER 421

where is defined as dc conversion ratio,

is the input voltage, is the output voltage, and n
is the transformer turns ratio.
This mode is finished when the inductor current
reaches zero.
b) Mode2: [ – ]
When reaches zero, DR2 and DR1 commutate
naturally, so that the soft commutation of the diodes is
achieved. As MT5 still turns on, the secondary side of the
transformer is shorted through MT5 and DR1, as shown
in Fig. 3(b), the input voltage directly applied on inductor
, and increases linearly. The energy is stored in the
inductor and the current can be expressed as

(2)

(a)
c) Mode3: [ – ]
At , MT5 turns off and MT6 turns on at ZVS con-
dition. The input power is delivered to the output via in-
ductor . Current is given as

(3)

The operation modes during the next half switching

cycle are the same as those described above.

B. DCM Operation
From (3), we can see that when , the inductor current
ip can reach zero. Then the converter operates in a DCM mode.
The boundary for CCM and DCM under will given in
Section III. The steady state operating waveforms for DCM is
shown in Fig. 2(b). There are also six operating modes during
(b)
a single steady state switching cycle. There is only a little dif-
Fig. 2. Steady state operation waveforms: (a) CCM operation and (b) DCM
>
operation at d 1.
firence between CCM and DCM operation as described as fol-
lows.
of the steady state circuit operation, it is assumed that all the a) Mode1: [ – ]
components used in this converter have ideal characteristics: the Before , the inductor current has decreased to zero.
snubber capacitors are negligible; the magnetizing inductance At , MT2 and MT3 turn off under ZCS condition; MT1
of the transformer is infinite; the capacity of the output filter and MT4 turn on softly due to the presence of inductor
capacitors is sufficiently large so that the output voltage can be . The inductor current increases linearly. This mode
considered as an ideal dc voltage source. There are six operating is the same as mode2 in CCM operation. The equivalent
modes during a single steady state switching cycle. The theoret- circuit is shown in Fig. 3(b) and the inductor current
ical waveforms and equivalent circuits of each mode are shown can also be expressed by (2).
in Figs. 2 and 3, respectively. Each operation mode is simply Since the magnetizing inductance of the transformer
described as follows. T1 is finite, ZVS turning on can also be achieved; detailed
analysis is given in Section III.
A. CCM Operation b) Mode2: [ – ]
This mode is the same as mode3 in CCM operation,
a) Mode1: [ – ]
the equivalent circuit is shown in Fig. 3(c). In this mode,
Before this mode, MT2, MT3, MT5 and DR2 are con-
the inductor current decreases to zero at time and
ducting. The input power is delivered to the output. At
DR1 softly commutates. The expression for the inductor
, MT2 and MT3 are turned off and MT1 and MT4
current is also given as (3).
are turned on at ZVS condition. The inductor current in-
c) Mode3: [ – ]
creases linearly. The inductor current in this mode is
In this mode, though MT1, MT4 and MT6 still turn on,
given by
there is no power delivered from input to the output, the
equivalent circuit is shown in Fig. 3(d). Actually, this is an
(1) idle mode. The load is powered by the output capacitors.
422 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 19, NO. 2, MARCH 2004

(a)

(b)

(c)

(d)
Fig. 3. Equivalent circuits for each operation mode: (a) CCM Mode1 [t –t ], (b) CCM Mode2 [t –t ] and DCM Mode1 [t –t ], (c) CCM Mode3 [t –t ] and
DCM Mode2 [t –t ], and (d) DCM Mode3 [t –t ].

The operation modes in next half switching cycle are For simplification, some variables can be normalized to the
the same as those mentioned above. following basesthe voltage base: , the current base:
, the power base: ,
where is the switching frequency in radians/s.
III. ELABORATE ANALYSIS OF THE PROPOSED TOPOLOGY
We can further discuss this topology under three operation
Based on the steady state operation mode analysis discussed conditions according to the dc conversion ratio as follows.
in Section II, an elaborate analysis of the proposed topology is a) : Buck mode
presented as follows. First, we assumed that is larger than as shown in Fig. 2(a).
We can rewrite (1)–(3) as
A. Output Characteristics
Fig. 2 shows that at the end of half cycle the inductor current (5)
can be expressed as

From (4) and (5), we can get

(4)
(6)
ZHANG et al.: NOVEL ZVS DC/DC CONVERTER 423

and

(7)

Based on the previous analysis, the average current drawn

from the input voltage source is

(8)
Assuming the input power is fully delivered to the output at
an ideal condition, using (6)–(8), we get

(9)

where
.
Nevertheless, in conditon might be larger than . Fig. 4. Steady state operation waveforms for d < 1 and  > 8.
The steady state waveforms for is shown in Fig. 4. The
operating modes is almost the same as those described in CCM
operation previously only with a little difference in Mode1 and
Mode2. The diffirence is briefly described as follows.
Mode1 : MT1, MT4, MT5 and DR2 are conducting.
The inductor currnt can also be expressed by (1). This mode
finishes when MT5 turns off and MT6 turns on instead of
reaching zero.
Mode2 : MT1, MT4, MT6 and DR2 are conducting.
The inductor currnt can also be expressed by (2). This mode
finishes when reaches zero instead of MT5 turning off and
MT6 turning on.
Though the operation modes only have very small change
and the expressions for inductor current in each mode keeps
the same, the expressions for output power and average input
current are changed. According to Fig. 4, we can rewrite (1)–(3)
for and condition as

(10) Fig. 5. Normalized output power versus 8 for d < 1 condition.

From (4) and (10), we can get always smaller than ; else, is larger than . Obviously, in
conditons, is always smaller than since

and
The average input current is
From (11)–(13), the output power is given as
where
The critical phase shift angle can be derived simply using
(7) = (12) and is given in (15). If is larger than
(11) (15)
The output power versus is shown in Fig. 5. In conclusion,
(12) in conditions, if , the output power can be
calculated by (9); else, the output power can be calculated by
(14).
From Fig. 5, when the phase shift angle reaches zero, there
is still a value of the output power. In other words, for a voltage
negative feedback converter, in order to keep the output voltage
(13) constant, a minimum load power is needed. If the minimum load
power is smaller than the minimum output power at ,
the output voltage will increase because the power delivered to
(14) the output side is accumulating. The minimum output power at
varies with d as shown in Fig. 6. The increasing of the
. output voltage will not stop until the load power reaches the
minimum output power at . For example, if the converter
, is operates at mode at heavy load condition and the min-
424 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 19, NO. 2, MARCH 2004

Fig. 6. Normalized minimum output power at 8 = 0 versus d for d < 1. Fig. 8. Normalized output power versus 8 for d > 1 condition.

zero at time , i.e., . At the boundary for CCM and DCM

operation, from (1)–(4) and Fig. 2(b), the inductor current is
given as

(16)

From (16), we can get the critical phase shift angle for CCM
and DCM as

(17)

If is larger than , the converter operates in CCM

mode; else, the converter operates in DCM mode. In CCM op-
Fig. 7. Normalized output power versus 8 for d = 1 condition. eration, the output power can also be expressed as (9). In DCM
operation, we can rewrite (2) and (3) as
imum load power is zero, when the load changes to zero, d will
finally increase to 1. In some applications, such as in a battery (18)
charger, minimum load power always exists and usually is very
large when battery voltage is low. Therefore, the converter can Then, . is the inductor current decreasing
be designed in Buck mode at low output voltage in these appli- period, as shown in Fig. 2(b).
cations. From (18) and Fig. 2(b), the averge input current and the
b) output power at DCM operation are expressed as
Based on the analysis for and condition, the
output power for can also be expressed by (9), which is
(19)
shown in Fig. 7. With , (6) can be simplified as
. Since , the inductor current
always meets . and
c) , Boost mode
As discussed in Section II, for condition, the converter (20)
can operated in either CCM or DCM mode. When the inductor
current decrease to zero during CCM mode3 described in Sec- The output power versus is shown in Fig. 8. In conclusion,
tion II, the converter will operate in a DCM mode. Therefore, the for conditions, if , the topology operates in
boundary for CCM and DCM is the inductor current reaches CCM mode and output power can be calculated by (9); else, the
ZHANG et al.: NOVEL ZVS DC/DC CONVERTER 425

Fig. 9. Equivalent circuit for switching transient t .

Fig. 11. u versus T @V = 400 V, C = 1000 pF ; and fs = 200 kHz.

Fig. 10. Magnetizing current.

topology operates in DCM mode and the output power can be

calculated by (20).

B. Soft Switching Operation

(a) ZVS for input bridge switches
Fig. 9 shows the primary referred equivalent circuit of the
converter at , where the transformer is equivalent to a T-type (a) (b)
circuit, with the leakage inductance split equally on each side
of the magnetizing inductance. It is valid to assume that the
snubber capacitors have same capacitance C and the winding
resistance is negligible. At shown in Fig. 2, the voltage across
the switch MT2 is given as

(21)

where is the primary side inductor current at and

, , the influence of the leakage in-
ductane is neglected due to the fact that inductance is
much larger than . If reaches , ZVS can be achieved (c)
for MT1 and MT4. Fig. 12 (a) Inductor current waveform for 8 < 8 . (b) Inductor current
From (21), we can see that ZVS condition for the input bridge waveform for 8 > 8 . (c) Equivalent circuit at switching transient t .
switches is always satisfied even at no load condition if the dead
time between gate drive signals of MT1, MT4, and MT2, as a triangle waveform as shown in Fig. 10, is estimated
MT3 is long enough, as shown in Fig. 10. as
However, due to the low resonant frequency , a minimum
current is still needed to charge to reach the input voltage
during the dead time in a practical circuit implementation. (22)
The primary side current reaches its minimum value in
DCM operation. By simply assuming the magnetizing current where is the switching frequency.
426 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 19, NO. 2, MARCH 2004

(a) (b)

(c) (d)
Fig. 13. Simulation waveforms, up trace: V for MT1&MT4; middle trace: V for MT6; down trace: i ; (up & mid.: 0.4 V/div, down: 5 A/div; time: 5 us/div).
>
(a) d = 1; (b) d >
1, CCM; (c) d 1, DCM; (d) d < 1, and 8 <  .

In order to achieve ZVS during the dead time , whcih is the voltage across MT5 is given as (24) with . If the
usually rather small compared to the resonant frequency , we current can’t reach zero during dead time , the resonance
can get and . Then, the will not occur and ZVS for MT6 is lost. If the current is al-
maximum is simply estimated from (21) and (22) as ready positive at time for condition as shown
in Fig. 12(b), the voltage across MT5 is also given as (24), and
(23) is the inductor current at the switching transient ,
the influence of magnetizing current is also neglected
The capacitor voltage given in (21) versus the dead time
with different magnetizing inductance is shown in Fig. 11. (24)
(b) ZVS conditions for output bridge switches
If the parasitic capacitance of the MOSFET is neligible, the where , and C is the
ZVS condition for the switches in the output bridge is primary referred snubber capacitance of MT5&MT6.
as shown in Fig. 2 and Fig. 3(c). It is easy to satisfy for The ZVS condition for output bridge switches is given in
and conditions. In conditon, can be negxtive. (24) reaching . From (24) and Fig. 12(a), it is clear that
Therefore, we discuss ZVS condition for output bridge switches ZVS conditions for MT5&MT6 can always be achieved if
under condition firstly. is long enough at condition. The most serious condition
In condition, if , the ZVS condition will be to achieve ZVS for MT5&MT6 at condition is .
lost as shown in Fig. 4. Actually, due to the existance of the input In order to maintain ZVS at any load conditions under
voltage, the ZVS condition can also be satisfied if the dead time condition, the dead time shown in Fig. 12(a) can be derived
is long enough, which is also shown in Fig. 12(a). At time from (24) and Fig. 12(a) as
shown in Fig. 12(a), though MT5 has turned off, the current
is still flowing through the body diode of MT5 until the cur- (25)
rent reaches zero at . Then the resonant between and
MOSFET parasitic capacitor begins, and the equivalent circuit For or condition, if the phase shift angle is
is shown in Fig. 12(c). By neglecting the magnetizing current, zero, equals zero too. This is also the most serious con-
ZHANG et al.: NOVEL ZVS DC/DC CONVERTER 427

TABLE I
EXPERIMENTAL DESIGN SPECIFICATIONS

(a)
dition to achieve ZVS for MT5&MT6. Form (24), we can con-
clude that ZVS condition can always be achieved under
conditon. The required time for to reach is given in
(26) below. For condition, a small amount of load current
given in (27) is needed to help achieving ZVS, which can also
be derived from (24)

(26)

(27)

The magnetizing current also helps to achieve ZVS for sec-

ondary side switches as well as primary side switches. Based on
the analysis above, if the dead time is limited for con-
dition or a small amount load current for condition is not (b)
available, with the help of the magnetizing current, ZVS con-
Fig. 14. Drain to source voltage V and drive voltage V waveforms: (a)
dition can also be achieved as indicated in (24) and Fig. 12(c). V (10 V/div) and V (100 V/div) waveforms of MT4 @ light load and (b)
Too low d or too large MOSFET parasitic capacitance needs a V (10 V/div) and V (100 V/div) waveforms of MT6 @ 230 V output.
high magnetizing current, which causes a high conduction loss.
It is not preferred in practical design. Due to the more complex
expression for magnetizing current, the expression for magne-
tizing current to ensure ZVS at any output voltage and load con-
dition with a given dead time is not derived in this paper.

IV. SIMULATION AND EXPERIMENT VERIFICATION

To verify theoretical analysis of the proposed topology, the
PSIM simulation results for different output voltage and load
condition are presented in Fig. 13.
A 200 kHz 2.8 kW prototype as a battery charger for power
station applications is built up to verify theoretical analysis
and simulation results. The input voltage is 400 V, the output
voltage is 200–280 V and the maximum output current is 10 A.
The design specifications are indicated in Table I. A UC3875 is
adopted as a control IC.
The main experimental results are shown in Figs. 14–16.
Fig. 14 shows the driving voltage and drain to source Fig. 15. Primary side inductor current waveform at 230 V output.
voltage of MT4 and MT6. Fig. 15 shows the primary side
inductor current and Fig. 16 shows the output diode voltage ficiency improvement is still possible by optimizing the circuit
waveform. From these figures, no reverse recovery current and design.
voltage overshoot of the rectifier diodes appear. The propose topology is more attractive in high power with
The measured efficiency at 230 V output is shown in Fig. 17. high output voltage applications, such as applications from sev-
The overall efficiency at full load is about 92%. A further ef- eral kilowatts to several ten kilowatts. For super high power ap-
428 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 19, NO. 2, MARCH 2004

The proposed topology is more attractive in high power with

high output voltage applications with high efficiency. Experi-
mental results from a 2.8 kW 200 kHz dc/dc converter confirm
the theoretical and simulation analysis.

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[5] J.-G. Cho et al., “Zero-voltage and zero-current-switching full bridge
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“A three-phase soft-switched high-power-density dc/dc converter for
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Jan./Feb. 1991.
[9] D. Doncker, D. M. Divan, and M. H. Kheraluwala, “Performance charac-
terization of a high-power dual active bridge dc-to-dc converter,” IEEE
Trans. Ind. Applicat., vol. 28, pp. 1294–1301, Nov./Dec. 1992.
[10] K. Wang, F. C. Lee, and J. Lai, “Operation principles of bi-directional
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[11] T. Morimoto, S. Shirakawa, O. Koudriavtsev, and M. Nakaoka, “Zero-
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[12] J. M. Zhang, D. M. Xu, and Z. Qian, “An improved dual active bridge
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plications, such as 100 kW or above, usually IGBT is adopted 2001, pp. 232–236.
and ZCS is more attractive for these applications. In low power
applications, for example, from 100 W to 1 kW applications, the
proposed topology seems a little bit complex. But in low power
high output voltage applications, such as 300 V or higher, the Junming Zhang was born in Zhejiang, China, in
proposed topology is more attractive due to no diode reverse re- 1975. He received the B.S. and M.S. degree in
electrical engineering from Zhejiang University,
covery problem. And half bridge can be adopted in the primary Hangzhou, China, in 1996 and 2000, respectively,
side in stead of full bridge to reduce the complexity. The pro- where he is presently pursuing the Ph.D. degree.
posed topology is not preferred for low output voltage and high His research interests include PFC techniques,
soft-switching techniques, dc/dc converters, and
current application due to high conduction loss and high capac- system integration. He is the holder of one patent.
itor ripple current.

V. CONCLUSION

This paper proposes a novel ZVS dc/dc converter. The Fan Zhang was born in Haining, Zhejiang Province,
proposed converter has very attractive features, such as soft China, in 1976. He received the B.S. and M.S. degree
in electrical engineering from Zhejiang University,
switching for all active switches in any load condition, no diode Hangzhou, China, in 1999 and 2001, respectively,
reverse recovery problem, low sensitivity to system parasitic where he is currently pursuing the Ph.D. degree in
parameters, simple topology and convenient control strategy electrical engineering.
His research interests include soft-switching, dc/dc
etc. The detailed topology operation under different output modules, and high power inverters etc.
voltage and load condition is explained. The soft switching
conditions for all switches are also analyzed.
ZHANG et al.: NOVEL ZVS DC/DC CONVERTER
Xiaogao Xie was born in Leiyang, Hunan Province,
China, in 1975. He received the B.S. and M.S. de-
grees in electrical engineering from Zhejiang Uni-
versity, Hangzhou, China, in 1997 and 2000, respec-
tively, where he is currently pursuing the Ph.D. de-
gree in electrical engineering.
His research interests include dc/dc converters and
soft-switching techniques.
Dezhi Jiao was born in Wenzhou, Zhejiang
Province, China, in 1978. He received the B.S.
degree in electrical engineering from Zhejiang
University, Hangzhou, China, in 2001, where he
is currently pursuing the M.S degree in electrical
engineering.
His research interests include soft-switching tech-
nique and dc/dc converter.
429
Zhaoming Qian (SM’92) received the M.S. degree
in radio engineering from the Electrical Engineering
Department, Zhejiang University, China, in 1961
and the Ph.D. degree in applied science from the
Interuniversity Microelectronics Center (IMEC),
Catholic University of Leuven, Leuven, Belgium, in
1989.
Since 1961, He has been teaching and doing
research work on electronics and power electronics
with the Zhejiang University of China. He was
promoted to Professor of the Electrical Engineering
Department, Zhejiang University, in 1992. He is currently the Deputy Director
of National Engineering Research Center for Applied Power Electronics,
Zhejiang University, and the Deputy Director of the Scientific Committee,
National Key Laboratory of Power Electronics, Zhejiang University. His main
professional interests include power electronics and its industrial applications,
power electronic system integration, and EMC in power electronic systems etc.
He has published one book on EMC design and more than 200 papers.
Dr. Qian received Excellent Education Awards from the China Education
Commission and from Zhejiang University in 1993, 1997, and 1999, respec-
tively, and Science and Technology Development Awards from the China Edu-
cation Commission, in 1999 and 2003, respectively.