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AG1280Q48 smallest system board V1

FPGA Scheme verification board

Introduction: AG1280Q48 smallest system board

Open source agreement: CC-BY-NC-SA 3.0

Release time: 2021-08-25 13:03:39

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describe

AG1280Q48 smallest system

Version V1.0
The appearance and pin definition refer to Arduino Pro Mini, four-layer board
Only need a single 3.6V~5.5V power supply, onboard two LDOs, IO level is 3.3V
Other on-board peripherals include: active crystal oscillator, SPI Nor Flash, buttons, programming interface, lights
SPI Flash power supply with diode, which can be programmed independently from the back of the fly line
I have eaten ashes after making it

Introduction to AG1280Q48
Calls itself CPLD, but I think it is an FPGA with built-in Flash. .
Logic Slice structure of LUT4+Carry+FF(chain)
1280 LUTs, 1 PLL, 14*4.5kbit Block RAM
Cheap
The downloader is also cheap, and a USB Blaster worth more than a dozen dollars can be used

Tutorial 1: Use the built-in PLL to light up the onboard LED

This tutorial:
Generate an inaccurate clock by using the no-input mode of the built-in PLL
Use this clock to light up, and randomly generate something to other IOs to prove that they are not broken

1.1 Install the software

This series of FPGA/CPLD needs to use Quartus II for logic synthesis, and use its own software Supra for Map, Place & Route, etc.
First install Quartus II 13.1 and the corresponding version of Cyclone IV series device library.

Official website portal In addition, don't

download the latest version, I have stepped on the pit () As for the correct installation method of Quartus II, please search by yourself .
Then install the software AGM of Supra, download links can here official website found.

Within a day of waiting for the download of Baidu Cloud, you can do something else first.

1.2 Install the software (the next day)

Take the Windows system as an example, decompress the downloaded Supra compressed package to a suitable location.

Supra does not need to be installed, just run bin/Supra.exe at startup.

1.3 Create a new project in Supra

Run Supra, select File-Project-New Project:

create a new project called blinky1280, fill in the project directory and project name according to the figure, and click Save.

1.4 Use built-in PLL in Supra

Since we need to use the internal PLL, we need to create an IP first. The steps to create IP in Supra are as follows, select Tools-Create IP-Create PLL:

Here we name the Verilog module generated by the IP as inpll; select PLLX for PLL Type; write casually for Input Frequency; select NO_REFERENCE for
Feedback Mode; select 1 for output count ; Fill in the output frequency of Output 1 as 25MHz; click Generate:

the actual and probably not accurate frequency will be printed below. Then two files, inpll.ip and inpll.v, will be generated in the project directory. The former
needs to be imported into Supra when compiling, and the latter is the prototype of the PLL module that needs to be instantiated in the lighting code.

1.5 Establish Quartus II project and complete logic synthesis

Click Tools-Migrate and fill in the project details as shown in the figure: After

clicking Next, run Quartus II and open the project (blinky1280.qpf in the directory). The project automatically includes a blinky1280.v.

Open the file and write the lighting code:

 module blinky1280 (

input wire clk,

input wire rst_n,

output wire led,

output [17:0] gpio

);

wire clk_pll_o;

inpll pll_inst (

.clkin(clk), // PLL.clkin MUST connect to PIN_XX_GB

.clkfb(clk_pll_o),

.pllen(1'b1),

.resetn(rst_n),

.clkout0en(1'b1),

.clkout1en(1'b0),

.clkout2en(1'b0),

.clkout3en(1'b0),

.clkout0(clk_pll_o),

.clkout1(),

.clkout2(),

.clkout3(),

.lock()

);

reg [24:0] counter;

assign led = counter[24];

assign gpio[17:0] = counter[23:6];

always @(posedge clk_pll_o or negedge rst_n) begin

if (!rst_n)

counter <= 25'b0;

else

counter <= counter + 1;

end

endmodule

Save the file. Then, make sure to set the PLL IP as Design Partition:

select Tools-Tcl Scripts in Quartus II,

select af_quartus.tcl in the directory and run:

1.6 Place & Route

When the Quartus II completes logic synthesis, return to Supra and click Next:

Don’t click Finish here, first open the blinky1280.asf assignment pin in the project directory:

set_location_assignment PIN_13 -to clk

set_location_assignment PIN_48 -to led

set_location_assignment PIN_41 -to rst_n

set_location_assignment PIN_9 -to gpio[0]

set_location_assignment PIN_11 -to gpio[1]

set_location_assignment PIN_12 -to gpio[2]

set_location_assignment PIN_14 -to gpio[3]

set_location_assignment PIN_15 -to gpio[4]

set_location_assignment PIN_16 -to gpio[5]

set_location_assignment PIN_17 -to gpio[6]

set_location_assignment PIN_18 -to gpio[7]

set_location_assignment PIN_19 -to gpio[8]

set_location_assignment PIN_20 -to gpio[9]

set_location_assignment PIN_22 -to gpio[10]

set_location_assignment PIN_23 -to gpio[11]

set_location_assignment PIN_25 -to gpio[12]

set_location_assignment PIN_42 -to gpio[13]

set_location_assignment PIN_43 -to gpio[14]

set_location_assignment PIN_44 -to gpio[15]

set_location_assignment PIN_45 -to gpio[16]

set_location_assignment PIN_46 -to gpio[17]

Save, and other parameters will do by default. Click Finish and Supra will start Place & Route. If everything goes well, the output will be like this:

If it

doesn’t go well, then try more by yourself .

If you can’t solve it, I suggest you change to Altera, or look forward to the original FAE.

1.7 Programming
Prepare a USB Blaster. I have tried Taobao with a dozen yuan and Punctual Atomic. Both can be used. The difference is that it is cheap and slow.

First connect the USB Blaster to the board according to the pin definitions, then power on the board, and connect the USB Blaster to the computer.

Open Tool-Program in Supra and click Query Device ID;

the Device ID of AG1280Q48 is 0x00120010, this value will be read if connected correctly. Select the burning file just generated, where:
blinky1280_sram.prg is burned to the internal SRAM and will be lost after power failure
If you need to save power off, select blinky1280_hybird.prg
Take SRAM as an example here. The programming is successful as shown in the figure below, and the light on the board should flash.

Use an oscilloscope to measure other pins, you can see the square wave output:

Tutorial 2: Eat ashes

Pack the illuminated board with an anti-static bag from Lichuang Mall, where the LDO bag used on this board is used.

You also need to put the desiccant delivered every time you hit the board, and try to exhaust the air:
then find a place to put it. When eating ashes, you need to pay attention to avoid squeezing by external force; avoid stepping on it after slipping; avoid
accidentally eating; do not add eggs.

Other information & reference

The codes and burning files involved in Tutorial 1 are attached, which can be used to quickly test whether they are good or bad.
Other references:
[LED light screen controller] Preliminary study of domestic FPGA AG10KSDE176 (1)-ReCclay The web disk link in this link contains Supra's
user manual
[LED light screen controller] AG10K programming program (2)-ReCclay AGM technology Questions and Answers Collection-Haizhenyuan
Technology (I didn’t ask for the full version of this

design diagram

ag1280q48-pro-mini-v1 Open in editor

PCB_ag1280q48-pro-mini-v1 Open in editor

BOM BOM download Place an order in Lichuang Mall

 ID Name Designator Footprint Quantity

1 1.25-6P-TESTPOINT 1 1.25-6P-TESTPOINT 1

2 100nF C1, C3, C8, C9, C10, C11, C12, C13, C16 C0402_NEW 9

3 4.7uF C4, C5, C6, C7 C0402 4

4 22uF C77 C0805 1

5 A2005WV-2X5P CN1 HDR-TH_10P-P2.00-V-R2-C5-S2.00 1

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Engineering accessories

blinky1280_inpll.zip

Engineering member

libc0607

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