Lecture 4: Component, Package, Function & Procedure Dr.

Fadhil Sahib Al-Moussawi

Component, Package, Function

& Procedure
1. COMPONENT
COMPONENT declaration:

COMPONENT component_name IS
PORT (
port_name : signal_mode signal_type;
port_name : signal_mode signal_type;
...);
END COMPONENT;
COMPONENT instantiation:

label: component_name PORT MAP (port_list);

Example: We want to implement the circuit shown

employing only COMPONENTS (inverter, nand_2, and
nand_3). Then four pieces of VHDL code are needed: one
for each component, plus one for the project (main code).

------ inverter.vhd Component ------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
------------------------------------------------------------
ENTITY inverter IS
PORT (a: IN STD_LOGIC;
b: OUT STD_LOGIC
);
END inverter;

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Lecture 4: Component, Package, Function & Procedure Dr. Fadhil Sahib Al-Moussawi

ARCHITECTURE inverter OF inverter IS

BEGIN
b <= NOT a;
END inverter;
------ nand_2.vhd Component ---------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--------------------------------------------------------------
ENTITY nand_2 IS
PORT (a, b: IN STD_LOGIC; c: OUT STD_LOGIC);
END nand_2;
ARCHITECTURE nand_2 OF nand_2 IS
BEGIN
c <= NOT (a AND b);
END nand_2;
----- nand_3.vhd Component ----------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY nand_3 IS
PORT (a, b, c: IN STD_LOGIC; d: OUT STD_LOGIC);
END nand_3;
ARCHITECTURE nand_3 OF nand_3 IS
BEGIN
d <= NOT (a AND b AND c);
END nand_3;
----- project.vhd (Main code) ---------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-------------------------------------------------------------
ENTITY project IS

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Lecture 4: Component, Package, Function & Procedure Dr. Fadhil Sahib Al-Moussawi

PORT (a, b, c, d: IN STD_LOGIC;

x, y: OUT STD_LOGIC);
END project;
ARCHITECTURE structural OF project IS
-------------------------------------------------------------------------------------
COMPONENT inverter IS
PORT (a: IN STD_LOGIC; b: OUT STD_LOGIC);
END COMPOENT;
--------------------------------------------------------------------------------------
COMPONENT nand_2 IS
PORT (a, b: IN STD_LOGIC; c: OUT STD_LOGIC);
END COMPONENT;
--------------------------------------------------------------------------------------
COMPONENT nand_3 IS
PORT (a, b, c: IN STD_LOGIC; d: OUT STD_LOGIC);
END COMPONENT;
---------------------------------------------------------------------------------------
SIGNAL w: STD_LOGIC;

BEGIN
U1: inverter PORT MAP (b, w);
U2: nand_2 PORT MAP (a, b, x);
U3: nand_3 PORT MAP (w, c, d, y);
END structural;
----------------------------------------------------------------

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Lecture 4: Component, Package, Function & Procedure Dr. Fadhil Sahib Al-Moussawi

2. PACKAGE
Its syntax is presented below.

PACKAGE package_name IS
(declarations)
END package_name;

[PACKAGE BODY package_name IS

(FUNCTION and PROCEDURE descriptions)
END package_name;]
The PACKAGE above can be compiled, becoming then part of our work LIBRARY
(or any other). To make use of it in a VHDL code, we have to add a new USE clause
to the main code:
USE work. Package_name.all;

Example: Components Declared in a Package

In this example we implement the same
project of the previous example using
package. The PACKAGE is created where all
the COMPONENTS (inverter, nand_2, and
nand_3) will be declared. Thus now five
pieces of VHDL code are needed: one for each
component, one for the PACKAGE, and
finally one for the project. Despite having an
extra file (PACKAGE), such extra file needs
to be created only once, thus avoiding the need
to declare the components in the main code every time they are instantiated.
------ File inverter.vhd: -------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY inverter IS
PORT (a: IN STD_LOGIC; b: OUT STD_LOGIC);
END inverter;

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Lecture 4: Component, Package, Function & Procedure Dr. Fadhil Sahib Al-Moussawi

ARCHITECTURE inverter OF inverter IS

BEGIN
b <= NOT a;
END inverter;
------ File nand_2.vhd: ---------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY nand_2 IS
PORT (a, b: IN STD_LOGIC; c: OUT STD_LOGIC);
END nand_2;
ARCHITECTURE nand_2 OF nand_2 IS
BEGIN
c <= NOT (a AND b);
END nand_2;
----- File nand_3.vhd: -------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY nand_3 IS
PORT (a, b, c: IN STD_LOGIC; d: OUT STD_LOGIC);
END nand_3;
ARCHITECTURE nand_3 OF nand_3 IS
BEGIN
d <= NOT (a AND b AND c);
END nand_3;
----- File my_components.vhd: ---------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE my_components IS
------ 1- inverter: -------
COMPONENT inverter IS

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Lecture 4: Component, Package, Function & Procedure Dr. Fadhil Sahib Al-Moussawi

PORT (a: IN STD_LOGIC; b: OUT STD_LOGIC);

END COMPONENT;
------ 2-input nand: -----------------------
COMPONENT nand_2 IS
PORT (a, b: IN STD_LOGIC; c: OUT STD_LOGIC);
END COMPONENT;
------ 3-input nand: -----------------------------
COMPONENT nand_3 IS
PORT (a, b, c: IN STD_LOGIC; d: OUT STD_LOGIC);
END COMPONENT;
END my_components;

----- File project.vhd: ---------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.my_components.all;

ENTITY project IS
PORT ( a, b, c, d: IN STD_LOGIC;
x, y: OUT STD_LOGIC);
END project;

ARCHITECTURE structural OF project IS

SIGNAL w: STD_LOGIC;
BEGIN
U1: inverter PORT MAP (b, w);
U2: nand_2 PORT MAP (a, b, x);
U3: nand_3 PORT MAP (w, c, d, y);
END structural;
-------------------------------------------------------

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Lecture 4: Component, Package, Function & Procedure Dr. Fadhil Sahib Al-Moussawi

3. FUNCTION

A FUNCTION is a section of sequential code. Its purpose is to create new

functions to deal with commonly encountered problems, like data type conversions,
logical operations, arithmetic computations, and new operators and attributes. By
writing such code as a FUNCTION, it can be shared and reused, also propitiating the
main code to be shorter and easier to understand. The Function Body is:

FUNCTION function_name [<parameter list>] RETURN data_type IS

[declarations]
BEGIN
(sequential statements)
END function_name;
Example: Function positive_edge( )
The FUNCTION below detects a positive (rising) clock edge. It is similar to the
IF (clk’EVENT and clk =‘1’) statement.

------ Function body: -------------------------------

FUNCTION positive_edge (SIGNAL s: STD_LOGIC) RETURN BOOLEAN IS
BEGIN
RETURN (s'EVENT AND s='1');
END positive_edge;
Function Location
The FUNCTION can be located either in Package or in main code. In main
code it can be located either in ENTITY or in ARCHITECTURE.
Example : FUNCTION Located in the Main Code
using positive_edge ( ) to write VHDL code for DFF circuit.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY dff IS
PORT ( d, clk, rst: IN STD_LOGIC;
q: OUT STD_LOGIC);
END dff;

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Lecture 4: Component, Package, Function & Procedure Dr. Fadhil Sahib Al-Moussawi

ARCHITECTURE my_arch OF dff IS

FUNCTION positive_edge(SIGNAL s: STD_LOGIC)

RETURN BOOLEAN IS
BEGIN
RETURN s'EVENT AND s='1';
END positive_edge;
BEGIN
PROCESS (clk, rst)
BEGIN
IF (rst='1') THEN q <= '0';
ELSIF positive_edge(clk) THEN q <= d;
END IF;
END PROCESS;
END my_arch;
Example: FUNCTION Located in a PACKAGE
Repeat Example above using function located in a package
------- Package: -----------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE my_package IS
FUNCTION positive_edge(SIGNAL s: STD_LOGIC) RETURN BOOLEAN;
END my_package;
PACKAGE BODY my_package IS

FUNCTION positive_edge(SIGNAL s: STD_LOGIC) RETURN BOOLEAN IS

BEGIN
RETURN s'EVENT AND s='1';
END positive_edge;

END my_package;
----------------------------------------------

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Lecture 4: Component, Package, Function & Procedure Dr. Fadhil Sahib Al-Moussawi

------ Main code: ----------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.my_package.all;
ENTITY dff IS
PORT ( d, clk, rst: IN STD_LOGIC;
q: OUT STD_LOGIC);
END dff;
ARCHITECTURE my_arch OF dff IS
BEGIN
PROCESS (clk, rst)
BEGIN
IF (rst='1') THEN q <= '0';
ELSIF positive_edge(clk) THEN q <= d; -- CALL FUNCTION
END IF;
END PROCESS;
END my_arch;

4. PROCEDURE
A PROCEDURE is very similar to a FUNCTION and has the same basic
purposes. However, a procedure can return more than one value.

PROCEDURE procedure_name [<parameter list>] IS [declarations]

BEGIN
(sequential statements)
END procedure_name;

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Lecture 4: Component, Package, Function & Procedure Dr. Fadhil Sahib Al-Moussawi

Example: PROCEDURE Located in the Main Code

The min_max code below makes use of a PROCEDURE

called sort. It takes two 8-bit unsigned integers as inputs
(inp1, inp2), sorts them, then outputs the smaller value at
min_out and the higher value at max_out. The
PROCEDURE is located in the declarative part of the
ARCHITECTURE (main code). Notice that the
PROCEDURE call, sort(inp1,inp2,min_out,max_out), is a statement on its own.
------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY min_max IS
GENERIC (limit : INTEGER := 255);
PORT ( ena: IN BIT;
inp1, inp2: IN INTEGER RANGE 0 TO limit;
min_out, max_out: OUT INTEGER RANGE 0 TO limit);
END min_max;
ARCHITECTURE my_architecture OF min_max IS

PROCEDURE sort (SIGNAL in1, in2: IN INTEGER RANGE 0 TO limit;

SIGNAL min, max: OUT INTEGER RANGE 0 TO limit) IS
BEGIN
IF (in1 > in2) THEN
max <= in1;
min <= in2;
ELSE
max <= in2;
min <= in1;
END IF;
END sort;

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Lecture 4: Component, Package, Function & Procedure Dr. Fadhil Sahib Al-Moussawi

BEGIN
PROCESS (ena)
BEGIN
IF (ena='1') THEN sort (inp1, inp2, min_out, max_out); -- CALL PROCEDURE
END IF;
END PROCESS;
END my_architecture;
----------------------------------------------------------------
The simulation results is shown.

Example: PROCEDURE Located in a PACKAGE-

------------ Package: ---------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE my_package IS
CONSTANT limit: INTEGER := 255;
PROCEDURE sort (SIGNAL in1, in2: IN INTEGER RANGE 0 TO limit;
SIGNAL min, max: OUT INTEGER RANGE 0 TO limit
);
END my_package;
PACKAGE BODY my_package IS

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Lecture 4: Component, Package, Function & Procedure Dr. Fadhil Sahib Al-Moussawi

PROCEDURE sort (SIGNAL in1, in2: IN INTEGER RANGE 0 TO limit;

SIGNAL min, max: OUT INTEGER RANGE 0 TO limit) IS
BEGIN
IF (in1 > in2) THEN
max <= in1;
min <= in2;
ELSE
max <= in2;
min <= in1;
END IF;
END sort;
END my_package;
--------- Main code: ----------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.my_package.all;
ENTITY min_max IS
GENERIC (limit: INTEGER := 255);
PORT ( ena: IN BIT;
inp1, inp2: IN INTEGER RANGE 0 TO limit;
min_out, max_out: OUT INTEGER RANGE 0 TO limit);
END min_max;
ARCHITECTURE my_architecture OF min_max IS
BEGIN
PROCESS (ena)
BEGIN
IF (ena='1') THEN sort (inp1, inp2, min_out, max_out); -- call procedure
END IF;
END PROCESS;
END my_architecture;

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