LA-C551P (AAPB0) 2015-08-18, Rev 1.0 (A00)

A B C D E
COMPAL
CONFIDENTIAL
MODEL NAME : AAPB0
1 1
PCB NO : LA-C551P
BOM P/N : 4319X331L01
GPIO MAP: Gen7 GPIO Master_0520
MIRAMAR17
Skylake H-type (2 chip)
2 2
REV : 1.0 (A00)

2015.08.18
@ : Nopop Component
EMC@ : EMI/ESD/RF part
CONN@ : Connector Component
XDP@ : Total debug Component (pop them until ST)
3 3
TB@ : Thunderbolt function
Layout Dell logo
COPYRIGHT 2014
ALL RIGHT RESERVED
REV: X00
PWB: XXXXX
DATE: 1403-06
4 4
PCB_178_LA-XXXXP_REV0_MB
Part
Number Description
DELL CONFIDENTIAL/PROPRIETARY
DAXXXXXXXXX PCB 178 LA-XXXXP REV0 MB
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
Cover Sheet
Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
1.0
Power CKT: LA-C551P
0108 Date: Tuesday, August 18, 2015 Sheet 1 of 74
A B C D E
A B C D E
Lane x4
eDP Panel eDP MUX eDP
Lane x4
Conn PS8331 Intel (DDR4) Memory Bus DDR4 ECC-SO-DIMM X4
DDI3 BANK 0, 1, 2, 3, 4 ,5 ,6 ,7 P.14~17
P.30 P.29
DDI1
SKYLAKE-H 1.2V DDR4 2133/2667/2933MHz (Overclocking)
DDI2 BGA CPU
PEG x16
DDI1 (Gen3) PEG 1440 Pins
Docking DP MUX SATA/PCIE
1
DP Port1 SATA Port 2 SATA EXPRESS HDD 1
PS8331 DPC PCIE Port 15 Repeater
P.31 P.42 P.41
mDP mDP DDI3 DP_D P.6~13

1.2 DP DEMUX DP MUX
Conn TBT_DP1 PS8338 PS8331 DPB USB3 Port 3 USB 3.0 Repeater
P.33 DP_C MXM DMI x4
gen 2 PS8713B P.7 USB 3.0 Conn
DP_BConn. Right Side
DDI2 TYPE A SATA3.0 USB2 Port 2 USB Power Share USB Charger
HDMI2.0 TBT TBT_DP0 DP MUX TPS2544 P.7 P.7
Conn AR-SP PS8331
P.34 DP DEMUX DPA
PS8338 DP_A USB3 Port 4 USB 3.0 Repeater
VGA P.18
P.32 PS8713B P.8 USB 3.0 Conn
PCIE
Port 5~8 Right Side
USB2 Port 3 USB Power Share USB Charger
UPD TPS2544 P.8 P.8
PIC32MX150F128DT5
Docking
DP Port2
Intel
Docking SKYLAKE-H USB3 Port 5 USB 3.0 Repeater
CRT PS8713B P.9
On Display
TBT board BGA USB3.0 USB 3.0 Conn
2
TBT Right Side 2
Conn 837 Pins USB2 Port 4 USB Power Share USB Charger
TPS2544 P.9
PCIE BUS P.9 On I/O
Port 3 Port 4 Port 5~8 Port 17~20 Port 9~12 Port 13 Port 2 USB2.0 board
USB3 Port 1 USB 3.0 Repeater

RTS5242 Intel Jacksonville M.2 Card slot_2 PS8713B P.12 USB 3.0 Conn
M.2 Card slot_3 M.2 Card slot_1
WGI219LM Thunderbolt WWAN/LTE/HCA/ WLAN/BT/WiGig Left Side
SD4.0/MMC SSD Cache
P.35 USB2 Port 1 USB Power Share
P.6 USB Charger
P.5~8 P.39 P.38 P.38
P.18~26
HD TPS2544 P.12 P.12
On Display I/O board USB2 Port8 USB2 Port 6
Audio On Display
LAN switch M.2 Card slot_4
board
SDXC P.6 PI3L720ZHEX SSD
LPC BUS
P.35 P.39 W25Q128FVSIQ USB2 Port 11 Digital Camera
On I/O
board P.22 P.30
SPI
Docking SMSC SIO BC BUS 128Mb 4K sector
LAN ECE5048 W25Q32FVSSIQ
P.45 P.22
RJ45 SMSC KBC 32Mb 4K sector
P.36
3
MEC5085 3
P.46 TDA8034HN
USB Port 7 BRCM58100
Discrete TPM TPM 1.2
FAN control NPCT650JAAYX Smart Card
CY8C4245AXI P.37
P.28 KB/TP
SATA Port 1
CONN P.48 SPI RFID/NFC
USB2 Port 7 FAN CONN
USB2 Port 5 P.28 SPI Fingerprint
DAI
CONN
On USH/B P.37
RGB
Micro SIM Card
P.38 Universal Jack
DC LAN
E-Dock P.4
Audio Codec
USB3.0 Port 6 Free Fall Sensor ALC3235 Int. Speaker
P.4
LPC
LNG2DMTR P.41 On I/O board
Docking
4
DP 4
Docking
DP P.43
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Block Diagram
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-C551P 1.0
Date: Tuesday, August 18, 2015 Sheet 2 of 74

A B C D E
5 4 3 2 1
POWER STATES
Signal SLP SLP SLP S4 SLP ALWAYS M SUS RUN CLOCKS USB PORT# DESTINATION
S3# S4# S5# STATE# M# PLANE PLANE PLANE PLANE
State
1 Left Side JUSB1
S0 (Full ON) / M0 HIGH HIGH HIGH HIGH HIGH ON ON ON ON ON
2 Right Side JUSB1
D
S3 (Suspend to RAM) / M1 LOW HIGH HIGH HIGH HIGH ON ON ON OFF OFF D
3 Right Side JUSB2
S4 (Suspend to DISK) / M1 LOW LOW HIGH LOW HIGH ON ON OFF OFF OFF
4 Right Side JUSB3
S5 (SOFT OFF) / M1 LOW LOW LOW LOW HIGH ON ON OFF OFF OFF
5 Docking USB3.0
S3 (Suspend to RAM) / M-OFF LOW HIGH HIGH HIGH LOW ON OFF ON OFF OFF
6 M.2 Slot-1 (WLAN/BT/WiGig)
S4 (Suspend to DISK) / M-OFF LOW LOW HIGH LOW LOW ON OFF OFF OFF OFF PCH
7 Docking USB 2.0
S5 (SOFT OFF) / M-OFF LOW LOW LOW LOW LOW ON OFF OFF OFF OFF
8 M.2 Slot-2 (WWAN/LTE/HCA)
PM TABLE 9 NA
+PWR_SRC +3.3V_SUS +5V_RUN +3.3V_M (M-OFF)
+5V_ALW +1.2V_MEM +3.3V_RUN +3.3V_M 10 USH
C
+3.3V_ALW +2.5V_MEM +1.5V_RUN +VCC_CORE C
power 11 Camera
plane +3.3V_ALW2 +1.0V_VCCST +0.675V_DDR_VTT +VCC_EDRAM SATA DESTINATION
+3.3V_ALW_DSW +3.3V_MXM +VCC_EOPIO
+3.3V_ALW_PCH +5V_MXM +VCC_GTU SATA 0 2280 SSD 12 NA
+3.3V_RTC_LDO +MXM_PWR_SRC +VCC_GT
+1.8V_ALW +1.0V_VCCSTG 13 NA
State SATA 1 Dock
+1.0V_PRIM +VCC_SA
14 NA
SATA 2
S0 ON ON ON ON ON
SATA 3 SATAe HDD 0 BIO
S3 ON ON OFF ON OFF USH
SATA 4 2280 SSD 1 NA
S5 S4/AC ON OFF OFF ON OFF
SATA 5
PCI EXPRESS DESTINATION
S5 S4/AC don't exist OFF OFF OFF OFF OFF
B
Lane 1 NA B
Stack up
USB3.0 DESTINATION Lane 2 M.2 Slot-1 (WLAN/Wigig)
Port 1 Left Side JUSB1 Lane 3 MMI(Card reader)
Port 2 M.2 Slot-2 (WWAN/LTE/HCA) Lane 4 10/100/1G LOM
Port 3 Right Side JUSB1 Lane 5~8 TBT-Alpine Ridge
Port 4 Right Side JUSB2 Lane 9~12 SSD 2280
Port 5 Right Side JUSB3 Lane 13 M.2 Slot-2 (WWAN/LTE/HCA)
Port 6 Docking Lane 15~16 HDD SATA-Express
A
Lane 17~20 SSD 2280 A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Index and Config.

5 4 3 2 1
5 4 3 2 1
EN_INVPWR
FDC654P
(Q21) +BL_PWR_SRC
3.3V_RUN_GFX_ON SI4835DDY
+MXM_PWR_SRC
(Q186)
IMVP_VR_ON ISL95812
Docking +VCC_CORE
(PU500)
D SIO_SLP_S3# SYX198DQNC D
+VCC_IO
(PU300)
IMVP_VR_ON NCP81382MNTXG
ADAPTER +VCC_GT
(PU1400,PU1401)
RUN_ON TPS22967
IMVP_VR_ON NCP81210MNTWG +1.0V_RUN
+VCC_GTU (UZ23)
(PU1600)
IMVP_VR_ON SYX198DQNC
+PWR_SRC +VCC_EDRAM SIO_SLP_S0# TPS22961
(PU500)
BATTERY SIO_SLP_S3# (UZ19) +1.0V_VCCSTG
SIO_SLP_SUS# TPS51212 SIO_SLP_S4# TPS22967

+1.0V_PRIM +1.0V_VCCST
(PU800) (UZ18)
ALWON TPS51225
CHARGER RUN_ON TPS22966
(PU101) +5V_RUN +5V_HDD
(UZ20)
C 3.3V_RUN_GFX_ON C
+5V_ALW EM5209VF +5V_MXM
(UZ26)
Left IO Board
SIO_SLP_S4#
USB_PWR_SHR_VBUS_EN
+3.3V_ALW TPS2544 +5V_USB_PWR1
(UI1)
USB1_VBUS_EN
TPS2544 +5V_USB_PWR1
(UI1)
SLOT3_SSD_PWR_EN
SLOT4_SSD_PWR_EN
RT8207
LCD_VCC_TEST_EN
3.3V_RUN_GFX_ON
USB2_VBUS_EN
3.3V_WWAN_EN
SIO_SLP_WLAN#
TPS2544
AUX_EN_WOWL
(PU200)
SIO_SLP_LAN#
+5V_USB_PWR2
MXM_ENVDD
PCH_ALW_ON
ENVDD_PCH
(UI3)
SIO_SLP_S4#
SIO_SLP_SUS#
SIO_SLP_S4#
SIO_SLP_A#
USB3_VBUS_EN
RUN_ON
TPS2544
A_ON
+5V_USB_PWR3
(UI5)
Right IO Board
EM5209VF EM5209VF
TPS22967 TPS22967 EM5209VF EM5209VF EM5209VF APL3512ABI SY8003DFC SY8003DFC
(UZ25) (UZ21)
B (UZ27) (UZ24) (UZ20) (UZ26) (UZ2) (U33) (PU900) (PU400) B
+V_DDR_REF +0.6V_DDR_VTT +1.2V_MEM
+3.3V_WWAN
+3.3V_RUN +LCDVDD +1.8V_ALW +2.5V_MEM

+3.3V_MXM
+3.3V_ALW_PCH
+3.3V_LAN
+3.3V_WLAN
+3.3V_SSD1
+3.3V_SSD2
+3.3V_SUS
+3.3V_M
3.3V_CAM_EN#
RUN_ON
EM5209VF
(UZ22)
DMG2301U
(Q24)
+1.8V_RUN
+CAMERA_VDD
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Power Rail
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
1.0
LA-C551P
5 4 3 2 1
5 4 3 2 1
2.2K
SMBUS Address [0x9a]
2.2K
+3.3V_ALW_PCH
AW44 MEM_SMBCLK 253
DMN66D0LDW SMBUS Address [A0h]
BB43 MEM_SMBDATA 254 DIMM1 A0h --> 1010 0000
DMN66D0LDW
2.2K 253
PCH SMBUS Address [A0h]
254 DIMM2 A0h --> 1010 0000
+3.3V_LAN
2.2K
253
D AY44 LAN_SMBCLK 28 SMBUS Address [A4h] D
254 DIMM3 A4h --> 1010 0100
LAN_SMBDATA 31 LOM SMBUS Address [0xC8]
BB39
AW45 AW42 253
SMBUS Address [A4h]
2.2K 254 DIMM4 A4h --> 1010 0100
SML1_SMBDATA
SML1_SMBCLK
+3.3V_ALW_PCH 53
2.2K
2.2K 51 XDP1 SMBUS Address [TBD]
A5 B6
2.2K +3.3V_ALW
1D 1D
SMBUS Address
APR_EC: 0x48 SMBUS Address
1A B4 DOCK_TNY_SMB_CLK 127 SPR_EC: 0x70 SMB_ADM1032: 0x98
MSLICE_EC: 0x72 SMB_DIAG_DUMP: 0x04
1A A3 DOCK_TNY_SMB_DAT 129 DOCKING USB: 0x59 SMB_DIAG_DUMP2: 0x05
AUDIO: 0x34 SMB_BLACKTOP: 0x60
SLICE_BATTERY: 0x17
SLICE_CHARGER: 0x13
C C
2.2K
+3.3V_RUN
2.2K
2.2K 1
4 LNG2DMTR
SMBUS Address [TBD]
+3.3V_ALW
2.2K
100 ohm 7
1C A56 PBAT_SMBCLK
6 BATTERY SMBUS Address [0x16]
1C B59 PBAT_SMBDAT 100 ohm CONN
KBC 1E
A50 USH_SMBCLK 5
B53 USH_SMBDAT 6 LYNX(CV2) SMBUS Address [0xa4]
1E
4.7K
MEC 5085
4.7K +3.3V_RUN
DMN66D0LDW 20
B
AAC B
21
DMN66D0LDW
2.2K
+3.3V_ALW
2.2K
B50 CHARGER_SMBCLK 9
1G
A47 CHARGER_SMBDAT 8 Charger
1G SMBUS Address [0xFF]
@4.7K
2.2K +3.3V_MXM
+3.3V_RUN @4.7K
2.2K
1H B49 UPD_GPU_SMBCLK 70
DMN66D0LDW
1H 68 MXM SMBUS Address [TBD]
B48 UPD_GPU_SMBDAT
DMN66D0LDW
4.7K
+3.3V_TBT_SX
4.7K
A DMN66D0LDW 24 A
UPD
23
DMN66D0LDW
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SMBUS Bolck Diagram

5 4 3 2 1
5 4 3 2 1
PEG_CRX_C_GTX_P[0..15]
PEG_CRX_C_GTX_P[0..15] <18>
PEG_CRX_C_GTX_N[0..15]
PEG_CRX_C_GTX_N[0..15] <18>
PEG_CTX_C_GRX_P[0..15]
PEG_CTX_C_GRX_P[0..15] <18>
PEG_CTX_C_GRX_N[0..15]
?
SKYLAKE_HALO PEG_CTX_C_GRX_N[0..15] <18>
CPU1C
D D
BGA1440
PEG_CRX_C_GTX_P15 CC32 2 1 0.22U_0402_10V6K PEG_CRX_GTX_P15 E25 B25 PEG_CTX_GRX_P15 CC64 2 1 0.22U_0402_10V6K PEG_CTX_C_GRX_P15
PEG_CRX_C_GTX_N15 CC16 2 1 0.22U_0402_10V6K PEG_CRX_GTX_N15 D25 PEG_RXP[0] PEG_TXP[0] A25 PEG_CTX_GRX_N15 CC50 2 1 0.22U_0402_10V6K PEG_CTX_C_GRX_N15
PEG_RXN[0] PEG_TXN[0]
PEG_CRX_C_GTX_N14 CC15 2 1 0.22U_0402_10V6K PEG_CRX_GTX_N14 F24 PEG_RXP[1] PEG_TXP[1] C24 PEG_CTX_GRX_N14 CC77 2 1 0.22U_0402_10V6K PEG_CTX_C_GRX_N14
C PEG_CRX_C_GTX_N8 CC9 2 1 0.22U_0402_10V6K PEG_CRX_GTX_N8 F18 PEG_RXP[7] PEG_TXP[7] C18 PEG_CTX_GRX_N8 CC75 2 1 0.22U_0402_10V6K PEG_CTX_C_GRX_N8 C
PEG_CRX_C_GTX_P7 CC24 2 1 0.22U_0402_10V6K PEG_CRX_GTX_P7 D17 A17 PEG_CTX_GRX_P7 CC70 2 1 0.22U_0402_10V6K PEG_CTX_C_GRX_P7
PEG_CRX_C_GTX_N7 CC8 2 1 0.22U_0402_10V6K PEG_CRX_GTX_N7 E17 PEG_RXP[8] PEG_TXP[8] B17 PEG_CTX_GRX_N7 CC56 2 1 0.22U_0402_10V6K PEG_CTX_C_GRX_N7
PEG_CRX_C_GTX_P6 CC23 2 1 0.22U_0402_10V6K PEG_CRX_GTX_P6 F16 C16 PEG_CTX_GRX_P6 CC55 2 1 0.22U_0402_10V6K PEG_CTX_C_GRX_P6
B B
PEG_COMP G2
PEG_RCOMP
+VCC_IO
PEG_COMP 2 1
24.9_0402_1% RC2 DMI_CRX_PTX_P0 D8 B8 DMI_CTX_PRX_P0 DMI_CTX_PRX_P0 <20>
<20> DMI_CRX_PTX_P0 DMI_CRX_PTX_N0 DMI_RXP[0] DMI_TXP[0] DMI_CTX_PRX_N0
E8 A8 DMI_CTX_PRX_N0 <20>
<20> DMI_CRX_PTX_N0 DMI_RXN[0] DMI_TXN[0]
CAD Note: DMI_CRX_PTX_P1 E6 C6 DMI_CTX_PRX_P1
Trace width=12 mils <20> DMI_CRX_PTX_P1 DMI_RXP[1] DMI_TXP[1] DMI_CTX_PRX_P1 <20>
DMI_CRX_PTX_N1 F6 B6 DMI_CTX_PRX_N1 DMI_CTX_PRX_N1 <20>
,Spacing=15mil <20> DMI_CRX_PTX_N1 DMI_RXN[1] DMI_TXN[1]
Max length= 400 mils. DMI_CRX_PTX_P2 D5 B5 DMI_CTX_PRX_P2 DMI_CTX_PRX_P2 <20>
E5 A5 DMI_CTX_PRX_N2 <20>
DMI_CRX_PTX_P3 J8 D4 DMI_CTX_PRX_P3 DMI_CTX_PRX_P3 <20>
J9 B4 DMI_CTX_PRX_N3 <20>
3 OF 14
REV = 1
SKL-H_BGA1440
?
A A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SKYLAKE-H (1/8)

5 4 3 2 1
5 4 3 2 1
+1.0V_PRIM_XDP
+1.0V_PRIM +1.0V_PRIM_XDP
CPU XDP
1 2 +1.0V_PRIM_XDP XDP@ CPU_XDP_HOOK6 1 2
@ RC216 0_0603_1% +1.0V_PRIM_XDP XDP_PRSNT_PIN1 1 2 CFG3 XDP@ RC6 2.2K_0402_5%
RC121 1K_0402_5% +1.0V_PRIM_XDP
1 2
@ RC122 0_0402_5%
0.1U_0402_25V6
0.1U_0402_25V6
JXDP1
1 2 10/23 Intel review
3 GND0 GND1
1
CPU_XDP_PREQ# +3.3V_ALW_PCH
@ CC37
@ CC33
4 CFG17
CPU_XDP_PRDY# 5 OBSFN_A0 OBSFN_C0 6 CFG16
7 OBSFN_A1 OBSFN_C1 8
2
CFG0 9 GND2 GND3 10 CFG8 XDP_DBRESET# 1 2
CFG1 11 OBSDATA_A0 OBSDATA_C0 12 CFG9 XDP@ RC316 1.5K_0402_5%
D 13 OBSDATA_A1 OBSDATA_C1 14 D
CFG2 15 GND4 GND5 16 CFG10 PCH_SPI_D0 1 2 +3.3V_SPI
CFG3 17 OBSDATA_A2 OBSDATA_C2 18 CFG11 XDP@ RC133 1.5K_0402_5%
19 OBSDATA_A3 OBSDATA_C3 20
Place near JXDP1 21 GND6 GND7
1
XDP_OBS0_R 22 CFG19
XDP_OBS1_R 23 OBSFN_B0 OBSFN_D0 24 CFG18 RC5
25 OBSFN_B1 OBSFN_D1 26 2.2K_0402_5%
CFG4 27 GND8 GND9 28 CFG12
CFG5 29 OBSDATA_B0 OBSDATA_D0 30 CFG13
2
RC5 need to close to JCPU1 31 OBSDATA_B1 OBSDATA_D1 32
33 GND10 GND11 XDP_DBRESET# SYS_PWROK_R
0.1U_0402_25V6
CFG6 34 CFG14
35 OBSDATA_B2 OBSDATA_D2
0.1U_0402_25V6
CFG7 36 CFG15
37 OBSDATA_B3 OBSDATA_D3 38
39 GND12 GND13
1
PCH_RSMRST#_R RC124 1 H_VCCST_PWRGD_XDP PCH_XDP_CLK_DP
CC35 XDP@
@ CC36
T191 @ PAD~D
2 40
PCH_XDP_CLK_DP <21>
XDP@ 1K_0402_5% SIO_PWRBTN# 41 PWRGOOD/HOOK0 ITPCLK/HOOK4 42 PCH_XDP_CLK_DN
<23,46> SIO_PWRBTN# PCH_XDP_CLK_DN <21>
@ RC217 1 2 0_0402_5% 43 HOOK1 ITPCLK#/HOOK5 44
2
CFG0 XDP@ RC126 1 2 1K_0402_5% FIVR_EN_R 45 VCC_OBS_AB VCC_OBS_CD 46 CPU_XDP_HOOK6 1 2 ITP_PMODE_CPU
ITP_PMODE_CPU <23>
XDP@ RC128 1 2 0_0402_5% SYS_PWROK_R 47 HOOK2 RESET#/HOOK6 48 XDP_DBRESET# XDP@ RC144 0_0402_5%
10/23 Intel review <22,37> PCH_SPI_D0
@ RC129 1 2 0_0402_5% 49 HOOK3 DBR#/HOOK7 50 XDP_DBRESET# <20>
<23,46> RESET_OUT#
51 GND14 GND15 52 CPU_XDP_TDO
<14,15,16,17,23,41> DDR_XDP_WAN_SMBDAT
53 SDA TD0 54 CPU_XDP_TRST#
<14,15,16,17,23,41> DDR_XDP_WAN_SMBCLK PCH_JTAG_TCK 55 SCL TRST# 56 CPU_XDP_TDI
CPU_XDP_TRST# <25> Place near JXDP1.47
<23> PCH_JTAG_TCK CPU_XDP_TCLK TCK1 TDI CPU_XDP_TMS
57 58
59 TCK0 TMS 60 CPU_XDP_PRS 1 2 PCH_SPI_D2_XDP
PCH_SPI_D2_XDP <22>
GND16 GND17 XDP@ RC127 1K_0402_5%
SAMTE_BSH-030-01-L-D-A CONN@
+1.0V_PRIM_XDP CFG0
Stall reset sequence after PCU
1
PLL lock until de-asserted
CPU_XDP_PREQ# 1 2 @ RC321
@ RC138 51_0402_5% 1K_0402_5%
C +VCC_IO +3.3V_ALW +3.3V_ALW
No Stall 1 C
EDS0.7
2
CH17
1 2 Stall 0
1
FIVR_EN_R
1.5K_0402_5%
XDP@ RC241
1 2
RC132 150_0402_5% 0.1U_0402_25V6K
UC4
5
SN74AHC1G08DCKR_SC70-5 CFG2
2
PCH_RSMRST# 1
P
<46> PCH_RSMRST# IN1
1
4 PM_RSMRST#_AND 1 2 PCH_RSMRST#_R SIO_PWRBTN# PEG LANE REVERSAL
O PCH_RSMRST#_R <23>
2 @ RC154 0_0402_5% RC181
<51> ALW_PWRGD_3V_5V IN2
0.1U_0402_25V6
XDP@ CC269
1K_0402_5%
1
NORMAL 1
1
RC318
2
+1.0V_VCCST 47K_0402_5% Place near JXDP1.41 LANE
0
* REVERSED
2
2 1 PCH_THERMTRIP# +1.0V_VCCSTG
10/23 Intel review
2
1K_0402_5% RC326
2 1 PCH_JTAGX
1K_0402_5% @ RC166 CPU_XDP_TDO 2 1
2 1 VCCST_PWRGD 51_0402_5% RC135 CFG4
1K_0402_5% RC164
1
2 1 H_CATERR#
10/23 Intel review ?
SKYLAKE_HALO CPU_XDP_TRST# 2
eDP enable
49.9_0402_1% @ RC172 CPU1E 1 RC322
51_0402_5% RC330 1K_0402_5%
+1.0V_VCCSTG PCH_CPU_BCLK_R_D BGA1440 CPU_XDP_TCLK
B31 BN25 CFG0 2 1 Disabled 1
<21> PCH_CPU_BCLK_R_D PCH_CPU_BCLK_R_D# BCLKP CFG[0]
A32 BN27 CFG1 51_0402_5% RC306
<21> PCH_CPU_BCLK_R_D#
2
BCLKN CFG[1] BN26 CFG2
1 2 H_PROCHOT# PCH_CPU_PCIBCLK_R_D D35 CFG[2] BN28 CFG3
<21> PCH_CPU_PCIBCLK_R_D PCH_CPU_PCIBCLK_R_D# PCI_BCLKP CFG[3] Enabled 0
RC180 1K_0402_5% C36 BR20 CFG4
<21> PCH_CPU_PCIBCLK_R_D# PCI_BCLKN CFG[4] CPU_XDP_TMS 1
BM20 CFG5 2
CPU_24MHZ_R_D CFG[5] PCH_JTAG_TMS <23>
E31 BT20 CFG6 @ RC307 0_0402_5%
<21> CPU_24MHZ_R_D CPU_24MHZ_R_D# CLK24P CFG[6] CPU_XDP_TDI
D31 BP20 CFG7 1 2
<21> CPU_24MHZ_R_D# CLK24N CFG[7] PCH_JTAG_TDI <23>
BR23 CFG8 @ RC308 0_0402_5% CFG5
CFG[8] BR22 CPU_XDP_TDO 1 2
B
CFG[9]
CFG9
PCH_JTAG_TDO <23> PCI Express* Bifurcation B
1
+1.0V_VCCST BT23 CFG10 @ RC309 0_0402_5% [6:5]
CFG[10] BT22 CFG11 CPU_XDP_TCLK 1 2 @ RC323
CFG[11] PCH_JTAGX <23> RC143 for XDP debug
BM19 CFG12 RC143 0_0402_5% 1K_0402_5%
CFG[12] BR19 CFG13 CPU_XDP_PREQ# 1 2
CFG[13] PCH_XDP_PREQ# <25> 1x8, 2x4 00
1
1
56.2_0402_1%
100_0402_5%
BP19 CFG14 @XDP@ RC315 0_0402_5%
2
CPU_VIDALERT# CFG[14] CPU_XDP_PRDY# 1
RC155
RC157
BH31 BT19 CFG15 2

VR_SVID_CLK VIDALERT# CFG[15] PCH_XDP_PRDY# <25>
<61,64> VR_SVID_CLK BH32 @XDP@ RC314 0_0402_5% Reserved 01
VR_SVID_DATA BH29 VIDSCK BN23 CFG17
H_PROCHOT# 1 2 H_PROCHOT#_R BR30 VIDSOUT CFG[17] BP23 CFG16 CFG6
<46,57,61,64> H_PROCHOT#
2
VR_SVID_DATA RC158 499_0402_1% PROCHOT# CFG[16] BP22 CFG19

<61,64> VR_SVID_DATA CFG[19] 2x8 10
1
DDR_PG_CTRL BT13 BN22 CFG18
<14> DDR_PG_CTRL DDR_VTT_CNTL CFG[18]
VR_SVID_ALERT# @ RC324
<61,64> VR_SVID_ALERT#
BR27 XDP_OBS0 1 2 XDP_OBS0_R
BPM#[0] 1K_0402_5% 1x16 11
1
XDP_OBS1 @ RC312 1 2 0_0402_5% XDP_OBS1_R

220_0402_5%
BT27
BPM#[1]
RC156
BM31 @ RC313 0_0402_5%
2
VCCST_PWRGD 1 2 VCCST_PWRGD_CPU H13 BPM#[2] BT30
<46> VCCST_PWRGD VCCST_PWRGD BPM#[3]
RC159 60.4_0402_1%
VR_SVID_DATA H_PWRGD BT31
<23> H_PWRGD
2
PLTRST_CPU# BP35 PROCPWRGD BT28 CPU_XDP_TDO

<19> PLTRST_CPU# H_PM_SYNC_R H_PM_SYNC RESET# PROC_TDO CPU_XDP_TDI PAD~D @ T184
<19> H_PM_SYNC_R 1 2 BM34 BL32
CPU_VIDALERT# H_PM_DOWN RC167 1 PM_SYNC PROC_TDI PAD~D @ T185
<19> H_PM_DOWN 2 30_0402_5%H_PM_DOWN_R BP31 BP28 CPU_XDP_TMS
H_PECI PM_DOWN PROC_TMS CPU_XDP_TCLK PAD~D @ T180
<19,46> H_PECI RC168 20_0402_5% BT34 BR28 CFG7
PCH_THERMTRIP# H_THERMTRIP# J31 PECI PROC_TCK PAD~D @ T181
<14,15,16,17,19,46> PCH_THERMTRIP# 1 2
THERMTRIP#
1
@ RC169 0_0402_5% BP30 CPU_XDP_TRST# PEG Training
H_SKTOCC# PROC_TRST# CPU_XDP_PREQ# PAD~D @ T179
1 2 BR33 BL30 @ RC325
SKTOCC# PROC_PREQ# PAD~D @ T190
@ RC319 1 2 0_0402_5% SKL_CNL# BN1 BP27 CPU_XDP_PRDY# 1K_0402_5% (default) PEG Train
PROC_SELECT# PROC_PRDY# PAD~D @ T189
@ RC171 0_0402_5% immediately following 1
H_CATERR# BM30 RESET# de-assertion
2
CATERR# BT25
1 2 CFG_RCOMP
PEG Wait for BIOS for
@ RC327 0_0402_5% training 0
1
+3.3V_ALW RC222
+3.3V_ALW 5 OF 14
REV = 1 49.9_0402_1%
A A
?
UC6
2
5
1 5
1 NC VCC
P
<46> IMVP_VR_ON_EC IN1 IMVP_VR_ON

4 2
2 O A 4 VCCST_PWRGD
<11,23,37,44,46> SIO_SLP_S3# IN2 Y
G
3
GND
3
UC5
SN74AHC1G08DCKR_SC70-5
74AUP1G07GW_TSSOP5
Title
IMVP_VR_ON <55,56,61,64>

5 4 3 2 1
SKL-H_BGA1440
5 4 3 2 1
?
SKYLAKE_HALO
CPU1B
?
SKYLAKE_HALO <16,17> DDR_B_D[0..63]
CPU1A BGA1440
BGA1440 DDR_B_D0 BT11 AM9 DDR_B_CLK0
<14,15> DDR_A_D[0..63] DDR_A_D0 DDR_A_CLK0 DDR_B_D1 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKP[0] DDR_B_CLK0 <17>
BR6 AG1 BR11 AN9 DDR_B_CLK#0
DDR_A_D1 DDR0_DQ[0] DDR0_CKP[0] DDR_A_CLK#0 DDR_A_CLK0 <15> DDR_B_D2 DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[0] DDR_B_CLK#0 <17>
BT6 AG2 BT8 AM8 DDR_B_CLK#1
DDR_A_D2 DDR0_DQ[1] DDR0_CKN[0] DDR_A_CLK#1 DDR_A_CLK#0 <15> DDR_B_D3 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKN[1] DDR_B_CLK#1 <17>
BP3 AK1 BR8 AM7 DDR_B_CLK1
DDR_A_D3 DDR0_DQ[2] DDR0_CKN[1] DDR_A_CLK1 DDR_A_CLK#1 <15> DDR_B_D4 DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] DDR_B_CLK1 <17>
BR3 AK2 BP11 AM11 DDR_B_CLK2
DDR_A_D4 DDR0_DQ[3] DDR0_CKP[1] DDR_A_CLK2 DDR_A_CLK1 <15> DDR_B_D5 DDR1_DQ[4]/DDR0_DQ[20] DDR1_CLKP[2] DDR_B_CLK2 <16>
BN5 AL3 BN11 AM10 DDR_B_CLK#2
DDR_A_D5 DDR0_DQ[4] DDR0_CLKP[2] DDR_A_CLK#2 DDR_A_CLK2 <14> DDR_B_D6 DDR1_DQ[5]/DDR0_DQ[21] DDR1_CLKN[2] DDR_B_CLK#2 <16>
BP6 AK3 BP8 AJ10 DDR_B_CLK3
DDR_A_D6 DDR0_DQ[5] DDR0_CLKN[2] DDR_A_CLK3 DDR_A_CLK#2 <14> DDR_B_D7 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CLKP[3] DDR_B_CLK3 <16>
D BP2 AL2 BN8 AJ11 DDR_B_CLK#3 D
DDR_A_D7 BN3 DDR0_DQ[6] DDR0_CLKP[3] AL1 DDR_A_CLK#3 DDR_A_CLK3 <14> DDR_B_D8 BL12 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CLKN[3] DDR_B_CLK#3 <16>
DDR_A_D8 BL4 DDR0_DQ[7] DDR0_CLKN[3] DDR_A_CLK#3 <14> DDR_B_D9 BL11 DDR1_DQ[8]/DDR0_DQ[24] AT8 DDR_B_CKE0
DDR_A_D9 DDR0_DQ[8] DDR1_DQ[9]/DDR0_DQ[25] DDR1_CKE[0] DDR_B_CKE0 <17>
BL5 AT1 DDR_A_CKE0 DDR_B_D10 BL8 AT10 DDR_B_CKE1
DDR_A_D10 DDR0_DQ[9] DDR0_CKE[0] DDR_A_CKE0 <15> DDR1_DQ[10]/DDR0_DQ[26] DDR1_CKE[1] DDR_B_CKE1 <17>
BL2 AT2 DDR_A_CKE1 DDR_B_D11 BJ8 AT7 DDR_B_CKE2
BM1 AT3 DDR_A_CKE2 DDR_B_D12 BJ11 AT11 DDR_B_CKE3
BK4 AT5 DDR_A_CKE3 DDR_B_D13 BJ10
DDR_A_D13 DDR0_DQ[12] DDR0_CKE[3] DDR_A_CKE3 <14> DDR_B_D14 DDR1_DQ[13]/DDR0_DQ[29]
BK5 BL7 AF11 DDR_B_CS#0
DDR_A_D14 DDR0_DQ[13] DDR_A_CS#0 DDR_B_D15 DDR1_DQ[14]/DDR0_DQ[30] DDR1_CS#[0] DDR_B_CS#0 <17>
BK1 AD5 BJ7 AE7 DDR_B_CS#1
DDR_A_D15 DDR0_DQ[14] DDR0_CS#[0] DDR_A_CS#1 DDR_A_CS#0 <15> DDR_B_D16 DDR1_DQ[15]/DDR0_DQ[31] DDR1_CS#[1] DDR_B_CS#1 <17>
BK2 AE2 BG11 AF10 DDR_B_CS#2
DDR_A_D16 DDR0_DQ[15] DDR0_CS#[1] DDR_A_CS#2 DDR_A_CS#1 <15> DDR_B_D17 DDR1_DQ[16]/DDR0_DQ[48] DDR1_CS#[2] DDR_B_CS#2 <16>
BG4 AD2 BG10 AE10 DDR_B_CS#3
DDR_A_D17 BG5 DDR0_DQ[16]/DDR0_DQ[32] DDR0_CS#[2] AE5 DDR_A_CS#3 DDR_A_CS#2 <14> DDR_B_D18 BG8 DDR1_DQ[17]/DDR0_DQ[49] DDR1_CS#[3] DDR_B_CS#3 <16>
DDR_A_D18 DDR0_DQ[17]/DDR0_DQ[33] DDR0_CS#[3] DDR_A_CS#3 <14> DDR_B_D19 DDR1_DQ[18]/DDR0_DQ[50]
BF4 BF8 AF7 DDR_B_ODT0
DDR_A_D19 DDR0_DQ[18]/DDR0_DQ[34] DDR_A_ODT0 DDR_B_D20 DDR1_DQ[19]/DDR0_DQ[51] DDR1_ODT[0] DDR_B_ODT0 <17>
BF5 AD3 BF11 AE8 DDR_B_ODT1
DDR_A_D20 DDR0_DQ[19]/DDR0_DQ[35] DDR0_ODT[0] DDR_A_ODT1 DDR_A_ODT0 <15> DDR_B_D21 DDR1_DQ[20]/DDR0_DQ[52] DDR1_ODT[1] DDR_B_ODT1 <17>
BG2 AE4 BF10 AE9 DDR_B_ODT2
BG1 AE1 BG7 AE11 DDR_B_ODT3
BF1 AD4 BF7
DDR_A_D23 DDR0_DQ[22]/DDR0_DQ[38] DDR0_ODT[3] DDR_A_ODT3 <14> DDR_B_D24 DDR1_DQ[23]/DDR0_DQ[55]
BF2 BB11 AH10 DDR_B_MA16
DDR_A_D24 DDR0_DQ[23]/DDR0_DQ[39] DDR_A_BA0 DDR_B_D25 DDR1_DQ[24]/DDR0_DQ[56] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] DDR_B_MA16 <16,17>
BD2 AH5 BC11 AH11 DDR_B_MA14
DDR_A_D25 DDR0_DQ[24]/DDR0_DQ[40] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDR_A_BA1 DDR_A_BA0 <14,15> DDR_B_D26 DDR1_DQ[25]/DDR0_DQ[57] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] DDR_B_MA14 <16,17>
BD1 AH1 BB8 AF8 DDR_B_MA15
DDR_A_D26 DDR0_DQ[25]/DDR0_DQ[41] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR_A_BG0 DDR_A_BA1 <14,15> DDR_B_D27 DDR1_DQ[26]/DDR0_DQ[58] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] DDR_B_MA15 <16,17>
BC4 AU1 BC8
DDR_A_D27 BC5 DDR0_DQ[26]/DDR0_DQ[42] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR_A_BG0 <14,15> DDR_B_D28 BC10 DDR1_DQ[27]/DDR0_DQ[59] AH8 DDR_B_BA0
DDR_A_D28 BD5 DDR0_DQ[27]/DDR0_DQ[43] AH4 DDR_A_MA16 DDR_B_D29 BB10 DDR1_DQ[28]/DDR0_DQ[60] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] AH9 DDR_B_BA1 DDR_B_BA0 <16,17>
DDR_A_D29 DDR0_DQ[28]/DDR0_DQ[44] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] DDR_A_MA16 <14,15> DDR1_DQ[29]/DDR0_DQ[61] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR_B_BA1 <16,17>
BD4 AG4 DDR_A_MA14 DDR_B_D30 BC7 AR9 DDR_B_BG0
DDR_A_D30 DDR0_DQ[29]/DDR0_DQ[45] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] DDR_A_MA14 <14,15> DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR_B_BG0 <16,17>
BC1 AD1 DDR_A_MA15 DDR_B_D31 BB7
DDR_A_D31 DDR0_DQ[30]/DDR0_DQ[46] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] DDR_A_MA15 <14,15> DDR_B_D32 DDR1_DQ[31]/DDR0_DQ[63] DDR_B_MA[0..13] <16,17>
BC2 AA11 AJ9 DDR_B_MA0
DDR_A_D32 DDR0_DQ[31]/DDR0_DQ[47] DDR_A_MA0 DDR_A_MA[0..13] <14,15> DDR_B_D33 DDR1_DQ[32]/DDR1_DQ[16] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
AB1 AH3 AA10 AK6 DDR_B_MA1
DDR_A_D33 AB2 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] AP4 DDR_A_MA1 DDR_B_D34 AC11 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] AK5 DDR_B_MA2
DDR_A_D34 AA4 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] AN4 DDR_A_MA2 DDR_B_D35 AC10 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] AL5 DDR_B_MA3
DDR_A_D35 AA5 DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] AP5 DDR_A_MA3 DDR_B_D36 AA7 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[3] AL6 DDR_B_MA4
DDR_A_D36 AB5 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] AP2 DDR_A_MA4 DDR_B_D37 AA8 DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[4] AM6 DDR_B_MA5
DDR_A_D37 AB4 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] AP1 DDR_A_MA5 DDR_B_D38 AC8 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AN7 DDR_B_MA6
C DDR_A_D38 AA2 DDR0_DQ[37]/DDR1_DQ[5] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] AP3 DDR_A_MA6 DDR_B_D39 AC7 DDR1_DQ[38]/DDR1_DQ[22] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] AN10 DDR_B_MA7 C
DDR_A_D39 AA1 DDR0_DQ[38]/DDR1_DQ[6] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] AN1 DDR_A_MA7 DDR_B_D40 W8 DDR1_DQ[39]/DDR1_DQ[23] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AN8 DDR_B_MA8
DDR_A_D40 V5 DDR0_DQ[39]/DDR1_DQ[7] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AN3 DDR_A_MA8 DDR_B_D41 W7 DDR1_DQ[40]/DDR1_DQ[24] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] AR11 DDR_B_MA9
DDR_A_D41 V2 DDR0_DQ[40]/DDR1_DQ[8] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] AT4 DDR_A_MA9 DDR_B_D42 V10 DDR1_DQ[41]/DDR1_DQ[25] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] AH7 DDR_B_MA10
DDR_A_D42 U1 DDR0_DQ[41]/DDR1_DQ[9] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] AH2 DDR_A_MA10 DDR_B_D43 V11 DDR1_DQ[42]/DDR1_DQ[26] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AN11 DDR_B_MA11
DDR_A_D43 U2 DDR0_DQ[42]/DDR1_DQ[10] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] AN2 DDR_A_MA11 DDR_B_D44 W11 DDR1_DQ[43]/DDR1_DQ[27] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AR10 DDR_B_MA12
DDR_A_D44 V1 DDR0_DQ[43]/DDR1_DQ[11] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] AU4 DDR_A_MA12 DDR_B_D45 W10 DDR1_DQ[44]/DDR1_DQ[28] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AF9 DDR_B_MA13
DDR_A_D45 V4 DDR0_DQ[44]/DDR1_DQ[12] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] AE3 DDR_A_MA13 DDR_B_D46 V7 DDR1_DQ[45]/DDR1_DQ[29] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] AR7 DDR_B_BG1
DDR_A_D46 DDR0_DQ[45]/DDR1_DQ[13] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] DDR_A_BG1 DDR_B_D47 DDR1_DQ[46]/DDR1_DQ[30] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR_B_BG1 <16,17>
U5 AU2 V8 AT9 DDR_B_ACT#
DDR_A_D47 U4 DDR0_DQ[46]/DDR1_DQ[14] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] AU3 DDR_A_ACT# DDR_A_BG1 <14,15> DDR_B_D48 R11 DDR1_DQ[47]/DDR1_DQ[31] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR_B_ACT# <16,17>
DDR_A_D48 DDR0_DQ[47]/DDR1_DQ[15] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR_A_ACT# <14,15> DDR_B_D49 DDR1_DQ[48]
R2 P11 AJ7 DDR_B_PARITY
DDR_A_D49 DDR0_DQ[48]/DDR1_DQ[32] DDR1_DQ[49] DDR1_PAR DDR_B_PARITY <16,17>
P5 AG3 DDR_A_PARITY DDR_B_D50 P7 AR8 DDR_B_ALERT#
DDR_A_D50 DDR0_DQ[49]/DDR1_DQ[33] DDR0_PAR DDR_A_PARITY <14,15> DDR1_DQ[50] DDR1_ALERT# DDR_B_ALERT# <16,17>
R4 AU5 DDR_A_ALERT# DDR_B_D51 R8
DDR_A_D51 DDR0_DQ[50]/DDR1_DQ[34] DDR0_ALERT# DDR_A_ALERT# <14,15> DDR_B_D52 DDR1_DQ[51]
P4 R10
DDR_A_D52 DDR0_DQ[51]/DDR1_DQ[35] DDR_B_D53 DDR1_DQ[52] DDR_B_DQS#0 DDR_B_DQS#[0..7] <16,17>
R5 P10 BP9
DDR_A_D53 DDR0_DQ[52]/DDR1_DQ[36] DDR_A_DQS#0 DDR_A_DQS#[0..3] <14,15> DDR_B_D54 DDR1_DQ[53] DDR1_DQSN[0]/DDR0_DQSN[2] DDR_B_DQS#1
P2 BR5 R7 BL9
DDR_A_D54 R1 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSN[0] BL3 DDR_A_DQS#1 DDR_B_D55 P8 DDR1_DQ[54] DDR1_DQSN[1]/DDR0_DQSN[3] BG9 DDR_B_DQS#2
DDR_A_D55 P1 DDR0_DQ[54]/DDR1_DQ[38] DDR0_DQSN[1] BG3 DDR_A_DQS#2 DDR_B_D56 L11 DDR1_DQ[55] DDR1_DQSN[2]/DDR0_DQSN[6] BC9 DDR_B_DQS#3
DDR_A_D56 M4 DDR0_DQ[55]/DDR1_DQ[39] DDR0_DQSN[2]/DDR0_DQSN[4] BD3 DDR_A_DQS#3 DDR_B_D57 M11 DDR1_DQ[56] DDR1_DQSN[3]/DDR0_DQSN[7] AC9 DDR_B_DQS#4
DDR_A_D57 DDR0_DQ[56]/DDR1_DQ[40] DDR0_DQSN[3]/DDR0_DQSN[5] DDR_A_DQS4 DDR_A_DQS[4..7] <14,15> DDR_B_D58 DDR1_DQ[57] DDR1_DQSN[4]/DDR1_DQSN[2] DDR_B_DQS#5
M1 AB3 L7 W9
DDR_A_D58 L4 DDR0_DQ[57]/DDR1_DQ[41] DDR0_DQSP[4]/DDR1_DQSP[0] V3 DDR_A_DQS5 DDR_B_D59 M8 DDR1_DQ[58] DDR1_DQSN[5]/DDR1_DQSN[3] R9 DDR_B_DQS#6
DDR_A_D59 L2 DDR0_DQ[58]/DDR1_DQ[42] DDR0_DQSP[5]/DDR1_DQSP[1] R3 DDR_A_DQS6 DDR_B_D60 L10 DDR1_DQ[59] DDR1_DQSN[6] M9 DDR_B_DQS#7
DDR_A_D60 M5 DDR0_DQ[59]/DDR1_DQ[43] DDR0_DQSP[6]/DDR1_DQSP[4] M3 DDR_A_DQS7 DDR_B_D61 M10 DDR1_DQ[60] DDR1_DQSN[7]
DDR_A_D61 DDR0_DQ[60]/DDR1_DQ[44] DDR0_DQSP[7]/DDR1_DQSP[5] DDR_B_D62 DDR1_DQ[61] DDR_B_DQS0 DDR_B_DQS[0..7] <16,17>
M2 M7 BR9
DDR_A_D62 DDR0_DQ[61]/DDR1_DQ[45] DDR_A_DQS0 DDR_A_DQS[0..3] <14,15> DDR_B_D63 DDR1_DQ[62] DDR1_DQSP[0]/DDR0_DQSP[2] DDR_B_DQS1
L5 BP5 L8 BJ9
DDR_A_D63 L1 DDR0_DQ[62]/DDR1_DQ[46] DDR0_DQSP[0] BK3 DDR_A_DQS1 DDR1_DQ[63] DDR1_DQSP[1]/DDR0_DQSP[3] BF9 DDR_B_DQS2
DDR0_DQ[63]/DDR1_DQ[47] DDR0_DQSP[1] DDR_A_DQS2 <16,17> DDR_B_CB[0..7] DDR_B_CB0 DDR1_DQSP[2]/DDR0_DQSP[6] DDR_B_DQS3
BF3 AW11 BB9
<14,15> DDR_A_CB[0..7] DDR_A_CB0 DDR0_DQSP[2]/DDR0_DQSP[4] DDR_A_DQS3 DDR_B_CB1 DDR1_ECC[0] DDR1_DQSP[3]/DDR0_DQSP[7] DDR_B_DQS4
BA2 BC3 AY11 AA9
DDR_A_CB1 DDR0_ECC[0] DDR0_DQSP[3]/DDR0_DQSP[5] DDR_A_DQS#4 DDR_A_DQS#[4..7] <14,15> DDR_B_CB2 DDR1_ECC[1] DDR1_DQSP[4]/DDR1_DQSP[2] DDR_B_DQS5
BA1 AA3 AY8 V9
DDR_A_CB2 AY4 DDR0_ECC[1] DDR0_DQSN[4]/DDR1_DQSN[0] U3 DDR_A_DQS#5 DDR_B_CB3 AW8 DDR1_ECC[2] DDR1_DQSP[5]/DDR1_DQSP[3] P9 DDR_B_DQS6
DDR_A_CB3 AY5 DDR0_ECC[2] DDR0_DQSN[5]/DDR1_DQSN[1] P3 DDR_A_DQS#6 DDR_B_CB4 AY10 DDR1_ECC[3] DDR1_DQSP[6] L9 DDR_B_DQS7
DDR_A_CB4 BA5 DDR0_ECC[3] DDR0_DQSN[6]/DDR1_DQSN[4] L3 DDR_A_DQS#7 DDR_B_CB5 AW10 DDR1_ECC[4] DDR1_DQSP[7]
B DDR_A_CB5 BA4 DDR0_ECC[4] DDR0_DQSN[7]/DDR1_DQSN[5] DDR_B_CB6 AY7 DDR1_ECC[5] AW9 DDR_B_DQS8 B
DDR_A_CB6 DDR0_ECC[5] DDR1_ECC[6] DDR1_DQSP[8] DDR_B_DQS8 <16,17>
AY1 AY3 DDR_A_DQS8 DDR_B_CB7 AW7 AY9 DDR_B_DQS#8
DDR_A_CB7 AY2 DDR0_ECC[6] DDR0_DQSP[8] BA3 DDR_A_DQS#8 DDR_A_DQS8 <14,15> DDR1_ECC[7] DDR1_DQSN[8] DDR_B_DQS#8 <16,17>
DDR0_ECC[7] DDR0_DQSN[8] DDR_A_DQS#8 <14,15>
DDR CHANNEL B
1 2 DDR_RCOMP0 G1 BN13
DDR CHANNEL A DDR_RCOMP[0] DDR_VREF_CA +DDR_VREF_CA
RD18 1 2 121_0402_1% DDR_RCOMP1 H1 BP13
DDR_RCOMP2 J2 DDR_RCOMP[1] DDR0_VREF_DQ PAD~D @ T199
RD21 1 2 75_0402_1% BR13 +DDR_VREF_B_DQ
RD22 100_0402_1% DDR_RCOMP[2] DDR1_VREF_DQ
2 OF 14
1 OF 14 SKL-H_BGA1440
REV = 1 ?
SKL-H_BGA1440
REV = 1 ?
A A
Title

5 4 3 2 1
5 4 3 2 1
?
SKYLAKE_HALO
CPU1D
BGA1440
CPU_DP1_P0 K36 D29 EDP_TXP0
<31> CPU_DP1_P0 CPU_DP1_N0 K37 DDI1_TXP[0] EDP_TXP[0] E29 EDP_TXN0 EDP_TXP0 <29>
<31> CPU_DP1_N0 CPU_DP1_P1 J35 DDI1_TXN[0] EDP_TXN[0] F28 EDP_TXP1 EDP_TXN0 <29>
<31> CPU_DP1_P1 CPU_DP1_N1 J34 DDI1_TXP[1] EDP_TXP[1] E28 EDP_TXN1 EDP_TXP1 <29>
<31> CPU_DP1_N1 CPU_DP1_P2 H37 DDI1_TXN[1] EDP_TXN[1] B29 EDP_TXN2 EDP_TXN1 <29>
<31> CPU_DP1_P2 CPU_DP1_N2 H36 DDI1_TXP[2] EDP_TXN[2] A29 EDP_TXP2 EDP_TXN2 <29>
Dock Port1 <31> CPU_DP1_N2 CPU_DP1_P3 DDI1_TXN[2] EDP_TXP[2] EDP_TXN3 EDP_TXP2 <29>
J37 B28
<31> CPU_DP1_P3 CPU_DP1_N3 J38 DDI1_TXP[3] EDP_TXN[3] C28 EDP_TXP3 EDP_TXN3 <29>
D <31> CPU_DP1_N3 DDI1_TXN[3] EDP_TXP[3] EDP_TXP3 <29> D
CPU_DP1_AUXP D27 C26 EDP_AUXP
<31> CPU_DP1_AUXP CPU_DP1_AUXN DDI1_AUXP EDP_AUXP EDP_AUXN EDP_AUXP <29>
E27 B26
<31> CPU_DP1_AUXN DDI1_AUXN EDP_AUXN EDP_AUXN <29>
CPU_DP2_P0 H34
<34> CPU_DP2_P0 CPU_DP2_N0 H33 DDI2_TXP[0]
<34> CPU_DP2_N0 CPU_DP2_P1 F37 DDI2_TXN[0] A33
<34> CPU_DP2_P1 CPU_DP2_N1 DDI2_TXP[1] EDP_DISP_UTIL PAD~D @ T194
G38
<34> CPU_DP2_N1 CPU_DP2_P2 F34 DDI2_TXN[1] COMPENSATION PU FOR
<34> CPU_DP2_P2 DDI2_TXP[2]
TBT <34> CPU_DP2_N2
CPU_DP2_N2
CPU_DP2_P3
F35
E37 DDI2_TXN[2] EDP_RCOMP
D37 EDP_COMP eDP
<34> CPU_DP2_P3 CPU_DP2_N3 E36 DDI2_TXP[3] +VCC_IO
<34> CPU_DP2_N3 DDI2_TXN[3]
CPU_DP2_AUXP F26
<34> CPU_DP2_AUXP CPU_DP2_AUXN E26 DDI2_AUXP EDP_COMP 2 1
<34> CPU_DP2_AUXN DDI2_AUXN 24.9_0402_1% RC1
CPU_DP3_P0 C34
<33> CPU_DP3_P0 CPU_DP3_N0 D34 DDI3_TXP[0]
<33> CPU_DP3_N0 CPU_DP3_P1 B36 DDI3_TXN[0] CAD Note:Trace width=20 mils
<33> CPU_DP3_P1 CPU_DP3_N1 B34 DDI3_TXP[1] ,Spacing=25mil,
<33> CPU_DP3_N1 CPU_DP3_P2 F33 DDI3_TXN[1] Max length=100 mils.
<33> CPU_DP3_P2 CPU_DP3_N2 E33 DDI3_TXP[2]
C <33> CPU_DP3_N2 CPU_DP3_P3 C33 DDI3_TXN[2] C
<33> CPU_DP3_P3 CPU_DP3_N3 B33 DDI3_TXP[3]
mDP/TBT <33> CPU_DP3_N3 DDI3_TXN[3] AUD_AZACPU_SCLK
G27
CPU_DP3_AUXP PROC_AUDIO_CLK AUD_AZACPU_SDO AUD_AZACPU_SCLK <23>
A27 G25
<33> CPU_DP3_AUXP CPU_DP3_AUXN DDI3_AUXP PROC_AUDIO_SDI AUD_AZACPU_SDI AUD_AZACPU_SDO <23>
B27 G29
<33> CPU_DP3_AUXN DDI3_AUXN PROC_AUDIO_SDO
4 OF 14
SKL-H_BGA1440 ?
REV = 1 AUD_AZACPU_SDI 1 2AUD_AZACPU_SDI_R
AUD_AZACPU_SDI_R <23>
RC66 20_0402_5%
B B
A DELL CONFIDENTIAL/PROPRIETARY A

Title
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-C551P
5 4 3 2 1
5 4 3 2 1
?
SKYLAKE_HALO
+VCC_EDRAM CPU1J
BGA1440
3.3A ?
SKYLAKE_HALO
BJ17 CPU1K
BJ19 VCCOPC
BJ20 VCCOPC BGA1440
BK17 VCCOPC PAD~D @ T1 D1 BM33 T26 @ PAD~D

BK19 VCCOPC PAD~D @ T2 E1 RSVD_TP RSVD_TP BL33 T25 @ PAD~D
BK20 VCCOPC PAD~D @ T3 E3 RSVD_TP RSVD_TP
BL16 VCCOPC PAD~D @ T4 E2 RSVD_TP BJ14 T28 @ PAD~D
BL17 VCCOPC RSVD_TP RSVD_TP BJ13 T27 @ PAD~D
BL18 VCCOPC PAD~D @ T5 BR1 RSVD_TP
BL19 VCCOPC PAD~D @ T6 BT2 RSVD_TP BK28 T29 @ PAD~D
BL20 VCCOPC RSVD_TP RSVD BJ28 T30 @ PAD~D
BL21 VCCOPC PAD~D @ T7 BN35 RSVD
D +VCC_EDRAM_ED2 BM17 VCCOPC RSVD BJ18 D
BN17 VCCOPC PAD~D @ T9 J24 VSS
VCCOPC PAD~D @ T10 H24 RSVD BJ16 T31 @ PAD~D
BJ23 PAD~D @ T11 BN33 RSVD RSVD_TP BK16 T32 @ PAD~D
BJ26 RSVD PAD~D @ T8 BL34 RSVD RSVD_TP
RSVD RSVD
1
100_0603_1%~D
BJ27
RSVD
@ RC173
BK23 PAD~D @ T14 N29 BK24 T34 @ PAD~D
BK26 RSVD PAD~D @ T13 R14 RSVD RSVD_TP BJ24 T33 @ PAD~D
BK27 RSVD PAD~D @ T15 AE29 RSVD RSVD_TP
+VCC_EDRAM_FUSEPRG_ED2 +1.8V_RUN_EDRAM_ED2 BL23 RSVD PAD~D @ T12 AA14 RSVD BK21 T36 @ PAD~D
2
BL24 RSVD RSVD RSVD BJ21 T35 @ PAD~D
BL25 RSVD A36 RSVD
1 2 BL26 RSVD A37 RSVD BT17 T37 @ PAD~D
@ RC226 100_0603_1% BL27 RSVD RSVD RSVD BR17 T38 @ PAD~D
BL28 RSVD PCH_2_CPU_TRIGGER H23 RSVD
BM24 RSVD <25> PCH_2_CPU_TRIGGER CPU_2_PCH_TRIGGER_R J23 PROC_TRIGIN BK18
RSVD PROC_TRIGOUT VSS
PAD~D @ T16 TP_SKL_F30 F30 BJ34 T39 @ PAD~D
VCC_EDRAM_SENSE BL15 PAD~D @ T17 TP_SKL_E30 E30 RSVD RSVD_TP BJ33 T40 @ PAD~D
<55> VCC_EDRAM_SENSE VSS_EDRAM_SENSE VCCOPC_SENSE RSVD RSVD_TP
BM16
<55> VSS_EDRAM_SENSE VSSOPC_SENSE PAD~D @ T18 B30
1 2 VCC_EDRAM_SENSE_ED2 BL22 PAD~D @ T19 C30 RSVD
@ RC174 1 2 100_0603_1% VSS_EDRAM_SENSE_ED2 BM22 RSVD RSVD G13 T42 @ PAD~D
@ RC223 0_0603_5% RSVD PAD~D @ T21 G3 RSVD AJ8 T41 @ PAD~D
PAD~D @ T20 J3 RSVD RSVD BL31 T44 @ PAD~D
3.2A RSVD RSVD
BP15
+VCC_EOPIO VCCEOPIO
BR15 B2 T43 @ PAD~D
BT15 VCCEOPIO NCTF B38 T45 @ PAD~D
VCCEOPIO NCTF BP1 T46 @ PAD~D
BP16 PAD~D @ T23 BR35 NCTF BR2 T47 @ PAD~D
+VCC_EOPIO_ED2 RSVD RSVD NCTF
BR16 PAD~D @ T24 BR31 C1 T48 @ PAD~D
1 2 BT16 RSVD PAD~D @ T22 BH30 RSVD NCTF C38 T49 @ PAD~D
@ RC175 100_0603_1% RSVD RSVD NCTF
BN15 11 OF 14
C <56> VCC_EOPIO_SENSE VCCEOPIO_SENSE C
BM15 SKL-H_BGA1440
<56> VSS_EOPIO_SENSE VSSEOPIO_SENSE REV = 1 ?
1 2 VCC_EOPIO_SENSE_ED3 BP17
@ RC176 1 2 100_0603_1% VSS_EOPIO_SENSE_ED3 BN16 RSVD
@ RC224 0_0603_5% RSVD
BM14
+1.8V_RUN_EDRAM VCC_OPC_1P8 CPU_2_PCH_TRIGGER 1 CPU_2_PCH_TRIGGER_R
BL14 2
+VCC_EDRAM_FUSEPRG VCC_OPC_1P8 <25> CPU_2_PCH_TRIGGER
RC177 30_0402_5%
BJ35
+1.8V_RUN_EDRAM_ED2 RSVD
BJ36
+VCC_EDRAM_FUSEPRG_ED2 RSVD TP_SKL_F30 1 2
TP_SKL_E30 @ RC1781 2 0_0402_5%
AT13 @ RC179 0_0402_5%
<55,56> CPU_ZVM# ZVM#
AW13
<56> CPU_MSM# MSM#
CPU_ZVM#_ED2 AU13
1 2 CPU_MSM#_ED2 AY13 ZVM2#
@ RC230 100_0603_1% MSM2#
1 2 CPU_EOPIO_RCOMP BT29
RC227 1 2 49.9_0402_1% EDRAM_OPIO_RCOMP BR25 OPC_RCOMP
RC228 1 2 49.9_0402_1% EDRAM_OPIO_RCOMP_ED2 BP25 OPCE_RCOMP
RC229 49.9_0402_1% OPCE_RCOMP2
10 OF 14
SKL-H_BGA1440
REV = 1 ?
B B
A A
Title

5 4 3 2 1
5 4 3 2 1
+VCC_GT +VCC_SA +1.2V_MEM

+VCC_GT
?
SKYLAKE_HALO ?
SKYLAKE_HALO
CPU1H CPU1I
BGA1440 BGA1440 12A
BG34 J30 AA6
VCCGT AV29 VCCSA VDDQ
BG35 VCCGT K29 AE12
BG36 VCCGT K30 AF5
BH33 VCCGT K31 AF6
BH34 VCCGT K32 AG5
BH35 VCCGT K33 AG9
VCCGT AV34 VCCSA VDDQ +1.2V_MEM +VCC_SFR_OC
BH36 VCCGT K34 AJ12
BH37 VCCGT K35 AL11
BH38 VCCGT L31 AP6 PDDG page19, if don`t support DS3, contact to VDDQ directly
VCCGT AW14 VCCSA VDDQ
BJ37 VCCGT L32 AP7 2 1
D VCCGT AW31 VCCSA VDDQ D
BJ38 VCCGT L35 AR12 @ RC302 0_0402_5%
BL36 VCCGT L36 AR6 UZ30
BL37 VCCGT L37 AT12 1
BM36 VCCGT L38 AW6 2 VIN1
VCCGT AW35 VCCSA VDDQ VIN2
BM37 VCCGT M29 AY6
VCCGT AW36 VCCSA VDDQ +5V_ALW
BN36 VCCGT M30 J5 7 6
VCCGT AW37 VCCSA VDDQ VIN thermal VOUT
BN37 VCCGT M31 J6
0.1U_0402_10V7K
BN38 VCCGT M32 K12 3
VCCGT AY29 VCCSA VDDQ VBIAS
@ CZ95
BP37 VCCGT M33 K6
VCCGT AY30 VCCSA VDDQ
BP38 VCCGT M34 L12 1 4 5
VCCGT AY31 VCCSA VDDQ ON GND
1
1U_0402_6.3V6K
0.1U_0402_10V7K
@ CZ96
BR37 VCCGT M35 L6
AY32
2
VCCGT VCCSA VDDQ
CZ97
BT37 VCCGT M36 R6
VCCGT AY35 VCCSA VDDQ
BE38 VCCGT T6 TPS22961DNYR_WSON8
AY36
2
BF13 VCCGT VDDQ W6 2
VCCGT AY37
BF14 VCCGT AG12 VDDQ
VCCGT AY38 +VCC_IO
BF29 VCCGT G15 VCCIO Y12
VCCGT BA13 +VCC_VDDQ_CLK
BF30 VCCGT G17 VCCIO VDDQC
VCCGT BA14
BF31 VCCGT G19 VCCIO BH13 1 2
VCCGT BA29 +VCC_SFR_OC <7,11,23,37,44,46> SIO_SLP_S3#
BF32 VCCGT G21 VCCIO VCCPLL_OC G11 @ RC332 0_0402_5%
VCCGT BA30
BF35 VCCGT H15 VCCIO VCCPLL_OC
VCCGT BA31
BF36 VCCGT H16 VCCIO
VCCGT BA32
BF37 VCCGT H17 VCCIO H30 +3.3V_ALW
VCCGT BA33 +1.0V_VCCST
BF38 VCCGT H19 VCCIO VCCST @ C1471
VCCGT BA34
BG29 VCCGT H20 VCCIO H29 1 2
VCCGT BA35 +1.0V_VCCSTG
BG30 VCCGT H21 VCCIO VCCSTG
VCCGT BA36
BG31 VCCGT H26 VCCIO G30 0.1U_0402_10V7K
VCCGT BB13
VCCGT VCCIO VCCSTG
5
BG32 VCCGT H27
VCCGT BB14 VCCIO
BG33 VCCGT J15 H28 1
P
VCCGT BB31 VCCIO VCCPLL +1.0V_VCCSFR <46,49,58,59> SIO_SLP_SUS# IN1
BC36 VCCGT J16 J28 4
VCCGT BB32 VCCIO VCCPLL O
BC37 VCCGT J17 2
VCCGT BB33 VCCIO <11,23,37,46,52,54> SIO_SLP_S4# IN2
G
BC38 VCCGT J19 UC7
VCCGT BB34 VCCIO VCC_SA_SENSE
BD13 VCCGT J20 M38 SN74AHC1G08DCKR_SC70-5
BB35 VCC_SA_SENSE <61>
3
C BD14 VCCGT J21 VCCIO VCCSA_SENSE M37 VSS_SA_SENSE C
VCCGT BB36 VSS_SA_SENSE <61>
BD29 VCCGT J26 VCCIO VSSSA_SENSE
VCCGT BB37
BD30 VCCGT J27 VCCIO H14 VCC_IO_SENSE
VCCGT BB38 VCC_IO_SENSE <53>
BD31 VCCGT VCCIO VCCIO_SENSE J14 VSS_IO_SENSE
VCCGT BC29 VSS_IO_SENSE <53>
BD32 VCCGT VSSIO_SENSE
VCCGT BC30
BD33 VCCGT
VCCGT BC31
BD34 VCCGT
VCCGT BC32
BD35 VCCGT
VCCGT BC35
BD36 VCCGT
VCCGT BE33
BE31 VCCGT
VCCGT BE34
BE32 VCCGT
VCCGT BE35
BE37 VCCGT
VCCGT BE36 9 OF 14
VCCGT SKL-H_BGA1440
VCCGT
REV = 1 ?
8 OF 14
SKL-H_BGA1440
?
REV = 1
+VCC_VDDQ_CLK +1.2V_MEM
+1.0V_VCCSTG +1.0V_VCCST
1 2
1 2 @ RC220 0_0402_5%
@ RC317 0_0402_5%
B B
+1.0V_VCCSTG source +1.0V_VCCSTG
+1.0V_VCCST source
1
@ +1.0V_PRIM
+1.0V_PRIM PJP7
PAD-OPEN1x3m UZ18
UZ19 1 +1.0V_VCCST +1.0V_VCCSFR
1 2 VIN1
2 VIN1 VIN2 @ PJP6
2
VIN2 +5V_ALW 7 6 +1.0V_VCCST_UZ18 2 1 1 2

+5V_ALW 7 6 +1.0V_VCCSTG_C 1 2 VIN thermal VOUT @ RC304 0_0603_5%
VIN thermal VOUT @ CZ82 0.1U_0402_10V7K 3
3 VBIAS PAD-OPEN1x1m
VBIAS 1
1
1U_0402_6.3V6K
0.1U_0402_10V7K
@ CZ89
1 4 5
ON GND
1
1
1U_0402_6.3V6K
0.1U_0402_10V7K
@ CZ86
CZ90
4 5
ON GND
CZ88
CZ63
2
2 TPS22961DNYR_WSON8 0.1U_0402_10V7K
2
2
2 TPS22961DNYR_WSON8 4.4mohm/6A @
4.4mohm/6A TR=12.5us@Vin=1.05V
TR=12.5us@Vin=1.05V
+3.3V_ALW
@ C1421
1 2 1 2
<11,23,37,46,52,54> SIO_SLP_S4#
RC303 0_0402_5%
0.1U_0402_10V7K
5
A A
1
P
<23,37> SIO_SLP_S0# IN1 4

1 2 2 O
<7,11,23,37,44,46> SIO_SLP_S3# IN2
G
RC331 0_0402_5% UC1

1 SN74AHC1G08DCKR_SC70-5 DELL CONFIDENTIAL/PROPRIETARY
3
@ CC273
220P_0402_25V8J 1 2 Compal Electronics, Inc.
2 @ RC320 0_0402_5% Title

5 4 3 2 1
5 4 3 2 1
PLACE CAP IN
SOCKET EDGE TOP PLACE CAP BACKSIDE
+VCC_EOPIO +1.8V_RUN_EDRAM +VCC_VDDQ_CLK +1.0V_VCCSTG +1.0V_VCCSFR +1.0V_VCCST +VCC_SFR_OC +VCC_GT +VCC_GTU
PLACE CAP BACKSIDE ?

SKYLAKE_HALO
CPU1N
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
BGA1440 +VCC_CORE +VCC_CORE
?
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 2 2 2 2 2 2 AJ29
AJ30 VCCGT
VCCGT AF29
CPU1GSKYLAKE_HALO
CC173
CC174
CC169
CC190
CC185
CC186
CC195
CC192
CC191
CC210
CC209
AJ31 VCCGTX
VCCGT AF30
AJ32 VCCGTX
2 2 2 2 2 1 1 1 1 1 1 VCCGT AF31 BGA1440
AJ33 VCCGTX
VCCGT AF32
AJ34 VCCGTX AA13 V32
VCCGT AF33 VCC VCC
AJ35 VCCGTX AA31 V33
VCCGT AF34 VCC VCC
D AJ36 VCCGTX AA32 V34 D
VCCGT AG13 VCC VCC
AK31 VCCGTX AA33 V35
VCCGT AG14 VCC VCC
VCCGT AG31 VCC VCC
VCCGT AG32 VCC VCC
VCCGT AG33 VCC VCC
AK35 VCCGTX AA37 W13
VCCGT AG34 VCC VCC
+VCC_EDRAM +VCC_IO AK36 VCCGTX AA38 W14
VCCGT AG35 VCC VCC
+VCC_SA AK37 VCCGTX AB29 W29
VCCGT AG36 VCC VCC
PLACE CAP BACKSIDE PLACE CAP BACKSIDE AK38 VCCGTX AB30 W30
VCCGT AH13 VCC VCC
PLACE CAP BACKSIDE AL13 VCCGTX AB31 W31
VCCGT AH14 VCC VCC
AL29 VCCGTX AB32 W32
VCCGT AH29 VCC VCC
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
VCCGT AH30 VCC VCC
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1 1 1 1 1 AL31 VCCGTX AB36 W36
VCCGT AH31 VCC VCC
1
CC189
CC188
CC187
CC272
1 1 1 1 1 1 1 AL32 VCCGTX AB37 W37
VCCGT AH32 VCC VCC
CC177
CC176
CC175
CC179
CC178
VCCGT AJ13 VCC VCC
CC198
CC197
CC196
CC201
CC200
CC199
CC202
AL36 VCCGTX AC13 Y29
AJ14
2
2 2 2 2 2 AL37 VCCGT AC14 VCC VCC Y30
VCCGTX
2 2 2 2 2 2 2 AL38 VCCGT AC29 VCC VCC Y31
AM13 VCCGT AC30 VCC VCC Y32
AM32 VCCGT AC35 VCC VCC L14
AM33 VCCGT AC36 VCC VCC P29
AM34 VCCGT AD13 VCC VCC P30
+1.0V_VCCST AM35 VCCGT AD14 VCC VCC P31
VCCGT VCC VCC
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
AM36 AD31 P32
VCCGT VCC VCC
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 2 2 2 AN13 AD32 P33
VCCGT VCC VCC
1
AN14 AD33 P34
VCCGT VCC VCC
CC182
CC181
CC180
CC184
CC183
CC203
CC204
CC205
CC213
CC212
CC211
CC208
AN31 AD34 P35
AN32 VCCGT AD35 VCC VCC P36
2
2 2 2 2 2 1 1 1 VCCGT VCC VCC
1U_0402_6.3V6K
1U_0402_6.3V6K
2 2 AN33 AD36 R13
AN34 VCCGT AD37 VCC VCC R31
VCCGT VCC VCC
CC193
C CC194 AN35
VCCGT
AD38
VCC VCC
R32
C
AN36 AE13 R33
1 1 AN37 VCCGT AE14 VCC VCC R34
AN38 VCCGT AE30 VCC VCC R35
PLACE CAP SIDE AP13 VCCGT AE31 VCC VCC R36
AP14 VCCGT AE32 VCC VCC R37
AP29 VCCGT AE35 VCC VCC R38
AP30 VCCGT AE36 VCC VCC T29
AP35 VCCGT AF35 VCC VCC T32
+1.2V_MEM AP38 VCCGT AF38 VCC VCC T37
PLACE CAP BACKSIDE AR29 VCCGT K13 VCC VCC T38
+1.2V_MEM DECOUPLING AR30 VCCGT K14 VCC VCC U29
AR31 VCCGT L13 VCC VCC U30
VCCGT VCC VCC
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
AR32 N13 U31

AR33 VCCGT AH38 VCCGT_SENSE N14 VCC VCC U32
1 1 1 1 1 1 1 1 1 1 VCCGT VCCGT_SENSE VCCGT_SENSE <61> VCC VCC
AR34 AH35 VSSGTX_SENSE N30 U33
VCCGT VSSGTX_SENSE VSSGT_SENSE VSSGTX_SENSE <64> VCC VCC
CC161
CC170
CC164
CC168
CC163
CC166
CC171
CC165
CC172
CC167
AR35 AH37 N31 U34

AR36 VCCGT VSSGT_SENSE AH36 VCCGTX_SENSE VSSGT_SENSE <61> N32 VCC VCC U35
2 2 2 2 2 2 2 2 2 2 AT14 VCCGT VCCGTX_SENSE VCCGTX_SENSE <64> N35 VCC VCC U36
AT31 VCCGT N36 VCC VCC V13
AT34 VCCGT P13 VCC VCC P14
AT35 VCCGT VCC VCC
AT36 VCCGT
AT37 VCCGT
AT38 VCCGT AG37 VCC_SENSE
VCCGT VCC_SENSE VSS_SENSE VCC_SENSE <61>
AU14 AG38
VCCGT VSS_SENSE VSS_SENSE <61>
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
AU29
AU30 VCCGT
VCCGT
1
AU31
B AU32 VCCGT B
VCCGT 7 OF 14
CC81
CC82
CC83
CC84
AU35 SKL-H_BGA1440
2
AU36 VCCGT
AU37 VCCGT REV = 1 ?
AU38 VCCGT 14 OF 14
VCCGT
SKL-H_BGA1440
?
REV = 1
VSS_SENSE 1 2 VCC_SENSE
@ RC221 49.9_0402_1%
A A
Title

5 4 3 2 1
5 4 3 2 1
?
SKYLAKE_HALO
CPU1L
CPU1M
SKYLAKE_HALO
BGA1440
BGA1440
BB4 AK30 C17 C25
SKYLAKE_HALO ? BB3 VSS VSS AK29 C13 VSS VSS C23
CPU1F
BB2 VSS VSS AK4 C9 VSS VSS C21
Y38 BGA1440
K1 BB1 VSS VSS AJ38 BT32 VSS VSS C19
Y37 VSS VSS J36 BA38 VSS VSS AJ37 BT26 VSS VSS C15
D Y14 VSS VSS J33 BA37 VSS VSS AJ6 BT24 VSS VSS C11 D
Y10 VSS VSS J22 BA10 VSS VSS AJ3 BT14 VSS VSS BM29
Y7 VSS VSS J7 BA7 VSS VSS AH34 BT5 VSS VSS BM11
W34 VSS VSS J4 BA6 VSS VSS AH33 BR36 VSS VSS BM8
W33 VSS VSS H35 B9 VSS ? VSS AH12 BR34 VSS VSS BM7
W12 VSS VSS H32 AY34 VSS VSS AH6 BR29 VSS VSS BM5
W5 VSS VSS H25 AY33 VSS VSS AG30 BR26 VSS VSS BM3
W4 VSS VSS H22 AY14 VSS VSS AG29 BR24 VSS VSS BL38
W3 VSS VSS H18 AY12 VSS VSS AG11 BR21 VSS VSS BL35
W2 VSS VSS H12 AW30 VSS VSS AG10 BR18 VSS VSS BL13
W1 VSS VSS H11 AW29 VSS VSS AG8 BR14 VSS VSS BL6
V30 VSS VSS G28 AW12 VSS VSS AG7 BR12 VSS VSS BK25
V29 VSS VSS G26 AW5 VSS VSS AG6 BR7 VSS VSS BK22
V12 VSS VSS G24 AW4 VSS VSS AF14 BP34 VSS VSS BK13
V6 VSS VSS G23 AW3 VSS VSS AF13 BP33 VSS VSS BK6
U38 VSS VSS G22 AW2 VSS VSS AF12 BP29 VSS VSS BJ30
U37 VSS VSS G20 AW1 VSS VSS AF4 BP26 VSS VSS BJ29
U6 VSS VSS G18 AV38 VSS VSS AF3 BP24 VSS VSS BJ15
T34 VSS VSS G16 AV37 VSS VSS AF2 BP21 VSS VSS BJ12
T33 VSS VSS G14 AU34 VSS VSS AF1 BP18 VSS VSS BH11
T14 VSS VSS G12 AU33 VSS VSS AE34 BP14 VSS VSS BH10
T11 VSS VSS G8 AU10 VSS VSS AD30 BN34 VSS VSS BH3
T10 VSS VSS G6 AU9 VSS VSS AD29 BN31 VSS VSS BH2
T9 VSS VSS G5 AU8 VSS VSS AD12 BN30 VSS VSS BG37
T8 VSS VSS G4 AU7 VSS VSS AD11 BN29 VSS VSS BG14
T7 VSS VSS F36 AU6 VSS VSS AD10 BN24 VSS VSS BG6
C T5 VSS VSS F31 AT30 VSS VSS AD9 BN21 VSS VSS BF34 C
T4 VSS VSS F29 AT29 VSS VSS AD8 BN20 VSS VSS BF6
T3 VSS VSS F27 AT6 VSS VSS AD7 BN19 VSS VSS BE30
T2 VSS VSS F25 AR38 VSS VSS AD6 BN18 VSS VSS BE5
T1 VSS VSS F23 AR37 VSS VSS AC38 BN14 VSS VSS BE4
R30 VSS VSS F21 AR14 VSS VSS AC37 BN12 VSS VSS BE3
P38 VSS VSS F15 AR4 VSS VSS AC5 BN4 VSS VSS BD38
P37 VSS VSS F13 AR3 VSS VSS AC4 BN2 VSS VSS BD37
P12 VSS VSS F11 AR2 VSS VSS AC3 BM38 VSS VSS BD12
P6 VSS VSS F9 AR1 VSS VSS AC2 BM35 VSS VSS BD11
N34 VSS VSS F8 AP34 VSS VSS AC1 BM28 VSS VSS BD10
N33 VSS VSS F5 AP33 VSS VSS AB34 BM27 VSS VSS BD8
N10 VSS VSS F2 AP10 VSS VSS AA30 BM21 VSS VSS BC33
N9 VSS VSS E38 AP9 VSS VSS AA29 BM13 VSS VSS BC14
N8 VSS VSS E35 AP8 VSS VSS AA12 BM12 VSS VSS BC13
N7 VSS VSS E34 AN30 VSS VSS A30 BM9 VSS VSS BC6
N6 VSS VSS E9 AN29 VSS VSS A28 BM6 VSS VSS BB30
N5 VSS VSS E4 AN12 VSS VSS A26 BM2 VSS VSS BB29
N4 VSS VSS D33 AN6 VSS VSS A24 BL29 VSS VSS BB6
N3 VSS VSS D30 AN5 VSS VSS A22 BK29 VSS VSS BB5
N2 VSS VSS D28 AM38 VSS VSS A20 BK15 VSS VSS
N1 VSS VSS D26 AM37 VSS VSS A18 BK14 VSS
M14 VSS VSS D24 AM12 VSS VSS A16 BJ32 VSS
L34 VSS VSS D16 AM2 VSS VSS A9 BH14 VSS
VSS VSS VSS VSS VSS C2
L33 D14 AM1 A6 BH12 NCTFVSS
VSS VSS VSS VSS VSS BT36
B L30 D12 AL34 BH9 NCTFVSS B
VSS VSS VSS VSS BT35
L29 D10 AL33 BH8 NCTFVSS
VSS VSS VSS VSS BT4
K38 D9 AL14 B37 BH5 NCTFVSS
VSS VSS VSS NCTFVSS VSS BT3
K11 D6 AL12 B3 BH4 NCTFVSS
VSS VSS VSS NCTFVSS VSS BR38
K10 D3 AL10 A34 BH1 NCTFVSS
K9 VSS VSS C37 AL9 VSS NCTFVSS A4 BG38 VSS
K8 VSS VSS C31 AL8 VSS NCTFVSS A3 BG13 VSS
K7 VSS VSS C29 AL7 VSS NCTFVSS BG12 VSS
K5 VSS VSS C27 AL4 VSS BF33 VSS
K4 VSS VSS VSS BF12 VSS
K3 VSS D38 BE29 VSS
K2 VSS NCTFVSS BE6 VSS
VSS 13 OF 14 BD9 VSS
? BC34 VSS
SKL-H_BGA1440
SKL-H_BGA1440 BC12 VSS
REV = 1
BB12 VSS
6 OF 14 VSS
SKL-H_BGA1440
REV = 1 ? 12 OF 14
?
REV = 1
A A
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS
DOCUMENT MAY NOT
SKYLAKE-H (8/8)
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. 1.0
IN ADDITION, LA-C551P
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED Date: Tuesday, August 18, 2015 Sheet 13 of 74
5 TO ANY4THIRD 3 2 1
5 4 3 2 1
All VREF traces should

JDIMM1 STD Type H=9.2
+1.2V_MEM +1.2V_MEM
have 10 mil trace width JDIMM1
1 2 STD
DDR_A_D4 3 VSS1
DQ5
VSS2
DQ4
4 DDR_A_D1
JDIMM1
STD
5 6
DDR_A_D0 7 VSS3
DQ1
VSS4
DQ0
8 DDR_A_D5 JDIMM3
9 10
DDR_A_DQS#0
DDR_A_DQS0
11
13
VSS5
DQS0_c
VSS6
DM0_n/DBI0_n
12
14
CPU D C Top Side
15 DQS0_t VSS7 16 DDR_A_D6
DDR_A_D7 17
19
VSS8
DQ7
VSS10
DQ6
VSS9
DQ2
18
20 DDR_A_D2 A B Bottom Side
DDR_A_D3 21 22
23 DQ3
VSS12
VSS11
DQ12
24 DDR_A_D9 JDIMM2 JDIMM4
DDR_A_D13 25 26
D DDR_A_D12
27 DQ13
VSS14
VSS13
DQ8
28 DDR_A_D8 STD REV D
29 30
31 DQ9 VSS15 32 DDR_A_DQS#1
<8,15> DDR_A_DQS#[0..7] VSS16 DQS1_c DDR_A_DQS1
33 34
35 DM1_n/DBI_n DQS1_t 36
<8,15> DDR_A_DQS[0..7] DDR_A_D15 VSS17 VSS18 DDR_A_D10 +1.2V_MEM
37 38
39 DQ15 DQ14 40
<8,15> DDR_A_D[0..63] DDR_A_D14 VSS19 VSS20 DDR_A_D11
41 42
43 DQ10 DQ11 44
<8,15> DDR_A_MA[0..13] VSS21 VSS22
1
DDR_A_D21 45 46 DDR_A_D16
47 DQ21 DQ20 48 RD7
+2.5V_MEM DDR_A_D20 49 VSS23 VSS24 50 DDR_A_D17 470_0402_1%
51 DQ17 DQ16 52
DDR_A_DQS#2 53 VSS25 VSS26 54
2
DDR_A_DQS2 55 DQS2_c DM2_n/DBI2_n 56
DQS2_t VSS27 DDR_A_D19 DDR_A_DRAMRST#
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
57 58 1 2
DDR_A_D22 VSS28 DQ22 <23> DDR4_DRAMRST#_PCH DDR_A_DRAMRST# <15>
1 1 1 1 59 60 @ RD6 1 20_0402_5% DDR_B_DRAMRST#
DQ23 VSS29 DDR_A_D23 DDR_B_DRAMRST# <16,17>
61 62 @ RD15 0_0402_5%
CD2 DDR_A_D18 VSS30 DQ18
CD3
CD7
CD8
0.1U_0402_10V6K
63 64
65 DQ19 VSS31 66 DDR_A_D24
2 2 2 2 VSS32 DQ28 1
DDR_A_D29
@ CD16
67 68
69 DQ29 VSS33 70 DDR_A_D25
DDR_A_D28 71 VSS34 DQ24 72
73 DQ25 VSS35 74 DDR_A_DQS#3 2
75 VSS36 DQS3_c 76 DDR_A_DQS3
77 DM3_n/DBI3_n DQS3_t 78
DDR_A_D27 79 VSS37 VSS38 80 DDR_A_D26
+1.2V_MEM 81 DQ30 DQ31 82
CD14 change to SGA20331E10 85 DQ26 DQ27 86
DDR_A_CB0 87 VSS41 VSS42 88 DDR_A_CB1 JDIMM1_EVENT# 1 2 PCH_THERMTRIP#
<8,15> DDR_A_CB0 CB5/NC CB4/NC DDR_A_CB1 <8,15> PCH_THERMTRIP# <7,15,16,17,19,46>
89 90 @ RD3 1K_0402_5%
DDR_A_CB5 VSS43 VSS44 DDR_A_CB4
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
91 92
<8,15> DDR_A_CB5 CB1/NC CB0/NC DDR_A_CB4 <8,15>
330U_D2_2V_Y
1 93 94
1 1 1 1 1 1 1 1 <8,15> DDR_A_DQS#8 DQS8_c DM8_n/DBI_n/NC
DDR_A_DQS8
CD89
CD15
CD9
CD10
CD11
CD12
CD13
CD90
CD14
+ 97 98
<8,15> DDR_A_DQS8 DQS8_t VSS47 DDR_A_CB7
99 100
DDR_A_CB3 VSS48 CB6/NC DDR_A_CB7 <8,15>
101 102
2 2 2 2 2 2 2 2 2 <8,15> DDR_A_CB3 CB2/NC VSS49 DDR_A_CB6
103 104
105 106
<8,15> DDR_A_CB2 CB3/NC VSS51 DDR_A_DRAMRST# +1.2V_MEM
C 107 108 1 2 C
DDR_A_CKE2 109 VSS52 RESET_n 110 DDR_A_CKE3 @ CD92 0.1U_0402_10V6K
<8> DDR_A_CKE2 CKE0 CKE1 DDR_A_CKE3 <8>
111 112
DDR_A_BG1 VDD1 VDD2 DDR_A_ACT#
0.1U_0402_10V6K
113 114
<8,15> DDR_A_BG1 BG1 ACT_n DDR_A_ACT# <8,15>
1
DDR_A_BG0 DDR_A_ALERT# +DDR_VREF_CA +V_DDR_REFCA_B
1K_0402_5%
@ CD129
115 116 1
<8,15> DDR_A_BG0 BG0 ALERT_n DDR_A_ALERT# <8,15>
RD9
117 118
DDR_A_MA12 119 VDD3 VDD4 120 DDR_A_MA11 1 2 +V_DDR_REFCA_B
DDR_A_MA9 121 A12 A11 122 DDR_A_MA7 @ RD45 2_0402_1%
123 A9 A7 124 2
2
DDR_A_MA8 VDD5 VDD6 DDR_A_MA5 +V_DDR_REFCA_A
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
125 126 1 2
DDR_A_MA6 127 A8 A5 128 DDR_A_MA4 RD23 2_0402_1%
1 1 1 1 1 1 1 1 A6 A4
0.022U_0402_16V7K
0.1U_0402_10V6K
129 130
VDD7 VDD8
1
DDR_A_MA3 DDR_A_MA2
CD4
CD5
CD6
CD93
CD95
CD94
CD96
CD97
@ CD128
1K_0402_5%
131 132 1 1
DDR_A_MA1 A3 A2 JDIMM1_EVENT#
RD10
133 134
2 2 2 2 2 2 2 2 A1 EVENT_n/NF
CD127
135 136
DDR_A_CLK2 137 VDD9 VDD10 138 DDR_A_CLK3
<8> DDR_A_CLK2 DDR_A_CLK#2 CK0_t CK1_t/NF DDR_A_CLK#3 DDR_A_CLK3 <8> 2 2
139 140
<8> DDR_A_CLK#2 DDR_A_CLK#3 <8>
2
141 CK0_c CK1_c/NF 142
DDR_A_PARITY 143 VDD11 VDD12 144 DDR_A_MA0
<8,15> DDR_A_PARITY PARITY A0
1
DDR_A_BA1 DDR_A_MA10
24.9_0402_1%
145 146
Layout Note: <8,15> DDR_A_BA1 BA1 A10/AP
RD16
147 148
VDD13 VDD14
Place near JDIMM1.258 <8> DDR_A_CS#2
DDR_A_CS#2
DDR_A_MA14
149
151 CS0_n BA0
150
152
DDR_A_BA0
DDR_A_MA16 DDR_A_BA0 <8,15>
<8,15> DDR_A_MA14 WE_n/A14 RAS_n/A16 DDR_A_MA16 <8,15>
153 154
2
DDR_A_ODT2 155 VDD15 VDD16 156 DDR_A_MA15
<8> DDR_A_ODT2 DDR_A_CS#3 ODT0 CAS_n/A15 DDR_A_MA13 DDR_A_MA15 <8,15>
157 158
<8> DDR_A_CS#3 CS1_n A13 +V_DDR_REFCA_A
159 160
+V_DDR_REFCA_A DDR_A_ODT3 161 VDD17 VDD18 162 T50 @ PAD~D
<8> DDR_A_ODT3 ODT1 C0/CS2_n/NC +V_DDR_REFCA_A
163 164
+0.6V_DDR_VTT PAD~D @ T51 165 VDD19 VREFCA 166 DIMM1_SA2
167 C1, CS3_n,NC SA2 168
DDR_A_D33 VSS53 VSS54 DDR_A_D36
0.1U_0402_10V6K
169 170
DQ37 DQ36
2.2U_0402_6.3V6M
1 1 171 172
DDR_A_D37 VSS55 VSS56 DDR_A_D32
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
@ CD75
173 174
DQ33 DQ32
CD76
1 1 1 175 176
DDR_A_DQS#4 VSS57 VSS58
CD98
177 178
2 2 DDR_A_DQS4 DQS4_c DM4_n/DBI4_n
CD17
CD19
179 180
B 2 2 2 DDR_A_D38 183 VSS60 DQ39 184 B
185 DQ38 VSS61 186 DDR_A_D34
DDR_A_D39 187 VSS62 DQ35 188
189 DQ34 VSS63 190 DDR_A_D40
DDR_A_D44 191 VSS64 DQ45 192
193 DQ44 VSS65 194 DDR_A_D45
DDR_A_D41 195 VSS66 DQ41 196
DIMM Select +3.3V_RUN +3.3V_RUN +3.3V_RUN
+3.3V_RUN
DDR_A_D43
DDR_A_D46
203
205
207
VSS69
DQ46
VSS71
VSS70
DQ47
VSS72
204
206
208
DDR_A_D47
DDR_A_D42
DQ42 DQ43
1
209 210
@ RD17 @ RD13 @ RD8 DDR_A_D50 211 VSS73 VSS74 212 DDR_A_D48
DQ52 DQ53
1
0_0402_5% 0_0402_5% 0_0402_5% 213 214

@ RD57 DDR_A_D52 215 VSS75 VSS76 216 DDR_A_D49 +3.3V_RUN
0_0603_5% 217 DQ49 DQ48 218
2

DIMM1_SA0 DDR_A_DQS6 221 DQS6_c DM6_n/DBI6_n 222
2
DQS6_t VSS79
1
DIMM1_SA1 +3.3V_RUN_DIMM1 DDR_A_D53
330K_0402_5%
223 224
DIMM1_SA2 DDR_A_D54 VSS80 DQ54
0.1U_0402_10V6K
RD61
SA0 SA1 SA2 225 226
DQ55 VSS81 DDR_A_D55
2.2U_0402_6.3V6M
1 1 227 228
VSS82 DQ50
1
DDR_A_D51
@ CD22
DIMM2 0 0 0 229 230

DQ51 VSS83 DDR_A_D56 +1.2V_MEM
CD21
@ RD30 @ RD29 @ RD28 231 232
2
0_0402_5% 0_0402_5% 0_0402_5% DDR_A_D57 233 VSS84 DQ60 234
DIMM4 0 1 0 2 2 235 DQ61 VSS85 236 DDR_A_D60 UD1
DDR_A_D61 237 VSS86 DQ57 238 1 5 1 2
* DIMM1 1 0 0
2
239 DQ56 VSS87 240 DDR_A_DQS#7 NC VCC @ CD144 0.1U_0402_25V6

241 VSS88 DQS7_c 242 DDR_A_DQS7 2
DIMM3 1 1 0 243 DM7_n/DBI7_n DQS7_t 244
<7> DDR_PG_CTRL A 4 0.6V_DDR_VTT_ON
DDR_A_D62 VSS89 VSS90 DDR_A_D59 Y 0.6V_DDR_VTT_ON <52>
245 246 3
247 DQ62 DQ63 248 GND
DDR_A_D58 249 VSS91 VSS92 250 DDR_A_D63 74AUP1G07GW_TSSOP5
251 DQ58 DQ59 252
253 VSS93 VSS94 254
<7,15,16,17,23,41> DDR_XDP_WAN_SMBCLK +3.3V_RUN_DIMM1 SCL SDA DIMM1_SA0 DDR_XDP_WAN_SMBDAT <7,15,16,17,23,41>
255 256
257 VDDSPD SA0 258
+2.5V_MEM VPP1 VTT +0.6V_DDR_VTT
259 260 DIMM1_SA1
261 VPP2 SA1 262
A A
GND1 GND2
BELLW_80888-6021
CONN@
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DDRIII-SODIMM SLOT1

5 4 3 2 1
5 4 3 2 1
JDIMM2 STD Type H=4

+1.2V_MEM
JDIMM2
+1.2V_MEM Top
1 2
Side
Side
JDIMM1
DDR_A_D1 3 VSS1
DQ5
VSS2
DQ4
4 DDR_A_D4 JDIMM3
5 6
<8,14> DDR_A_DQS#[0..7]
DDR_A_D5 7
9
VSS3
DQ1
VSS4
DQ0
8
10
DDR_A_D0 CPU D C
<8,14> DDR_A_DQS[0..7]
<8,14> DDR_A_D[0..63]
DDR_A_DQS0 13
15
DQS0_c
DQS0_t
VSS8
DM0_n/DBI0_n
VSS7
DQ6
14
16 DDR_A_D7 A B
DDR_A_D6 17 18
<8,14> DDR_A_MA[0..13]
19 DQ7
VSS10
VSS9
DQ2
20 DDR_A_D3 JDIMM2 JDIMM4
DDR_A_D2 21 22
23 DQ3 VSS11 24 DDR_A_D13
D DDR_A_D9 25 VSS12
DQ13
DQ12
VSS13
26
DDR_A_D12
Bottom D
27 28
DDR_A_D8 29 VSS14
DQ9
DQ8
VSS15
30 Side
+2.5V_MEM 31 32 DDR_A_DQS#1
DQ15 DQ14
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
39 40
1 1 1 1 DQ10 DQ11
43 44
DDR_A_D16 VSS21 VSS22 DDR_A_D21 DDR_A_DRAMRST#
CD33
CD35
CD38
CD37
45 46
DQ21 DQ20 DDR_A_DRAMRST# <14>
47 48
2 2 2 2 DDR_A_D17 49 VSS23 VSS24 50 DDR_A_D20
51 DQ17 DQ16 52
DDR_A_D19 59 VSS28 DQ22 60 JDIMM2_EVENT# 1 2 PCH_THERMTRIP#
DQ23 VSS29 DDR_A_D18 PCH_THERMTRIP# <7,14,16,17,19,46>
61 62 @ RD4 1K_0402_5%
+1.2V_MEM DDR_A_D23 63 VSS30 DQ18 64
65 DQ19 VSS31 66 DDR_A_D29
CD14 change to SGA20331E10 DDR_A_D24 67 VSS32 DQ28 68
69 DQ29 VSS33 70 DDR_A_D28
DDR_A_D25 71 VSS34 DQ24 72
10U_0603_6.3V6M DQ25 VSS35 DDR_A_DQS#3
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
73 74
VSS36 DQS3_c DDR_A_DQS3
330U_D2_2V_Y
1 75 76
1 1 1 1 1 1 1 1 VSS37 VSS38
DDR_A_D26 DDR_A_D27
CD91
CD18
CD31
CD32
CD28
CD27
CD34
CD99
CD25
+ 79 80
81 DQ30 DQ31 82
2 2 2 2 2 2 2 2 2 85 DQ26 DQ27 86
DDR_A_CB0 87 VSS41 VSS42 88 DDR_A_CB1
89 90
DDR_A_CB5 91 VSS43 VSS44 92 DDR_A_CB4
93 94
<8,14> DDR_A_DQS#8 DDR_A_DQS8 DQS8_c DM8_n/DBI_n/NC
97 98
<8,14> DDR_A_DQS8 DQS8_t VSS47 DDR_A_CB7
99 100
101 102
<8,14> DDR_A_CB3 CB2/NC VSS49 DDR_A_CB6
C 103 104 C
105 106
<8,14> DDR_A_CB2 CB3/NC VSS51 DDR_A_DRAMRST#
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
107 108 1 2
DDR_A_CKE0 109 VSS52 RESET_n 110 DDR_A_CKE1 @ CD122 0.1U_0402_10V6K
1 1 1 1 1 1 1 1 <8> DDR_A_CKE0 CKE0 CKE1 DDR_A_CKE1 <8>
111 112
DDR_A_BG1 VDD1 VDD2 DDR_A_ACT#
CD20
CD23
CD24
CD100
CD103
CD101
CD102
CD104
113 114
<8,14> DDR_A_BG1 DDR_A_BG0 BG1 ACT_n DDR_A_ALERT# DDR_A_ACT# <8,14>
115 116
2 2 2 2 2 2 2 2 <8,14> DDR_A_BG0 BG0 ALERT_n DDR_A_ALERT# <8,14>
117 118
DDR_A_MA12 119 VDD3 VDD4 120 DDR_A_MA11
DDR_A_MA9 121 A12 A11 122 DDR_A_MA7
123 A9 A7 124
DDR_A_MA6 127 A8 A5 128 DDR_A_MA4
129 A6 A4 130
Layout Note: DDR_A_MA1 133 A3 A2 134 JDIMM2_EVENT#
A1 EVENT_n/NF
Place near JDIMM2.258 DDR_A_CLK0
135
137 VDD9 VDD10
136
138 DDR_A_CLK1
<8> DDR_A_CLK0 DDR_A_CLK#0 CK0_t CK1_t/NF DDR_A_CLK#1 DDR_A_CLK1 <8>
139 140
<8> DDR_A_CLK#0 CK0_c CK1_c/NF DDR_A_CLK#1 <8>
141 142
DDR_A_PARITY 143 VDD11 VDD12 144 DDR_A_MA0
<8,14> DDR_A_PARITY PARITY A0
+V_DDR_REFCA_A DDR_A_BA1 145 146 DDR_A_MA10

<8,14> DDR_A_BA1 BA1 A10/AP
+0.6V_DDR_VTT 147 148
DDR_A_CS#0 149 VDD13 VDD14 150 DDR_A_BA0
<8> DDR_A_CS#0 CS0_n BA0 DDR_A_BA0 <8,14>
DDR_A_MA14 151 152 DDR_A_MA16
<8,14> DDR_A_MA14 WE_n/A14 RAS_n/A16 DDR_A_MA16 <8,14>
0.1U_0402_10V6K
153 154
DDR_A_ODT0 VDD15 VDD16 DDR_A_MA15
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
2.2U_0402_6.3V6M
1 1 155 156
<8> DDR_A_ODT0 DDR_A_CS#1 ODT0 CAS_n/A15 DDR_A_MA13 DDR_A_MA15 <8,14>
@ CD77
1 1 1 157 158
<8> DDR_A_CS#1 CS1_n A13 +V_DDR_REFCA_A
CD105
CD78
159 160
DDR_A_ODT1 VDD17 VDD18
CD36
CD30
161 162 T52 @ PAD~D

2 2 <8> DDR_A_ODT1 ODT1 C0/CS2_n/NC +V_DDR_REFCA_A
163 164
2 2 2 PAD~D @ T53 165 VDD19 VREFCA 166 DIMM2_SA2
167 C1, CS3_n,NC SA2 168
171 DQ37 DQ36 172
175 DQ33 DQ32 176
B DDR_A_DQS4 179 DQS4_c DM4_n/DBI4_n 180 B
DDR_A_D35 183 VSS60 DQ39 184
+3.3V_RUN
DDR_A_D34
185
187
189
DQ38
VSS62
DQ34
VSS61
DQ35
VSS63
186
188
190
DDR_A_D39
DDR_A_D44
VSS64 DQ45
1
DDR_A_D40 191 192

@ RD26 @ RD20 @ RD19 193 DQ44 VSS65 194 DDR_A_D41
VSS66 DQ41
1
0_0402_5% 0_0402_5% 0_0402_5% DDR_A_D45 195 196

@ RD58 197 DQ40 VSS67 198 DDR_A_DQS#5
0_0603_5% 199 VSS68 DQS5_c 200 DDR_A_DQS5
2

DIMM2_SA0 DDR_A_D47 203 VSS69 VSS70 204 DDR_A_D43
2
DIMM2_SA1 +3.3V_RUN_DIMM2 205 DQ46 DQ47 206

DIMM2_SA2 DDR_A_D42 VSS71 VSS72 DDR_A_D46
0.1U_0402_10V6K
SA0 SA1 SA2 207 208

DQ42 DQ43
2.2U_0402_6.3V6M
1 1 209 210
VSS73 VSS74
1
DDR_A_D48 DDR_A_D50
@ CD26
DIMM2 211 212

* 0 0 0 DQ52 DQ53
CD29
@ RD35 @ RD36 @ RD31 213 214

0_0402_5% 0_0402_5% 0_0402_5% DDR_A_D49 215 VSS75 VSS76 216 DDR_A_D52
DIMM4 0 1 0 2 2 217 DQ49 DQ48 218
DIMM1 1 0 0
2

DIMM3 1 1 0 DDR_A_D53 225 VSS80 DQ54 226
227 DQ55 VSS81 228 DDR_A_D51
DDR_A_D55 229 VSS82 DQ50 230
231 DQ51 VSS83 232 DDR_A_D57
DDR_A_D56 233 VSS84 DQ60 234
235 DQ61 VSS85 236 DDR_A_D61
DDR_A_D60 237 VSS86 DQ57 238
247 DQ62 DQ63 248
251 DQ58 DQ59 252
253 VSS93 VSS94 254
255 256
257 VDDSPD SA0 258
A +2.5V_MEM +0.6V_DDR_VTT A
259 VPP1 VTT 260 DIMM2_SA1
261 VPP2 SA1 262
GND1 GND2
LOTES_ADDR0106-P005A
CONN@
Title

5 4 3 2 1
5 4 3 2 1
JDIMM3 STD Type H=5.2

+1.2V_MEM
JDIMM3
+1.2V_MEM Top
1 2
Side
Side
JDIMM1
DDR_B_D4 3 VSS1
DQ5
VSS2
DQ4
4 DDR_B_D5 JDIMM3
5 6
<8,17> DDR_B_DQS#[0..7] DDR_B_D1 7
9
VSS3
DQ1
VSS4
DQ0
8
10
DDR_B_D0 CPU D C
<8,17> DDR_B_DQS[0..7] DDR_B_DQS#0 VSS5 VSS6
11 12
<8,17> DDR_B_D[0..63]
DDR_B_DQS0 13
15
DQS0_c
DQS0_t
VSS8
DM0_n/DBI0_n
VSS7
DQ6
14
16 DDR_B_D2 A B
DDR_B_D6 17 18
<8,17> DDR_B_MA[0..13]
19 DQ7
VSS10
VSS9
DQ2
20 DDR_B_D7 JDIMM2 JDIMM4
DDR_B_D3 21 22
23 DQ3 VSS11 24 DDR_B_D8
D DDR_B_D10 25 VSS12
DQ13
DQ12
VSS13
26
DDR_B_D14
Bottom D
27 28
DDR_B_D9 29 VSS14
DQ9
DQ8
VSS15
30 Side
+2.5V_MEM 31 32 DDR_B_DQS#1
33 VSS16 DQS1_c 34 DDR_B_DQS1
DDR_B_D12 37 VSS17 VSS18 38 DDR_B_D11
DQ15 DQ14
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
39 40
1 1 1 1 DQ10 DQ11
43 44
DDR_B_D18 VSS21 VSS22 DDR_B_D17
CD51
CD53
CD56
CD55
45 46
47 DQ21 DQ20 48
2 2 2 2 DDR_B_D22 49 VSS23 VSS24 50 DDR_B_D16
51 DQ17 DQ16 52
DDR_B_DQS#2 53 VSS25 VSS26 54
DDR_B_DQS2 55 DQS2_c DM2_n/DBI2_n 56
57 DQS2_t VSS27 58 DDR_B_D23
DDR_B_D19 59 VSS28 DQ22 60
61 DQ23 VSS29 62 DDR_B_D21
+1.2V_MEM DDR_B_D20 63 VSS30 DQ18 64 DDR_B_DRAMRST#
DQ19 VSS31 DDR_B_D28 DDR_B_DRAMRST# <14,17>
65 66
CD14 change to SGA20331E10 DDR_B_D25 67 VSS32 DQ28 68
69 DQ29 VSS33 70 DDR_B_D27
DDR_B_D30 71 VSS34 DQ24 72
DQ25 VSS35 DDR_B_DQS#3
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
73 74
VSS36 DQS3_c DDR_B_DQS3 JDIMM3_EVENT# PCH_THERMTRIP#
330U_D2_2V_Y
1 75 76 1 2
DM3_n/DBI3_n DQS3_t PCH_THERMTRIP# <7,14,15,17,19,46>
1 1 1 1 1 1 1 1 77 78 @ RD5 1K_0402_5%
CD106
CD39
CD49
CD50
CD46
CD45
CD52
CD107
CD43
+ 79 80
81 DQ30 DQ31 82
2 2 2 2 2 2 2 2 2 85 DQ26 DQ27 86
DDR_B_CB4 87 VSS41 VSS42 88 DDR_B_CB1
<8,17> DDR_B_CB4 CB5/NC CB4/NC DDR_B_CB1 <8,17>
89 90
DDR_B_CB2 91 VSS43 VSS44 92 DDR_B_CB3 +1.2V_MEM
93 94
<8,17> DDR_B_DQS#8 DDR_B_DQS8 DQS8_c DM8_n/DBI_n/NC
0.1U_0402_10V6K
97 98
<8,17> DDR_B_DQS8 DQS8_t VSS47
1
DDR_B_CB6
1K_0402_5%
@ CD139
99 100 1
DDR_B_CB7 VSS48 CB6/NC DDR_B_CB6 <8,17>
RD43
101 102
<8,17> DDR_B_CB7 CB2/NC VSS49 DDR_B_CB0 +DDR_VREF_B_DQ
C 103 104 C
105 106
<8,17> DDR_B_CB5 CB3/NC VSS51 DDR_B_DRAMRST# 2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
107 108 1 2
2
DDR_B_CKE2 109 VSS52 RESET_n 110 DDR_B_CKE3 @ CD123 0.1U_0402_10V6K
1 1 1 1 1 1 1 1 <8> DDR_B_CKE2 CKE0 CKE1 DDR_B_CKE3 <8>
111 112
DDR_B_BG1 VDD1 VDD2 DDR_B_ACT# +DIMM_DQ_R_VREF_B
CD40
CD41
CD42
CD108
CD111
CD109
CD110
CD112
113 114 1 2
<8,17> DDR_B_BG1 DDR_B_BG0 BG1 ACT_n DDR_B_ALERT# DDR_B_ACT# <8,17>
115 116 RD41 2_0402_1%
2 2 2 2 2 2 2 2 <8,17> DDR_B_BG0 BG0 ALERT_n DDR_B_ALERT# <8,17>
0.022U_0402_16V7K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
117 118
VDD3 VDD4
1
DDR_B_MA12 DDR_B_MA11
@ CD137
@ CD138
1K_0402_5%
@ CD140
119 120 1 1 1 1
DDR_B_MA9 A12 A11 DDR_B_MA7
RD44
121 122
A9 A7
CD136
123 124
DDR_B_MA8 125 VDD5 VDD6 126 DDR_B_MA5
DDR_B_MA6 127 A8 A5 128 DDR_B_MA4 2 2 2 2
2
129 A6 A4 130
Layout Note: DDR_B_MA1 133 A3 A2 134 JDIMM3_EVENT#
A1 EVENT_n/NF
Place near JDIMM3.258 135
VDD9 VDD10
136
1
DDR_B_CLK2 DDR_B_CLK3
24.9_0402_1%
137 138
<8> DDR_B_CLK2 DDR_B_CLK#2 CK0_t CK1_t/NF DDR_B_CLK#3 DDR_B_CLK3 <8>
RD34
139 140
<8> DDR_B_CLK#2 CK0_c CK1_c/NF DDR_B_CLK#3 <8>
141 142
DDR_B_PARITY 143 VDD11 VDD12 144 DDR_B_MA0
<8,17> DDR_B_PARITY PARITY A0
2
+V_DDR_REFCA_B DDR_B_BA1 145 146 DDR_B_MA10
<8,17> DDR_B_BA1 BA1 A10/AP
+0.6V_DDR_VTT 147 148
DDR_B_CS#2 149 VDD13 VDD14 150 DDR_B_BA0
<8> DDR_B_CS#2 CS0_n BA0 DDR_B_BA0 <8,17>
DDR_B_MA14 151 152 DDR_B_MA16
<8,17> DDR_B_MA14 WE_n/A14 RAS_n/A16 DDR_B_MA16 <8,17>
0.1U_0402_10V6K
153 154
DDR_B_ODT2 VDD15 VDD16 DDR_B_MA15 +1.2V_MEM
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
2.2U_0402_6.3V6M
1 1 155 156
<8> DDR_B_ODT2 DDR_B_CS#3 ODT0 CAS_n/A15 DDR_B_MA13 DDR_B_MA15 <8,17>
@ CD79
1 1 1 157 158
<8> DDR_B_CS#3 CS1_n A13 +V_DDR_REFCA_B
CD113
CD80
159 160
DDR_B_ODT3 VDD17 VDD18
CD54
CD48
0.1U_0402_10V6K
161 162 T54 @ PAD~D
<8> DDR_B_ODT3 ODT1 C0/CS2_n/NC
1
2 2 +V_DDR_REFCA_B
1K_0402_5%
163 164 @ 1 @
2 2 2 VDD19 VREFCA DIMM3_SA2
RD46
CD142
PAD~D @ T55 165 166
167 C1, CS3_n,NC SA2 168
171 DQ37 DQ36 172 2
2
175 DQ33 DQ32 176
DDR_B_DQS#4 177 VSS57 VSS58 178 +DIMM_DQ_R_VREF_B 1 2 +V_DDR_REFCA_B 1 2
B DDR_B_DQS4 179 DQS4_c DM4_n/DBI4_n 180 @ RD11 0_0402_5% @ RD14 0_0402_5% B
VSS60 DQ39
1
DDR_B_D33
0.1U_0402_10V6K
1K_0402_5%
183 184 @
DIMM Select +3.3V_RUN +3.3V_RUN +3.3V_RUN DQ38 VSS61 DDR_B_D37
@ CD143
RD47
185 186 1
DDR_B_D32 187 VSS62 DQ35 188
+3.3V_RUN 189 DQ34 VSS63 190 DDR_B_D44
VSS64 DQ45
1
DDR_B_D40 191 192
2
@ RD38 @ RD37 @ RD27 193 DQ44 VSS65 194 DDR_B_D45 2
VSS66 DQ41
1
0_0402_5% 0_0402_5% 0_0402_5% DDR_B_D41 195 196

@ RD59 197 DQ40 VSS67 198 DDR_B_DQS#5
0_0603_5% 199 VSS68 DQS5_c 200 DDR_B_DQS5
2

DIMM3_SA0 DDR_B_D42 203 VSS69 VSS70 204 DDR_B_D47
2
DIMM3_SA1 +3.3V_RUN_DIMM3 205 DQ46 DQ47 206

DIMM3_SA2 DDR_B_D46 VSS71 VSS72 DDR_B_D43
0.1U_0402_10V6K
SA0 SA1 SA2 207 208

DQ42 DQ43
2.2U_0402_6.3V6M
1 1 209 210
VSS73 VSS74
1
DDR_B_D48 DDR_B_D51
@ CD44
DIMM2 211 212

0 0 0 DQ52 DQ53
CD47
@ RD40 @ RD42 @ RD39 213 214

0_0402_5% 0_0402_5% 0_0402_5% DDR_B_D52 215 VSS75 VSS76 216 DDR_B_D54
DIMM4 0 1 0 2 2 217 DQ49 DQ48 218
DIMM1 1 0 0
2

* DIMM3 1 1 0 DDR_B_D50 225 VSS80 DQ54 226
227 DQ55 VSS81 228 DDR_B_D49
DDR_B_D55 229 VSS82 DQ50 230
231 DQ51 VSS83 232 DDR_B_D59
DDR_B_D57 233 VSS84 DQ60 234
235 DQ61 VSS85 236 DDR_B_D62
DDR_B_D61 237 VSS86 DQ57 238
239 DQ56 VSS87 240 DDR_B_DQS#7
247 DQ62 DQ63 248
251 DQ58 DQ59 252
253 VSS93 VSS94 254
255 256
257 VDDSPD SA0 258
A +2.5V_MEM +0.6V_DDR_VTT A
259 VPP1 VTT 260 DIMM3_SA1
261 VPP2 SA1 262
GND1 GND2
BELLW_80888-2021
CONN@
Title

5 4 3 2 1
5 4 3 2 1
JDIMM4 REV Type H=4

+1.2V_MEM +1.2V_MEM
JDIMM4
DDR_B_D5
1
VSS1 VSS2
2
DDR_B_D4
Top
3 4
<8,16> DDR_B_DQS#[0..7]
5 DQ5
VSS3
DQ4
VSS4
6 Side
Side
JDIMM1
DDR_B_D0 7 8 DDR_B_D1
9 DQ1 DQ0 10 JDIMM3
<8,16> DDR_B_DQS[0..7] VSS5 VSS6
<8,16> DDR_B_D[0..63]
DDR_B_DQS#0
DDR_B_DQS0
11
13
15
DQS0_c
DQS0_t
DM0_n/DBI0_n
VSS7
12
14
16 DDR_B_D6
CPU D C
DDR_B_D2 17 VSS8 DQ6 18
<8,16> DDR_B_MA[0..13]
DDR_B_D7
19
21
DQ7
VSS10
VSS9
DQ2
20
22
DDR_B_D3
A B
DDR_B_D8 25 VSS12 DQ12 26 JDIMM2 JDIMM4
D DDR_B_D14 VSS14 DQ8 D
29
31 DQ9 VSS15
30
32 DDR_B_DQS#1 Bottom
VSS16 DQS1_c
33
35 DM1_n/DBI_n DQS1_t
34
36
DDR_B_DQS1
Side
+2.5V_MEM DDR_B_D11 37 VSS17 VSS18 38 DDR_B_D12
39 DQ15 DQ14 40
43 DQ10 DQ11 44
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
45 46
47 DQ21 DQ20 48
1 1 1 1 VSS23 VSS24
DDR_B_D16 49 50 DDR_B_D22
DQ17 DQ16
CD69
CD71
CD74
CD73
51 52
2 2 2 2 DDR_B_DQS2 55 DQS2_c DM2_n/DBI2_n 56
DDR_B_D23 59 VSS28 DQ22 60
61 DQ23 VSS29 62 DDR_B_D20
DDR_B_D21 63 VSS30 DQ18 64 DDR_B_DRAMRST#
DQ19 VSS31 DDR_B_D25 DDR_B_DRAMRST# <14,16>
65 66
DDR_B_D28 67 VSS32 DQ28 68
+1.2V_MEM 69 DQ29 VSS33 70 DDR_B_D30
DDR_B_D27 71 VSS34 DQ24 72
CD14 change to SGA20331E10 73 DQ25 VSS35 74 DDR_B_DQS#3
75 VSS36 DQS3_c 76 DDR_B_DQS3 JDIMM4_EVENT# 1 2 PCH_THERMTRIP#
DM3_n/DBI3_n DQS3_t PCH_THERMTRIP# <7,14,15,16,19,46>
77 78 @ RD12 1K_0402_5%
10U_0603_6.3V6M DDR_B_D26 VSS37 VSS38 DDR_B_D29
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
79 80
DQ30 DQ31
330U_D2_2V_Y
1 81 82
1 1 1 1 1 1 1 1 DQ26 DQ27
CD114
CD57
CD67
CD68
CD64
CD63
CD70
CD115
CD61
+ 85 86
DDR_B_CB4 87 VSS41 VSS42 88 DDR_B_CB1
89 90
2 2 2 2 2 2 2 2 2 DDR_B_CB2 91 VSS43 VSS44 92 DDR_B_CB3
93 94
<8,16> DDR_B_DQS#8 DDR_B_DQS8 DQS8_c DM8_n/DBI_n/NC
97 98
<8,16> DDR_B_DQS8 DQS8_t VSS47 DDR_B_CB6
99 100
101 102
<8,16> DDR_B_CB7 CB2/NC VSS49 DDR_B_CB0
103 104
105 106
<8,16> DDR_B_CB5 CB3/NC VSS51 DDR_B_DRAMRST#
C 107 108 1 2 C
DDR_B_CKE0 109 VSS52 RESET_n 110 DDR_B_CKE1 @ CD124 0.1U_0402_10V6K
<8> DDR_B_CKE0 CKE0 CKE1 DDR_B_CKE1 <8>
111 112
DDR_B_BG1 VDD1 VDD2 DDR_B_ACT#
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
113 114
<8,16> DDR_B_BG1 DDR_B_BG0 BG1 ACT_n DDR_B_ALERT# DDR_B_ACT# <8,16>
1 1 1 1 1 1 1 1 115 116
<8,16> DDR_B_BG0 BG0 ALERT_n DDR_B_ALERT# <8,16>
117 118
DDR_B_MA12 VDD3 VDD4 DDR_B_MA11
CD58
CD59
CD60
CD116
CD119
CD117
CD118
CD120
119 120
DDR_B_MA9 121 A12 A11 122 DDR_B_MA7
2 2 2 2 2 2 2 2 123 A9 A7 124
DDR_B_MA6 127 A8 A5 128 DDR_B_MA4
129 A6 A4 130
DDR_B_MA1 133 A3 A2 134 JDIMM4_EVENT#
135 A1 EVENT_n/NF 136
DDR_B_CLK0 137 VDD9 VDD10 138 DDR_B_CLK1
Layout Note: <8>
<8>
DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK#0 139 CK0_t CK1_t/NF 140 DDR_B_CLK#1 DDR_B_CLK1
DDR_B_CLK#1
<8>
<8>
CK0_c CK1_c/NF
Place near JDIMM4.258 DDR_B_PARITY
141
143 VDD11 VDD12
142
144 DDR_B_MA0
<8,16> DDR_B_PARITY PARITY A0
DDR_B_BA1 145 146 DDR_B_MA10

<8,16> DDR_B_BA1 BA1 A10/AP
147 148
DDR_B_CS#0 149 VDD13 VDD14 150 DDR_B_BA0
+V_DDR_REFCA_B <8> DDR_B_CS#0 DDR_B_MA14 CS0_n BA0 DDR_B_MA16 DDR_B_BA0 <8,16>
151 152
<8,16> DDR_B_MA14 WE_n/A14 RAS_n/A16 DDR_B_MA16 <8,16>
+0.6V_DDR_VTT 153 154
DDR_B_ODT0 155 VDD15 VDD16 156 DDR_B_MA15
<8> DDR_B_ODT0 DDR_B_CS#1 ODT0 CAS_n/A15 DDR_B_MA13 DDR_B_MA15 <8,16>
157 158
<8> DDR_B_CS#1 CS1_n A13 +V_DDR_REFCA_B
0.1U_0402_10V6K
159 160
DDR_B_ODT1 VDD17 VDD18
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
2.2U_0402_6.3V6M
1 1 161 162 T56 @ PAD~D

<8> DDR_B_ODT1 ODT1 C0/CS2_n/NC +V_DDR_REFCA_B
@ CD81
1 1 1 163 164
VDD19 VREFCA DIMM4_SA2
CD121
CD82
PAD~D @ T57 165 166

C1, CS3_n,NC SA2
CD72
CD66
167 168
2 2 DDR_B_D38 169 VSS53 VSS54 170 DDR_B_D35
2 2 2 171 DQ37 DQ36 172
175 DQ33 DQ32 176
B DDR_B_D36 183 VSS60 DQ39 184 B
185 DQ38 VSS61 186 DDR_B_D32
DDR_B_D37 187 VSS62 DQ35 188
189 DQ34 VSS63 190 DDR_B_D40
+3.3V_RUN
DDR_B_D44
DDR_B_D45
191
193
195
VSS64
DQ44
VSS66
DQ45
VSS65
DQ41
192
194
196
DDR_B_D41
DQ40 VSS67
1
197 198 DDR_B_DQS#5

@ RD53 @ RD52 @ RD51 199 VSS68 DQS5_c 200 DDR_B_DQS5
DM5_n/DBI5_n DQS5_t
1
0_0402_5% 0_0402_5% 0_0402_5% 201 202

@ RD60 DDR_B_D47 203 VSS69 VSS70 204 DDR_B_D42
0_0603_5% 205 DQ46 DQ47 206
2

DIMM4_SA0 209 DQ42 DQ43 210
2
DIMM4_SA1 +3.3V_RUN_DIMM4 DDR_B_D51 211 VSS73 VSS74 212 DDR_B_D48

DIMM4_SA2 DQ52 DQ53
0.1U_0402_10V6K
213 214
SA0 SA1 SA2 DDR_B_D54 VSS75 VSS76 DDR_B_D52
2.2U_0402_6.3V6M
1 1 215 216
DQ49 DQ48
1
@ CD62
217 218
DIMM2 0 0 0 DDR_B_DQS#6 VSS77 VSS78
CD65
@ RD55 @ RD56 @ RD54 219 220

0_0402_5% 0_0402_5% 0_0402_5% DDR_B_DQS6 221 DQS6_c DM6_n/DBI6_n 222
* DIMM4 0 1 0 2 2 223 DQS6_t VSS79 224 DDR_B_D50
DDR_B_D53 225 VSS80 DQ54 226
DIMM1 1 0 0
2
227 DQ55 VSS81 228 DDR_B_D55

DDR_B_D49 229 VSS82 DQ50 230
DIMM3 1 1 0 231 DQ51 VSS83 232 DDR_B_D57
DDR_B_D59 233 VSS84 DQ60 234
235 DQ61 VSS85 236 DDR_B_D61
DDR_B_D62 237 VSS86 DQ57 238
239 DQ56 VSS87 240 DDR_B_DQS#7
247 DQ62 DQ63 248
251 DQ58 DQ59 252
253 VSS93 VSS94 254
255 256
257 VDDSPD SA0 258
+2.5V_MEM VPP1 VTT +0.6V_DDR_VTT
259 260 DIMM4_SA1
261 VPP2 SA1 262
A A
GND1 GND2
LOTES_ADDR0107-P005A
CONN@
Title
5 4 3 2 1
5 4 3 2 1
+3.3V_MXM
+3.3V_MXM
DGPU_PEX_RST#
+3.3V_MXM
4.7K_0402_5%
4.7K_0402_5%
1
1
+3.3V_MXM
PEG_CRX_C_GTX_P[0..15]
10K_0402_5%
@
<6> PEG_CRX_C_GTX_P[0..15] DAT_DDC2_DOCK
R1
R2
1 2
1
PEG_CRX_C_GTX_N[0..15] @ R3 4.3K_0402_5%
<6> PEG_CRX_C_GTX_N[0..15]
2
2 CLK_DDC2_DOCK
R4
1
2
PEG_CTX_C_GRX_P[0..15] @ R5 4.3K_0402_5%
<6> PEG_CTX_C_GRX_P[0..15] 1 2 DGPU_PWROK GPU_SMBDAT_R 1 6 UPD_GPU_SMBDAT <44,46>
2
PEG_CTX_C_GRX_N[0..15]
G
R1977 10K_0402_5%
<6> PEG_CTX_C_GRX_N[0..15]
2
1 2 MXM_CLK_REQ# Q295A
5
R1978 10K_0402_5% MXM_ALERT# 3 1 DMN66D0LDW-7_SOT363-6
DGPU_ALERT# <45>
D
GPU_SMBCLK_R 4 3
UPD_GPU_SMBCLK <44,46>
Q5 Q295B
D DMN65D8LW-7_SOT323-3 DMN66D0LDW-7_SOT363-6 D
+MXM_PWR_SRC +MXM_PWR_SRC
JMXM1A 400mil(10A)
1 2 JMXM1B
3 PWR_SRC PWR_SRC 4 167 166
PWR_SRC PWR_SRC PEG_CRX_C_GTX_N2 GND GND PEG_CTX_C_GRX_N2
10U_0805_25VAK
680P_0603_50V7K
68P_0402_50V8J
0.1U_0603_25V7K
5 6 169 168
7 PWR_SRC PWR_SRC 8 PEG_CRX_C_GTX_P2 171 PEX_RX2# PEX_TX2# 170 PEG_CTX_C_GRX_P2
PWR_SRC 1 1 1 1
9
PWR_SRCE1 E2 PWR_SRC
PWR_SRC
10
PEG_CRX_C_GTX_N1
173 PEX_RX2
GND
PEX_TX2
GND
172
PEG_CTX_C_GRX_N1
C2
C3
C4
C1
11 12 175 174
15 PWR_SRC PWR_SRC 16 2 2 2 2 179 PEX_RX1 PEX_TX1 178
17 PWR_SRC PWR_SRC 18 PEG_CRX_C_GTX_N0 181 GND GND 180 PEG_CTX_C_GRX_N0
+5V_MXM 21 PWR_SRC PWR_SRC 22 185 PEX_RX0 PEX_TX0 184
23 GND GND 24 CLK_PEG_N0 187 GND GND 186 MXM_CLK_REQ#
GND GND <21> CLK_PEG_N0 CLK_PEG_P0 PEX_REFCLK# PEX_CLK_REQ# DGPU_PEX_RST#
25 26 189 188
GND GND <21> CLK_PEG_P0 PEX_REFCLK PEX_RST# DAT_DDC2_DOCK
27 28 191 190 DAT_DDC2_DOCK <43>
GND GND GND VGA_DDC_DAT CLK_DDC2_DOCK
0.1U_0402_16V7K
10U_0805_6.3V6M
29 30 193 192 CLK_DDC2_DOCK <43>
1 1 31
33
GND
GND
GND E3 E4
GND
GND
GND
32
34
195
197
RSVD
RSVD
RSVD
VGA_DDC_CLK
VGA_VSYNC
VGA_HSYNC
194
196
VSYNC_DOCK
HSYNC_DOCK VSYNC_DOCK
HSYNC_DOCK
<43>
<43> Docking
C7
C328
35 36 199 198
GND GND RSVD GND
CRT
+5V_MXM 37 38 201 200 RED_DOCK
2 2 GND GND RSVD VGA_RED GREEN_DOCK RED_DOCK <43>
39 40 203 202
GND GND LVDS_UCLK# VGA_GREEN BLUE_DOCK GREEN_DOCK <43>
41 42 MXM_PRESENTR# <19> 205 204 BLUE_DOCK <43>
43 5V PRSNT_R# 44 @ R1972 1 2 0_0402_5% 207 LVDS_UCLK VGA_BLUE 206
5V WAKE# DGPU_PWROK PCIE_WAKE# <38,39,44,45> GND GND
45 46 DGPU_PWROK <23,45> 209 208
47 5V PWR_GOOD 48 211 LVDS_UTX3# LVDS_LCLK# 210
5V PWR_EN DGPU_PWR_EN <45> LVDS_UTX3 LVDS_LCLK
49 50 213 212
51 5V RSVD 52 215 GND GND 214
100mil(2.5A, 5VIA) 53 GND RSVD 54 217 LVDS_UTX2# LVDS_LTX3# 216
55 GND RSVD 56 219 LVDS_UTX2 LVDS_LTX3 218
57 GND RSVD 58 MXM_PWR_LEVEL 221 GND GND 220
GND PWR_LEVEL MXM_OVERT# MXM_PWR_LEVEL <57> LVDS_UTX1# LVDS_LTX2#
@ R1970 1 2 0_0402_5% 59 60 223 222
@ R1971 1 2 0_0402_5% 61 PEX_STD_SW# TH_OVERT# 62 MXM_ALERT# 225 LVDS_UTX1 LVDS_LTX2 224
<45> MXM_VGA_DIS#
63 VGA_DISABLE# TH_ALERT# 64
MXM_PIN80_R for 3D function usage 227 GND GND 226
<30> MXM_ENVDD
<30> MXM_PANEL_BKEN 65 PNL_PWR_EN TH_PWM 66 (JMXM1_pin 80). 229 LVDS_UTX0# LVDS_LTX1# 228
67 PNL_BL_EN GPIO0 68 310 pin connector=Pin80 231 LVDS_UTX0 LVDS_LTX1 230
<30> MXM_BIA_PWM PNL_BL_PWM GPIO1 GND GND
69 70 MXM_DPC_N0 233 232
C
71 HDMI_CEC GPIO2 72 GPU_SMBDAT_R
314 pin connector=pin84 <31> MXM_DPC_N0
MXM_DPC_P0 235 DP_C_L0# LVDS_LTX0# 234 C
PAD~D @ T215 <31> MXM_DPC_P0
73 DVI_HPD SMB_DAT 74 GPU_SMBCLK_R 237 DP_C_L0 LVDS_LTX0 236
75 LVDS_DDC_DAT SMB_CLK 76 MXM_DPC_N1 239 GND GND 238 MXM_EDP_N0
SYSTEM <31> MXM_DPC_N1
PAD~D @ T208 OEM1
77
79
LVDS_DDC_CLK
GND
OEM
GND
OEM
OEM
78
80
OEM0
OEM2
T210 @ PAD~D
T211 @ PAD~D
Docking port1 <31> MXM_DPC_P1
MXM_DPC_P1 241
243
DP_C_L1#
DP_C_L1
GND
DP_D_L0#
DP_D_L0
GND
240
242
MXM_EDP_P0 MXM_EDP_N0
MXM_EDP_P0
<29>
<29>
PAD~D @ T207 81 82 GPU_EVENT#_D 2 1 GPU_EVENT# MXM_DPC_N2 245 244 MXM_EDP_N1
GC6_FB_EN
OEM3 OEM OEM OEM4 GPU_EVENT# <24> <31> MXM_DPC_N2
MXM_DPC_P2 DP_C_L2# DP_D_L1# MXM_EDP_P1 MXM_EDP_N1 <29>
<24> GC6_FB_EN OEM5 83 84 OEM6 D94 RB751VM-40TE-17_SOD323-2 <31> MXM_DPC_P2 247 246
OEM OEM DP_C_L2 DP_D_L1 MXM_EDP_P1 <29>
PAD~D @ T209 OEM7 85 86 T212 @ PAD~D 249 248
87 OEM GND 88 PEG_CTX_C_GRX_N15 MXM_DPC_N3 251 GND GND 250 MXM_EDP_N2
GND PEX_TX15# <31> MXM_DPC_N3 DP_C_L3# DP_D_L2# MXM_EDP_N2 <29>
PEG_CRX_C_GTX_N15
PEG_CRX_C_GTX_P15
89
91 PEX_RX15#
PEX_RX15
PEX_TX15
GND
90
92
PEG_CTX_C_GRX_P15
PEG_CTX_C_GRX_N14
<31> MXM_DPC_P3
MXM_DPC_P3
MXM_DPC_AUXN
253
255 DP_C_L3
GND
DP_D_L2
GND
252
254
MXM_EDP_P2
MXM_EDP_N3
MXM_EDP_P2 <29> eDP MUX
93 94 <31> MXM_DPC_AUXN 257 256
PEG_CRX_C_GTX_N14 GND PEX_TX14# PEG_CTX_C_GRX_P14 MXM_DPC_AUXP DP_C_AUX# DP_D_L3# MXM_EDP_P3 MXM_EDP_N3 <29>
95 96 <31> MXM_DPC_AUXP 259 258
PEG_CRX_C_GTX_P14 PEX_RX14# PEX_TX14 DP_C_AUX DP_D_L3 MXM_EDP_P3 <29>
97 98 261 260
99 PEX_RX14 GND 100 PEG_CTX_C_GRX_N13 263 RSVD GND 262 MXM_EDP_AUXN
GND PEX_TX13# RSVD DP_D_AUX# MXM_EDP_AUXN <29>
PEG_CRX_C_GTX_N13 101 102 PEG_CTX_C_GRX_P13 265 264 MXM_EDP_AUXP
PEX_RX13# PEX_TX13 RSVD DP_D_AUX MXM_EDP_AUXP <29>
PEG_CRX_C_GTX_P13 103 104 267 266 MXM_DPC_HPD_GATE
105 PEX_RX13 GND 106 PEG_CTX_C_GRX_N12 269 RSVD DP_C_HPD 268 MXM_EDP_HPD
PEG_CRX_C_GTX_N12 GND PEX_TX12# PEG_CTX_C_GRX_P12 RSVD DP_D_HPD MXM_EDP_HPD <29>
107 108 271 270
PEG_CRX_C_GTX_P12 109 PEX_RX12# PEX_TX12 110 273 RSVD RSVD 272
111 PEX_RX12 GND 112 PEG_CTX_C_GRX_N11 275 RSVD RSVD 274
PEG_CRX_C_GTX_N11 GND PEX_TX11# PEG_CTX_C_GRX_P11 RSVD RSVD +3.3V_MXM
113 114 277 276
PEG_CRX_C_GTX_P11 115 PEX_RX11# PEX_TX11 116 279 RSVD GND 278 MXM_DPB_N0
PEX_RX11 GND PEG_CTX_C_GRX_N10 RSVD DP_B_L0# MXM_DPB_P0 MXM_DPB_N0 <33>
117 118 281 280
PEG_CRX_C_GTX_N10 GND PEX_TX10# PEG_CTX_C_GRX_P10 RSVD DP_B_L0 MXM_DPB_P0 <33>
119 120 283 282
PEG_CRX_C_GTX_P10 121 PEX_RX10# PEX_TX10 122 285 RSVD GND 284 MXM_DPB_N1
PEX_RX10 GND PEG_CTX_C_GRX_N9 MXM_DPA_N0 GND DP_B_L1# MXM_DPB_P1 MXM_DPB_N1 <33>
123 124 <32> MXM_DPA_N0 287 286 MXM_DPB_P1 <33>
PEG_CRX_C_GTX_N9 125 GND PEX_TX9# 126 PEG_CTX_C_GRX_P9 MXM_DPA_P0 289 DP_A_L0# DP_B_L1 288
PEX_RX9# PEX_TX9 <32> MXM_DPA_P0 DP_A_L0 GND
PEG_CRX_C_GTX_P9 127 128 291 290 MXM_DPB_N2
PEX_RX9 GND PEG_CTX_C_GRX_N8 MXM_DPA_N1 GND DP_B_L2# MXM_DPB_P2 MXM_DPB_N2 <33>
129 130 <32> MXM_DPA_N1 293 292
PEG_CRX_C_GTX_N8
PEG_CRX_C_GTX_P8
131
133
GND
PEX_RX8#
PEX_TX8#
PEX_TX8
132
134
PEG_CTX_C_GRX_P8
<32> MXM_DPA_P1
MXM_DPA_P1 295
297
DP_A_L1#
DP_A_L1
DP_B_L2
GND
294
296 MXM_DPB_N3
MXM_DPB_P2 <33>
TBT/mDP
PEG_CRX_C_GTX_N7
135
137
PEX_RX8
GND
GND
PEX_TX7#
136
138
PEG_CTX_C_GRX_N7
PEG_CTX_C_GRX_P7
TBT/ <32> MXM_DPA_N2
MXM_DPA_N2
MXM_DPA_P2
299
301
GND
DP_A_L2#
DP_B_L3#
DP_B_L3
298
300
MXM_DPB_P3 MXM_DPB_N3
MXM_DPB_P3
<33>
<33>
<32> MXM_DPA_P2
PEG_CRX_C_GTX_P7 139
141
PEX_RX7#
PEX_RX7
PEX_TX7
GND
140
142 PEG_CTX_C_GRX_N6
Docking DP port 2 <32> MXM_DPA_N3
MXM_DPA_N3
303
305
DP_A_L2
GND
GND
DP_B_AUX#
302
304
MXM_DPB_AUXN
MXM_DPB_AUXP
MXM_DPB_AUXN
MXM_DPB_AUXP
<33>
<33>
PEG_CRX_C_GTX_N6 143 GND PEX_TX6# 144 PEG_CTX_C_GRX_P6 MXM_DPA_P3 307 DP_A_L3# DP_B_AUX 306 MXM_DPB_HPD_GATE
PEX_RX6# PEX_TX6 <32> MXM_DPA_P3 DP_A_L3 DP_B_HPD
PEG_CRX_C_GTX_P6 145 146 309 308 MXM_DPA_HPD_GATE
147 PEX_RX6 GND 148 PEG_CTX_C_GRX_N5 MXM_DPA_AUXN 311 GND DP_A_HPD 310
GND PEX_TX5# <32> MXM_DPA_AUXN DP_A_AUX# 3V3 +3.3V_MXM
PEG_CRX_C_GTX_N5 149 150 PEG_CTX_C_GRX_P5 MXM_DPA_AUXP 313 312
PEX_RX5# PEX_TX5 <32> MXM_DPA_AUXP DP_A_AUX 3V3
PEG_CRX_C_GTX_P5 151 152 MXM_PRESENTL# 314
PEX_RX5 GND <19> MXM_PRESENTL# PRSNT_L#
153 154 PEG_CTX_C_GRX_N4
PEG_CRX_C_GTX_N4 155 GND PEX_TX4# 156 PEG_CTX_C_GRX_P4 315 316
PEG_CRX_C_GTX_P4 157 PEX_RX4# PEX_TX4 158 GND GND
159 PEX_RX4 GND 160 PEG_CTX_C_GRX_N3 FOX_AS0B826-S43B1-7H
B B
PEG_CRX_C_GTX_N3 161 GND PEX_TX3# 162 PEG_CTX_C_GRX_P3
PEX_RX3# PEX_TX3 CONN@
PEG_CRX_C_GTX_P3 163 164
165 PEX_RX3 GND 40mil(1A)
GND LInk CIS +3.3V_MXM
FOX_AS0B826-S43B1-7H
CONN@
10U_0603_6.3V6M
0.1U_0402_10V6K
LInk CIS 1 1
C332
C8
+3.3V_MXM
+3.3V_MXM +3.3V_MXM 2 2
+3.3V_ALW @ C96 @ C95 @ C94
1 2 1 2 1 2
@ C90 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K

5
5
1 2
1 DGPU_PEX_RST#_D 1 DGPU_PEX_RST#_D 1 DGPU_PEX_RST#_D
P
P
0.1U_0402_10V7K MXM_DPB_HPD_GATE 4 IN1 MXM_DPC_HPD_GATE 4 IN1 MXM_DPA_HPD_GATE 4 IN1
O 2 O 2 O 2
IN2 MXM_DPB_HPD <33> IN2 MXM_DPC_HPD <31> IN2 MXM_DPA_HPD <32>
G
G
100K_0402_5%
100K_0402_5%
100K_0402_5%
5
1
@ R758
@ R519
U14 U25 U27

3
3
@ R60
1 SN74AHC1G08DCKR_SC70-5 SN74AHC1G08DCKR_SC70-5 SN74AHC1G08DCKR_SC70-5
P
DGPU_PEX_RST# IN1 DGPU_HOLD_RST# <24>

4
O 2
IN2 PLTRST_GPU# <22>
G
100K_0402_5%
2
1
1
@ R3750
100K_0402_5%
U16
3
R51
2
+3.3V_MXM
1 2 +3.3V_MXM +3.3V_ALW
@ R19 0_0402_5% +3.3V_ALW
DGPU_PEX_RST#
+3.3V_MXM
1
10K_0402_5%
@ R71
@ C92
1
100K_0402_5%
10K_0402_5%
1 2
1
10K_0402_5%
1
0.1U_0402_10V7K
2
R37
R10
R11
D7 @ D95
MXM_DPC_HPD 2 1 DGPU_PEX_RST# 1 2 DGPU_PEX_RST#_D 1 2 DGPU_PWROK
MXM_DP_HDMI_HPD <45>
2
1000P_0402_50V7K
U17 @ R72 0_0402_5%
2
2
A A
100K_0402_5%
G
RB751VM-40TE-17_SOD323-2 1 RB751VM-40TE-17_SOD323-2
G VCC
ACAV_IN <46,57,60>
2
B
1
MXM_PWR_LEVEL 4
Y 1
MXM_OVERT#
@ C1470
D8 2 3 1 THERMATRIP3# <46>
MXM_DPA_HPD A GPU_PWR_LEVEL <45>
R135
2 1
D
MC74VHC1G09DFT2G_SC70-5
3
RB751VM-40TE-17_SOD323-2 2
2
Q4
D18 DMN65D8LW-7_SOT323-3
MXM_DPB_HPD 2 1
RB751VM-40TE-17_SOD323-2
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, MXM
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-C551P
5 4 3 2 1
5 4 3 2 1
SPT-H_PCH
UH1C
PCH_CL_CLK1 AV2 PCIE_PRX_DTX_N9

<38> PCH_CL_CLK1 PCH_CL_DATA1 CL_CLK G31 PCIE_PRX_DTX_P9 PCIE_PRX_DTX_N9 <39>
AV3 PCIE9_RXN/SATA0A_RXN
<38> PCH_CL_DATA1 PCH_CL_RST1# CL_DATA CLINK H31 PCIE_PTX_DRX_N9 PCIE_PRX_DTX_P9 <39>
AW2 PCIE9_RXP/SATA0A_RXP
<38> PCH_CL_RST1# CL_RST# C31 PCIE_PTX_DRX_P9 PCIE_PTX_DRX_N9 <39>
+3.3V_ALW_PCH PCIE9_TXN/SATA0A_TXN
D B31 PCIE_PTX_DRX_P9 <39> D
R44 PCIE9_TXP/SATA0A_TXP M.2 SSD
R43 GPP_G8/FAN_PWM_0
U39 GPP_G9/FAN_PWM_1 G29 PCIE_PRX_DTX_N10 Slot#3
TBT_CIO_PLUG_EVENT# GPP_G10/FAN_PWM_2 PCIE10_RXN/SATA1A_RXN PCIE_PRX_DTX_P10 PCIE_PRX_DTX_N10 <39>
1 2 N42 E29
GPP_G11/FAN_PWM_3 PCIE10_RXP/SATA1A_RXP PCIE_PTX_DRX_N10 PCIE_PRX_DTX_P10 <39>
RH341 10K_0402_5% C32
CAM_MIC_CBL_DET# FAN PCIE10_TXN/SATA1A_TXN B32 PCIE_PTX_DRX_P10 PCIE_PTX_DRX_N10 <39>
<30> CAM_MIC_CBL_DET# U43 PCIE10_TXP/SATA1A_TXP PCIE_PTX_DRX_P10 <39>
U42 GPP_G0/FAN_TACH_0
TBT_CIO_PLUG_EVENT# GPP_G1/FAN_TACH_1 F41 PCIE_PRX_DTX_N15
<44> TBT_CIO_PLUG_EVENT# MXM_PRESENTL# U41 PCIE15_RXN/SATA2_RXN PCIE_PRX_DTX_P15 PCIE_PRX_DTX_N15 <42>
+3.3V_RUN GPP_G2/FAN_TACH_2 E41
<18> MXM_PRESENTL# CONTACTLESS_DET# M44 PCIE15_RXP/SATA2_RXP PCIE_PTX_DRX_N15 PCIE_PRX_DTX_P15 <42>
GPP_G3/FAN_TACH_3 B39
<37> CONTACTLESS_DET# U36 PCIE15_TXN/SATA2_TXN PCIE_PTX_DRX_P15 PCIE_PTX_DRX_N15 <42>
GPP_G4/FAN_TACH_4 A39
MXM_PRESENTR# P44 PCIE15_TXP/SATA2_TXP PCIE_PTX_DRX_P15 <42>
GPP_G5/FAN_TACH_5
1 2 CAM_MIC_CBL_DET# <18> MXM_PRESENTR# T45
T44 GPP_G6/FAN_TACH_6 D43 PCIE_PRX_DTX_N16
PCIE_PRX_DTX_N16 <42>
SATA Express
PCIe/SATA
RH319 10K_0402_5% PCIE16_RXN/SATA3_RXN E42 PCIE_PRX_DTX_P16
GPP_G7/FAN_TACH_7 PCIE_PRX_DTX_P16 <42>
PCIE_PTX_DRX_P11 PCIE16_RXP/SATA3_RXP A41 PCIE_PTX_DRX_N16
M.2 SSD <39> PCIE_PTX_DRX_P11 PCIE_PTX_DRX_N11 B33 PCIE16_TXN/SATA3_TXN PCIE_PTX_DRX_P16 PCIE_PTX_DRX_N16 <42>
PCIE11_TXP A40
1 2 MXM_PRESENTL# Slot#3 <39> PCIE_PTX_DRX_N11 PCIE_PRX_DTX_P11 C33
PCIE11_TXN
PCIE16_TXP/SATA3_TXP PCIE_PTX_DRX_P16 <42>
<39> PCIE_PRX_DTX_P11 PCIE_PRX_DTX_N11 K31 PCIE_PRX_DTX_N17
RH317 10K_0402_5% PCIE11_RXP H42
<39> PCIE_PRX_DTX_N11 L31 PCIE17_RXN/SATA4_RXN PCIE_PRX_DTX_P17 PCIE_PRX_DTX_N17 <39>
PCIE11_RXN H40
BIOS_REC PCIE17_RXP/SATA4_RXP PCIE_PTX_DRX_N17 PCIE_PRX_DTX_P17 <39>
Tell EC don't read GFX Temp.in GC6 E45
BIOS_REC AB33 PCIE17_TXN/SATA4_TXN PCIE_PTX_DRX_P17 PCIE_PTX_DRX_N17 <39>
1 2 GPP_F10/SCLOCK F45
RH76 10K_0402_5% High: Read; Low: Don`t read 1 2 CS_CTR AB35 PCIE17_TXP/SATA4_TXP PCIE_PTX_DRX_P17 <39>
<45> GC6_THM_ON AA44 GPP_F11/SLOAD
PCIE_PRX_DTX_N18
M.2 SSD
RH342 0_0402_5% GPP_F13/SDATAOUT0 K37
AA45
GPP_F12/SDATAOUT1
PCIE18_RXN/SATA5_RXN G37 PCIE_PRX_DTX_P18 PCIE_PRX_DTX_N18 <39> Slot#4
SATA_PTX_DRX_N1 PCIE18_RXP/SATA5_RXP PCIE_PTX_DRX_N18 PCIE_PRX_DTX_P18 <39>
B38 G45
<43> SATA_PTX_DRX_N1 SATA_PTX_DRX_P1 C38 PCIE14_TXN/SATA1B_TXN PCIE18_TXN/SATA5_TXN G44 PCIE_PTX_DRX_P18 PCIE_PTX_DRX_N18 <39>
1 2 CONTACTLESS_DET# <43> SATA_PTX_DRX_P1 SATA_PRX_DTX_N1 D39 PCIE14_TXP/SATA1B_TXP PCIE18_TXP/SATA5_TXP PCIE_PTX_DRX_P18 <39>
Dock <43> SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 PCIE14_RXN/SATA1B_RXN PCH_SATA_LED#
RH90 10K_0402_5% E37 AD44
MXM_PRESENTR# <43> SATA_PRX_DTX_P1 PCIE14_RXP/SATA1B_RXP GPP_E8/SATALED# M2_SLOT3_PEDET PCH_SATA_LED# <47>
1 2
PCIE_PTX_DRX_N13 AG36 M2_SLOT3_PEDET <39>
RH91 10K_0402_5% C36 GPP_E0/SATAXPCIE0/SATAGP0 SATAGP1 SPSGP0 1 M2_SLOT3_PEDET 0=SATA 1=PCIE
SATA_EXP_IFDET <38> PCIE_PTX_DRX_N13 PCIE_PTX_DRX_P13 PCIE13_TXN/SATA0B_TXN AG35 HDD_DET#
1 2 B36 GPP_E1/SATAXPCIE1/SATAGP1
<38> PCIE_PTX_DRX_P13 PCIE_PRX_DTX_N13 PCIE13_TXP/SATA0B_TXP AG39 SATA_EXP_IFDET HDD_DET# <41>
RH321 10K_0402_5% WWAN G35 GPP_E2/SATAXPCIE2/SATAGP2
<38> PCIE_PRX_DTX_N13 PCIE_PRX_DTX_P13 PCIE13_RXN/SATA0B_RXN AD35 M2_SLOT4_PEDET SATA_EXP_IFDET <41,42>
E35 GPP_F0/SATAXPCIE3/SATAGP3 SPSGP3 0 SATA_EXP_IFDET 0=SATA 1=PCIE
<38> PCIE_PRX_DTX_P13 PCIE13_RXP/SATA0B_RXP AD31 M2_SLOT4_PEDET <39>
1 2 SATAGP1 GPP_F1/SATAXPCIE4/SATAGP4 SATAGP5
PCIE_PTX_DRX_P12 AD38
RH323 10K_0402_5% A35 GPP_F2/SATAXPCIE5/SATAGP5 SATAGP6
HDD_DET# <39> PCIE_PTX_DRX_P12 PCIE_PTX_DRX_N12 PCIE12_TXP AC43
1 2 M.2 SSD B35 GPP_F3/SATAXPCIE6/SATAGP6 SATAGP7 SPSGP4 0 M2_SLOT4_PEDET 0=SATA 1=PCIE
<39> PCIE_PTX_DRX_N12 PCIE_PRX_DTX_P12 PCIE12_TXN AB44
RH324 10K_0402_5% H33 GPP_F4/SATAXPCIE7/SATAGP7
1 2 SATAGP5
Slot#3 <39> PCIE_PRX_DTX_P12 PCIE_PRX_DTX_N12 G33 PCIE12_RXP BIA_PWM_PCH
<39> PCIE_PRX_DTX_N12 PCIE12_RXN W36 PANEL_BKEN_PCH BIA_PWM_PCH <30>
RH354 10K_0402_5% GPP_F21/EDP_BKLTCTL
PCIE_PTX_DRX_P20 J45 W35 ENVDD_PCH PANEL_BKEN_PCH <30>
C 1 2 SATAGP6 PCIE20_TXP/SATA7_TXP GPP_F20/EDP_BKLTEN C
<39> PCIE_PTX_DRX_P20 PCIE_PTX_DRX_N20 K44 W42 ENVDD_PCH <30,46>
RH326 10K_0402_5% PCIE20_TXN/SATA7_TXN GPP_F19/EDP_VDDEN
<39> PCIE_PTX_DRX_N20 PCIE_PRX_DTX_P20 N38 PCH_THERMTRIP#_R PCH_THERMTRIP#
1 2 SATAGP7 PCIE20_RXP/SATA7_RXP HOST 1 2
<39> PCIE_PRX_DTX_P20 PCIE_PRX_DTX_N20 N39 AJ3 PCH_PECI PCH_THERMTRIP# <7,14,15,16,17,46>
RH322 10K_0402_5% PCIE20_RXN/SATA7_RXN THERMTRIP# RH75 1 2 620_0402_5% H_PECI
<39> PCIE_PRX_DTX_N20 PCIE_PTX_DRX_P19 H44 AL3 H_PM_SYNC_R H_PECI <7,46>
PCIE19_TXP/SATA6_TXP PECI RH73 43_0402_1%
<39> PCIE_PTX_DRX_P19 PCIE_PTX_DRX_N19 H43 AJ4 PLTRST_CPU# H_PM_SYNC_R <7>
M.2 SSD <39> PCIE_PTX_DRX_N19 PCIE_PRX_DTX_P19 L39 PCIE19_TXN/SATA6_TXN PM_SYNC AK2 H_PM_DOWN PLTRST_CPU# <7>
PCIE19_RXP/SATA6_RXP PLTRST_PROC#
Slot#4 <39> PCIE_PRX_DTX_P19 PCIE_PRX_DTX_N19 L37
PCIE19_RXN/SATA6_RXN PM_DOWN
AH2 H_PM_DOWN <7>
<39> PCIE_PRX_DTX_N19
SKL-H-PCH_BGA837 REV = 1.3 3 OF 12
PCH_PECI
1
@ RH74
10K_0402_5%
2
B B
A A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SKYLAKE PCH-H (1/9)
5 4 3 2 1
5 4 3 2 1
1 2
@ RH66 0_0402_5%
D D
+3.3V_RUN
@ CH10
1 2
0.1U_0402_25V6K
5
@ UC3
1
G VCC
<7> XDP_DBRESET# B SYS_RESET#
4
2 1 ME_RESET# 2 Y SYS_RESET# <23,37>
A
@ RH70 8.2K_0402_5% CIS LINK OK
MC74VHC1G09DFT2G_SC70-5
3
SPT-H_PCH
UH1B
DMI_CTX_PRX_N0
<6> DMI_CTX_PRX_N0 DMI_CTX_PRX_P0 L27 USB20_N1
DMI_RXN0 AF5
<6> DMI_CTX_PRX_P0 DMI_CRX_PTX_N0 N27
DMI_RXP0
USB2N_1 AG7 USB20_P1 USB20_N1 <44> ----->Left Side JUSB1
<6> DMI_CRX_PTX_N0 DMI_CRX_PTX_P0 C27 USB2P_1 USB20_N2 USB20_P1 <44>
DMI_TXN0 AD5
<6> DMI_CRX_PTX_P0 DMI_CTX_PRX_N1 B27
DMI_TXP0
USB2N_2 AD7 USB20_P2 USB20_N2 <44> ----->Right Side JUSB1
<6> DMI_CTX_PRX_N1 DMI_CTX_PRX_P1 E24 USB2P_2 USB20_N3 USB20_P2 <44>
AG8
<6> DMI_CTX_PRX_P1 DMI_CRX_PTX_N1 G24 DMI_RXN1
DMI_RXP1
USB2N_3 AG10 USB20_P3 USB20_N3 <44> ----->Right Side JUSB2
<6> DMI_CRX_PTX_N1 DMI_CRX_PTX_P1 B28 USB2P_3 USB20_N4 USB20_P3 <44>
DMI_TXN1 AE1
<6> DMI_CRX_PTX_P1 DMI_CTX_PRX_N2 A28
DMI_TXP1 DMI
USB2N_4 AE2 USB20_P4 USB20_N4 <44> ----->Right Side JUSB3
<6> DMI_CTX_PRX_N2 DMI_CTX_PRX_P2 G27 USB2P_4 USB20_N5 USB20_P4 <44>
DMI_RXN2 AC2
<6> DMI_CTX_PRX_P2 DMI_CRX_PTX_N2 E26
DMI_RXP2
USB2N_5 AC3 USB20_P5 USB20_N5 <43> ----->MLK DOCK
C <6> DMI_CRX_PTX_N2 DMI_CRX_PTX_P2 B29 USB2P_5 USB20_N6 USB20_P5 <43> C
DMI_TXN2 AF2
<6> DMI_CRX_PTX_P2 DMI_CTX_PRX_N3 C29
DMI_TXP2
USB2N_6 AF3 USB20_P6 USB20_N6 <38> ----->M.2 Slot-1 (WLAN/BT/WiGig)
<6> DMI_CTX_PRX_N3 DMI_CTX_PRX_P3 L29 USB2P_6 USB20_N7 USB20_P6 <38>
AB3
<6> DMI_CTX_PRX_P3 DMI_CRX_PTX_N3 K29 DMI_RXN3
DMI_RXP3 USB 2.0
USB2N_7 AB2 USB20_P7 USB20_N7 <43> ----->MLK DOCK
<6> DMI_CRX_PTX_N3 DMI_CRX_PTX_P3 B30 USB2P_7 USB20_N8 USB20_P7 <43>
AL8
<6> DMI_CRX_PTX_P3 A30 DMI_TXN3
DMI_TXP3
USB2N_8 AL7 USB20_P8 USB20_N8 <38> ----->M.2 Slot-2 (WWAN/LTE/HCA)
USB2P_8 USB20_P8 <38>
1 2 PCIECOMP# AA1
B18 USB2N_9
RH192 100_0402_1% PCIECOMP PCIE_RCOMPN AA2
C17 USB2P_9 USB20_N10
PCIE_RCOMPP AJ8
USB2N_10 AJ7 USB20_P10 USB20_N10 <37> ----->USH
USB2P_10 USB20_N11 USB20_P10 <37>
H15 W2
G15 PCIE1_RXN/USB3_7_RXN USB2N_11 W3 USB20_P11 USB20_N11 <30> ----->Camera
PCIE1_RXP/USB3_7_RXP USB2P_11 USB20_P11 <30>
A16 AD3
B16 PCIE1_TXN/USB3_7_TXN USB2N_12 AD2
PCIe/USB 3
PCIE_PTX_DRX_N2 B19 PCIE1_TXP/USB3_7_TXP USB2P_12 V2

<38> PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2 C19 PCIE2_TXN/USB3_8_TXN USB2N_13 V1
<38> PCIE_PTX_DRX_P2 PCIE_PRX_DTX_N2 E17 PCIE2_TXP/USB3_8_TXP USB2P_13 AJ11
WLAN <38> PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 PCIE2_RXN/USB3_8_RXN USB2N_14
G17 AJ13
<38> PCIE_PRX_DTX_P2 PCIE_PRX_DTX_N3 PCIE2_RXP/USB3_8_RXP USB2P_14
L17
<44> PCIE_PRX_DTX_N3 PCIE_PRX_DTX_P3 PCIE3_RXN/USB3_9_RXN +3.3V_ALW_PCH
K17
<44> PCIE_PRX_DTX_P3 PCIE_PTX_DRX_N3 PCIE3_RXP/USB3_9_RXP
Card reader B20
<44> PCIE_PTX_DRX_N3 PCIE_PTX_DRX_P3 C20 PCIE3_TXN/USB3_9_TXN USB_OC0# RPH6
<44> PCIE_PTX_DRX_P3 PCIE_PRX_DTX_N4 PCIE3_TXP/USB3_9_TXP AD43 USB_OC1# USB_OC0# <44> USB_OC1#
E20 GPP_E9/USB2_OC0# 1 8
<35> PCIE_PRX_DTX_N4 PCIE_PRX_DTX_P4 PCIE4_RXN/USB3_10_RXN AD42 USB_OC2# USB_OC1# <44> USB_OC2#
G19 GPP_E10/USB2_OC1# 2 7
<35> PCIE_PRX_DTX_P4 PCIE_PTX_DRX_N4 PCIE4_RXP/USB3_10_RXP AD39 USB_OC3# USB_OC2# <44> USB_OC3#
LAN B21 GPP_E11/USB2_OC2# 3 6
<35> PCIE_PTX_DRX_N4 PCIE_PTX_DRX_P4 PCIE4_TXN/USB3_10_TXN AC44 USB_OC3# <44> USB_OC0#
A21 GPP_E12/USB2_OC3# 4 5
<35> PCIE_PTX_DRX_P4 PCIE_PRX_DTX_N5 PCIE4_TXP/USB3_10_TXP Y43
K19 GPP_F15/USB2_OCB_4
<44> PCIE_PRX_DTX_N5 PCIE_PRX_DTX_P5 PCIE5_RXN Y41
L19 GPP_F16/USB2_OCB_5 10K_8P4R_5%
<44> PCIE_PRX_DTX_P5 PCIE_PTX_DRX_N5 PCIE5_RXP W44
D22 GPP_F17/USB2_OCB_6
<44> PCIE_PTX_DRX_N5 PCIE_PTX_DRX_P5 PCIE5_TXN W43
C22 GPP_F18/USB2_OCB_7
<44> PCIE_PTX_DRX_P5 PCIE_PRX_DTX_N6 G22 PCIE5_TXP
<44> PCIE_PRX_DTX_N6 PCIE_PRX_DTX_P6 PCIE6_RXN USB2_COMP
E22 1 2
<44> PCIE_PRX_DTX_P6 PCIE_PTX_DRX_N6 PCIE6_RXP AG3
B22 USB2_COMP RH193 1 2113_0402_1%
<44> PCIE_PTX_DRX_N6 PCIE_PTX_DRX_P6 PCIE6_TXN AD10
TBT A23 USB2_VBUSSENSE RH355 1K_0402_5%
<44> PCIE_PTX_DRX_P6 PCIE_PRX_DTX_N7 PCIE6_TXP AB13
B L22 RSVD_AB13 1 2 B
<44> PCIE_PRX_DTX_N7 PCIE_PRX_DTX_P7 PCIE7_RXN AG2
K22 USB2_ID @ RH356 0_0402_5%
<44> PCIE_PRX_DTX_P7 PCIE_PTX_DRX_N7 PCIE7_RXP
C23
<44> PCIE_PTX_DRX_N7 PCIE_PTX_DRX_P7 B23 PCIE7_TXN
<44> PCIE_PTX_DRX_P7 PCIE_PRX_DTX_N8 K24 PCIE7_TXP BD14 3.3V_CAM_EN#
<44> PCIE_PRX_DTX_N8 PCIE_PRX_DTX_P8 PCIE8_RXN GPD7/RSVD 3.3V_CAM_EN# <30>
L24
<44> PCIE_PRX_DTX_P8 PCIE_PTX_DRX_N8 PCIE8_RXP
C24
<44> PCIE_PTX_DRX_N8 PCIE_PTX_DRX_P8 B24 PCIE8_TXN
<44> PCIE_PTX_DRX_P8 PCIE8_TXP
A A
Title
1.0
5 4 3 2 1
5 4 3 2 1
D D
SPT-H_PCH
UH1G
AR17
GPP_A16/CLKOUT_48
CPU_24MHZ_R_D 1 2 PCH_CPU_NSSC_CLK_D L1 PCH_XDP_CLK_DN_R 1 2 PCH_XDP_CLK_DN
<7> CPU_24MHZ_R_D CPU_24MHZ_R_D# PCH_CPU_NSSC_CLK_D# G1 CLKOUT_ITPXDP_N PCH_XDP_CLK_DP_R PCH_XDP_CLK_DN <7>
@ RH169 1 2 0_0402_5% CLKOUT_CPUNSSC_P L2 @ RH154 1 2 0_0402_5% PCH_XDP_CLK_DP
<7> CPU_24MHZ_R_D# F1 CLKOUT_ITPXDP_P PCH_CPU_PCIBCLK_D# @ RH155 1 PCH_XDP_CLK_DP <7>
@ RH170 0_0402_5% CLKOUT_CPUNSSC_N 2 0_0402_5% PCH_CPU_PCIBCLK_R_D#
PCH_CPU_BCLK_R_D PCH_CPU_BCLK_D J1 PCH_CPU_PCIBCLK_D @ RH168 1 PCH_CPU_PCIBCLK_R_D# <7>
1 2 CLKOUT_CPUPCIBCLK_N 2 0_0402_5% PCH_CPU_PCIBCLK_R_D
<7> PCH_CPU_BCLK_R_D PCH_CPU_BCLK_R_D# PCH_CPU_BCLK_D# G2 J2 PCH_CPU_PCIBCLK_R_D <7>
@ RH161 1 2 0_0402_5% CLKOUT_CPUBCLK_P CLKOUT_CPUPCIBCLK_P @ RH167 0_0402_5%
<7> PCH_CPU_BCLK_R_D# H2
@ RH166 0_0402_5% CLKOUT_CPUBCLK_N
XTAL24_OUT_R1 N7 CLK_PEG_N0
+1.0V_CLK5 XTAL24_IN_R A5 CLKOUT_PCIE_N0 CLK_PEG_P0 CLK_PEG_N0 <18>
XTAL24_OUT N8 MXM
A6 CLKOUT_PCIE_P0 CLK_PEG_P0 <18>
XTAL24_IN
1 2 XCLK_RBIAS L7 CLK_PCIE_N1
E1 CLKOUT_PCIE_N1 CLK_PCIE_P1 CLK_PCIE_N1 <44>
RH171 2.7K_0402_1% XCLK_BIASREF L5 Card reader
PCH_RTCX1 CLKOUT_PCIE_P1 CLK_PCIE_P1 <44>
PCH_RTCX2 BC9 CLK_PCIE_N2
RTCX1 D3
BD10 CLKOUT_PCIE_N2 CLK_PCIE_P2 CLK_PCIE_N2 <38>
RTCX2 F2 M.2 Slot2 WWAN
CLKREQ_PEG#0 CLKOUT_PCIE_P2 CLK_PCIE_P2 <38>
MXM BC24 CLK_PCIE_N3
+3.3V_RUN RH124 2 1 10K_0402_5% GPP_B5/SRCCLKREQ0# E5
CLKREQ_PCIE#1 AW24 CLKOUT_PCIE_N3 CLK_PCIE_P3 CLK_PCIE_N3 <35>
Card reader GPP_B6/SRCCLKREQ1# G4 LAN
<44> CLKREQ_PCIE#1 AT24 CLKOUT_PCIE_P3 CLK_PCIE_P3 <35>
+3.3V_RUN RH125 2 1 10K_0402_5% GPP_B7/SRCCLKREQ2#
CLKREQ_PCIE#2 BD25 CLK_PCIE_N4
M.2 Slot2 WWAN GPP_B8/SRCCLKREQ3# D5
C <38> CLKREQ_PCIE#2 BB24 CLKOUT_PCIE_N4 CLK_PCIE_P4 CLK_PCIE_N4 <44> C
+3.3V_RUN RH126 2 1 10K_0402_5% GPP_B9/SRCCLKREQ4# E6 TBT
CLKREQ_PCIE#3 BE25 CLKOUT_PCIE_P4 CLK_PCIE_P4 <44>
LAN <35> CLKREQ_PCIE#3 AT33 GPP_B10/SRCCLKREQ5#
CLK_PCIE_N5
+3.3V_RUN RH127 2 1 10K_0402_5% GPP_H0/SRCCLKREQ6# D8
CLKREQ_PCIE#4 AR31 CLKOUT_PCIE_N5 CLK_PCIE_P5 CLK_PCIE_N5 <41>
TBT GPP_H1/SRCCLKREQ7# D7 HDD
<44> CLKREQ_PCIE#4 BD32 CLKOUT_PCIE_P5 CLK_PCIE_P5 <41>
+3.3V_RUN RH131 2 1 10K_0402_5% GPP_H2/SRCCLKREQ8#
CLKREQ_PCIE#5 BC32 CLK_PCIE_N6
HDD GPP_H3/SRCCLKREQ9# R8
<41> CLKREQ_PCIE#5 BB31 CLKOUT_PCIE_N6 CLK_PCIE_P6 CLK_PCIE_N6 <38>
+3.3V_RUN RH132 2 1 10K_0402_5% GPP_H4/SRCCLKREQ10# R7 M.2 Slot1 WLAN
CLKREQ_PCIE#6 BC33 CLKOUT_PCIE_P6 CLK_PCIE_P6 <38>
M.2 Slot1 WLAN <38> CLKREQ_PCIE#6 BA33 GPP_H5/SRCCLKREQ11#
CLK_PCIE_N7
+3.3V_RUN RH133 2 1 10K_0402_5% GPP_H6/SRCCLKREQ12# U5
CLKREQ_PCIE#7 AW33 CLKOUT_PCIE_N7 CLK_PCIE_P7 CLK_PCIE_N7 <39>
M.2 Slot3 SSD1 GPP_H7/SRCCLKREQ13# U7 M.2 Slot3 SSD2
<39> CLKREQ_PCIE#7 BB33 CLKOUT_PCIE_P7 CLK_PCIE_P7 <39>
+3.3V_RUN RH332 2 1 10K_0402_5% GPP_H8/SRCCLKREQ14#
CLKREQ_PCIE#8 BD33 CLK_PCIE_N8
M.2 Slot4 SSD2 GPP_H9/SRCCLKREQ15# W10
<39> CLKREQ_PCIE#8 CLKOUT_PCIE_N8 CLK_PCIE_P8 CLK_PCIE_N8 <39>
W11 M.2 Slot4 SSD3
R13 CLKOUT_PCIE_P8 CLK_PCIE_P8 <39>
R11 CLKOUT_PCIE_N15
CLKOUT_PCIE_P15 N3
CLKOUT_PCIE_N9 N2
P1 CLKOUT_PCIE_P9
R2 CLKOUT_PCIE_N14
CLKOUT_PCIE_P14 P3
CLKOUT_PCIE_N10 P2
W7 CLKOUT_PCIE_P10
Y5 CLKOUT_PCIE_N13
CLKOUT_PCIE_P13 R3
CLKOUT_PCIE_N11 R4
U2 CLKOUT_PCIE_P11
U3 CLKOUT_PCIE_N12
CLKOUT_PCIE_P12
+3.3V_ALW_PCH
2
10K_0402_5%
B B
RH128
1
CLKREQ_PEG#0
CH13
CH4
1 2 PCH_RTCX1_R 1 2 PCH_RTCX1 XTAL24_IN_R 1 2
1
@ RH43 0_0402_5% D
18P_0402_50V8J 2 QH3
15P_0402_50V8J <45,49> 3.3V_RUN_GFX_ON
1
2
1M_0402_1%
G DMN65D8LW-7_SOT323-3
3
4
RH153
YH1 RH44 S
3
32.768KHZ_12.5PF_9H03200042 10M_0402_5% YH2
24MHZ_12PF_X3G024000DC1H
2
1
2
CH5
PCH_RTCX2 CH14
1 2
XTAL24_OUT_R1 1 2 XTAL24_OUT_R 1 2
18P_0402_50V8J @ RH152 0_0402_5%
15P_0402_50V8J
A A
Title
1.0
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW_PCH +3.3V_RUN
1
RH349 @ RH350
0_0402_5% 0_0402_5%
2
+U638_PWR
U638
5
+3.3V_ALW_PCH SN74AHC1G08DCKR_SC70-5
D PCH_PLTRST# 1 D
P
IN1 4 PCH_PLTRST#_EC
2 O 1 2 PCH_PLTRST#_EC <38,39,45,46>
IN2 PLTRST_TBT# <44>
1
@ RH197 1 2 0_0402_5%
@ RH196 @ RH212 0_0402_5% PLTRST_HDD# <41>
3
2 1 SIO_EXT_SMI# 100K_0402_5% 1 2 PLTRST_TPM#
10K_0402_5% RH310 @ RH346 0_0402_5%
+3.3V_RUN
2
GPP_B4 1 2
RH336 100K_0402_5%
SPT-H_PCH
11/11 BC/PC for verb table
UH1A detect
PAD~D @ T178 PME# PCH_PLTRST# @ RH187 1 2 0_0402_5%
BD17 BB27 PLTRST_TPM# <37>
GPP_A11/PME# GPP_B13/PLTRST# @ RH194 1 2 0_0402_5%
PAD~D @ T59 @ RH195 1 2 0_0402_5% PLTRST_LAN# <35>
AG15 TBT_FORCE_PWR PLTRST_GPU# <18>
PAD~D @ T60 RSVD P43 @ RH211 1 2 0_0402_5%
AG14 GPP_G16/GSXCLK RTD3_CIO_PWR_EN TBT_FORCE_PWR <44> PLTRST_MMI# <44>
PAD~D @ T61 RSVD R39 @ RH210 1 2 0_0402_5%
AF17 GPP_G12/GSXDOUT RTD3_CIO_PWR_EN <44,45> @ RH359 PLTRST_USH# <37>
PAD~D @ T58 RSVD R36 1 2 0_0402_5%
AE17 GPP_G13/GSXSLOAD <45> PLTRST_USH#_EC
RSVD R42
PAD~D @ T63 GPP_G14/GSXDIN R41
AR19 GPP_G15/GSXSRESET#
PAD~D @ T62 TP2
AN17
+3.3V_SPI TP1
11/6 MOW(BC) PCH_SPI_D0 AF41 SIO_EXT_SMI#
<7,37> PCH_SPI_D0 PCH_SPI_D1 BB29 GPP_E3/CPU_GP0 SIO_EXT_SMI# <46>
SPI0_MOSI AE44
PCH_SPI_D3 <37> PCH_SPI_D1 PCH_SPI_CS#0 BE30 GPP_E7/CPU_GP1 TOUCHPAD_INTR#
1 2 SPI0_MISO BC23
PCH_SPI_CLK BD31 GPP_B3/CPU_GP2 GPP_B4 TOUCHPAD_INTR# <48>
@ RH335 1K_0402_5% SPI0_CS0# BD24
<37> PCH_SPI_CLK PCH_SPI_CS#1 BC31 GPP_B4/CPU_GP3
AW31 SPI0_CLK
C SPI0_CS1# BC36 C
PCH_SPI_D2_XDP1 2 PCH_SPI_D2 BC29 GPP_H18/SML4ALERT# BE34 +RTC_CELL
<7> PCH_SPI_D2_XDP PCH_SPI_D3 SPI0_IO2 GPP_H17/SML4DATA
@ RH180 0_0402_5% BD30 BD39
PCH_SPI_CS#2 AT31 SPI0_IO3 GPP_H16/SML4CLK BB36
<37> PCH_SPI_CS#2 SPI0_CS2# GPP_H15/SML3ALERT#
1
BA35
MEDIACARD_IRQ# AN36 GPP_H14/SML3DATA
GPP_D1/SPI1_CLK BC35 RH198
<44> MEDIACARD_IRQ# FFS_INT2 AL39 GPP_H13/SML3CLK
GPP_D0/SPI1_CS# BD35 330K_0402_5%
<41> FFS_INT2 TPM_PIRQ# AN41 GPP_H12/SML2ALERT#
GPP_D3/SPI1_MOSI AW35
<37> TPM_PIRQ# AN38 GPP_H11/SML2DATA
GPP_D2/SPI1_MISO BD34
AH43
2
GPP_H10/SML2CLK PCH_INTRUDER_HDR#
AG44 GPP_D22/SPI1_IO3 BE11
GPP_D21/SPI1_IO2 INTRUDER#
PCH_SPI_D3 1 2 PCH_SPI_CLK_0_R
@ RH334 1K_0402_5% SKL-H-PCH_BGA837 REV = 1.3 1 OF 12 ?
1
@
Intel required for pre-ES1/ES2 sample RE1
33_0402_5%
2
1
@
CE1
27P_0402_50V8J
+3.3V_SPI 2
1 2 PCH_SPI_D2_0_R +3.3V_SPI
R3664 1K_0402_5%
1 2 PCH_SPI_D3_0_R C746
R3668 1K_0402_5% 200 MIL SO8 1 2
B 16MB Flash ROM 0.1U_0402_25V6K B
JSPI1
U52 2 1 PCH_SPI_CS#1_R1 1
PCH_SPI_CS#0_R1 @ R7 1 2 0_0402_5% PCH_SPI_CS#0_R2 1 8 0_0402_5% RH177 PCH_SPI_CS#1 2 1
PCH_SPI_D1_R1 R8 1 2 33_0402_5% PCH_SPI_D1_0_R 2 /CS VCC 7 PCH_SPI_D3_0_R R3669 1 2 33_0402_5%PCH_SPI_D3_R1 2 1 PCH_SPI_D0_R1 3 2 2
PCH_SPI_D2_R1 R9 1 2 33_0402_5% PCH_SPI_D2_0_R 3 DO(IO1) /HOLD(IO3) 6 PCH_SPI_CLK_0_R EMC@ R899 1 2 33_0402_5%PCH_SPI_CLK_R1 0_0402_5% RH178 PCH_SPI_D0 4 3
4 /WP(IO2) CLK 5 PCH_SPI_D0_0_R R901 1 2 33_0402_5%PCH_SPI_D0_R1 2 1 PCH_SPI_D1_R1 5 4 4
GND DI(IO0) 0_0402_5% RH179 PCH_SPI_D1 6 5
W25Q128FVSIQ_SO8 2 1 PCH_SPI_CLK_R1 7 6 6
+3.3V_SPI 0_0402_5% RH181 PCH_SPI_CLK 8 7
CIS LINK OK 2 1 PCH_SPI_CS#0_R1 9 8 8
0_0402_5% RH182 PCH_SPI_CS#0 10 9
1 2 PCH_SPI_D2_1_R 2 1 PCH_SPI_D2_R1 11 10 10
@ R3665 1K_0402_5% 0_0402_5% RH183 PCH_SPI_D2 12 11
1 2 PCH_SPI_D3_1_R +3.3V_SPI 2 1 PCH_SPI_D3_R1 13 12 12
@ R3666 1K_0402_5% 0_0402_5% RH184 PCH_SPI_D3 14 13
@ C1216 15 14 14
200 MIL SO8 1 2
+3.3V_SPI
+3.3V_ALW_PCH
2 1 +3.3V_SPI_PWR 16 15
RH343 0_0402_5% 17 16 16
4MB Flash ROM 0.1U_0402_25V6K 18 17
@ U53 +3.3V_M 2 1 19 18 18
PCH_SPI_CS#1_R1@ R936 1 2 0_0402_5% PCH_SPI_CS#1_R2 1 8 @ RH344 0_0402_5% 20 19
PCH_SPI_D1_R1 @ R895 1 2 33_0402_5% PCH_SPI_D1_1_R 2 /CS VCC 7 PCH_SPI_D3_1_R @ R3670 1 2 33_0402_5% PCH_SPI_D3_R1 1 2 20 20
PCH_SPI_D2_R1 @ R3667 1 2 33_0402_5% PCH_SPI_D2_1_R 3 DO/IO1 /HOLD/IO3 6 PCH_SPI_CLK_1_R
@EMC@ R897 1 2 33_0402_5% PCH_SPI_CLK_R1 @ RH185 0_0402_5% 21
4 /WP/IO2 CLK 5 PCH_SPI_D0_1_R @ R900 1 2 33_0402_5% PCH_SPI_D0_R1 G1 22
GND DI/IO0 G2 23
W25Q32FVSSIQ_SO8 G3 24
11/17 RF request G4
PCH_SPI_CLK_1_R CIS LINK OK ACES_50559-02001-001
CONN@
CIS link OK
1
A A
@EMC@ R3755
33_0402_5%
2
1
@EMC@ C1466 Compal Electronics, Inc.
27P_0402_50V8J Title
2 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
1.0
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW_PCH
1 2 MEM_SMBCLK
RH56 1K_0402_5%
1 2 MEM_SMBDATA UH1F SPT-H_PCH
RH65 1K_0402_5%
USB3_PTX_DRX_N1 C11 AT22 LPC_AD0
LPC/eSPI
SML0_SMBCLK <44> USB3_PTX_DRX_N1 USB3_PTX_DRX_P1 USB3_1_TXN GPP_A1/LAD0/ESPI_IO0 LPC_AD1 LPC_AD0 <45,46>
1 2 B11 AV22
<44> USB3_PTX_DRX_P1 USB3_PRX_DTX_N1 USB3_1_TXP GPP_A2/LAD1/ESPI_IO1 LPC_AD2 LPC_AD1 <45,46>
RH67 499_0402_1% Left Side B7 AT19
SML0_SMBDATA <44> USB3_PRX_DTX_N1 USB3_PRX_DTX_P1 USB3_1_RXN GPP_A3/LAD2/ESPI_IO2 LPC_AD3 LPC_AD2 <45,46>
1 2 A7 BD16
<44> USB3_PRX_DTX_P1 USB3_PTX_DRX_N2 USB3_1_RXP GPP_A4/LAD3/ESPI_IO3 LPC_AD3 <45,46>
RH77 499_0402_1%
SML1_SMBCLK <38> USB3_PTX_DRX_N2 USB3_PTX_DRX_P2 B12 LPC_FRAME#
1 2 USB3_2_TXN/SSIC_1_TXN
D <38> USB3_PTX_DRX_P2 USB3_PRX_DTX_N2 A12 BE16 IRQ_SERIRQ LPC_FRAME# <45,46> D
RH80 1K_0402_5%
SML1_SMBDATA
WWAN <38> USB3_PRX_DTX_N2 USB3_PRX_DTX_P2 C8 USB3_2_TXP/SSIC_1_TXP GPP_A5/LFRAME#/ESPI_CS0# BA17 HDD_FALL_INT IRQ_SERIRQ <45,46>
1 2 USB3_2_RXN/SSIC_1_RXN GPP_A6/SERIRQ/ESPI_CS1#
<38> USB3_PRX_DTX_P2 B8 AW17 SIO_RCIN# HDD_FALL_INT <41>
RH81 1K_0402_5% USB3_2_RXP/SSIC_1_RXP GPP_A7/PIRQA#/ESPI_ALERT0#
USB3_PTX_DRX_N6 AT17 GPP_A14 SIO_RCIN# <46>
B15 GPP_A0/RCIN#/ESPI_ALERT1#
<43> USB3_PTX_DRX_N6 USB3_PTX_DRX_P6 USB3_6_TXN BC18
C15 GPP_A14/SUS_STAT#/ESPI_RESET#
<43> USB3_PTX_DRX_P6 USB3_PRX_DTX_N6 K15 USB3_6_TXP 1 2
EDOCK <43> USB3_PRX_DTX_N6 USB3_6_RXN CLK_PCI_5048 <45>
USB
USB3_PRX_DTX_P6 K13 BC17 PCI_CLK_LPC0 EMC@ RH96 1 2 22_0402_5%
<43> USB3_PRX_DTX_P6 USB3_PTX_DRX_N5 USB3_6_RXP GPP_A9/CLKOUT_LPC0/ESPI_CLK PCI_CLK_LPC1 CLK_PCI_MEC <46>
AV19 EMC@ RH97 1 2 22_0402_5%
<44> USB3_PTX_DRX_N5 USB3_PTX_DRX_P5 B14 GPP_A10/CLKOUT_LPC1 CLK_PCI_LPDEBUG <46>
USB3_5_TXN EMC@ RH99 1 2 22_0402_5%
<44> USB3_PTX_DRX_P5 USB3_PRX_DTX_N5 C14 CLK_PCI_DOCK <43>
Right Side JUSB1 USB3_5_TXP M45 EMC@ RH98 22_0402_5%
<44> USB3_PRX_DTX_N5 USB3_PRX_DTX_P5 G13 GPP_G19/SMI#
USB3_5_RXN N43
<44> USB3_PRX_DTX_P5 H13 GPP_G18/NMI#
USB3_5_RXP
+3.3V_RUN +3.3V_ALW_PCH USB3_PTX_DRX_P3
<44> USB3_PTX_DRX_P3 USB3_PTX_DRX_N3 D13 CLK_PCI_5048
USB3_3_TXP/SSIC_2_TXP AE45 1 2
<44> USB3_PTX_DRX_N3 USB3_PRX_DTX_P3 C13 GPP_E6/DEVSLP2
RH353 Right Side JUSB2 USB3_3_TXN/SSIC_2_TXN AG43 EMC@ CH42 12P_0402_50V8J
<44> USB3_PRX_DTX_P3 A9 GPP_E5/DEVSLP1
2
2
0_0402_5% USB3_PRX_DTX_N3 USB3_3_RXP/SSIC_2_RXP AG42 CLK_PCI_MEC 1 2
<44> USB3_PRX_DTX_N3 B10 GPP_E4/DEVSLP0
@ RH347 2 1 RH329 USB3_3_RXN/SSIC_2_RXN AB39 EMC@ CH49 12P_0402_50V8J
150K_0402_5% 150K_0402_5% USB3_PTX_DRX_P4 GPP_F9/DEVSLP7 AB36 CLK_PCI_LPDEBUG 1 2
B13
SATA
<44> USB3_PTX_DRX_P4 USB3_PTX_DRX_N4 GPP_F8/DEVSLP6 AB43 EMC@ CH50 12P_0402_50V8J
<44> USB3_PTX_DRX_N4 A14 USB3_4_TXP
USB3_PRX_DTX_P4 GPP_F7/DEVSLP5 AB42 CLK_PCI_DOCK 1 2
Right Side JUSB3 <44> USB3_PRX_DTX_P4 G11 USB3_4_TXN
1
GPP_B23 3 1 GPP_B23_Q USB3_PRX_DTX_N4 GPP_F6/DEVSLP4 AB41

S
USB3_4_RXP EMC@ CH51 12P_0402_50V8J

<44> USB3_PRX_DTX_N4 E11 GPP_F5/DEVSLP3
USB3_4_RXN
@ QH5
DMN65D8LW-7_SOT323-3 SKL-H-PCH_BGA837 REV = 1.3 6 OF 12 +3.3V_ALW_PCH
G
2
<23,37,46,49> SIO_SLP_A# GPP_A14 1 2

@ RH95 10K_0402_5%
VRALERT# 1 2
EXI BOOT STALL BYPASS @ RH203 10K_0402_5%
11/17 RF request UH1D SPT-H_PCH SIO_SLP_LAN# 1 2
HIGH ENABLED EMC@ 1 2 @ RH204 10K_0402_5%
CH268 22P_0402_50V8J ME_SUS_PWR_ACK 1 2
C LOW(DEFAULT) DIABLED 1 2 HDA_BIT_CLK BA9 BB17 RH327 10K_0402_5% C
WEAK INTERNAL PD <44> HDA_BIT_CLK_R RH46 1 2 33_0402_5% HDA_RST# BD8 HDA_BCLK GPP_A12/BMBUSY#/ISH_GP6/SX_EXIT_HOLDOFF# AW22 CLKRUN#
<44> HDA_RST#_R HDA_SDIN0 HDA_RST# GPP_A8/CLKRUN# CLKRUN# <45,46>
RH50 33_0402_5% BE7
<44> HDA_SDIN0 HDA_SDI0 PM_LANPHY_ENABLE +3.3V_DSW
BC8 AR15
ME_FWP HDA_SDI1 GPD11/LANPHYPC PM_LANPHY_ENABLE <35>
1 2
RH328 1 2 1K_0402_5% HDA_SDOUT BB7 AV13 SIO_SLP_WLAN# PM_LANPHY_ENABLE 1 2
<44> HDA_SDOUT_R HDA_SYNC HDA_SDO GPD9/SLP_WLAN# SIO_SLP_WLAN# <40,45>
RH45 1 2 33_0402_5% BD9 RH338 100K_0402_5%
<44> HDA_SYNC_R RH48 33_0402_5% HDA_SYNC BC14 DDR4_DRAMRST#_PCH PCH_PCIE_WAKE# 1 2
DRAM_RESET# DDR4_DRAMRST#_PCH <14>
BD1 BD23 VRALERT# RH92 1K_0402_5%
BE2 RSVD_BD1 GPP_B2/VRALERT# AL27 LAN_WAKE# 1 2
RSVD_BE2 GPP_B1 AR27 RH93 10K_0402_5%
AUD_AZACPU_SDO 1 2 AUD_AZACPU_SDO_R AM1 AUDIO GPP_B0 N44 PCH_BATLOW# 1 2
<9> AUD_AZACPU_SDO AUD_AZACPU_SDI_R DISPA_SDO GPP_G17/ADR_COMPLETE
RH39 30_0402_5% AN2 AN24 RH94 8.2K_0402_5%
<9> AUD_AZACPU_SDI_R AUD_AZACPU_SCLK AUD_AZACPU_SCLK_R DISPA_SDI GPP_B11 RESET_OUT#
+3.3V_PGPPBCH 1 2 AM2 AY1
<9> AUD_AZACPU_SCLK DISPA_BCLK SYS_PWROK RESET_OUT# <7,46>
RH38 30_0402_5%
BC13 PCH_PCIE_WAKE# +3.3V_RUN
AL42 WAKE# SIO_SLP_A# PCH_PCIE_WAKE# <46>
GPP_D8/I2S0_SCLK BC15
PCH_SMB_ALERT# AN42 GPD6/SLP_A# SIO_SLP_LAN# SIO_SLP_A# <23,37,46,49> SIO_RCIN#
1 2 GPP_D7/I2S0_RXD AV15 1 2
AM43 SLP_LAN# SIO_SLP_S0# SIO_SLP_LAN# <40,46>
RH61 4.7K_0402_5% GPP_D6/I2S0_TXD BC26 RH213 10K_0402_5%
AJ33 GPP_B12/SLP_S0# SIO_SLP_S3# SIO_SLP_S0# <11,37>
TLS CONFIDENTIALITY GPP_D5/I2S0_SFRM AW15 CLKRUN# 1 2
AH44 GPD4/SLP_S3# SIO_SLP_S4# SIO_SLP_S3# <7,11,37,44,46>
HIGH ENABLE GPP_D20/DMIC_DATA0 BD15 RH202 8.2K_0402_5%
LOW(DEFAULT) DISABLE DGPU_PWROK AJ35 GPD5/SLP_S4# SIO_SLP_S5# SIO_SLP_S4# <11,37,46,52,54> RESET_OUT#
GPP_D19/DMIC_CLK0 BA13 1 2
<18,45> DGPU_PWROK AJ38 GPD10/SLP_S5# SIO_SLP_S5# <37,44,46>
GPP_D18/DMIC_DATA1 RH199 100K_0402_5%
AJ42 IRQ_SERIRQ
+RTC_CELL GPP_D17/DMIC_CLK1 AN15 SUSCLK 1 2
GPD8/SUSCLK PCH_BATLOW# SUSCLK <38,39>
+3.3V_ALW_PCH BD13 10/23 RH340 10K_0402_5%
GPD0/BATLOW# BB19 SUSACK#
PCH_RTCRST# GPP_A15/SUSACK# ME_SUS_PWR_ACK SUSACK# <46>
1 2 BC10 BD19
GPP_C5 RTCRST# GPP_A13/SUSWARN#/SUSPWRDNACK ME_SUS_PWR_ACK <46>
1 2 RH200 1 220K_0402_5% SRTCRST# BB10
@ RH78 4.7K_0402_5% RH201 20K_0402_5% SRTCRST# PCH_JTAG_TCK 2 1
EC interface PCH_PWROK AW11 BD11 LAN_WAKE# 51_0402_5% @XDP@ RH313
<61,64> PCH_PWROK PCH_RSMRST#_R PCH_PWROK GPD2/LAN_WAKE# AC_PRESENT_R LAN_WAKE# <35,46>
HIGH ESPI BA11 BB15
LOW(DEFAULT) LPC <7> PCH_RSMRST#_R RSMRST# GPD1/ACPRESENT SIO_SLP_SUS#_R
BB13 SUSCLK 1K_0402_5% 2 1 @ RH83
B PCH_DPWROK SLP_SUS# SIO_PWRBTN# SIO_SLP_SUS#_R <46>
AT13 B
<46> PCH_DPWROK PCH_SMB_ALERT# AV11 GPD3/PWRBTN# SYS_RESET# SIO_PWRBTN# <7,46>
DSW_PWROK AW1
MEM_SMBCLK BB41 SYS_RESET# SYS_RESET# <20,37>
+3.3V_ALW_PCH GPP_C2/SMBALERT# BD26 SPKR
SMBUS
MEM_SMBDATA AW44 GPP_B14/SPKR H_PWRGD SPKR <44>
GPP_C0/SMBCLK AM3
GPP_C5 BB43 PROCPWRGD H_PWRGD <7>
BA40 GPP_C1/SMBDATA PAD~D @ T192
1 2 SPKR SML0_SMBCLK GPP_C5/SML0ALERT# AT2 ITP_PMODE_CPU
<35> SML0_SMBCLK SML0_SMBDATA AY44 ITP_PMODE PCH_JTAGX ITP_PMODE_CPU <7>
@ RH86 4.7K_0402_5% GPP_C3/SML0CLK AR3
<35> SML0_SMBDATA GPP_B23 BB39 JTAGX PCH_JTAG_TMS PCH_JTAGX <7> +1.0V_VCCSTG
TOP SWAP STRAP GPP_C4/SML0DATA JTAG AR2
SML1_SMBCLK AT27 JTAG_TMS PCH_JTAG_TDO PCH_JTAG_TMS <7>
HIGH ENABLE GPP_B23/SML1ALERT#/PCHHOT# AP1
LOW(DEFAULT) DISABLE <46> SML1_SMBCLK SML1_SMBDATA AW42 JTAG_TDO PCH_JTAG_TDI PCH_JTAG_TDO <7>
GPP_C6/SML1CLK AP2
<46> SML1_SMBDATA AW45 JTAG_TDI PCH_JTAG_TCK PCH_JTAG_TDI <7> PCH_JTAG_TMS
GPP_C7/SML1DATA AN3 2 1
JTAG_TCK PCH_JTAG_TCK <7>
51_0402_5% RH312
PCH_JTAG_TDI 2 1
PAD~D @ T182
SKL-H-PCH_BGA837 REV = 1.3 4 OF 12 @ T183 51_0402_5% RH314
PAD~D PCH_JTAG_TDO
@ 2 1
PAD~D T186
Service Mode Switch: @ T187 51_0402_5% RH315
PAD~D
+3.3V_RUN @ T188
Add a switch to ME_FWP signal to unlock the ME region and PAD~D
allow the entire region of the SPI flash to be updated using FPT.
+3.3V_ALW_PCH RH215
2
ME_FWP_EC 2 1 ME_FWP
RC301 0_0402_5%
POP NO Support Deep sleep
PT,ST pop R3728 and SW2; MP pop RC301 DE-POP Support Deep sleep MEM_SMBCLK 6 1
DDR_XDP_WAN_SMBCLK <7,14,15,16,17,41>
1
@ R3728 PCH_DPWROK 1 2 PCH_RSMRST#_R QH4A

5
1K_0402_5% @ RH215 0_0402_5% DMN66D0LDW-7_SOT363-6

ME_SUS_PWR_ACK 0_0402_5% 2 1 @ RH84 SUSACK#
1
MEM_SMBDATA AC_PRESENT AC_PRESENT_R

0.01U_0402_16V7K
1M_0402_5%
1 3 4 0_0402_5% 2 1 @ RH85
DDR_XDP_WAN_SMBDAT <7,14,15,16,17,41> <46> AC_PRESENT
2
@ SW2
CH266
RH308
<45> ME_FWP_EC 1 QH4B

A 2 A DMN66D0LDW-7_SOT363-6 A
ME_FWP 3 B 2
2
4 C
5 G1 1 2 SRTCRST#
G2 CH41 1U_0402_6.3VAK
SS3-CMFTQR9_3P
CH40
1 2
1U_0402_6.3VAK
PCH_RTCRST# DELL CONFIDENTIAL/PROPRIETARY
ME_FWP PCH has internal 20K PD.
(suspend power rail) <37> PCH_RTCRST# Compal Electronics, Inc.
FLASH DESCRIPTOR SECURITY OVERRIDE Title
1 2 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
LOW = ENABLE (DEFAULT) -->Pin1 & Pin3 short
1 2 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SKYLAKE PCH-H (5/9)
HIGH = DISABLE (ME can update) -->Pin2 & Pin3 short @ CMOS1 SHORT PADS~D NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW_PCH
+3.3V_RUN 8/21 KB_DET# 1 2

RC74 10K_0402_5%
1 2 GPP_C8 GPP_D16 1 2
SPT-H_PCH
RH207 100K_0402_5% UH1K RC75 10K_0402_5%
BBS_BIT0
SBIOS_TX AT29 DIMM_TYPE GPP_D14
1 2 GPP_B22/GSPI1_MOSI AL44 1 2
SIO_EXT_SCI# AR29 GPP_D9 DGPU_HOLD_RST#
RH71 10K_0402_5% GPP_B21/GSPI1_MISO AL36 RC76 10K_0402_5%
<46> SIO_EXT_SCI# 3.3V_TP_EN AV29 GPP_D10 DGPU_HOLD_RST# <18>
GPP_B20/GSPI1_CLK AL35
BC27 GPP_D11
D 1 2 3.3V_TP_EN GPP_B19/GSPI1_CS# AJ39 D
RH79 10K_0402_5% NRB_BIT BD28 GPP_D12
BD27 GPP_B18/GSPI0_MOSI AJ43 GPP_D16
1 2 NRB_BIT 11/14 GC6_FB_EN AW27 GPP_B17/GSPI0_MISO GPP_D16/ISH_UART0_CTS# AL43 +3.3V_RUN
<18> GC6_FB_EN GPU_EVENT# AR24 GPP_B16/GSPI0_CLK GPP_D15/ISH_UART0_RTS# AK44 GPP_D14
@ RH331 4.7K_0402_5%
<18> GPU_EVENT# GPP_B15/GSPI0_CS# GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C2_SCL AK45
1 2 SIO_EXT_SCI# SBIOS_TX AV44 GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C2_SDA
<46> SBIOS_TX GPP_C8 BA41 GPP_C9/UART0_TXD LCD_CBL_DET# 1 2
RH339 10K_0402_5%
HOST_SD_WP# AU44 GPP_C8/UART0_RXD RC79 10K_0402_5%
+3.3V_ALW_PCH <44> HOST_SD_WP# AV43 GPP_C11/UART0_CTS# PCH_DPC_CTRL_CLK 1 2
GPP_C10/UART0_RTS# PCH_DPC_CTRL_DATA RH220 1 22.2K_0402_5%
AU41 BC38 PCH_DPB_CTRL_CLK RH221 1 22.2K_0402_5%
LCD_CBL_DET# AT44 GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_H20/ISH_I2C0_SCL BB38 PCH_DPB_CTRL_DATA RH222 1 22.2K_0402_5%
1 2 SIO_EXT_WAKE# <30> LCD_CBL_DET# AT43 GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_H19/ISH_I2C0_SDA PCH_DPD_CTRL_CLK RH223 1 22.2K_0402_5%
RH309 10K_0402_5% AU43 GPP_C13/UART1_TXD/ISH_UART1_TXD BD38 PCH_DPD_CTRL_DATA RH224 1 22.2K_0402_5%
8/20 GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_H22/ISH_I2C1_SCL BE39 RH225 2.2K_0402_5%
1 2 GPU_EVENT# AN43 GPP_H21/ISH_I2C1_SDA
@ RH345 10K_0402_5% SIO_EXT_WAKE# AN44 GPP_C23/UART2_CTS#
<46> SIO_EXT_WAKE# LPSS_UART2_TXD AR39 GPP_C22/UART2_RTS#
1 2 LPSS_UART2_TXD LPSS_UART2_RXD AR45 GPP_C21/UART2_TXD BC22 IR_CAM_DET#
GPP_C20/UART2_RXD GPP_A23/ISH_GP5 BD18 IR_CAM_DET# <30>
RH351 49.9K_0402_1%
I2C_1_SCL AR41 GPP_A22/ISH_GP4 BE21 AUD_PWR_EN T201 @ PAD~D DIMM_TYPE 1 2
1 2 LPSS_UART2_RXD <48> I2C_1_SCL I2C_1_SDA AR44 GPP_C19/I2C1_SCL GPP_A21/ISH_GP3 BD22 KB_DET# RC329 10K_0402_5%
<48> I2C_1_SDA AR38 GPP_C18/I2C1_SDA GPP_A20/ISH_GP2 BD21 KB_DET# <48> GPP_F23 1 2
RH352 49.9K_0402_1%
<28> PCH_AAC_SMBCLK AT42 GPP_C17/I2C0_SCL GPP_A19/ISH_GP1 BB22
<28> PCH_AAC_SMBDAT CLKDET# RH214 100K_0402_5%
GPP_C16/I2C0_SDA GPP_A18/ISH_GP0 BC19 CLKDET# <41>
AM44 GPP_A17/ISH_GP7
AJ44 GPP_D4/ISH_I2C2_SDA/ISH_I2C3_SDA
GPP_D23/ISH_I2C2_SCL/ISH_I2C3_SCL
SKL-H-PCH_BGA837 11 OF 12 REV = 1.3
C C
+3.3V_ALW_PCH
+5V_ALW
CONN@
1
JUART1
@ RH311 1
8.2K_0402_5% LPSS_UART2_TXD 2 1
LPSS_UART2_RXD 3 2
4 3
2
4
BBS_BIT0 5
6 GND
GND
BOOT BIOS Destination(Bit 10) ACES_50207-00471-P01
UH1E
HIGH LPC SPT-H_PCH
LOW(DEFAULT) SPI PCH_DPC_CTRL_CLK
PCH_DPB_HPD BB3 PCH_DPC_CTRL_DATA PCH_DPC_CTRL_CLK <34>
AW4 GPP_I7/DDPC_CTRLCLK
<31> PCH_DPB_HPD PCH_DPC_HPD GPP_I0/DDPB_HPD0 BD6 PCH_DPB_CTRL_CLK PCH_DPC_CTRL_DATA <34>
AY2 GPP_I8/DDPC_CTRLDATA
<34> PCH_DPC_HPD PCH_DPD_HPD GPP_I1/DDPC_HPD1 BA5 PCH_DPB_CTRL_DATA PCH_DPB_CTRL_CLK <31>
AV4 GPP_I5/DDPB_CTRLCLK
<33> PCH_DPD_HPD GPP_I2/DDPD_HPD2 BC4 PCH_DPD_CTRL_CLK PCH_DPB_CTRL_DATA <31>
BA4 GPP_I6/DDPB_CTRLDATA
GPP_I3/DDPE_HPD3 BE5 PCH_DPD_CTRL_DATA PCH_DPD_CTRL_CLK <33>
GPP_I9/DDPD_CTRLCLK BE6 PCH_DPD_CTRL_DATA <33>
GPP_I10/DDPD_CTRLDATA
Y44
GPP_F14 V44 GPP_F23
CPU_EDP_HPD GPP_F23 W39
<29> CPU_EDP_HPD BD7 GPP_F22
GPP_I4/EDP_HPD L43
GPP_G23 L44
GPP_G22 U35
GPP_G21 R35
GPP_G20 BD36
GPP_H23
B B
A A
Title
1.0
5 4 3 2 1
5 4 3 2 1
SPT-H_PCH
+3.3V_ALW +3.3V_PUSBDSW +1.0V_PRIM UH1H
+2.8V_FHV
+1.0V_PRIM +1.0V_ALW_PCH NO CAP AA23
1 2 AA26 VCCPRIM_1P0 +3.3V_DSW
@ RH276 0_0603_5% AA28 VCCPRIM_1P0 AL22 +3.3V_1.8V_GPPA
VCCPRIM_1P0 VCCPRIM_1P0
CORE
1 2 AC23
RH254 0_1206_5% AC26 VCCPRIM_1P0 BA24 NO CAP +3.3V_PGPPBCH
+1.0V_CLK5 AC28 VCCPRIM_1P0 VCCDSW_3P3
VCCPRIM_1P0 BA31
VCCGPIO
+RTC_CELL +3.3V_PRTC +1.0V_CLK2 AE23 VCCPGPPA +3.3V_PGPPEF
+1.0V_ALW_PCH +1.0V_DSW AE26 VCCPRIM_1P0 BC42 +3.3V_PGPPG
+1.0V_DSW Y23 VCCPRIM_1P0 VCCPGPPBCH BD40 +3.3V_PHVC
1 2 0.0002A +1.0V_CLK4 Y25 VCCPRIM_1P0 VCCPGPPBCH AJ41
D 1 2 0.0454A @ RH297 0_0402_5% +1.0V_CLK1 BA29 VCCPRIM_1P0 VCCPGPPEF AL41 D
@ RH255 0_0402_5% +1.0V_CLK3 DCPDSW_1P0 VCCPGPPEF AD41
NO CAP N17 VCCPGPPG AN5
+1.0V_CLK1 NO CAP R19 VCCCLK1 VCCPRIM_3P3 +1.0V_DTS
NO CAP U20 VCCCLK3 +3.3V_RUN_ATS
1 2 0.0348A NO CAP V17 VCCCLK4 AD15 +3.3V_PRTCPRIM
@ RH256 0_0402_5% R17 VCCCLK2 VCCPRIM_1P0 AD13 +3.3V_PRTC
VCCCLK2 VCCATS BA20
K2 VCCRTCPRIM_3P3
+1.0V_CLK3 VCCCLK5 BA22
K3 VCCRTC
+1.0V_MPHY VCCCLK5 BA26 +DCPRTC
DCPRTC
0.1U_0402_25V6
1 2 0.0237A +1.0V_PRIM 1
@ RH257 0_0402_5% U21
VCCMPHY_1P0 AJ20
CH68
U23
MPHY
+3.3V_ALW_PCH +3.3V_ALW_PCHRES VCCPRIM_1P0
VCCMPHY_1P0 AJ21
+1.0V_CLK4 U25 VCCPRIM_1P0
VCCMPHY_1P0 AJ23 2
+1.0V_AMPHYPLL U26 VCCPRIM_1P0
VCCMPHY_1P0 AJ25
1 2 0.0327A 1 2 V26 VCCPRIM_1P0 +3.3V_1.8V_SPI
@ RH258 0_0402_5% @ RH279 0_0603_5% A43 VCCMPHY_1P0
B43 VCCMPHYPLL_1P0 BE41 NO CAP
+1.0V_CLK2 +1.0V_APLLEBB C44 VCCMPHYPLL_1P0 VCCSPI BE43
+3.3V_ALW_PCHRES +3.3V_1.8V_GPPA +1.0V_AAZPLL +1.0V_DUSB C45 VCCPCIE3PLL_1P0 VCCSPI BE42 +3.3V_1.8V_GPPD
1 2 0.205A NO CAP VCCPCIE3PLL_1P0 VCCSPI
V28 BC44 NO CAP
@ RH259 0_0402_5% +3.3V_1.8V_AZIO +1.0V_AUSB VCCAPLLEBB_1P0 VCCPGPPD
AC17 BA45
USB
1 2 0.0879A VCCPRIM_1P0 VCCPGPPD
AJ5 BC45
+1.0V_F24 @ RH291 0_0402_5% +3.3V_PUSBDSW VCCUSB2PLL_1P0 VCCPGPPD
NO CAP AL5 BB45
+1.8V_ALW_PCHRES VCCUSB2PLL_1P0 VCCPGPPD +3.3V_1.8V_FUSE
AN19
1 2 0.0046A VCCHDAPLL_1P0 BD3
@ RH260 0_0402_5% BA15 VCCPRIM_3P3
VCCHDA BE3
1 2 VCCPRIM_3P3
W15 BE4
+1.0V_DUSB @ RH294 0_0402_5% VCCDSW_3P3 VCCPRIM_3P3
1 2 0.533A SKL-H-PCH_BGA837 REV = 1.3 8 OF 12

@ RH286 0_0402_5% +3.3V_ALW_PCHRES +3.3V_1.8V_AZIO
C C
+2.8V_FHV
1 2 0.075A
1 2 0.0908A @ RH292 0_0402_5%
@ RH287 0_0402_5% +1.8V_ALW_PCHRES
SPT-H_PCH
+1.0V_DTS UH1J
1 2
1 2 0.0061A @ RH295 0_0402_5%
@ RH288 0_0402_5%
BD2 AR22 @ T66
VSS RSVD PAD~D
+1.0V_MPHY BD45 W13 @ T67
VSS RSVD PAD~D
PJP8 +3.3V_ALW_PCHRES +3.3V_1.8V_GPPD BD44 U13 @ T68
VSS RSVD PAD~D
2 1 2.10A BE44 @ T69
2 1 VSS P31 PAD~D
1 2 0.0395A D45 RSVD @ T70
VSS N31 PAD~D
JUMP_43X79 @ RH293 0_0402_5% A42 RSVD
+1.0V_AMPHYPLL +1.8V_ALW_PCHRES B45 VSS P27
VSS RSVD PAD~D @ T71
B44 R27
1 2 0.0248A 1 2 A4 N29
@ RH289 0_0402_5% @ RH296 0_0402_5% A3 P29
B2 VSS RSVD AN29 PAD~D @ T73
+1.0V_APLLEBB A2 R24
B1 P24
1 2 0.095A BB1
VSS AT3 PCH_XDP_PREQ#
@ RH290 0_0402_5% BC1 PREQ#
VSS AT4 PCH_XDP_PRDY# PCH_XDP_PREQ# <7>
A44 PRDY#
VSS AY5 CPU_XDP_TRST# PCH_XDP_PRDY# <7>
C1 CPU_TRST# AL2 CPU_XDP_TRST# <7>
RSVD PCH_TRIGOUT PCH_2_CPU_TRIGGER_R
D1 AK1 CPU_2_PCH_TRIGGER
RSVD PCH_TRIGIN CPU_2_PCH_TRIGGER <10>
+3.3V_ALW_PCH
+3.3V_PRTCPRIM +1.8V_RUN +1.8V_RUN_EDRAM
B SKL-H-PCH_BGA837 REV = 1.3 10 OF 12 B
1 2 0.0002A 1 2
@ RH298 0_0402_5% @ RH252 0_0603_5%
+3.3V_PHVC
+VCC_EDRAM_FUSEPRG
1 2 0.2875A
@ RH299 0_0402_5% 1 2
+3.3V_1.8V_FUSE @ RH253 0_0603_5% PCH_2_CPU_TRIGGER_R 1 2 PCH_2_CPU_TRIGGER
PCH_2_CPU_TRIGGER <10>
RH42 30_0402_5%
1 2 0.0811A
@ RH300 0_0402_5%
+3.3V_DSW
1 2 0.0811A
@ RH306 0_0402_5%
+3.3V_ALW_PCHRES +3.3V_1.8V_SPI
+3.3V_ALW
1 2
1 2 0.403A RH246 0_0603_5%
@ RH301 0_0603_5% +3.3V_M
1 2
@ RH348 0_0603_5%
+3.3V_RUN +3.3V_RUN_ATS
+1.8V_ALW_PCHRES
1 2 0.0066A 1 2
@ RH302 0_0402_5% @ RH250 0_0603_5%
+1.8V_ALW
+3.3V_ALW_PCH 1 2
+3.3V_PGPPEF @ RH247 0_0603_5%
A A
1 2 0.14107A
@ RH303 0_0402_5%
+3.3V_PGPPBCH
@ RH304
1 2 0.27262A
0_0402_5%
+3.3V_PGPPG
1 2 0.1318A Title
@ RH305 0_0402_5% PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
1.0
5 4 3 2 1
5 4 3 2 1
+1.0V_AMPHYPLL +3.3V_PUSBDSW +1.0V_MPHY +3.3V_PRTCPRIM
1U_0402_6.3VAK
1U_0402_6.3VAK
1U_0402_6.3VAK
22U_0603_6.3V6M
1U_0402_6.3VAK
0.1U_0402_25V6
1 1 1 1 1 1
@ CH31
CH267
CH34
CH47
CH37
CH67
2 2 2 2 2 2
D D
+1.0V_DUSB
+1.0V_DSW
+3.3V_PGPPEF +3.3V_1.8V_AZIO
+1.0V_ALW_PCH +VCCAUSB_VCCAAZPLL_1P0 +1.0V_AUSB
0.1U_0402_25V6
1U_0402_6.3VAK
1 1
@ CH269
1U_0402_6.3VAK
1 2 1 2 1
0.1U_0402_25V6
CH38
RH238 0_0603_5% RH239 0_0603_5% 1
22U_0805_6.3VAM
22U_0805_6.3VAM
@ CH62
CH35
2 2
1 1 2
@ CH44
@ CH45
+1.0V_AAZPLL 2
2 2 CRB 0.7
1 2
RH240 0_0603_5%
+3.3V_RUN_ATS
+3.3V_PGPPBCH
+1.0V_F24 +1.0V_CLK5
1U_0402_6.3VAK
C 1 C
0.1U_0402_25V6
1 2 1
@ CH63
CH36
@ RH241 0_0603_5%
22U_0805_6.3VAM
22U_0805_6.3VAM
2
1U_0402_6.3VAK
1 1 1 2
@ CH29
@ CH46
@ CH32
2 2 2
+3.3V_PHVC
+3.3V_PGPPG
+3.3V_PRTC
0.1U_0402_25V6
1
0.1U_0402_25V6
@ CH66
1
1U_0402_6.3VAK
0.1U_0402_25V6
1 1 @ CH64
@ CH33
@ CH65
2
2
2 2
B B
A A
Title
5 4 3 2 1
5 4 3 2 1
D D
UH1I
SPT-H_PCH
UH1LSPT-H_PCH
AC18 AR5
AN4 VSS VSS AR7
AN10 VSS VSS U15
VSS VSS C42 AB11
BE14 AL4 VSS VSS
VSS VSS D10 AB7
BE18 AE29 VSS VSS
VSS VSS D12 AB14
BE23 AE4 VSS VSS
VSS VSS D15 AB31
BE28 AE42 VSS VSS
VSS VSS D16 AB32
BE32 AF18 VSS VSS
VSS VSS D17 AB38
BE37 AF20 VSS VSS
VSS VSS D19 AB4
BE40 AF21 VSS VSS
VSS VSS D21 AB5
BE9 AF23 VSS VSS
VSS VSS D24 AC1
C10 AF25 VSS VSS
VSS VSS D25 AC20
C2 AF26 VSS VSS
VSS VSS D27 AC21
C28 AF28 VSS VSS
VSS VSS D29 AC25
C37 AF29 VSS VSS
C VSS VSS D30 AC29 C
J7 AG11 VSS VSS
VSS VSS D31 AC45
K10 AG13 VSS VSS
VSS VSS D33 AB8
K27 AG31 VSS VSS
VSS VSS D35 AD11
K33 AG32 VSS VSS
VSS VSS D36 AD14
K36 AG33 VSS VSS
VSS VSS E13 AB15
K4 AG38 VSS VSS
VSS VSS E15 AD32
K42 AG4 VSS VSS
VSS VSS E31 AD33
K43 AH1 VSS VSS
VSS VSS E33 AD36
L12 AH17 VSS VSS
VSS VSS F44 AD4
L13 AH18 VSS VSS
VSS VSS F8 AD8
L15 AH20 VSS VSS
VSS VSS G42 AE18
L4 AH21 VSS VSS
VSS VSS G9 AE20
L41 AH23 VSS VSS
VSS VSS H17 AE21
L8 AH25 VSS VSS
VSS VSS H19 AE25
M35 AH26 VSS VSS
VSS VSS H22 AE28
M42 AH28 VSS VSS
VSS VSS H24 AL10
N10 AH29 VSS VSS
VSS VSS H27 AL11
N15 AH45 VSS VSS
VSS VSS H29 AL13
N19 AJ10 VSS VSS
VSS VSS H3 AL17
N22 AJ14 VSS VSS
VSS VSS H35 AL19
N24 AJ15 VSS VSS
VSS VSS J10 AL24
N35 AJ17 VSS VSS
VSS VSS J11 AL29
N36 AJ18 VSS VSS
VSS VSS J3 AL32
N4 AJ26 VSS VSS
VSS VSS J39 AL33
N41 AJ28 VSS VSS
VSS VSS J5 AL38
N5 AJ29 VSS VSS
VSS VSS T42 AM15
P17 AJ31 VSS VSS
VSS VSS U10 AM17
P19 AJ32 VSS VSS
VSS VSS U11 AM19
P22 AJ36 VSS VSS
VSS VSS U14 AM22
P45 AK4 VSS VSS
VSS VSS U17 AM24
R10 AK42 VSS VSS
VSS VSS U18 AM27
R14 AU7 VSS VSS
B VSS VSS U28 AM29 B
R22 AV17 VSS VSS
VSS VSS U29 AM45
R29 AV24 VSS VSS
VSS VSS U31 AN11
R33 AV27 VSS VSS
VSS VSS U32 AN22
R38 AV31 VSS VSS
VSS VSS U33 AN27
R5 AV33 VSS VSS
VSS VSS U38 AN31
T1 AV6 VSS VSS
VSS VSS U4 AN39
T2 AW13 VSS VSS
VSS VSS U8 AN7
T4 AW19 VSS VSS
VSS VSS V18 AN8
Y18 AW29 VSS VSS
VSS VSS V20 AP11
Y20 AW37 VSS VSS
VSS VSS V21 AP4
Y21 AW9 VSS VSS
VSS VSS V23 AR33
Y26 AY38 VSS VSS
VSS VSS V25 AR34
Y28 AY45 VSS VSS
VSS VSS V29 AR42
Y29 B25 VSS VSS
VSS VSS V3 AR9
A18 B3 VSS VSS
VSS VSS V45 AT10
A25 B37 VSS VSS
VSS VSS W14 AT15
A32 B40 VSS VSS
VSS VSS W31 AT36
A37 B6 VSS VSS
VSS VSS W32 AT9
AA17 BA1 VSS VSS
VSS VSS W33 AU1
AA18 BB11 VSS VSS
VSS VSS W38 AU35
AA20 BB16 VSS VSS
VSS VSS W4 AU36
AA21 BB21 VSS VSS
VSS VSS W8 AU39
AA25 BB25 VSS VSS
VSS VSS Y17 AU45
AA29 BB30 VSS VSS
VSS VSS C4
AA4 BB34 VSS
AA42 VSS VSS BC2
AB10 VSS VSS BD43
VSS VSS
SKL-H-PCH_BGA837 SKL-H-PCH_BGA837
REV = 1.3 9 OF 12 REV = 1.3 12 OF 12
A A
Title
1.0
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
+3.3V_RUN
4.7K_0402_5%
4.7K_0402_5%
1
1
U8 AAC@
@ R3738
@ R3739
+3.3V_RUN CY8C4245
2 1 33 9 ADC_M 11/3
VCCD P2[7]
2
AAC@ C35 1U_0402_6.3V6K 8
2
19 P2[6] 7
D VDDD0 P2[5] D
AAC@ C31
34 6 AAC_SMBDAT 1 2 1 6 USH_SMBDAT <37,46>
VDDD1 P2[4]
0.1U_0402_25V6K
1U_0402_6.3V6K
AAC@ C32
5 FAN2_PWM_EC_AAC @ R38 0_0402_5%
35 P2[3] 4 FAN1_PWM_EC_AAC @ Q366A
1 1 VDDA P2[2]
Input
5
3 FAN2_PWM_AAC DMN66D0LDW-7_SOT363-6
P2[1] 2 FAN1_PWM_AAC
P2[0]
Output
AAC_SMBCLK 1 2 4 3
2 2 P0_7 USH_SMBCLK <37,46>
31 18 AAEN @ R39 0_0402_5%
P0[7] P3[7] AAEN <45>
30 17 @ Q366B
<30> DMIC_CLK_R P0[6] P3[6]
29 16 DMN66D0LDW-7_SOT363-6
28 P0[5] P3[5] 15
+3.3V_RUN
11/12 P0[4] P3[4]
FAN2_TACH_EC_AAC 27 14 SWV_CLK 1 2
P0[3] P3[3] PCH_AAC_SMBDAT <24>
Input FAN1_TACH_EC_AAC 26 13 SWV_IO @ R40 0_0402_5%
FAN2_TACH_FB_AAC 25 P0[2] P3[2] 12 1 2
FAN1_TACH_FB_AAC P0[1] P3[1] PCH_AAC_SMBCLK <24>
Output 24 11 @ R41 0_0402_5%
P0[0] P3[0]
AAC@ C33
0.1U_0402_25V6K
1U_0402_6.3V6K
AAC@ C34
ADC_BYPASS 44
1 1 P1[7]
43 23 11/12
P1[6] P4[3] +3.3V_RUN
1U_0402_6.3V6K
AAC@ C36 ADC_M 42 22
OA_M1 41 P1[5] P4[2] 21 AAC_SMBDAT
2 2 1 P1[4] P4[1] PAD~D @ T205
OA_OUT1 40 20 AAC_SMBCLK FAN2_PWM_D 2 1
1 P1[3] P4[0] PAD~D @ T206
560_0402_5% LTW-270US5_WHITE
OA_OUT2 39 10K_0402_5% R403
OA_M2 38 P1[2] FAN1_PWM 2 1
2 ADC_M 37 P1[1] 36 10K_0402_5% R407
P1[0] VSSA
@ R371
10 FAN2_PWM 2 1
nXRES 32 VSS1 1 10K_0402_5% @ R409
2
XRES VSS0 FAN2_TACH_FB 2 1

10K_0402_5% R405
CY8C4245AXI-483_TQFP44_10X10 FAN1_TACH_FB 2 1
2
C 10K_0402_5% R408 C
ADC_M 2 1
@ LED5
10K_0402_5% AAC@ R410

P0_7 2 1
10K_0402_5% AAC@ R413
1
+3.3V_RUN
AAC@ R27 1 2 0_0402_5% FAN2_PWM_AAC

AAC@ R28 1 2 0_0402_5% FAN1_PWM_AAC From CY8C4245AXI JP2 XDP@ ADC_M 2 1
1 10K_0402_5% AAC@ R411
FAN2_PWM @AAC@ R21 1 2 0_0402_5% FAN2_PWM_EC 2 1
FAN1_PWM FAN1_PWM_EC FAN2_PWM_EC <46> 2
To FAN Connector @AAC@ R22 1 2 0_0402_5% nXRES 3
FAN1_PWM_EC <46> 3
To CY8C4245AXI
FAN1_PWM_EC_AAC
FAN2_PWM_EC_AAC
AAC@ R25 1
AAC@ R26 1
2 0_0402_5%
2 0_0402_5%
SWV_CLK
SWV_IO
4
5
6
4
5
6
CPU FAN
SUYIN_254201MS006G291ZO JFAN1
AAC@ R29 1 2 0_0402_5% FAN2_TACH_FB_AAC 6
AAC@ R30 1 2 0_0402_5% FAN1_TACH_FB_AAC 5 G6
From CY8C4245AXI G5
4
FAN2_TACH_FB @AAC@ R12 1 2 0_0402_5% FAN1_PWM 3 4
FAN1_TACH_FB FAN2_TACH_EC <46> FAN1_TACH_FB 3
To FAN Connector @AAC@ R13 1 2 0_0402_5% 2
FAN1_TACH_EC <46> 2
+5V_RUN 1
FAN1_TACH_EC_AAC AAC@ R23 1 2 0_0402_5% 1
10U_0805_10V6K
0.1U_0402_25V6K
To CY8C4245AXI FAN2_TACH_EC_AAC AAC@ R24 1 2 0_0402_5% ACES_50273-0040N-001
1 1 CONN@
C30
C364
B
Link CIS B
AAC@ C143
1 2
1500P_0402_50V7K
2 2
OK
OA_OUT2 1 2 OA_M2
AAC@ R376 20K_0402_5%
11/12
OA_M2 1 2 1 2 1 2
R375
AAC@
1K_0402_5% C1420
AAC@
2.2U_0402_6.3V6M
OA_OUT1
AAC@ C141
AAC@ R414
1
3300P_0402_25V7K
2
10K_0402_5%
OA_M1 MXM FAN
JFAN2
@ R213 2 1 0_0603_5% 6
OA_M1 1 2 1 2 5 G6
DMIC0_R <30> D90 G5
AAC@ R373 2.2K_0402_5% C365 2.2U_0402_6.3V6M 4
AAC@ FAN2_PWM 1 2 FAN2_PWM_D 3 4
FAN2_TACH_FB 2 3
1 2
+5V_RUN
RB751S40T1G_SOD523-2 1
10U_0603_6.3V6M
0.1U_0402_25V6K
ACES_50273-0040N-001
1 1 CONN@
C370
Link CIS
C330
2 2
OK
A A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT FAN control
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
+3.3V_RUN
4.7U_0603_6.3V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
EDP_MUX_PC0 @ R100 1 2 4.7K_0402_5%
1 1 1 1 1
C784
C500
C501
C554
C502
EDP_MUX_PC1 @ R109 1 2 4.7K_0402_5%
2 2 2 2 2 EDP_IN1_AEQ# @ R140 1 2 4.7K_0402_5%
D
U630 CIS LINK OK EDP_IN2_AEQ# @ R142 1 2 4.7K_0402_5% D
21
26 VDD33 EDP_IN1_PEQ @ R127 1 2 4.7K_0402_5%
35 VDD33
49 VDD33 32 SW1_EDP_AUXP EDP_IN2_PEQ @ R133 1 2 4.7K_0402_5%
60 VDD33 OUT_AUXp_SCL 31 SW1_EDP_AUXN SW1_EDP_AUXP <30>
VDD33 OUT_AUXn_SDA SW1_EDP_AUXN <30> EDP_MUX_PI0 @ R143 1 2 4.7K_0402_5%
EDP_IN2_PEQ 51
EDP_IN1_PEQ 52 IN2_PEQ/SCL_CTL 53
EDP_IN1_AEQ# 59 IN1_PEQ/SDA_CTL I2C_CTL_EN MUX_CET C98 2 1 2.2U_0402_6.3V6M
EDP_IN2_AEQ# 58 IN1_AEQ#
IN2_AEQ# 56 EDP_MUX_PI0 EDP_MUX_PI0 @ R139 1 2 4.7K_0402_5%
PI0 38 EDP_MUX_PC0
MXM_EDP_P0 C549 1 2 0.1U_0402_10V6K MXM_EDP_P0_C 1 PC0 55 EDP_MUX_PC1 EDP_MUX_PC0 @ R136 1 2 4.7K_0402_5%
<18> MXM_EDP_P0 MXM_EDP_N0 MXM_EDP_N0_C IN1_D0p PC1
C537 1 2 0.1U_0402_10V6K 2
<18> MXM_EDP_N0 MXM_EDP_P1 MXM_EDP_P1_C IN1_D0n EDP_MUX_PC1 @ R141 1
C557 1 2 0.1U_0402_10V6K 4 2 4.7K_0402_5%
<18> MXM_EDP_P1 MXM_EDP_N1 MXM_EDP_N1_C IN1_D1p
C556 1 2 0.1U_0402_10V6K 5
<18> MXM_EDP_N1 MXM_EDP_P2 1 2 MXM_EDP_P2_C 6 IN1_D1n 48 1 2 EDP_IN1_PEQ @ R137 1 2 4.7K_0402_5%
C560 0.1U_0402_10V6K
MXM <18>
<18>
<18>
MXM_EDP_P2
MXM_EDP_N2
MXM_EDP_P3
MXM_EDP_N2
MXM_EDP_P3
C559
C564
1
1
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
MXM_EDP_N2_C
MXM_EDP_P3_C
7
9
IN1_D2p
IN1_D2n
IN1_D3p
CA_DET R3722 1M_0402_5%
EDP_IN2_PEQ @ R138 1 2 4.7K_0402_5%
MXM_EDP_N3 C562 1 2 0.1U_0402_10V6K MXM_EDP_N3_C 10 46 SW1_EDP_P0
<18> MXM_EDP_N3 IN1_D3n OUT_D0p SW1_EDP_N0 SW1_EDP_P0 <30>
45
MXM_EDP_AUXP C566 1 2 0.1U_0402_10V6K MXM_EDP_AUXP_C 28 OUT_D0n 43 SW1_EDP_P1 SW1_EDP_N0 <30>
<18> MXM_EDP_AUXP MXM_EDP_AUXN MXM_EDP_AUXN_C IN1_AUXp OUT_D1p SW1_EDP_N1 SW1_EDP_P1 <30>
C568 1 2 0.1U_0402_10V6K 27 42
<18> MXM_EDP_AUXN
23
22
IN1_AUXn
IN1_SCL
OUT_D1n
OUT2_D2p
40
39
SW1_EDP_P2
SW1_EDP_N2
SW1_EDP_N1
SW1_EDP_P2
SW1_EDP_N2
<30>
<30>
<30>
eDP
IN1_SDA OUT2_D2n
EDP_TXP0 C561 1 2 0.1U_0402_10V6K EDP_TXP0_C 11

OUT_D3p
OUT_D3n
37
36
SW1_EDP_P3
SW1_EDP_N3 SW1_EDP_P3
SW1_EDP_N3
<30>
<30>
Conn
<9> EDP_TXP0 EDP_TXN0 EDP_TXN0_C IN2_D0p
C C563 1 2 0.1U_0402_10V6K 12 C
<9> EDP_TXN0 EDP_TXP1 EDP_TXP1_C IN2_D0n
C565 1 2 0.1U_0402_10V6K 14 54
<9> EDP_TXP1 EDP_TXN1 EDP_TXN1_C IN2_D1p SW DGPU_SELECT# <30,45>
C567 1 2 0.1U_0402_10V6K 15
<9> EDP_TXN1 EDP_TXP2 EDP_TXP2_C IN2_D1n SW1_EDP_HPD
C569 1 2 0.1U_0402_10V6K 16 44
CPU <9>
<9>
<9>
EDP_TXP2
EDP_TXN2
EDP_TXP3
EDP_TXN2
EDP_TXP3
C571
C570
1
1
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
EDP_TXN2_C
EDP_TXP3_C
17
19
IN2_D2p
IN2_D2n
IN2_D3p
OUT_HPD SW1_EDP_HPD <30>
EDP_TXN3 C572 1 2 0.1U_0402_10V6K EDP_TXN3_C 20

<9> EDP_TXN3 IN2_D3n MUX_REXT
34 DGPU_SELECT#; 0: MXM ; 1: i-GPU
EDP_AUXP C558 1 2 0.1U_0402_10V6K EDP_AUXP_C 30 REXT 47 MUX_CET
<9> EDP_AUXP IN2_AUXp CEXT
2
EDP_AUXN C555 1 2 0.1U_0402_10V6K EDP_AUXN_C 29
<9> EDP_AUXN IN2_AUXn
25 R101 SW Input
24 IN2_SCL 8
IN2_SDA GND 18 4.99K_0402_1%
GND 33 H IN2
1
MXM_EDP_HPD 3 GND 41
<18> MXM_EDP_HPD CPU_EDP_HPD IN1_HPD GND 57 L (Default) IN1
13
<24> CPU_EDP_HPD IN2_HPD GND 61
Epad 50
PD
PS8331BQFN60GTR-A0_QFN60_5X9
B INy_PEQ = Programmable input equalization levels B

L: default, LEQ, compensate channel loss up to 11.5dB @ HBR2
H: HEQ, compensate channel loss up to 14.5dB @ HBR2
M: LLEQ, compensate channel loss up to 8.5dB @ HBR2
INy_AEQ# = Automatic EQ disable

L: Automatic EQ enable (default)
H: Automatic EQ disable
PI0 = Auto test enable

L: Auto test disable & input offset cancellation enable (default)
H: Auto test enable & input offset cancellation enable
M: Auto test disable & input offset cancellation disable
PC0 = AUX interception disable

L: AUX interception enable, driver configuration is set by link training (default)
H: AUX interception disable, driver output with fixed 800mV and 0dB
M: AUX interception disable, driver output with fixed 400mV and 0dB
A PC1 = Output swing adjustment A
L: default
H: +20%
M: -16.7% DELL CONFIDENTIAL/PROPRIETARY
eDP MUX (PS8331)
1.0
LA-C551P
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
Close to JEDP1
100K_0402_5%
IR Conn. 40mil
R366
Q21
@EMC@ CONN@ +BL_PWR_SRC +PWR_SRC DMP3050LVT-7_TSOT26-6 +BL_PWR_SRC
D22 JIR1
CONN@ DMIC_CLK 2 1 6
40mil
D
2
ACES_50398-04041-001 1 1 2 4 5
S
1 DMIC0 3 2 3 IR_CAM_DET# 2
1 2 +BL_PWR_SRC 3 IR_CAM_DET# <24>
100K_0402_5%
4 1
2 3 4
1U_1206_50V7
0.1U_0603_50V7K
5 1
3 4 PESD5V0U2BT_SOT23-3 5
1
C297
6 1
3
4 5 6
R422
5 6
C296
+LCDVDD 7
D 6 7 G1 8 2 D
7 8 1 2 G2 2
DMIC0_R <28>
2
8 9 AAC@ R362 1 2 0_0402_5% ACES_50228-0067N-001
9 10 +CAMERA_VDD DMIC_CLK_R <28>
AAC@ R361 0_0402_5% BL_PWR_SRC_ON
10 11 +3.3V_RUN DMIC_CLK
11/17 RF request
11 12 DMIC_CLK <44> DMIC_CLK Q22
1 2
12 13 DMN65D8LW-7_SOT323-3
0.01U_0402_50V7K
DMIC0 EMC@ C1467 100P_0402_50V8J 1
13 14 DMIC0 <44>
DMIC0 1 2
14 15 USB20_N11_R
C293
EMC@ C1468 100P_0402_50V8J 1 2 1 3
S
15 16 USB20_P11_R R423 47K_0402_5%
16 17 2
17 18 CAM_MIC_CBL_DET# <19>
R208 @EMC@ 2 1 0_0603_5% BIA_PWM
G
2
18 19 DISP_ON
19 20
20 21 LCD_CBL_DET# <24> <46> EN_INVPWR
21 22
22 23 Panel backlight power control
23 24 by EC
24 25 LCD_TST <45>
25 26 SW1_EDP_HPD <29>
26 27
27 28 SW1_EDP_AUXP_C 0.1U_0402_10V6K 2 1 C371
28 29 SW1_EDP_AUXN_C SW1_EDP_AUXP <29>
0.1U_0402_10V6K 2 1 C373 1 2
29 30 SW1_EDP_AUXN <29> PANEL_BKEN_PCH <19>
30 31 D65
31 32 SW1_EDP_N3_C 0.1U_0402_10V6K 2 1 C374 RB751VM-40TE-17_SOD323-2
32 33 SW1_EDP_P3_C SW1_EDP_N3 <29>
0.1U_0402_10V6K 2 1 C372
33 34 SW1_EDP_N2_C SW1_EDP_P3 <29>
0.1U_0402_10V6K 2 1 C376 D64
34 35 SW1_EDP_P2_C SW1_EDP_N2 <29> DISP_ON
0.1U_0402_10V6K 2 1 C375 1 2
35 36 SW1_EDP_N1_C SW1_EDP_P2 <29> MXM_PANEL_BKEN <18>
41 0.1U_0402_10V6K 2 1 C378
SW1_EDP_N1 <29>
42 G1 36 37 SW1_EDP_P1_C
100K_0402_5%
0.1U_0402_10V6K 2 1 C377 RB751VM-40TE-17_SOD323-2
SW1_EDP_P1 <29>
43 G2 37 38
1
SW1_EDP_N0_C 0.1U_0402_10V6K 2 1 C380
G3 38 39 SW1_EDP_P0_C SW1_EDP_N0 <29>
R1138
44 0.1U_0402_10V6K 2 1 C379 D69
SW1_EDP_P0 <29>
45 G4 39 40 1 2
G5 40 PANEL_BKEN_EC <45>
JEDP1 RB751VM-40TE-17_SOD323-2
2
CIS link
C OK C
+BL_PWR_SRC +LCDVDD +3.3V_RUN +LCDVDD
SW1_EDP_AUXN SW1_EDP_HPD
0.1U_0603_50V7K
0.1U_0402_25V6K
2 1 4.7K_0402_5% 2 1 R103
100K_0402_5% R339 D66
2 1 11/10 1 2
BIA_PWM_PCH <19>
C298
SW1_EDP_HPD
C249
2 1 RB751VM-40TE-17_SOD323-2
100K_0402_5% @ R222
1 2 SW1_EDP_AUXP 2 1
100K_0402_5% R336 +3.3V_RUN
C248
1 2
<29,45> DGPU_SELECT#
0.1U_0402_10V7K
Close to
JEDP1
5
D68
OE#
P
BIA_PWM 1 2 4 2
Y A MXM_BIA_PWM <18>
G
RB751VM-40TE-17_SOD323-2 U3
10K_0402_5%
TC7SH125FU_SSOP5
3
1
R1137
D71
2
1 2
BIA_PWM_EC <46>
RB751VM-40TE-17_SOD323-2
B B
Webcam PWR CTRL

+3.3V_RUN Q24
LP2301ALT1G_SOT23-3
+CAMERA_VDD LCD Power +LCDVDD
@ C396 +3.3V_ALW
S
3 1 10U_0603_6.3V6M U33
2 1 1
VOUT
0.1U_0402_25V6K
0.1U_0402_25V6K
5
VIN
10U_0603_6.3V6M
G
2
1 1 1 2
GND
C301
@ C300
C299
4
EN
1 2 3
2 2 2 @ R42 100K_0402_5% /OC
3.3V_CAM_EN# <20>
G524B1T11U_SOT23-5
EMC request change main source
to SM070003Z00 D92
RB751VM-40TE-17_SOD323-2
2 1
<19,46> ENVDD_PCH
EMC@ L10
1 2 USB20_N11_R
<20> USB20_N11
100K_0402_5%
1
4 3 USB20_P11_R 2
<20> USB20_P11 <45> LCD_VCC_TEST_EN
R3727
1
MCM1012B900F06BP_4P
3
<18> MXM_ENVDD
3
2
@EMC@ D21
PESD5V0U2BT_SOT23-3 D93
BAT54CW_SOT323-3
A A
1
Close to
JEDP1 DELL CONFIDENTIAL/PROPRIETARY
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT eDP / CAM / TS

5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
4.7U_0603_6.3V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1 1 1 1 1
C783
C495
C499
C504
C494
2 2 2 2 2
D D
U629 CIS LINK OK +3.3V_RUN
21
26 VDD33 DP1_MUX_PC0 @ R98 1 2 4.7K_0402_5%
35 VDD33
49 VDD33 32 SW2_DP_AUXP DP1_MUX_PC1 R99 1 2 4.7K_0402_5%
60 VDD33 OUT_AUXp_SCL 31 SW2_DP_AUXN SW2_DP_AUXP <43>
VDD33 OUT_AUXn_SDA SW2_DP_AUXN <43> DP1_MUX_IN1_AEQ# @ R117 1 2 4.7K_0402_5%
DP1_MUX_IN2_PEQ 51
DP1_MUX_IN1_PEQ 52 IN2_PEQ/SCL_CTL 53 DP1_MUX_IN2_AEQ# R118 1 2 4.7K_0402_5%
DP1_MUX_IN1_AEQ# 59 IN1_PEQ/SDA_CTL I2C_CTL_EN
DP1_MUX_IN2_AEQ# 58 IN1_AEQ# DP1_MUX_IN1_PEQ R119 1 2 4.7K_0402_5%
IN2_AEQ# 56 DP1_MUX_PI0
PI0 38 DP1_MUX_PC0 DP1_MUX_IN2_PEQ R120 1 2 4.7K_0402_5%
MXM_DPC_P0 C523 1 2 0.1U_0402_10V6K MXM_DPC_P0_C 1 PC0 55 DP1_MUX_PC1
<18> MXM_DPC_P0 MXM_DPC_N0 1 2 MXM_DPC_N0_C 2 IN1_D0p PC1 DP1_MUX_PI0
C525 0.1U_0402_10V6K @ R124 1 2 4.7K_0402_5%
<18> MXM_DPC_N0 MXM_DPC_P1 1 2 MXM_DPC_P1_C 4 IN1_D0n
C524 0.1U_0402_10V6K
<18> MXM_DPC_P1 MXM_DPC_N1 1 2 MXM_DPC_N1_C 5 IN1_D1p
C527 0.1U_0402_10V6K
<18> MXM_DPC_N1 MXM_DPC_P2 1 2 MXM_DPC_P2_C 6 IN1_D1n 48 DPD_CA_DET DP1_MUX_CEXT 2 1 2.2U_0402_6.3V6M
C526 0.1U_0402_10V6K C97
MXM <18>
<18>
<18>
MXM_DPC_P2
MXM_DPC_N2
MXM_DPC_P3
MXM_DPC_N2
MXM_DPC_P3
C529
C530
1
1
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
MXM_DPC_N2_C
MXM_DPC_P3_C
7
9
IN1_D2p
IN1_D2n
IN1_D3p
CA_DET DPD_CA_DET <43>
DP1_MUX_PI0 @ R123 1 2 4.7K_0402_5%
MXM_DPC_N3 C528 1 2 0.1U_0402_10V6K MXM_DPC_N3_C 10 46 SW2_DP_P0
<18> MXM_DPC_N3 IN1_D3n OUT_D0p 45 SW2_DP_N0 SW2_DP_P0 <43> DP1_MUX_PC0 @ R115 1 2 4.7K_0402_5%
MXM_DPC_AUXP 1 2 0.1U_0402_10V6K MXM_DPC_AUXP_C 28 OUT_D0n 43 SW2_DP_P1 SW2_DP_N0 <43>
C532
<18> MXM_DPC_AUXP MXM_DPC_AUXN 1 2 0.1U_0402_10V6K MXM_DPC_AUXN_C 27 IN1_AUXp OUT_D1p 42 SW2_DP_N1 SW2_DP_P1 <43> DP1_MUX_PC1
C531 @ R116 1 2 4.7K_0402_5%
<18> MXM_DPC_AUXN 23
22
IN1_AUXn
IN1_SCL
IN1_SDA
OUT_D1n
OUT2_D2p
OUT2_D2n
40
39
SW2_DP_P2
SW2_DP_N2
SW2_DP_N1
SW2_DP_P2
SW2_DP_N2
<43>
<43>
<43>
Docking DP1_MUX_IN1_PEQ R121 1 2 4.7K_0402_5%
CPU_DP1_P0 C593 1 2 0.1U_0402_10V6K CPU_DP1_P0_C 11

OUT_D3p
OUT_D3n
37
36
SW2_DP_P3
SW2_DP_N3 SW2_DP_P3
SW2_DP_N3
<43>
<43>
DP1 DP1_MUX_IN2_PEQ R122 1 2 4.7K_0402_5%
<9> CPU_DP1_P0 CPU_DP1_N0 1 2 CPU_DP1_N0_C 12 IN2_D0p
C597 0.1U_0402_10V6K
<9> CPU_DP1_N0 CPU_DP1_P1 1 2 CPU_DP1_P1_C 14 IN2_D0n 54 PBA_GPU_SEL#
C598 0.1U_0402_10V6K
<9> CPU_DP1_P1 CPU_DP1_N1 1 2 CPU_DP1_N1_C 15 IN2_D1p SW PBA_GPU_SEL# <45>
C626 0.1U_0402_10V6K
<9> CPU_DP1_N1 CPU_DP1_P2 1 2 CPU_DP1_P2_C 16 IN2_D1n 44 SW2_DP_HPD
C628 0.1U_0402_10V6K
C CPU <9>
<9>
<9>
CPU_DP1_P2
CPU_DP1_N2
CPU_DP1_P3
CPU_DP1_N2
CPU_DP1_P3
C629
C586
1
1
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
CPU_DP1_N2_C
CPU_DP1_P3_C
17
19
IN2_D2p
IN2_D2n
IN2_D3p
OUT_HPD SW2_DP_HPD <43>
PBA_GPU_SEL#; 0: MXM ; 1: i-GPU
C
CPU_DP1_N3 C584 1 2 0.1U_0402_10V6K CPU_DP1_N3_C 20
<9> CPU_DP1_N3 IN2_D3n 34 DP1_MUX_REXT
CPU_DP1_AUXP 1 2 0.1U_0402_10V6K CPU_DP1_AUXP_C 30 REXT 47 DP1_MUX_CEXT
<9> CPU_DP1_AUXP
C591
IN2_AUXp CEXT SW Input
2
CPU_DP1_AUXN C588 1 2 0.1U_0402_10V6K CPU_DP1_AUXN_C 29
<9> CPU_DP1_AUXN PCH_DPB_CTRL_CLK 25 IN2_AUXn
<24> PCH_DPB_CTRL_CLK PCH_DPB_CTRL_DATA IN2_SCL
R96 H IN2
24 8 4.99K_0402_1%
<24> PCH_DPB_CTRL_DATA IN2_SDA GND 18
GND L (Default) IN1
33
1
MXM_DPC_HPD 3 GND 41
<18> MXM_DPC_HPD PCH_DPB_HPD 13 IN1_HPD GND 57
<24> PCH_DPB_HPD IN2_HPD GND 61
Epad 50
PD
INy_PEQ = Programmable input equalization levels

+3.3V_RUN M: LLEQ, compensate channel loss up to 8.5dB @ HBR2
DOCK DPD (PORT1) DDC-before 11/11
PS8331 DDC between PS8331/PS8338, do not need pull up.
1
4.7K_0402_5%
@R2195
+3.3V_RUN H: Automatic EQ disable
2
6
B @ Q365A
L: Auto test disable & input offset cancellation enable (default) B
+5V_RUN +3.3V_RUN H: Auto test enable & input offset cancellation enable
DPD_CA_DET_Q 2 M: Auto test disable & input offset cancellation disable
DMN66D0LDW-7_SOT363-6
1
3
6

1
1
Q343B
Q343A
100K_0402_5%
100K_0402_5%
5 2 L: AUX interception enable, driver configuration is set by link training (default)

R721
R722
4
SW2_DP_AUXP
2
DPD_CA_DET_Q +3.3V_RUN
3
PC1 = Output swing adjustment

4.7K_0402_5%
L: default
Q347B
@R2196
1 2 MXM_DPC_AUXP 5 H: +20%
R129 4.7K_0402_5% M: -16.7%
4
2
6
1 2 MXM_DPC_AUXN
Q347A
R132 4.7K_0402_5%
3
DPD_CA_DET
2
@ Q365B
1
5
4
A SW2_DP_AUXN A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, MXM/CPU MUX(PS8331)
LA-C551P 1.0

5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
CV62 CV90 close to pin30 &57 +3.3V_RUN
CV66,CV69,CV70 close to pin5,21,51
1 2 DP1_DEMUX_CFG0
Dock has high priority when both ports plugged
0.01U_0402_16V7K
0.01U_0402_16V7K
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
RV42 4.7K_0402_5%
1 2 DP1_DEMUX_SW
1
@ RV43 4.7K_0402_5% UV2
DP1_DEMUX_PI0
CV27
CV30
CV28
CV29
CV31
1 2
@ RV44 4.7K_0402_5% 5
2
21 VDD33 50 SW3_DP1_P0
30 VDD33 OUT1_D0p 49 SW3_DP1_N0 SW3_DP1_P0 <43>
D 51 VDD33 OUT1_D0n SW3_DP1_N0 <43> D
57 VDD33 47 SW3_DP1_P1
1 2 MID1_CA_DET VDD33 OUT1_D1p 46 SW3_DP1_N1 SW3_DP1_P1 <43>
RV28
1 2
1M_0402_5%
DPC_CA_DET
<18> MXM_DPA_P0
MXM_DPA_P0 C545 1 2 0.1U_0402_10V6K MXM_DPA_P0_C 6
IN_D0p
OUT1_D1n
OUT1_D2p
45 SW3_DP1_P2
SW3_DP1_N1
SW3_DP1_P2
<43>
<43>
Docking port2
RV45 1M_0402_5% MXM_DPA_N0 C540 1 2 0.1U_0402_10V6K MXM_DPA_N0_C 7 44 SW3_DP1_N2
<18> MXM_DPA_N0 IN_D0n OUT1_D2n SW3_DP1_N2 <43>
MXM_DPA_P1 C551 1 2 0.1U_0402_10V6K MXM_DPA_P1_C 9 42 SW3_DP1_P3
<18> MXM_DPA_P1 MXM_DPA_N1 MXM_DPA_N1_C IN_D1p OUT1_D3p SW3_DP1_N3 SW3_DP1_P3 <43>
C550 1 2 0.1U_0402_10V6K 10 41
<18> MXM_DPA_N1 IN_D1n OUT1_D3n SW3_DP1_N3 <43>
MXM <18>
<18>
MXM_DPA_P2
MXM_DPA_N2
MXM_DPA_P2
MXM_DPA_N2
C573
C553
1
1
2 0.1U_0402_10V6K
2 0.1U_0402_10V6K
MXM_DPA_P2_C
MXM_DPA_N2_C
12
13 IN_D2p
IN_D2n OUT2_D0p
40
SW3_DP2_P0 <34>
39
MXM_DPA_P3 C577 1 2 0.1U_0402_10V6K MXM_DPA_P3_C 15 OUT2_D0n SW3_DP2_N0 <34>
<18> MXM_DPA_P3 MXM_DPA_N3 MXM_DPA_N3_C IN_D3p
C575 1 2 0.1U_0402_10V6K 16 37
<18> MXM_DPA_N3 IN_D3n OUT2_D1p SW3_DP2_P1 <34>
36
+3.3V_RUN OUT2_D1n SW3_DP2_N1 <34>
DPC_CA_DET_IN 4
IN_CA_DET
OUT2_D2p
OUT2_D2n
35
34 SW3_DP2_P2
SW3_DP2_N2
<34>
<34>
MUX
3
<18> MXM_DPA_HPD 2 IN_HPD 32
I2C_CTL_EN OUT2_D3p SW3_DP2_P3 <34>
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
DP1_DEMUX_PI1 1 31
Pl1/SCL_CTL OUT2_D3n SW3_DP2_N3 <34>
1
DP1_DEMUX_PI0 60
Pl0/SDA_CTL
RV29
@ RV30
@ RV31
@ RV32
@ RV33
@ RV34
26 SW3_DP1_AUXP
22 OUT1_AUXp_SCL 27 SW3_DP1_AUXN SW3_DP1_AUXP <43>
IN_DDC_SCL OUT1_AUXn_SDA SW3_DP1_AUXN <43>
23
2
2
DP1_DEMUX_PI1 MXM_DPA_AUXP C1438 1 2 0.1U_0402_10V6K MXM_DPA_AUXP_C 24 IN_DDC_SDA 28
<18> MXM_DPA_AUXP MXM_DPA_AUXN MXM_DPA_AUXN_C IN_AUXp OUT2_AUXp_SCL SW3_DP2_AUXP <34>
C1437 1 2 0.1U_0402_10V6K 25 29
DP1_DEMUX_PC10 <18> MXM_DPA_AUXN IN_AUXn OUT2_AUXn_SDA SW3_DP2_AUXN <34>
DP1_DEMUX_CFG0 59 43 DPC_CA_DET
DP1_DEMUX_PC11 CFG0 OUT1_CA_DET SW3_DP1_HPD DPC_CA_DET <43>
58 48
DP1_DEMUX_PC10 CFG1 OUT1_HPD SW3_DP1_HPD <43>
56
DP1_DEMUX_PC20 DP1_DEMUX_PC11 55 PC10 33 MID1_CA_DET
DP1_DEMUX_PC20 PC11 OUT2_CA_DET MID1_CA_DET <34,44>
54 38
DP1_DEMUX_PC21 DP1_DEMUX_PC21 PC20 OUT2_HPD SW3_DP2_HPD <34>
53
PC21 18 DP1_DEMUX_SW
DP1_DEMUX_PEQ 11 SW 8 DP1_DEMUX_PEQ
GND PEQ
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
19 14
GND PD
1
1
52 17
GND CEXT
RV35
RV36
RV38
RV37
RV39
RV40
61 20
PAD(GND) REXT
2.2U_0402_6.3V6M
1
4.99K_0402_1%
C PS8338BQFN60GTR-A0_QFN60_5X9 C
1
@
RV41
2
CV42
2
2
Port switching control or priority configuration. Internal pull down ~150KΩ, 3.3V I/O
For Control Switching Mode (CFG0 = L):
SW = L: Port1 is selected (default) H L
SW = H: Port2 is selected
For Automatic Switching Mode (CFG0 = H): (By OUT1_HPD and OUT2_HPD)
CFG0 V
SW = L: Port1 has higher priority when both ports are plugged (default)
SW = H: Port2 has higher priority when both ports are plugged SW V
+3.3V_RUN +3.3V_RUN
DOCK DPC (PORT2) 11/11
DDC DDC between PS8331/PS8338, do not need pull up.
4.7K_0402_5%
4.7K_0402_5%
1
1
+5V_RUN
@R3737
R2194
100K_0402_5%
2
1
+3.3V_RUN
R2189
6
6
100K_0402_5%
@ Q364A
B B
Q355A
2
1
DPC_CA_DET_Q 2 DPC_CA_DET_Q 2
R2197
1
Q353B
2
5 4
6
MXM_DPA_AUXP SW3_DP1_AUXP
+3.3V_RUN +3.3V_RUN
Q353A
DPC_CA_DET_IN 2
1
4.7K_0402_5%
4.7K_0402_5%
@R3736
R2198
1
0.01U_0402_16V7K
1
C1344
2
2
3
3
@ Q364B
Q355B
5 5
4
4
MXM_DPA_AUXN SW3_DP1_AUXN
A A
DP DeMUX (PS8338)
LA-C551P 1.0

5 4 3 2 1
2 1
+3.3V_RUN
4.7U_0603_6.3V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1 1 1 1 1
C786
C506
C507
C508
C509
2 2 2 2 2
U636 CIS LINK OK +3.3V_RUN

21
26 VDD33 DP3_MUX_PC0 @ R105 1 2 4.7K_0402_5%
35 VDD33
49 VDD33 32 SW5_DP_AUXP DP3_MUX_PC1 @ R107 1 2 4.7K_0402_5%
VDD33 OUT_AUXp_SCL SW5_DP_AUXN SW5_DP_AUXP <44>
60 31
VDD33 OUT_AUXn_SDA SW5_DP_AUXN <44> DP3_MUX_IN1_AEQ# @ R159 1 2 4.7K_0402_5%
DP3_MUX_IN2_PEQ 51
DP3_MUX_IN1_PEQ 52 IN2_PEQ/SCL_CTL 53 DP3_MUX_IN2_AEQ# @ R161 1 2 4.7K_0402_5%
DP3_MUX_IN2_AEQ# 58 IN1_AEQ# DP3_MUX_IN1_PEQ R153 1 2 4.7K_0402_5%
IN2_AEQ# 56 DP3_MUX_PI0
PI0 38 DP3_MUX_PC0 DP3_MUX_IN2_PEQ R154 1 2 4.7K_0402_5%
MXM_DPB_P0 C587 1 2 0.1U_0402_10V6K MXM_DPB_P0_C 1 PC0 55 DP3_MUX_PC1
<18> MXM_DPB_P0 MXM_DPB_N0 MXM_DPB_N0_C IN1_D0p PC1 DP3_MUX_PI0
C585 1 2 0.1U_0402_10V6K 2 @ R162 1 2 4.7K_0402_5%
<18> MXM_DPB_N0 MXM_DPB_P1 MXM_DPB_P1_C IN1_D0n
C590 1 2 0.1U_0402_10V6K 4
<18> MXM_DPB_P1 MXM_DPB_N1 MXM_DPB_N1_C IN1_D1p
C589 1 2 0.1U_0402_10V6K 5
<18> MXM_DPB_N1 MXM_DPB_P2 MXM_DPB_P2_C IN1_D1n MID2_CA_DET
C594 1 2 0.1U_0402_10V6K 6 48
B
MXM <18>
<18>
<18>
MXM_DPB_P2
MXM_DPB_N2
MXM_DPB_P3
MXM_DPB_N2
MXM_DPB_P3
C592
C596
1
1
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
MXM_DPB_N2_C
MXM_DPB_P3_C
7
9
IN1_D2p
IN1_D2n
CA_DET MID2_CA_DET <44> B
MXM_DPB_N3 C595 1 2 0.1U_0402_10V6K MXM_DPB_N3_C 10 IN1_D3p 46 SW5_DP_P0 DP3_MUX_CEXT C100 2 1 2.2U_0402_6.3V6M

<18> MXM_DPB_N3 IN1_D3n OUT_D0p SW5_DP_N0 SW5_DP_P0 <44>
45
MXM_DPB_AUXP C601 1 2 0.1U_0402_10V6K MXM_DPB_AUXP_C 28 OUT_D0n 43 SW5_DP_P1 SW5_DP_N0 <44> DP3_MUX_PI0 @ R158 1 2 4.7K_0402_5%
<18> MXM_DPB_AUXP MXM_DPB_AUXN MXM_DPB_AUXN_C IN1_AUXp OUT_D1p SW5_DP_N1 SW5_DP_P1 <44>
C627 1 2 0.1U_0402_10V6K 27 42
<18> MXM_DPB_AUXN
23
22
IN1_AUXn
IN1_SCL
OUT_D1n
OUT2_D2p
40
39
SW5_DP_P2
SW5_DP_N2
SW5_DP_N1
SW5_DP_P2
SW5_DP_N2
<44>
<44>
<44>
mDP DP3_MUX_PC0 @ R155 1 2 4.7K_0402_5%
IN1_SDA OUT2_D2n 37 SW5_DP_P3 DP3_MUX_PC1 @ R160 1 2 4.7K_0402_5%
OUT_D3p 36 SW5_DP_N3 SW5_DP_P3 <44>
CPU_DP3_P0 C1448 1 2 0.1U_0402_10V6K CPU_DP3_P0_C 11 OUT_D3n SW5_DP_N3 <44> DP3_MUX_IN1_PEQ R156 1 2 4.7K_0402_5%
<9> CPU_DP3_P0 CPU_DP3_N0 CPU_DP3_N0_C IN2_D0p
C1450 1 2 0.1U_0402_10V6K 12
<9> CPU_DP3_N0 CPU_DP3_P1 CPU_DP3_P1_C IN2_D0n DP2_GPU_SEL# DP3_MUX_IN2_PEQ
C1453 1 2 0.1U_0402_10V6K 14 54 R157 1 2 4.7K_0402_5%
<9> CPU_DP3_P1 CPU_DP3_N1 CPU_DP3_N1_C IN2_D1p SW DP2_GPU_SEL# <45>
C1451 1 2 0.1U_0402_10V6K 15
<9> CPU_DP3_N1 CPU_DP3_P2 CPU_DP3_P2_C IN2_D1n SW5_DP_HPD MID2_CA_DET
C1449 1 2 0.1U_0402_10V6K 16 44 RV48 1 2 1M_0402_5%
CPU <9>
<9>
<9>
CPU_DP3_P2
CPU_DP3_N2
CPU_DP3_P3
CPU_DP3_N2
CPU_DP3_P3
C1454
C1455
1
1
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
CPU_DP3_N2_C
CPU_DP3_P3_C
17
19
IN2_D2p
IN2_D2n
IN2_D3p

<9> CPU_DP3_N3 IN2_D3n DP3_MUX_REXT
34
CPU_DP3_AUXP C1447 1 2 0.1U_0402_10V6K CPU_DP3_AUXP_C 30 REXT 47 DP3_MUX_CEXT
<9> CPU_DP3_AUXP IN2_AUXp CEXT
2
<9> CPU_DP3_AUXN PCH_DPD_CTRL_CLK IN2_AUXn
25 R106 DP2_GPU_SEL#; 0: MXM ; 1: i-GPU
<24> PCH_DPD_CTRL_CLK PCH_DPD_CTRL_DATA IN2_SCL
24 8 4.99K_0402_1%
<24> PCH_DPD_CTRL_DATA IN2_SDA GND 18
GND 33
SW Input
1
MXM_DPB_HPD 3 GND 41
<18> MXM_DPB_HPD PCH_DPD_HPD 13 IN1_HPD GND 57
<24> PCH_DPD_HPD IN2_HPD GND 61 H IN2
Epad 50
PD L (Default) IN1
11/11 INy_PEQ = Programmable input equalization levels

Vendor review, MXM card need add DDC pull up
+3.3V_RUN M: LLEQ, compensate channel loss up to 8.5dB @ HBR2

+5V_RUN +3.3V_RUN L: Automatic EQ enable (default)
3
6

1
1
Q369B
Q369A
100K_0402_5%
100K_0402_5%
5 2 H: Auto test enable & input offset cancellation enable

M: Auto test disable & input offset cancellation disable
R3746
R3744
4
MID2_CA_DET_Q
3

Q367B
1 2 MXM_DPB_AUXP 5 M: AUX interception disable, driver output with fixed 400mV and 0dB
R3745 4.7K_0402_5%
4
1 2 MXM_DPB_AUXN
Q367A
R3747 4.7K_0402_5%
2 MID2_CA_DET L: default
H: +20%
M: -16.7%
1
A A
PROPRIETARY NOTE:
Title
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
DOCUMENT MAY NOT
HDMI CONN
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. 1.0
2 TO ANY THIRD 1
5 4 3 2 1
+3.3V_RUN
+3.3V_RUN
D DP2_MUX_PC0 D
@ R102 1 2 4.7K_0402_5%
4.7U_0603_6.3V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
DP2_MUX_PC1 @ R104 1 2 4.7K_0402_5%
1 1 1 1 1
DP2_MUX_IN1_AEQ#
C785
C496
C503
C505
C497
@ R149 1 2 4.7K_0402_5%
2 2 2 2 2 DP2_MUX_IN2_AEQ# @ R151 1 2 4.7K_0402_5%
U631 CIS LINK OK DP2_MUX_IN1_PEQ @ R125 1 2 4.7K_0402_5%

21
26 VDD33 DP2_MUX_IN2_PEQ @ R126 1 2 4.7K_0402_5%
35 VDD33
49 VDD33 32 SW4_DP_AUXP DP2_MUX_PI0 @ R152 1 2 4.7K_0402_5%
VDD33 OUT_AUXp_SCL SW4_DP_AUXN SW4_DP_AUXP <44>
60 31
VDD33 OUT_AUXn_SDA SW4_DP_AUXN <44> SW4_DP_AUXN
11/11 R381 1 2 100K_0402_5%
DP2_MUX_IN2_PEQ 51
DP2_MUX_IN1_PEQ 52 IN2_PEQ/SCL_CTL 53
DP2_MUX_IN2_AEQ# 58 IN1_AEQ#
IN2_AEQ# 56 DP2_MUX_PI0 DP2_MUX_CEXT C99 2 1 2.2U_0402_6.3V6M
PI0 38 DP2_MUX_PC0
SW3_DP2_P0 C1460 1 2 0.1U_0402_10V6K SW3_DP2_P0_C 1 PC0 55 DP2_MUX_PC1 DP2_MUX_PI0 @ R148 1 2 4.7K_0402_5%
<32> SW3_DP2_P0 SW3_DP2_N0 SW3_DP2_N0_C IN1_D0p PC1
C1463 1 2 0.1U_0402_10V6K 2
<32> SW3_DP2_N0 SW3_DP2_P1 SW3_DP2_P1_C IN1_D0n DP2_MUX_PC0
C1457 1 2 0.1U_0402_10V6K 4 @ R128 1 2 4.7K_0402_5%
<32> SW3_DP2_P1 SW3_DP2_N1 SW3_DP2_N1_C IN1_D1p
C1458 1 2 0.1U_0402_10V6K 5
<32> SW3_DP2_N1 SW3_DP2_P2 SW3_DP2_P2_C IN1_D1n MID1_CA_DET DP2_MUX_PC1
C1461 1 2 0.1U_0402_10V6K 6 48 @ R150 1 2 4.7K_0402_5%
MUX <32>
<32>
<32>
SW3_DP2_P2
SW3_DP2_N2
SW3_DP2_P3
SW3_DP2_N2
SW3_DP2_P3
C1464
C1462
1
1
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
SW3_DP2_N2_C
SW3_DP2_P3_C
7
9
IN1_D2p
IN1_D2n
IN1_D3p
CA_DET MID1_CA_DET <32,44>
DP2_MUX_IN1_PEQ @ R146 1 2 4.7K_0402_5%
SW3_DP2_N3 C1459 1 2 0.1U_0402_10V6K SW3_DP2_N3_C 10 46
<32> SW3_DP2_N3 IN1_D3n OUT_D0p SW4_DP_P0 <44> DP2_MUX_IN2_PEQ
45 @ R147 1 2 4.7K_0402_5%
SW3_DP2_AUXP 28 OUT_D0n 43 SW4_DP_N0 <44>
<32> SW3_DP2_AUXP SW3_DP2_AUXN IN1_AUXp OUT_D1p SW4_DP_P1 <44>
27 42
<32> SW3_DP2_AUXN
23
22
IN1_AUXn
IN1_SCL
IN1_SDA
OUT_D1n
OUT2_D2p
OUT2_D2n
40
39
SW4_DP_N1
SW4_DP_P2
SW4_DP_N2
<44>
<44>
<44>
TBT/HDMI
37
OUT_D3p 36 SW4_DP_P3 <44>
CPU_DP2_P0 C574 1 2 0.1U_0402_10V6K CPU_DP2_P0_C 11 OUT_D3n SW4_DP_N3 <44>
<9> CPU_DP2_P0 CPU_DP2_N0 CPU_DP2_N0_C IN2_D0p
C576 1 2 0.1U_0402_10V6K 12
<9> CPU_DP2_N0 CPU_DP2_P1 CPU_DP2_P1_C IN2_D0n DP1_GPU_SEL#
C578 1 2 0.1U_0402_10V6K 14 54
<9> CPU_DP2_P1 CPU_DP2_N1 CPU_DP2_N1_C IN2_D1p SW DP1_GPU_SEL# <45>
C C580 1 2 0.1U_0402_10V6K 15 C
<9> CPU_DP2_N1 CPU_DP2_P2 CPU_DP2_P2_C IN2_D1n SW4_DP_HPD
C581 1 2 0.1U_0402_10V6K 16 44
CPU <9>
<9>
<9>
CPU_DP2_P2
CPU_DP2_N2
CPU_DP2_P3
CPU_DP2_N2
CPU_DP2_P3
C583
C546
1
1
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
CPU_DP2_N2_C
CPU_DP2_P3_C
17
19
IN2_D2p
IN2_D2n
IN2_D3p

<9> CPU_DP2_N3 IN2_D3n DP2_MUX_REXT
34 DP1_GPU_SEL#; 0: MXM ; 1: i-GPU
CPU_DP2_AUXP C552 1 2 0.1U_0402_10V6K CPU_DP2_AUXP_C 30 REXT 47 DP2_MUX_CEXT
<9> CPU_DP2_AUXP IN2_AUXp CEXT
2
<9> CPU_DP2_AUXN PCH_DPC_CTRL_CLK IN2_AUXn
25 R97 SW Input
<24> PCH_DPC_CTRL_CLK PCH_DPC_CTRL_DATA IN2_SCL
24 8 4.99K_0402_1%
<24> PCH_DPC_CTRL_DATA IN2_SDA GND 18
GND 33 H IN2
1
SW3_DP2_HPD 3 GND 41
<32> SW3_DP2_HPD PCH_DPC_HPD IN1_HPD GND 57 L (Default) IN1
13
<24> PCH_DPC_HPD IN2_HPD GND 61
Epad 50
PD
INy_PEQ = Programmable input equalization levels

M: LLEQ, compensate channel loss up to 8.5dB @ HBR2


H: Auto test enable & input offset cancellation enable
B
M: Auto test disable & input offset cancellation disable B


L: default
H: +20%
M: -16.7%
A A
VGA CONN
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Size Document Number Rev
LA-C551P 1.0

5 4 3 2 1
5 4 3 2 1
+3.3V_LAN
1 2 TP_LAN_JTAG_TMS
@ R545 10K_0402_5%
1 2 TP_LAN_JTAG_TCK
@ R546 10K_0402_5% U31
+3.3V_LAN 48 13 LAN_MDIP0
<21> CLKREQ_PCIE#3 36 CLK_REQ_N MDI_PLUS0 14 LAN_MDIN0
<22> PLTRST_LAN# PE_RST_N MDI_MINUS0
2 1 LAN_WAKE#_R CLK_PCIE_P3 44 17 LAN_MDIP1 +0.9V_LAN
<21> CLK_PCIE_P3 CLK_PCIE_N3 PE_CLKP MDI_PLUS1 LAN_MDIN1
D @ R559 4.7K_0402_5% 45 18 D
<21> CLK_PCIE_N3 PE_CLKN MDI_MINUS1
2 1 PCIE_PRX_C_DTX_P4
PCIE
L29
MDI
<20> PCIE_PRX_DTX_P4 LAN_MDIP2 +REGCTL_PNP10
C458 0.1U_0402_10V7K 38 20 1 2
2 1 PCIE_PRX_C_DTX_N4 39 PETp MDI_PLUS2 21 LAN_MDIN2 4.7UH_BRC2012T4R7MD_20%
<20> PCIE_PRX_DTX_N4 PETn MDI_MINUS2
10U_0603_6.3V6M
0.1U_0402_10V7K
C459 0.1U_0402_10V7K Idc
1 2 PCIE_PTX_C_DRX_P4 41 23 LAN_MDIP3
1 1
+3.3V_LAN <20> PCIE_PTX_DRX_P4 PERp MDI_PLUS3 LAN_MDIN3 min=500mA
C462
C463
C460 0.1U_0402_10V7K 42 24
1 2 PCIE_PTX_C_DRX_N4 PERn MDI_MINUS3 @ R558 1 2 0_0402_5% DCR=100m
<20> PCIE_PTX_DRX_N4
C461 0.1U_0402_10V7K ohm
VCT_LAN_R1 2 2
10K_0402_5%
28 6 @ R553 2 1 4.7K_0402_5% +3.3V_LAN
<23> SML0_SMBCLK SMB_CLK SVR_EN_N
1
@ 31
SMBUS
<23> SML0_SMBDATA SMB_DATA +RSVD_VCC3P3_2
R549
SMBus Device Address 0xC8 1 R554 2 1 4.7K_0402_5%
RSVD1_VCC3P3
@ R556 1 2 0_0402_5% LAN_WAKE#_R 2 5
<23,46> LAN_WAKE# LAN_DISABLE#_R 3 LANWAKE_N VDD3P3_IN
2
<45> LAN_DISABLE#_R LAN_DISABLE_N 4 +3.3V_LAN_OUT @ R209 1 2 0_0603_1%
VDD3P3_4 +3.3V_LAN
LAN_DISABLE#_R
1U_0603_10V7K
@ R555 1 2 0_0402_5% 15 1 Place C462, C463 and L29 close
<23> PM_LANPHY_ENABLE LOM_ACTLED_YEL# VDD3P3_15
26 19
LOM_SPD100LED_ORG# LED0 VDD3P3_19 to U31
C464
27 29
LED1 VDD3P3_29
10K_0402_5%
LOM_SPD10LED_GRN# 25
LED
LED2
1
2
@ R557
47
VDD0P9_47 +0.9V_LAN
46
TP_LAN_JTAG_TDI 32 VDD0P9_46 37 +0.9V_LAN +3.3V_LAN
@ T142 PAD~D TP_LAN_JTAG_TDO 34 JTAG_TDI VDD0P9_37
2
@ T143 PAD~D TP_LAN_JTAG_TMS 33 JTAG_TDO 43
JTAG
TP_LAN_JTAG_TCK 35 JTAG_TMS VDD0P9_43
JTAG_TCK
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
22U_0805_6.3V6M
22U_0805_6.3V6M
11
VDD0P9_11
0.1U_0402_10V7K
1 1 1 1 1
C1177
XTALO 9 40 1 1
XTAL_OUT VDD0P9_40
C466
C467
C468
C469
C1178
XTALI 10 22
XTAL_IN VDD0P9_22
C1418
16
VDD0P9_16 8 2 2 2 2 2
LAN_TEST_EN 30 VDD0P9_8 2 2
XTALO_R 1 2 XTALO TEST_EN
@ R1144 0_0402_5% RES_BIAS 12 7 +REGCTL_PNP10
RBIAS CTRL0P9
C C
1K_0402_1%
3.01K_0402_1%
XTALI 49
VSS_EPAD
1
R561
R562
WGI219LM-QREF-A0_QFN48_6X6 Note: +1.0V_LAN will work at 0.95V to Place C1178 close to
PN change to SA000081G1L
Y3 1.15V pin5
25MHZ_18PF_X3G025000DI1H-H
2
3 1
OUT IN
22P_0402_50V8J
27P_0402_50V8J
4 2
GND GND
1 1
C470
C471
2 2
+3.3V_LAN LAN ANALOG

SWITCH
0.1U_0402_25V6K
0.1U_0402_25V6K
0.1U_0402_25V6K
B 1 1 1 B
C472
C473
C474
Layout Notice : Place 2 2 2

bead as close PI3L720
as possible
39
30
21
14
8
4
1
U32
VDD
VDD
VDD
VDD
VDD
VDD
VDD
38 SW1_LAN0_MDIN3
B0+ SW1_LAN0_MDIP3 SW1_LAN0_MDIN3 <36> +3.3V_LAN
37
LAN_MDIN3 LAN_MDIN3_L B0- SW1_LAN0_MDIP3 <36>
1 2 2 @ C478
R63 0_0603_5% A0+ 34 SW1_LAN0_MDIN2 1 2
LAN_MDIP3 1 2 LAN_MDIP3_L 3 B1+ 33 SW1_LAN0_MDIP2 SW1_LAN0_MDIN2 <36>
R64 0_0603_5% A0- B1- SW1_LAN0_MDIP2 <36> 0.1U_0402_10V7K
29 SW1_LAN0_MDIN1
LAN_MDIN2 LAN_MDIN2_L B2+ SW1_LAN0_MDIP1 SW1_LAN0_MDIN1 <36> U15
1 2 6 28
A1+ B2- SW1_LAN0_MDIP1 <36>
5
R65 0_0603_5% SN74AHC1G08DCKR_SC70-5
LAN_MDIP2 1 2 LAN_MDIP2_L 7 25 SW1_LAN0_MDIN0 LOM_SPD100LED_ORG# 1
P
A1- B3+ SW1_LAN0_MDIP0 SW1_LAN0_MDIN0 <36> IN1
R66 0_0603_5% 24 4
B3- SW1_LAN0_MDIP0 <36> LOM_SPD10LED_GRN# O WLAN_DISBL# <45>
Q325A 2
IN2
G
LAN_MDIN1 1 2 LAN_MDIN1_L 9 17 LAN_ACTLED_YEL# DMN66D0LDW-7_SOT363-6
R67 0_0603_5% A2+ LEDB0 18 LED_100_ORG# LAN_ACTLED_YEL# 1 6
LAN_ACTLED_YEL#_Q <36>
3
LAN_MDIP1 1 2 LAN_MDIP1_L 10 LEDB1 41 LED_10_GRN#
R68 0_0603_5% A2- LEDB2
36 SW1_LAN1_MDIN3 +3.3V_LAN +3.3V_LAN
SW1_LAN1_MDIN3 <43>
2
LAN_MDIN0 1 2 LAN_MDIN0_L 11 C0+ 35 SW1_LAN1_MDIP3
A3+ C0- SW1_LAN1_MDIP3 <43> SYS_LED_MASK#
R69 0_0603_5%
SYS_LED_MASK# <45,47>
1
LAN_MDIP0 1 2 LAN_MDIP0_L 12 32 SW1_LAN1_MDIN2
R70 0_0603_5% A3- C1+ 31 SW1_LAN1_MDIP2 SW1_LAN1_MDIN2 <43> R377 R378
C1- SW1_LAN1_MDIP2 <43>
1M_0402_5% 1M_0402_5% Q327
13 27 SW1_LAN1_MDIN1
<45> DOCKED SEL C2+ SW1_LAN1_MDIP1 SW1_LAN1_MDIN1 <43> DMN65D8LW-7_SOT323-3
26 Q325B
SW1_LAN1_MDIP1 <43> TO
2
C2- DMN66D0LDW-7_SOT363-6
LOM_ACTLED_YEL# SW1_LAN1_MDIN0 DOCK LED_100_ORG# LED_10_GRN#
D
15 23 4 3 3 1
LOM_SPD100LED_ORG# LEDA0 C3+ SW1_LAN1_MDIP0 SW1_LAN1_MDIN0 <43> LED_100_ORG#_Q <36> LED_10_GRN#_Q <36>
16 22
LOM_SPD10LED_GRN# LEDA1 C3- SW1_LAN1_MDIP0 <43>
42
LEDA2 19 DOCK_LOM_ACTLED_YEL#
G
A DOCK_LOM_ACTLED_YEL# <43> A
2
5 LEDC0 20 DOCK_LOM_SPD100LED_ORG#
PD LEDC1 DOCK_LOM_SPD10LED_GRN# DOCK_LOM_SPD100LED_ORG# <43> SYS_LED_MASK#
40
LEDC2 DOCK_LOM_SPD10LED_GRN# <43> SYS_LED_MASK#
43
PAD_GND
1: TO DOCK
FROM DOCKED
NIC 0: TO RJ45 PI3L720ZHEX_TQFN42_9X3P5~D DELL CONFIDENTIAL/PROPRIETARY
PN change from SA00003B20L to SA00003B200
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, LAN/LAN SW
LA-C551P 1.0

5 4 3 2 1
5 4 3 2 1
+3.3V_LAN/+3.3V_LAN_LOM:20mils
+3.3V_LAN
D D
JLOM1
1 2 13
<35> LAN_ACTLED_YEL#_Q Yellow_LED-
R1171 150_0402_5%
12
Yellow_LED+
RJ45_MDIN3 8
PR4-
DVT1 change from SP050006P00 to SP050006Y00 RJ45_MDIP3 7
PR4+
T156 RJ45_MDIN1 6
PR2-
RJ45_MDIN2 5
SW1_LAN0_MDIP0 1 1:1 24 RJ45_MDIP0 PR3-
<35> SW1_LAN0_MDIP0 TD1+ TX1+ RJ45_MDIP2 4
PR3+
RJ45_MDIP1 3
SW1_LAN0_MDIN0 2 PR2+
<35> SW1_LAN0_MDIN0 TD1- RJ45_MDIN0 RJ45_MDIN0
23 2 15
TX1- PR1- SHLD2
C RJ45_MDIP0 C
1 14
+TRM_CT1 3 22 Z2805 PR1+ SHLD1
TDCT1 TXCT1 1 2 10
<35> LED_10_GRN#_Q Green_LED-
R1170 150_0402_5%
+TRM_CT2 4 21 Z2807 9
SW1_LAN0_MDIP1 5 TDCT2 TXCT2 20 RJ45_MDIP1 LED+
<35> SW1_LAN0_MDIP1 TD2+ 1:1 TX2+
0.47U_0603_10V7K
0.47U_0603_10V7K
1 2 11
<35> LED_100_ORG#_Q ORANGE_LED-
R1167 150_0402_5%
1 1 SANTA_130454-3
C479
C480
CONN@
SW1_LAN0_MDIN1 6 19 RJ45_MDIN1
<35> SW1_LAN0_MDIN1 TD2- TX2- +3.3V_LAN LInk
2 2
CIS
1U_0603_10V6K
0.1U_0402_10V7K
470P_0402_50V7K
SW1_LAN0_MDIP2 7 1:1 18 RJ45_MDIP2
<35> SW1_LAN0_MDIP2 TD3+ TX3+ 1 1 1
C481
C483
C1167
SW1_LAN0_MDIN2 8 2 2 2
<35> SW1_LAN0_MDIN2 TD3- RJ45_MDIN2
17
TX3-
B +TRM_CT3 9 16 Z2806 B
TDCT3 TXCT3
+TRM_CT4 10 15 Z2808
TDCT4 TXCT4
0.47U_0603_10V7K
SW1_LAN0_MDIP3 11 1:1 14 RJ45_MDIP3
75_0402_1%
75_0402_1%
75_0402_1%
75_0402_1%
<35> SW1_LAN0_MDIP3 TD4+ TX4+
0.47U_0603_10V7K
1 1
Close to JLOM1
C484
C486
SW1_LAN0_MDIN3 12 13 RJ45_MDIN3
2 2 <35> SW1_LAN0_MDIN3 TD4- TX4-
1
350uH_IH-115-F
2
R571
R572
R573
R574
1 2 GND_CHASSIS
EMC@ C485 150P_1808_2.5KV8J
A A
GND CHASSIS DELL CONFIDENTIAL/PROPRIETARY

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, RJ45
LA-C551P 1.0

5 4 3 2 1
5 4 3 2 1
D D
power rail option: TPM power rail must same as +3.3V_SPI (SPI ROM)
+3.3V_M +3.3V_M_TPM 1 2 USH_PWR_STATE#
RZ10 1M_0402_5%
@ RZ75 2 1 0_0603_5%
DZ3
12/3 +3.3V_M_TPM
1 2 2 1
@ RZ88 0_0402_5%
RB751S40T1G_SOD523-2 JUSH1
+3.3V_ALW_PCH +3.3V_M_TPM 1 2 +U637_TPM 1 2 USH_DET#_R 1
+3.3V_RUN
PJP@ RZ89 0_0402_5% <45> USH_DET# @ RZ76 0_0402_5% 2 1
PJP2 3 2 2
4 3
0.1U_0402_25V6
1 2 1 <19> CONTACTLESS_DET#
5 4 4
+3.3V_ALW <45> USH_PWR_STATE# 6 5
CZ4
PAD-OPEN1x1m
<22> PLTRST_USH#
+5V_RUN 7 6 6
+3.3V_M_TPM 2 +5V_RUN +3.3V_RUN +3.3V_ALW
+3.3V_RUN
8 7
+5V_ALW
9 8 8
10 9
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
1 2 +5V_ALW2_R
+5V_ALW2
2 TPM_PIRQ# 11 10 10
10U_0603_25V6M
0.1U_0402_25V6
1 1 1 @ RZ72 0_0402_5%
12 11
@
RZ69 10K_0402_5%
13 12 12
1
CZ8
CZ7
CZ10
CZ11
@
+3.3V_ALW
14 13
CZ12
2 2 <45> BCM5882_ALERT# 15 14 14
<28,46> USH_SMBDAT
2
16 15
<28,46> USH_SMBCLK
17 16 16
SIO_SLP_S0# 1 2 U637 18 17
<11,23,37> SIO_SLP_S0# <20> USB20_P10
RZ111 0_0402_5% 1 19 18 18
VSB <20> USB20_N10
+3.3V_RUN
1 2 29 +3.3V_M_TPM 20 19
@ RZ90 10K_0402_5% 30 GPIO0/SDA/XOR_OUT 8 +U637_TPM 21 20 20
C TPM_LPM# 3 GPIO1/SCL VDD 14 Close to JUSH1 <46> EC_FPM_EN
22 21 C
6 GPIO2/GPX VDD 22 23 22 22
GPIO3/BADD VDD <46> POA_WAKE# 24 23
<46> CV2_ON
25 24 24
10U_0603_25V6M
0.1U_0402_25V6
0.1U_0402_25V6
RZ30 1 2 33_0402_5% SPI_DINTPM 24 2 1 1 1 +3.3V_ALW2 @ RZ70 1 2 0_0402_5% +3.3V_ALW2_R
<22> PCH_SPI_D1 RZ29 1 2 33_0402_5% SPI_DOTPM 21 LAD0/MISO NC 7 1 2 +PWR_SRC_R 26 25
<7,22> PCH_SPI_D0 LAD1/MOSI NC +PWR_SRC 26 26
CZ15
CZ6
CZ5
TPM_PIRQ# 18 10 @ RZ73 0_0402_5%
<22> TPM_PIRQ# 15 LAD2/SPI_IRQ# NC 11 27
LAD3 NC 25 2 2 2 G1 28
RZ26 1 2 33_0402_5% SPI_CLKTPM 19 NC 26 PLTRST_USH# G2 29
<22> PCH_SPI_CLK PCH_SPI_CS#2_R LCKL/SCLK NC G3
RZ17 1 2 0_0402_5% 20 31 30
<22> PCH_SPI_CS#2 LFRAME#/SCS# NC G4
0.047U_0402_16V4Z
17
<22> PLTRST_TPM# LRESET#/SPI_RST#/SRESET#
27 9 ACES_50559-02601-001
TPM_GPIO4 13 SERIRQ GND 16
CLKRUN#/GPIO4/SINT# GND 1 CONN@
28 23
LPCPD# GND CIS link OK
CZ57
32 ESD request
4 GND 33
PP PGND 2
10K_0402_5%
5 12
TEST Reserved
1
RZ20
NPCT650JAAYX_QFN32_5X5
PN change to 1.2(SA00008EL20)
2
Check ME about wire to board PN

JAPS1
+3.3V_ALW_PCH 1
2 1
<7,11,23,44,46> SIO_SLP_S3# 2
+3.3V_ALW
3
4 3
<23,44,46> SIO_SLP_S5# 4
5
<11,23,46,52,54> SIO_SLP_S4# 5
6
PCH_SPI_CS#2_R 1 <23,46,49> SIO_SLP_A# 6
2 TPM_GPIO4 +3.3V_ALW
7
B @ RZ110 0_0402_5% 8 7 B
9 8
<23> PCH_RTCRST# 10 9
SPI_CLKTPM 11 10
<44,46> POWER_SW#_MB 11
12
12
33_0402_5%
13
<20,23> SYS_RESET# 13
2
@EMC@
14
14
RZ35
15
+3.3V_M_TPM <11,23,37> SIO_SLP_S0# 16 15
17 16
18 17
1
18
0.1U_0402_25V6
19
20 GND
GND
1
S
@EMC@
LP2301ALT1G_SOT23-3
CZ9
PCH_SPI_CS#2_R
G
1 2 2 CONN@
RZ112 100_0402_5% QZ2 ACES_50506-01841-P01
Intel Management Engine Test Suite
2
D
1
TPM_LPM#
RZ112 RZ82 POP

1
RZ82
1K 1K MMBT3906 10K_0402_5%
2
100 10K LP2301A
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS Title
CONFIDENTIAL TPM/USH
DOCUMENT MAY NOT 1.0
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN
ADDITION,
LA-C551P
5 4 NEITHER THIS
3 SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO
2 1
ANY THIRD
5 4 3 2 1
WLAN/BT/WiGig
NGFF slot_1 Key A
+3.3V_WLAN
JNGFF1 CONN@
1 2
3 1 2 4
D <20> USB20_P6 3 4 D
5 6
<20> USB20_N6 7 5 6
7 10/23
8
9 8 10
11 9 10 12
13 11 12 14
15 13 14 16
17 15 16 18
19 17 18 20
21 19 20 22
23 21 22 24
25 23 24 26
CZ3 1 2 0.1U_0402_10V7K PCIE_PTX_C_DRX_P2 27 25 26 28
<20> PCIE_PTX_DRX_P2 2 0.1U_0402_10V7K PCIE_PTX_C_DRX_N2 27 28
CZ58 1 29 30
<20> PCIE_PTX_DRX_N2 29 30 PCH_CL_RST1# <19>
31 32
33 31 32 34 PCH_CL_DATA1 <19>
<20> PCIE_PRX_DTX_P2 35 33 34 36 PCH_CL_CLK1 <19>
<20> PCIE_PRX_DTX_N2 37 35 36 38
39 37 38 40
<21> CLK_PCIE_P6 39 40
41 42
<21> CLK_PCIE_N6 43 41 42 44 PCH_PLTRST#_EC SUSCLK <23,38,39>
45 43 44 46 BT_RADIO_DIS#_R PCH_PLTRST#_EC <22,39,45,46>
<21> CLKREQ_PCIE#6 PCIE_WAKE# 47 45 46 48 WLAN_WIGIG60GHZ_DIS#_R
<18,39,44,45> PCIE_WAKE# 49 47 48 50
51 49 50 52
53 51 52 54
55 53 54 56
57 55 56 58
59 57 58 60
61 59 60 62
63 61 62 64
65 63 64 66
67 65 66
67
69 68
GND GND
BELLW_80148-4221
Need update
WLAN_WIGIG60GHZ_DIS#_R 2 1
WLAN_WIGIG60GHZ_DIS# <45>
RB751S40T1G_SOD523-2 D31
C +3.3V_WLAN C
BT_RADIO_DIS#_R 2 1
BT_RADIO_DIS# <45>
0.047U_0402_16V4Z
0.047U_0402_16V4Z
0.1U_0402_25V6K
0.1U_0402_25V6K
4.7U_0603_6.3V6K
330U_D2E_6.3VM_R25M
0.1U_0402_25V6K
RB751S40T1G_SOD523-2 D36
1
1 1 1 2 2 1
@ C603
+ @
C604
C605
C606
C607
C608
C1402
2 2 2 1 1 2 2
WWAN/LTE/HCA/Cache WWAN_RADIO_DIS#_R 2 1
WWAN_RADIO_DIS# <45>
+3.3V_WWAN DZ1
NGFF slot_2 Key B RB751S40T1G_SOD523-2
1 2 WWAN_PWR_EN
@ RZ3 0_0402_5%
+3.3V_WWAN
HW_GPS_DISABLE#_R 2 1
1 2 HW_GPS_DISABLE# <45>
JNGFF2
@EMC@ RZ77 0_0402_5% 1 2 DZ2
1 2 <45> SLOT2_CONFIG_3 3 1 2 4 RB751S40T1G_SOD523-2
@EMC@ RZ71 0_0402_5% 5 3 4 6 WWAN_PWR_EN
7 5 6 8 WWAN_RADIO_DIS#_R
11/17 RF request
<20>
<20>
USB20_P8
USB20_N8
9
11
7
9
11
8
10
10 10/23 SIM Card Push-Push
EMC@ LI2 JSIM1
USB3_PRX_DTX_N2 2 1 USB3_PRX_L_DTX_N2 2 1 1 2 SIM_DET
B <23> USB3_PRX_DTX_N2 2 1 12 NC DETECT B
RZ113 0_0402_5%
13 12 14 UIM_DATA 4 3
USB3_PRX_DTX_P2 3 4 USB3_PRX_L_DTX_P2 <45> SLOT2_CONFIG_0 15 13 14 16 I/O NC
<23> USB3_PRX_DTX_P2 3 4 <45> WWAN_WAKE# 15 16 HW_GPS_DISABLE#_R UIM_CLK
17 18 6 5
DLW21HN900HQ2L_4P 19 17 18 20 VPP CLK +SIM_PWR
USB3_PRX_L_DTX_N2 21 19 20 22 UIM_RESET 8 7 UIM_RESET
EMC@ LI3 USB3_PRX_L_DTX_P2 23 21 22 24 UIM_CLK GND RST
USB3_PTX_DRX_N2 CZ91 1 2 0.1U_0402_10V7K USB3_PTX_C_DRX_N2 USB3_PTX_L_DRX_N2 23 24 UIM_DATA
1U_0402_6.3V6K
2 1 25 26 10 9
<23> USB3_PTX_DRX_N2 2 1 USB3_PTX_L_DRX_N2 27 25 26 28 NC VCC
+SIM_PWR
1
USB3_PTX_L_DRX_P2 29 27 28 30 12 11
USB3_PTX_DRX_P2 CZ92 1 2 0.1U_0402_10V7K USB3_PTX_C_DRX_P2 USB3_PTX_L_DRX_P2 29 30 GND GND
C1356
3 4 31 32
<23> USB3_PTX_DRX_P2 3 4 33 31 32 34 14 13
2
DLW21HN900HQ2L_4P <19> PCIE_PRX_DTX_P13 35 33 34 36 GND GND
<19> PCIE_PRX_DTX_N13 37 35 36 38 16 15
CZ1 1 2 0.1U_0402_10V7K PCIE_PTX_C_DRX_N13 39 37 38 40 GND GND
1 2 <19> PCIE_PTX_DRX_N13 PCIE_PTX_C_DRX_P13 39 40 PCH_PLTRST#_EC
CZ2 1 2 0.1U_0402_10V7K 41 42 18 17
<19> PCIE_PTX_DRX_P13 41 42 GND GND
@EMC@ RZ78 0_0402_5% 43 44
1 2 45 43 44 46 PCIE_WAKE# CLKREQ_PCIE#2 <21> T-SOL_159-1000302602
<21> CLK_PCIE_N2 45 46
@EMC@ RZ74 0_0402_5% 47 48 CONN@
<21> CLK_PCIE_P2 49 47 48 50
51 49 50 52 CIS link
51 52
53
55 53 54
54
56
OK
57 55 56 58 SIM_DET
+3.3V_WWAN 59 57 58 60
61 59 60 62 SUSCLK <23,38,39>
<45> SLOT2_CONFIG_1 61 62
63 64
65 63 64 66
67 65 66
<45> SLOT2_CONFIG_2 67
0.047U_0402_16V4Z
0.047U_0402_16V4Z
33P_0402_50V8J
33P_0402_50V8J
330U_D2E_6.3VM_R25M
330U_D2E_6.3VM_R25M
EMC@ C610
EMC@ C611
EMC@ C612
22U_0603_6.3V6M
EMC@ C614
EMC@ C615
1 1
EMC@ C613
1 1 1 1 69 68
1
GND GND
@ C1176
+ +
UIM_RESET
2
2 2 2 2 2 2 BELLW_80149-4221
CONN@
CIS link OK UIM_CLK
Net on platform UIM_DATA
33P_0402_50V8J
@EMC@ CZ65
33P_0402_50V8J
@EMC@ CZ66
33P_0402_50V8J
@EMC@ CZ67
C613 change to 0603
due to height limitation.
STATE # CONFIG_0 CONFIG_1 CONFIG_2 CONFIG_3 Module Type 1 1 1
C615 footprint change to C_APXK2R5ARA331MF451

2 2 2
0 0 0 0 0 SSD-SATA
A A
8 1 0 0 0 WWAN
For RF Team request
14 1 0 1 1 HCA-PCIE
15 1 1 1 1 Cache
M.2 Card-1/2
LA-C551P 1.0

5 4 3 2 1
5 4 3 2 1
SSD
NGFF slot_3 Key M
+3.3V_SSD1
JNGFF3 CONN@
10/24 1 2
3 GND 3P3VAUX 4
PCIE_PRX_DTX_N12 5 GND 3P3VAUX 6
<19> PCIE_PRX_DTX_N12 PCIE_PRX_DTX_P12 7 PERn3 NC 8
<19> PCIE_PRX_DTX_P12 9 PERp3 NC 10
0.22U_0402_10V6K 1 2 CN95 PCIE_PTX_C_DRX_N12 11 GND DAS/DSS# 12 SLOT3_SATA_LED# <47>
<19> PCIE_PTX_DRX_N12 PCIE_PTX_C_DRX_P12 PETn3 3P3VAUX
0.22U_0402_10V6K 1 2 CN97 13 14
D <19> PCIE_PTX_DRX_P12 PETp3 3P3VAUX D
15 16
<19> PCIE_PRX_DTX_N11 PCIE_PRX_DTX_P11 19 PERn2 3P3VAUX 20
0.22U_0402_10V6K 1 2 CN91 PCIE_PTX_C_DRX_N11 23 GND NC 24
<19> PCIE_PTX_DRX_N11 PCIE_PTX_C_DRX_P11 PETn2 NC
0.22U_0402_10V6K 1 2 CN92 25 26
<19> PCIE_PTX_DRX_P11 PETp2 NC
27 28
PCIE_PRX_DTX_N10 29 GND NC 30
<19> PCIE_PTX_DRX_N10 PCIE_PTX_C_DRX_P10 PETn1 NC
0.22U_0402_10V6K 1 2 CN87 37 38
<19> PCIE_PTX_DRX_P10 PETp1 DEVSLP
39 40
PCIE_PRX_DTX_P9 41 GND NC 42
<19> PCIE_PRX_DTX_P9 PCIE_PRX_DTX_N9 43 PERn0/SATA-B+ NC 44 +3.3V_SSD1
<19> PCIE_PRX_DTX_N9 45 PERp0/SATA-B- NC 46
+3.3V_RUN <19> PCIE_PTX_DRX_N9 PCIE_PTX_C_DRX_P9 PETn0/SATA-A- NC
0.22U_0402_10V6K 1 2 CN83 49 50
<19> PCIE_PTX_DRX_P9 PETp0/SATA-A+ PERST# PCH_PLTRST#_EC <22,38,39,45,46>
0.047U_0402_16V4Z
0.047U_0402_16V4Z
330U_D2E_6.3VM_R25M
33P_0402_50V8J
22U_0805_6.3VAM
33P_0402_50V8J
51 52 1
GND CLKREQ# CLKREQ_PCIE#7 <21>
10K_0402_5%
53 54 1 1 1 1 1
<21> CLK_PCIE_N7 REFCLKN PEWake# PCIE_WAKE# <18,38,39,44,45>
C619
55 56 +
<21> CLK_PCIE_P7 REFCLKP NC
R363
C623
C621
C618
C622
C617
57 58
GND NC
2 2 2 2 2 2
1
59 60 SUSCLK_R 1 2 SUSCLK
NC SUSCLK(32kHz) SUSCLK <23,38>
1 2 PEDET3 61 62 R360 0_0402_5%
<19> M2_SLOT3_PEDET @ R372 0_0402_5% 63 PEDET(NC-PCIE/GND-SATA) 3P3VAUX 64
GND 3P3VAUX
DMN65D8LW-7_SOT323-3
65 66
GND 3P3VAUX
1
D 67
GND
@ QN5
2 PEDET3 68
G GND1 69
GND2
S
3
BELLW_SD-80159-4221
PEDET Module Type
1
@ R364
20K_0402_5%
Net name on Platform
C 0 SATA Need update symbol C
2
1 PCIE
SSD
NGFF slot_4 Key M
+3.3V_SSD2
JNGFF4 CONN@
1 2
3 GND 3P3VAUX 4
10/24 PCIE_PRX_DTX_N20 5 GND 3P3VAUX 6
0.22U_0402_10V6K 1 2 CN113 PCIE_PTX_C_DRX_N20 11 GND DAS/DSS# 12 SLOT4_SATA_LED# <47>
<19> PCIE_PTX_DRX_N20 PETn3 3P3VAUX
0.22U_0402_10V6K 1 2 CN112 PCIE_PTX_C_DRX_P20 13 14
<19> PCIE_PTX_DRX_P20 PETp3 3P3VAUX
15 16
<19> PCIE_PRX_DTX_N19 PCIE_PRX_DTX_P19 19 PERn2 3P3VAUX 20
<19> PCIE_PTX_DRX_N19 PETn2 NC
<19> PCIE_PTX_DRX_P19 PETp2 NC
27 28
PCIE_PRX_DTX_N18 29 GND NC 30
B <19> PCIE_PRX_DTX_P18 33 PERp1 NC 34 B
<19> PCIE_PTX_DRX_N18 PETn1 NC
<19> PCIE_PTX_DRX_P18 PETp1 DEVSLP
39 40
PCIE_PRX_DTX_P17 41 GND NC 42 +3.3V_SSD2
<19> PCIE_PRX_DTX_P17 PCIE_PRX_DTX_N17 43 PERn0/SATA-B+ NC 44
<19> PCIE_PRX_DTX_N17 45 PERp0/SATA-B- NC 46
+3.3V_RUN <19> PCIE_PTX_DRX_N17 PETn0/SATA-A- NC
2 CN102 PCIE_PTX_C_DRX_P17
0.047U_0402_16V4Z
0.047U_0402_16V4Z
330U_D2E_6.3VM_R25M
33P_0402_50V8J
22U_0805_6.3VAM
33P_0402_50V8J
0.22U_0402_10V6K 1 49 50 1
<19> PCIE_PTX_DRX_P17 PETp0/SATA-A+ PERST# PCH_PLTRST#_EC <22,38,39,45,46>
@ C1442
51 52 1 1 1 1 1
53 GND CLKREQ# 54 CLKREQ_PCIE#8 <21> +
<21> CLK_PCIE_N8 REFCLKN PEWake# PCIE_WAKE# <18,38,39,44,45>
10K_0402_5%
C1440
C1441
C1422
C1439
C1443
55 56
<21> CLK_PCIE_P8 REFCLKP NC
2
57 58
GND NC 2 2 2 2 2 2
R3742
1
59 60 SUSCLK_R 1 2 SUSCLK
1 2 PEDET4 61 NC SUSCLK(32kHz) 62 R3756 0_0402_5%
<19> M2_SLOT4_PEDET @ R3751 0_0402_5% 63 PEDET(NC-PCIE/GND-SATA) 3P3VAUX 64
GND 3P3VAUX
DMN65D8LW-7_SOT323-3
65 66
GND 3P3VAUX
1
D 67
GND
@ QN6
2 PEDET4 68
GND1 69
G
GND2
S
3
BELLW_SD-80159-4221
PEDET Module Type
1
@ R3743
20K_0402_5%
0 SATA
2
1 PCIE
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, M.2 Card-2/2
LA-C551P 1.0

5 4 3 2 1
5 4 3 2 1
D D
Power Control for M.2 slot 1. Power Control for M.2 slot 2.
& +3.3V_RUN Source
+3.3V_WLAN_PWR +3.3V_WLAN
UZ25 @ PJP10 +3.3V_ALW +3.3V_WWAN

1 14 +3.3V_WLAN_PWR 2 1
+3.3V_ALW VIN1 VOUT1 2 1
2 13
VIN1 VOUT1
10U_0603_6.3V6M
JUMP_43X79
1 2 AUX_EN_WOWL_R 3 12 UZ24
<45> AUX_EN_WOWL ON1 CT1 1
C536
@ R840 0_0402_5%
4 11 1 7
+5V_ALW VBIAS GND VIN VOUT
1
100K_0402_5%
1 2 +3.3V_LAN_PWR +3.3V_LAN 2 8
<23,45> SIO_SLP_WLAN# 2 VIN VOUT
10U_0603_6.3V6M
@ R820 0_0402_5% 5 10
ON2 CT2
R723
@ PJP11 3 6 1
6 9 +3.3V_LAN_PWR 2 1 <45> 3.3V_WWAN_EN ON CT
1
100K_0402_5%
C762
7 8
2
VIN2 VOUT2
470P_0402_50V7K
JUMP_43X79 +5V_ALW
4 1
VBIAS 2
470P_0402_50V7K
470P_0402_50V7K
R720
C541
15 2 2 5
GPAD GND 9
GND
C436
C538
EM5209VF_DFN14_3X2
2
2
1 1 AOZ1336_DFN8_2X2
<23,46> SIO_SLP_LAN#
C C
B Power Control for M.2 slot 3. Source B
Power Control for M.2 slot 4. Source

+3.3V_SSD1_PWR +3.3V_SSD1
UZ21 @ PJP9
1 14 2 1
2 13
VIN1 VOUT1
10U_0603_6.3V6M
1 JUMP_43X79
3 12
<45> SLOT3_SSD_PWR_EN ON1 CT1
C400
4 11
+5V_ALW VBIAS GND 2 +3.3V_SSD2_PWR +3.3V_SSD2
5 10
<45> SLOT4_SSD_PWR_EN ON2 CT2
6 9 @ PJP1
+3.3V_ALW VIN2 VOUT2
7 8 2 1
VIN2 VOUT2 2 1
470P_0402_50V7K
470P_0402_50V7K
10U_0603_6.3V6M
15 2 2
GPAD JUMP_43X79
1
C476
C477
C475
EM5209VF_SON14_2X3
1 1
2
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, M.2 Card PWR
LA-C551P 1.0

5 4 3 2 1
5 4 3 2 1
+3.3V_RUN +3.3V_RUN
R501
1 2 DDR_XDP_WAN_SMBDAT
10K_0402_5%
Free Fall Sensor
D D
2 DDR_XDP_WAN_SMBCLK
10U_0603_6.3V6M
0.1U_0402_25V6K
1
R502 10K_0402_5%
1 2 HDD_FALL_INT 1 1
R503 100K_0402_5%
2 FFS_INT2
C392
C391
1
R504 100K_0402_5% U88
2 2
LNG2DM
10 5
9 VDD_IO RES
VDD 12 HDD_FALL_INT
3 INT 1 11 FFS_INT2 HDD_FALL_INT <23>
4 SDO/SA0 INT 2
<7,14,15,16,17,23> DDR_XDP_WAN_SMBDAT SDA/SDI/SDO
1 6
<7,14,15,16,17,23> DDR_XDP_WAN_SMBCLK SCL/SPC GND 7
2 GND 8
CS GND
LNG2DMTR_LGA12_2X2
C C
HDD1 CONN
JSATA1
1
2 1
<42> PCIE_PTX_C_DRX_P16 2
3
<42> PCIE_PTX_C_DRX_N16 3
4
5 4
<42> PCIE_PRX_C_DTX_N16 6 5
<42> PCIE_PRX_C_DTX_P16 7 6
8 7
+5V_HDD <42> PCIE_PTX_C_DRX_P15 8
9
<42> PCIE_PTX_C_DRX_N15 9
10
+3.3V_HDD 10
100K_0402_5%
11
<42> PCIE_PRX_C_DTX_N15
1
12 11
<42> PCIE_PRX_C_DTX_P15 12
@ R506
13
+3.3V_RUN 1 2 CLKDET# CLK_PCIE_P5 14 13
<21> CLK_PCIE_P5 CLK_PCIE_N5 14
R3753 100K_0402_5% 15
<21> CLK_PCIE_N5 15
100K_0402_5%
CLKDET# 16
2
<24> CLKDET#
1
17 16
<22> PLTRST_HDD# 17
R513
18
FFS_INT2_QR <21> CLKREQ_PCIE#5 HDD_IFDET 18
19
HDD_DET# 20 19
<19> HDD_DET# 20
21
2
@ PJP4 FFS_INT2_Q 22 21
1 2 +5V_HDD 23 22
+5V_RUN 23
Q29B
24
5 PAD-OPEN1x1m 25 24
@ PJP5 26 25
+3.3V_HDD1 26
1 2 27 31
+3.3V_HDD
4
1 2 27 GND 32
6
28
29 28 GND 33
JUMP_43X79 29 GND 34
Q29A
30
2 30 GND
<22> FFS_INT2 STARC_7300L30-100000-G4
B B
CONN@
1
CIS link OK
+3.3V_HDD1 +5V_HDD
SATA_EXP_IFDET channel on
HDD_IFDET DEVICE interface SATA_EXP_IFDET DEVICE interface
1000P_0402_50V7K
0.1U_0402_25V6K
10U_0603_6.3V6M
0 A-->B1
0.1U_0402_25V6
22U_0603_6.3V6M
1 1 1 1 1 0 SATA 0 SATA
C404
C403
C395
C406
C5
1 A-->B2
2 2 2 2 2
1 PCIE 1 PCIE
@ R386 1 2 0_0402_5% +3.3V_RUN
+1.0V_RUN
11/21
Pleace near JSATA1 CONN Pleace near JSATA1 CONN U639
FFS_INT2_QR 3 4 FFS_INT2_Q
U6 2 B1 A 5
1 5 1 2 1 GND VCC 6 SATA_EXP_IFDET
NC VCC C401 0.1U_0402_25V6K <47> SATAE_LED# B2 S
HDD_IFDET 2 SN74LVC1G3157DCKR_SC70-6
A 4
3 Y SATA_EXP_IFDET <19,42>
GND
1
20K_0402_5%
A 74AUP1G07GW_TSSOP5 A
R317
2
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, HDD CONN
LA-C551P 1.0

5 4 3 2 1
5 4 3 2 1
+3.3V_HDD +3.3V_HDD +3.3V_HDD
+3.3V_RUN +3.3V_HDD +3.3V_HDD
@ PJP3 +3.3V_HDD
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
1 2
1 2
1
@ RN99
@ RN52
@ RN50
@ RN54
@ RN104
@ RN109
@ RN108
@ RN110
@ RN115
@ RN114
@
RN78
JUMP_43X79
0.1U_0402_10V6K
0.01U_0402_16V7K
1 1
2
CN67
CN75
DE0_A_UN8
PWD_UN8
D 2 2 DE1_A_UN8 EQ0_A_UN8 EQ0_B_UN8 D
PCIE/SATA Repeater DE0_B_UN8
DE1_B_UN8
EQ1_A_UN8
EQ2_A_UN8
EQ1_B_UN8
EQ2_B_UN8
UN8
12
VDD_3.3
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
24
VDD_3.3
1
@ RN100
@ RN102
@ RN101
@ RN103
@ RN105
@ RN107
@ RN106
@ RN111
@ RN51
@ RN60
0.22U_0402_10V6K 1 2 CN70 PCIE_PTX_C_RD_DRX_P15 1 18 PCIE_PTX_RD_DRX_P15 CN64 2 1 0.22U_0402_10V6K
<19> PCIE_PTX_DRX_P15 PCIE_PTX_C_RD_DRX_N15 A_INP A_OUTP PCIE_PTX_RD_DRX_N15 PCIE_PTX_C_DRX_P15 <41>
0.22U_0402_10V6K 1 2 CN63 2 17 CN72 2 1 0.22U_0402_10V6K
<19> PCIE_PTX_DRX_N15 A_INN A_OUTN PCIE_PTX_C_DRX_N15 <41>
2
0.22U_0402_10V6K 1 2 CN69 PCIE_PRX_C_RD_DTX_P15 5 14 PCIE_PRX_RD_DTX_P15 RN131 2 1 0_0402_5%
<19> PCIE_PRX_DTX_P15 PCIE_PRX_C_RD_DTX_N15 B_OUTP B_INP PCIE_PRX_RD_DTX_N15 PCIE_PRX_C_DTX_P15 <41>
0.22U_0402_10V6K 1 2 CN76 4 15 RN132 2 1 0_0402_5%
<19> PCIE_PRX_DTX_N15 B_OUTN B_INN PCIE_PRX_C_DTX_N15 <41>
EQ0_A_UN8 23 6 DE0_A_UN8
EQ1_A_UN8 22 A_EQ0 A_DE0 8 DE1_A_UN8
EQ2_A_UN8 19 A_EQ1 A_DE1
A_EQ2
EQ0_B_UN8 11 13 DE0_B_UN8
EQ1_B_UN8 21 B_EQ0 B_DE0 9 DE1_B_UN8
EQ2_B_UN8 16 B_EQ1 B_DE1
B_EQ2
3 PWD_UN8
7 PWD 10 M_REXT_UN8 RN53 1 2 4.99K_0402_1%
25 GND REXT 20 SATA_EXP_IFDET Equalizer control and program for channel A.
EPAD MODE SATA_EXP_IFDET <19,41> Programmable output de-emphasis level A_EQ0, A_EQ1 and A_EQ2: internally pulled down at ~150K
PS8558BTQFN24GTR2-A_TQFN24_4X4 setting for channel A .
A_DE0: internally pulled up at ~150K; [A_EQ2,A_EQ1,A_EQ0] ==
A_DE1 internally pulled down at ~150K LLL: EQ Level1(default)
C LHL: EQ Level2 C
[A_DE1,A_DE0] == HLL: EQ Level3
PWD Funtion SATA_EXP_IFDET DEVICE interface LL: -7.5dB HHL: EQ Level4
HL: -2dB LLH: EQ Level5
0 Normal mode(Default) 0 SATA LH: -3.5dB (default) LHH: EQ Level6
HH: -6dB HLH: EQ Level7
HHH: EQ Level8
1 1 PCIE
Chip power down
Programmable output de-emphasis level Equalizer control and program for channel B.
setting for channel B. B_EQ0, B_EQ1 and B_EQ2: internally pulled down at ~150K
B_DE0: internally pulled up at ~150K;
+3.3V_HDD B_DE1 internally pulled down at ~150K [B_EQ2,B_EQ1,B_EQ0] ==
+3.3V_HDD
LLL: EQ Level1(default)
[B_DE1,B_DE0] == LHL: EQ Level2
10K_0402_5%
LL: -7.5dB HLL: EQ Level3
1
@ HL: -2dB HHL: EQ Level4
0.1U_0402_10V6K
0.01U_0402_16V7K
RN79
1 1
LH: -3.5dB (default) LLH: EQ Level5
HH: -6dB LHH: EQ Level6
CN73
CN71
HLH: EQ Level7
2
2 2 HHH: EQ Level8
PCIE/SATA Repeater PWD_UN9
UN9
12
24 VDD_3.3 +3.3V_HDD +3.3V_HDD +3.3V_HDD
B VDD_3.3 B
0.22U_0402_10V6K 1 2 CN79 PCIE_PTX_C_RD_DRX_P16 1 18 PCIE_PTX_RD_DRX_P16 CN66 2 1 0.22U_0402_10V6K
<19> PCIE_PTX_DRX_P16 1 2 CN65 PCIE_PTX_C_RD_DRX_N16 2 A_INP A_OUTP 17 PCIE_PTX_RD_DRX_N16 PCIE_PTX_C_DRX_P16 <41>
0.22U_0402_10V6K CN81 2 1 0.22U_0402_10V6K
<19> PCIE_PTX_DRX_N16 A_INN A_OUTN PCIE_PTX_C_DRX_N16 <41>
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
1
1
@ RN116
@ RN62
@ RN61
@ RN59
@ RN123
@ RN122
@ RN121
@ RN127
@ RN130
@ RN129
0.22U_0402_10V6K 1 2 CN74 PCIE_PRX_C_RD_DTX_P16 5 14 PCIE_PRX_RD_DTX_P16 RN133 2 1 0_0402_5%
<19> PCIE_PRX_DTX_P16 PCIE_PRX_C_RD_DTX_N16 B_OUTP B_INP PCIE_PRX_RD_DTX_N16 PCIE_PRX_C_DTX_P16 <41>
0.22U_0402_10V6K 1 2 CN80 4 15 RN134 2 1 0_0402_5%
<19> PCIE_PRX_DTX_N16 B_OUTN B_INN PCIE_PRX_C_DTX_N16 <41>
EQ0_A_UN9 23 6 DE0_A_UN9
EQ1_A_UN9 22 A_EQ0 A_DE0 8 DE1_A_UN9
2
EQ2_A_UN9 19 A_EQ1 A_DE1
A_EQ2 DE0_A_UN9
EQ0_B_UN9 11 13 DE0_B_UN9
EQ1_B_UN9 21 B_EQ0 B_DE0 9 DE1_B_UN9 DE1_A_UN9 EQ0_A_UN9 EQ0_B_UN9
EQ2_B_UN9 16 B_EQ1 B_DE1
B_EQ2 DE0_B_UN9 EQ1_A_UN9 EQ1_B_UN9
3 PWD_UN9
7 PWD 10 M_REXT_UN9 RN58 1 2 4.99K_0402_1% DE1_B_UN9 EQ2_A_UN9 EQ2_B_UN9
25 GND REXT 20 SATA_EXP_IFDET
EPAD MODE
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
PS8558BTQFN24GTR2-A_TQFN24_4X4
1
@ RN117
@ RN119
@ RN118
@ RN120
@ RN124
@ RN126
@ RN125
@ RN128
@ RN57
@ RN55
2
2
PWD Funtion SATA_EXP_IFDET DEVICE interface
0 Normal mode(Default) 0 SATA

A A
1 1 PCIE
Chip power down
HDD PCIE/SATA repeater
LA-C541P 1.0
5 4 3 2 1
5 4 3 2 1
DPD_CA_DET
EMI request add 33ohm for DOCK DVI signals.
1 2
R492 1M_0402_5%
Dock DPD (Port 1) JDOCK1 Dock DPC (Port 2)
DOCK_DET_1 1 2
3 1 2 4 DOCK_AC_OFF <60>
<35> DOCK_LOM_SPD10LED_GRN# 5 3 4 6 DOCK_LOM_SPD100LED_ORG# <35>
<31> DPD_CA_DET 7 5 6 8 DPC_CA_DET <32>
C366 2 1 0.1U_0402_10V7K SW2_DP_P0_C EMC@ R2164 1 2 33_0402_5% SW2_DP_P0_R 9 7 8 10 SW3_DP1_P0_R EMC@ R2172 1 2 33_0402_5% SW3_DP1_P0_C 0.1U_0402_10V7K 1 2 C431
<31> SW2_DP_P0 1 0.1U_0402_10V7K SW2_DP_N0_C SW2_DP_N0_R 9 10 SW3_DP1_N0_R SW3_DP1_N0_C SW3_DP1_P0 <32>
C367 2 EMC@ R2165 1 2 33_0402_5% 11 12 EMC@ R2173 1 2 33_0402_5% 0.1U_0402_10V7K 1 2 C438
<31> SW2_DP_N0 13 11 12 14 SW3_DP1_N0 <32>
D D
C369 2 EMC@ R2167 1 2 33_0402_5% 17 18 EMC@ R2175 1 2 33_0402_5% 0.1U_0402_10V7K 1 2 C440
<31> SW2_DP_N1 19 17 18 20 SW3_DP1_N1 <32>
C425 2 EMC@ R2169 1 2 33_0402_5% 23 24 EMC@ R2177 1 2 33_0402_5% 0.1U_0402_10V7K 1 2 C442
<31> SW2_DP_N2 25 23 24 26 SW3_DP1_N2 <32>
C427 2 EMC@ R2171 1 2 33_0402_5% 29 30 EMC@ R2179 1 2 33_0402_5% 0.1U_0402_10V7K 1 2 C444
<31> SW2_DP_N3 31 29 30 32 SW3_DP1_N3 <32>
SW2_DP_AUXP 33 31 32 34 SW3_DP1_AUXP
<31> SW2_DP_AUXP SW2_DP_AUXN 35 33 34 36 SW3_DP1_AUXN SW3_DP1_AUXP <32>
<31> SW2_DP_AUXN 37 35 36 38 SW3_DP1_AUXN <32>
SW2_DP_HPD 39 37 38 40 SW3_DP1_HPD
<31> SW2_DP_HPD 39 40 SW3_DP1_HPD <32>
0.033U_0402_16V7K
41 42
+NBDOCK_DC_IN_SS 41 42 ACAV_DOCK_SRC# <57,60>
0.033U_0402_16V7K
1 43 44
BLUE_DOCK 43 44
@ C695
@ C696
45 46 1
<18> BLUE_DOCK 47 45 46 48 DAT_DDC2_DOCK <18>
49 47 48 50 CLK_DDC2_DOCK <18>
2 51 49 50 52
RED_DOCK 53 51 52 54 SATA_PRX_C_DTX_P1 C697 2 1 0.01U_0402_16V7K 2
<18> RED_DOCK 55 53 54 56 SATA_PRX_C_DTX_N1 SATA_PRX_DTX_P1 <19>
C698 2 1 0.01U_0402_16V7K
Close to DOCK 57 55 56 58 SATA_PRX_DTX_N1 <19>
Its for Enhance ESD on dock issue. GREEN_DOCK 59 57 58 60 SATA_PTX_C_DRX_P1 C700 1 2 0.01U_0402_16V7K Close to DOCK
<18> GREEN_DOCK 59 60 SATA_PTX_DRX_P1 <19>
61
63 61 62
62
64
SATA_PTX_C_DRX_N1 C699 1 2 0.01U_0402_16V7K
SATA_PTX_DRX_N1 <19> Its for Enhance ESD on dock issue.
65 63 64 66
<18> HSYNC_DOCK 67 65 66 68 USB20_P5 <20>
<18> VSYNC_DOCK 69 67 68 70 USB20_N5 <20>
SW2_DP_HPD 71 69 70 72
<46> CLK_MSE 73 71 72 74 USB20_P7 <20>
<46> DAT_MSE 75 73 74 76 USB20_N7 <20> SW3_DP1_HPD
75 76
100K_0402_5%
77 78
<44> DAI_BCLK# 77 78 CLK_KBD <46>
1
79 80
<44> DAI_LRCK# 79 80 DAT_KBD <46>
R757
100K_0402_5%
81 82
C 81 82 C
1
83 84
<44> DAI_DI 83 84 USB3_PRX_DTX_N6 <23>
R2160
85 86
<44> DAI_DO# 87 85 86 88 USB3_PRX_DTX_P6 <23>
2
89 87 88 90
<44> DAI_12MHZ# 91 89 90 92 USB3_PTX_DRX_N6 <23>
2
93 91 92 94 USB3_PTX_DRX_P6 <23>
95 93 94 96
97 95 96 98
<45> D_LAD0 99 97 98 100 BREATH_LED# <46,47>
<45> D_LAD1 101 99 100 102 DOCK_LOM_ACTLED_YEL# <35>
<45> D_LAD2
103
105
101
103
102
104
104
106 SW1_LAN1_MDIP0 <35>
audio not transfer to DP display if
<45> D_LAD3 107
109
105
107
106
108
108
110
SW1_LAN1_MDIN0 <35>
play movie when attached external DP
<45> D_LFRAME#
<45> D_CLKRUN#
111 109
111
110
112
112 SW1_LAN1_MDIP1
SW1_LAN1_MDIN1
<35>
<35>
+LOM_VCT
display
1U_0402_6.3V6K
113 114
115 113 114 116
<45> D_SERIRQ 115 116 1
@ C701
117 118 +3.3V_ALW
<45> D_DLDRQ1# 117 118 +LOM_VCT
119 120
121 119 120 122
<23> CLK_PCI_DOCK 123 121 122 124 SW1_LAN1_MDIP2 <35> 2 DOCK_DET# 2 1
125 123 124 126 SW1_LAN1_MDIN2 <35>
10K_0402_5% R755
127 125 126 128
<44,46> DOCK_TNY_SMB_CLK 129 127 128 130 SW1_LAN1_MDIP3 <35>
<44,46> DOCK_TNY_SMB_DAT 131 129 130 132 SW1_LAN1_MDIN3 <35> System hangs after hot dock.
133 131 132 134
<44,45,50> DOCK_TNY_SMBUS_ALRT# 135 133 134 136 DOCK_DCIN_IS+ <57>
<50> DOCK_PSID 137 135 136 138 DOCK_DCIN_IS- <57>
139 137 138 140
<46> DOCK_PWR_BTN# 141 139 140 142 DOCK_POR_RST# <46> D32
143 141 142 144 DOCK_DET_R# 1 2
<45,50,60> SLICE_BAT_PRES# 143 144 DOCK_DET# <45>
145 149
146 GND1 PWR2 150 RB751S40T1G_SOD523-2
+DOCK_PWR_BAR PWR1 PWR2 +DOCK_PWR_BAR
L30ESD24VC3-2_SOT23-3
B 147 151 B
PWR1 PWR2
3
2
0.1U_0603_50V7K
@ D33
0.1U_0603_50V7K
148 152
PWR1 GND2
4.7U_0805_25V6-K
1 1 @ 153 159 1 @
Shield_G Shield_G
@ CE6
C702
C703
154 160
155 Shield_G Shield_G 161
2 2 157 Shield_G Shield_G 163 2
Shield_G Shield_G
1
JAE_WD2F144WB5R400
CONN@
PN change to SP0300019A0
DAI_12MHZ# DAI_BCLK# CLK_PCI_DOCK

1
1
EMC@ EMC@ EMC@
RE11 RE12 R756
10_0402_1% 10_0402_1% 33_0402_5%
2
1 1 1
EMC@ EMC@ EMC@
CE8 CE9 C704
4.7P_0402_50V8C 4.7P_0402_50V8C 12P_0402_50V8J
2 2 2
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Docking
LA-C551P 1.0

5 4 3 2 1
5 4 3 2 1
USB/Codec/Card reader IO/B Display daughter /B

JIO2
162 161
160 G2 G1 159
PCIE_PRX_DTX_P8 158 160 159 157 SW4_DP_P0
<20> PCIE_PRX_DTX_P8 PCIE_PRX_DTX_N8 156 158 157 155 SW4_DP_N0 SW4_DP_P0 <34>
<20> PCIE_PRX_DTX_N8 154 156 155 153 SW4_DP_N0 <34>
PCIE_PTX_DRX_P8 152 154 153 151 SW4_DP_P1
<20> PCIE_PTX_DRX_P8 PCIE_PTX_DRX_N8 152 151 149 SW4_DP_N1 SW4_DP_P1 <34>
150
<20> PCIE_PTX_DRX_N8 150 149 147 SW4_DP_N1 <34>
CONN@ JIO1 148
D 2 1 PCIE_PRX_DTX_P7 146 148 147 145 SW4_DP_P2 D
4 2 1 3 <20> PCIE_PRX_DTX_P7 PCIE_PRX_DTX_N7 144 146 145 143 SW4_DP_N2 SW4_DP_P2 <34>
<23> USB3_PTX_DRX_N3 4 3 USB3_PRX_DTX_N4 <23> <20> PCIE_PRX_DTX_N7 144 143 141 SW4_DP_N2 <34>
6 5 142
<23> USB3_PTX_DRX_P3
8 6 5 7
USB3_PRX_DTX_P4 <----- Right Side JUSB2
<23> PCIE_PTX_DRX_P7 140 142 141 139 SW4_DP_P3
Right Side JUSB1-----> 10 8 7 9
<20> PCIE_PTX_DRX_P7 PCIE_PTX_DRX_N7 138 140 139 137 SW4_DP_N3 SW4_DP_P3 <34> TO TBT
<23> USB3_PRX_DTX_N3 10 9 USB3_PTX_DRX_N4 <23> <20> PCIE_PTX_DRX_N7 138 137 135 SW4_DP_N3 <34>
12 11 136
<23> USB3_PRX_DTX_P3 12 11 USB3_PTX_DRX_P4 <23> PCIE_PRX_DTX_P6 136 135 133 SW4_DP_AUXP
14 13 134
14 13 <20> PCIE_PRX_DTX_P6 PCIE_PRX_DTX_N6 134 133 131 SW4_DP_AUXN SW4_DP_AUXP <34>
16 15 132
<20> USB20_N2 16 15 USB20_N3 <20> <20> PCIE_PRX_DTX_N6 132 131 129 SW4_DP_AUXN <34>
18 17 130
<20> USB20_P2 18 17 USB20_P3 <20> PCIE_PTX_DRX_P6 130 129 127 SW5_DP_P0
20 19 128
20 19 USB_OC2# <20> <20> PCIE_PTX_DRX_P6 PCIE_PTX_DRX_N6 128 127 125 SW5_DP_N0 SW5_DP_P0 <33>
22 21 126
<20> USB_OC1# 22 21 <20> PCIE_PTX_DRX_N6 126 125 123 SW5_DP_N0 <33>
24 23 124
<20> USB_OC3# 24 23 PCIE_PRX_DTX_P5 124 123 121 SW5_DP_P1
26 25 122
26 25 USB3_PRX_DTX_N5 <23> <20> PCIE_PRX_DTX_P5 PCIE_PRX_DTX_N5 122 121 119 SW5_DP_N1 SW5_DP_P1 <33>
28 27 120
<20> USB20_N4 28 27 USB3_PRX_DTX_P5 <23> <20> PCIE_PRX_DTX_N5 120 119 117 SW5_DP_N1 <33>
30 29 118
<20> USB20_P4
32 30 29 31 <----- Right Side JUSB3 PCIE_PTX_DRX_P5 116 118 117 115 SW5_DP_P2
32 31 USB3_PTX_DRX_N5 <23> <20> PCIE_PTX_DRX_P5 PCIE_PTX_DRX_N5 116 115 113 SW5_DP_N2 SW5_DP_P2 <33>
34 33 114
<20> PCIE_PTX_DRX_P3 34 33 USB3_PTX_DRX_P5 <23> <20> PCIE_PTX_DRX_N5 114 113 111 SW5_DP_N2 <33>
36 35 112
<20> PCIE_PTX_DRX_N3 38 36 35 37 CLK_PCIE_N4 110 112 111 109 SW5_DP_P3
40 38 37 39 DAI_DI <43> <21> CLK_PCIE_N4 CLK_PCIE_P4 108 110 109 107 SW5_DP_N3 SW5_DP_P3 <33> TO DP
<20> PCIE_PRX_DTX_P3 40 39 DAI_DO# <43> <21> CLK_PCIE_P4 108 107 105 SW5_DP_N3 <33>
42 41 106
<20> PCIE_PRX_DTX_N3 42 41 DAI_BCLK# <43> CLKREQ_PCIE#4 106 105 103 SW5_DP_AUXP
44 43 104
44 43 DAI_LRCK# <43> <21> CLKREQ_PCIE#4 PCIE_WAKE# 104 103 101 SW5_DP_AUXN SW5_DP_AUXP <33>
<45> USB_PWR_SHR_VBUS_RHT_EN1 46 45 102
46 45 EN_I2S_NB_CODEC# <45> <18,38,39,45> PCIE_WAKE# PLTRST_TBT# 102 101 99 SW5_DP_AUXN <33>
48 47 100
<45> USB_PWR_SHR_RHT_EN1# 48 47 DMIC_CLK <30> <22> PLTRST_TBT# TBT_FORCE_PWR 100 99 97 USB3_PTX_DRX_N1
50 49 DMIC0 <30> <22> TBT_FORCE_PWR SIO_SLP_S3# 98 97 95 USB3_PTX_DRX_P1 USB3_PTX_DRX_N1 <23>
52 51 96
<45> USB_PWR_SHR_RHT_EN2# 52 51 AUD_NB_MUTE# <45> <7,11,23,37,46> SIO_SLP_S3# TBT_CIO_PLUG_EVENT# 96 95 93 USB3_PTX_DRX_P1 <23>
54 53 BEEP <46> <19> TBT_CIO_PLUG_EVENT# RTD3_USB_PWR_EN 94 93 91 USB3_PRX_DTX_N1
56 55 TBT GOIP/HPD 92 USB3_PRX_DTX_N1 <23>
<45> USB_PWR_SHR_RHT_EN3# 56 55 SPKR <23> <45> RTD3_USB_PWR_EN RTD3_CIO_PWR_EN 92 91 89 USB3_PRX_DTX_P1
58 57 90 USB3_PRX_DTX_P1 <23>
60 58 57 59 <22,45> RTD3_CIO_PWR_EN TBT_DP0_HPD 88 90 89 87
+RTC_CELL 60 59 CLK_PCIE_P1 <21> <34> SW4_DP_HPD SW5_DP_HPD 88 87 85
62 61 86
+3.3V_ALW 62 61 CLK_PCIE_N1 <21> <33> SW5_DP_HPD MID2_CA_DET 86 85 83 USB20_N1 <20>
64 63 84
+3.3V_RUN 64 63 <33> MID2_CA_DET TBT_PWR_EN 84 83 81 USB20_P1 <20>
66 65 82
66 65 CLKREQ_PCIE#1 <21> <45> TBT_PWR_EN USB_OC0# 82 81 79 TRIN_DOCK_DET
68 67 80
68 67 MEDIACARD_IRQ# <22> <20> USB_OC0# USB_PWR_SHR_LFT_EN# 80 79 77 TCABLE_ID TRIN_DOCK_DET <45>
70 69 78 TCABLE_ID <46>
C 70 69 PLTRST_MMI# <22> <45> USB_PWR_SHR_LFT_EN# USB_PWR_SHR_VBUS_LFT_EN 78 77 75 C
72 71 USB GPIO/OC 76
72 71 HOST_SD_WP# <24> <45> USB_PWR_SHR_VBUS_LFT_EN 76 75 73 DOCK_TNY_SMB_DAT <43,46>
74 73 <18,46> UPD_GPU_SMBDAT 74
76 74 73 75 HDA_BIT_CLK_R <23> 72 74 73 71 DOCK_TNY_SMB_CLK <43,46>
76 75 HDA_SDIN0 <23> <18,46> UPD_GPU_SMBCLK 72 71 69 TDOCK_BATLOW# DOCK_TNY_SMBUS_ALRT# <43,45,50>
78 77 <45> UPD_SMBUS_ALERT# 70
+5V_ALW 78 77 HDA_SDOUT_R <23> 70 69 67 LPS_PROTECT# TDOCK_BATLOW# <45>
80 79 68
80 79 HDA_SYNC_R <23> <45> 5VUSB_OFF 68 67 65 DOCK_5V_IS LPS_PROTECT# <45>
82 81 PD GPIO/SMBUS 66
82 81 HDA_RST#_R <23> <45> PWR_SRC_ON 66 65 63 UPD_EN1_4# DOCK_5V_IS <45>
84 83 64
84 83 DAI_12MHZ# <43> <46,50,57> PBAT_PRES# 64 63 61 UPD_EN1_4# <45>
86 85 62
86 85 DOCK_HP_DET <45> <23,37,46> SIO_SLP_S5# 62 61 59 EN_PIC_LDO <45>
88 87 60
88 87 DOCK_MIC_DET <45> <46> TDOCK_PWR_BTN# 60 59 57 MID1_CA_DET <32,34> Add for PS8407
90 89 Miramar17 only 58
92 90 89 91
AUD_HP_NB_SENSE <45> <45,47> LID_CL#
56 58 57 55 +5V_RUN (LS-C552P)
92 91 <45> DETECT_PWR_EN 56 55 53
94 93 54 +5V_ALW
94 93 <45> SS1_ON 54 53 51
96 95 52
96 95 +5V_RUN +3.3V_RUN 52 51 49
98 97 50
100 98 97 99 48 50 49 47
100 99 +3.3V_ALW2 48 47 45
+3.3V_ALW
46
102 101 44 46 45 43
GND GND 42 44 43 41
FOX_QT50A01-29100-9H 40 42 41 39
38 40 39 37
36 38 37 35
Footprint change to "-S" <57>
<45>
DCIN_ACOK#
PD_ACE_DET#
1 2 34 36 35 33
@ R388 0_0402_5% 32 34 33 31
30 32 31 29
28 30 29 27
26 28 27 25
+SDC_IN 26 25 23
24
22 24 23 21
22 21 19 +NBDOCK_DC_IN_SS
20 +DC_IN_SS
+5V_RUN +5V_ALW +3.3V_RUN +3.3V_ALW 18 20 19 17
18 17 15 +VBUS_DC_SS
16
16 15 13 +PWR_SRC
14
14 13 11
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
12
10 12 11 9
1 1 1 1 10 9 7
@ C763
@ C721
@ C722
@ C723
B 8 B
6 8 7 5
4 6 5 3
2 2 2 2 2 4 3 1
2 1
FOX_QT50A61-29100-9H
CONN@
Footprint change to "-S"
+5V_RUN +5V_ALW +3.3V_RUN +3.3V_ALW +NBDOCK_DC_IN_SS +PWR_SRC +SDC_IN
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1 1 1 1 1 1 1 1 1 1 1
@ C766
@ C724
@ C1431
@ C725
@ C726
@ C1430
@ C1425
@ C1426
@ C1427
@ C1428
@ C1456
Power Button CONN Power Switch for 2 2 2 2 2 2 2 2 2 2 2
debug
JPB1
POWER_SW#_MB 1
2 1
+5V_ALW 2
3 1 2
3 <37,46> POWER_SW#_MB 1 2
100P_0402_50V8J
4
<47> BREATH_WHITE_LED 4
5 1
5
@ C759
6
6 @ SW1
A POWER_SW#_MB A
7 @ PWRSW1 2 1
8 GND 2 @SHORT PADS~D
GND
ACES_50228-0067N-001 4 3
CONN@
Place on Bottom
SKRBAAE010_4P
Link CIS OK DELL CONFIDENTIAL/PROPRIETARY
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT IO / PWR Button

5 4 3 2 1
5 4 3 2 1
+3.3V_ALW
1 2 USB_PWR_SHR_LFT_EN# +3.3V_ALW_U46 +3.3V_ALW

RE72 100K_0402_5% @ PJP12
1 2 USB_PWR_SHR_RHT_EN1# PAD-OPEN1x1m
RE69 100K_0402_5% 2 1
1 2 USB_PWR_SHR_RHT_EN2#
0.1U_0402_25V6K
0.1U_0402_25V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
RE70 100K_0402_5% SHORT DEFAULT
1 2 USB_PWR_SHR_RHT_EN3# 1 1
RE71 100K_0402_5% 1 1 1 1
WWAN_RADIO_DIS#
C710
C709
C708
C717
C718
C719
1 2
RE14 100K_0402_5%
1 2 DOCK_TNY_SMBUS_ALRT# 2 2
D R763 10K_0402_5% 2 2 2 2 D
1 2 HW_GPS_DISABLE#
R779 10K_0402_5%
1 2 SLICE_BAT_PRES#
A17
B30
A43
A54
CIS LINK OK
B5
R2158 100K_0402_5%
1 2 PCIE_WAKE# U46
R759 10K_0402_5%
VCC1
VCC1
VCC1
VCC1
VCC1
1 2 WWAN_WAKE# A23 TBT_PWR_EN
R773 10K_0402_5% @ R3748 1 2 10K_0402_5% B52 GPIOI0 B63 SS1_ON TBT_PWR_EN <44>
2 1 UPD_SMBUS_ALERT# RTD3_CIO_PWR_EN A49 GPIOA0 GPIOI1 A60 PD_ACE_DET# SS1_ON <44>
R3740 100K_0402_5% <22,44> RTD3_CIO_PWR_EN LAN_DISABLE#_R B53 GPIOA1 GPIOI2/TACH0 A61 PROCHOT_GATE PD_ACE_DET# <44>
<35> LAN_DISABLE#_R AC_DIS GPIOA2 GPIOI3 PROCHOT_GATE <57>
RP9 A50 B65
SLOT2_CONFIG_0 <50,60> AC_DIS LID_CL_SIO# GPIOA3 GPIOI4 PLTRST_USH#_EC
1 8 B54 A62
2 7 SLOT2_CONFIG_1 DOCK_TNY_SMBUS_ALRT# A51 GPIOA4 GPIOI5 B66 LPS_PROTECT# PLTRST_USH#_EC <22>
3 6 SLOT2_CONFIG_2 <43,44,50> DOCK_TNY_SMBUS_ALRT# B55 GPIOA5 GPIOI6 A63 LPS_PROTECT# <44>
4 5 SLOT2_CONFIG_3 GPU_PWR_LEVEL A52 GPIOA6 GPIOI7 DOCK_AC_OFF_EC <60>
<18> GPU_PWR_LEVEL GPIOA7 B67 AUX_EN_WOWL
100K_0804_8P4R_5% USB_PWR_SHR_RHT_EN2# A33 GPIOJ0 A64 ME_FWP_EC AUX_EN_WOWL <40>
<44> USB_PWR_SHR_RHT_EN2# EN_I2S_NB_CODEC# GPIOB0 GPIOJ1/TACH1 ME_FWP_EC <23>
B36 A5
<44> EN_I2S_NB_CODEC# GPIOB1 GPIOJ2/TACH2
1 2USB_PWR_SHR_VBUS_LFT_EN USH_PWR_STATE# A34 B6 AAEN
<37> USH_PWR_STATE# EN_DOCK_PWR_BAR GPOC2 GPIOJ3 GPIO_PSID_SELECT AAEN <28>
RE73 100K_0402_5% B37 A6
<60> EN_DOCK_PWR_BAR GPOC3 GPIOJ4 GPIO_PSID_SELECT <50>
1 2USB_PWR_SHR_VBUS_RHT_EN1 HW_GPS_DISABLE# A35 B7 DP2_GPU_SEL#
<38> HW_GPS_DISABLE# PANEL_BKEN_EC GPOC4 GPIOJ5 DOCK_HP_DET DP2_GPU_SEL# <33>
RE74 100K_0402_5% B38 A7
<30> PANEL_BKEN_EC GPOC5 GPIOJ6 DOCK_HP_DET <44>
1 2USB_PWR_SHR_VBUS_RHT_EN2 LCD_TST A36 B8 DOCK_MIC_DET
<30> LCD_TST PSID_DISABLE# GPOC6/TACH4 GPIOJ7 DOCK_MIC_DET <44>
RE75 100K_0402_5% A37
1 2USB_PWR_SHR_VBUS_RHT_EN3 <50> PSID_DISABLE# SLOT4_SSD_PWR_EN B40 GPIOC7 A8 USB_PWR_SHR_LFT_EN#
<40> SLOT4_SSD_PWR_EN GPIOD0 GPIOK0 MASK_SATA_LED# USB_PWR_SHR_LFT_EN# <44>
RE76 100K_0402_5% DOCKED A38 B9
PD_ACE_DET# <35> DOCKED DOCK_DET# GPIOC1 GPIOK1/TACH3 PCIE_WAKE# MASK_SATA_LED# <47>
1 2 B41 B10
<43> DOCK_DET# AUD_NB_MUTE# GPIOC0 GPIOK2 LED_SATA_DIAG_OUT# PCIE_WAKE# <18,38,39,44>
RE77 100K_0402_5% A39 A10
PROCHOT_GATE <44> AUD_NB_MUTE# 3.3V_WWAN_EN GPIOB7 GPIOK3 RTD3_USB_PWR_EN LED_SATA_DIAG_OUT# <47>
1 2 B42 B11
<40> 3.3V_WWAN_EN LCD_VCC_TEST_EN GPIOB6 GPIOK4 USB_PWR_SHR_VBUS_RHT_EN2 RTD3_USB_PWR_EN <44>
@ R415 100K_0402_5% A40 A11
<30> LCD_VCC_TEST_EN WWAN_WAKE# GPIOB5 GPIOK5 SLOT2_CONFIG_0 USB_PWR_SHR_VBUS_RHT_EN2 <44>
B43 B12
<38> WWAN_WAKE# AUD_HP_NB_SENSE GPIOB4 GPIOK6 USB_PWR_SHR_VBUS_RHT_EN3 SLOT2_CONFIG_0 <38>
A41 A12
<44> AUD_HP_NB_SENSE USB_PWR_SHR_RHT_EN1# GPIOB3 GPIOK7 USB_PWR_SHR_VBUS_RHT_EN3 <44>
B44
<44> USB_PWR_SHR_RHT_EN1# GPIOB2 B60 GPIOL0
C GPIOL0/PWM7 A57 C
+3.3V_RUN SLOT3_SSD_PWR_EN B32 GPIOL1/PWM8 B64
<40> SLOT3_SSD_PWR_EN SLICE_BAT_ON GPIOD1 GPIOL2/PWM0 WLAN_DISBL#
A31 B68
<60> SLICE_BAT_ON SLICE_BAT_PRES# GPIOD2 GPIOL3/PWM1 CCD_OFF WLAN_DISBL# <35>
B33 A9
<43,50,60> SLICE_BAT_PRES# TB_STAT# GPIOD3 GPIOL4/PWM3 PAD~D @ T213
RP3 <57> TB_STAT# B15 B1
D_CLKRUN# PBA_GPU_SEL# GPIOD4 GPIOL5/PWM2 SLOT2_CONFIG_1 PAD~D @ T165
1 8 A15 A18
D_SERIRQ <31> PBA_GPU_SEL# MXM_VGA_DIS# GPIOD5 GPIOL6 SLOT2_CONFIG_2 SLOT2_CONFIG_1 <38>
2 7 B16 A44
D_DLDRQ1# <18> MXM_VGA_DIS# USH_DET# GPIOD6 GPIOL7/PWM5 SLOT2_CONFIG_2 <38>
3 6 A16
DGPU_ALERT# <37> USH_DET# GPIOD7 SLOT2_CONFIG_3
4 5 B34
GPIOM1 SLOT2_CONFIG_3 <38>
B39
100K_0804_8P4R_5% WLAN_WIGIG60GHZ_DIS# A1 GPIOM3/PWM4 B51
2 1 GPU_PWR_LEVEL <38> WLAN_WIGIG60GHZ_DIS# EC5048_TX B2 GPIOE0/RXD GPIOM4/PWM6
R782 100K_0402_5% <46> EC5048_TX UPD_EN1_4# A2 GPIOE1/TXD
2 1 LPC_LDRQ1# <44> UPD_EN1_4# DETECT_PWR_EN B3 GPIOE2/RTS# A27 LPC_AD0
<44> DETECT_PWR_EN DOCK_5V_IS GPIOE3/DSR# LAD0 LPC_AD1 LPC_AD0 <23,46>
R783 100K_0402_5% A3 A26
<44> DOCK_5V_IS DGPU_PWR_EN GPIOE4/CTS# LAD1 LPC_AD2 LPC_AD1 <23,46>
B45 B26
M2_SLOT2_PCIE#_SATA <18> DGPU_PWR_EN DGPU_ALERT# GPIOE5/DTR# LAD2 LPC_AD3 LPC_AD2 <23,46>
1 2 A42 B25 RP4
<18> DGPU_ALERT# MXM_DP_HDMI_HPD GPIOE6/RI# LAD3 LPC_FRAME# LPC_AD3 <23,46>
RH318 10K_0402_5% B4 A21 1 8
<18> MXM_DP_HDMI_HPD GPIOE7/DCD# LFRAME# PCH_PLTRST#_EC LPC_FRAME# <23,46> LCD_TST
B22 2 7
USH_DET# LRESET# CLK_PCI_5048 PCH_PLTRST#_EC <22,38,39,46> SLICE_BAT_ON
1 2 A28 3 6
TRIN_DOCK_DET PCICLK CLK_PCI_5048 <23> MXM_DP_HDMI_HPD
R379 10K_0402_5% A59 B20 CLKRUN# 4 5
<44> TRIN_DOCK_DET BCM5882_ALERT# GPIOF0 CLKRUN# CLKRUN# <23,46>
B62
<37> BCM5882_ALERT# UPD_SMBUS_ALERT# GPIOF1 LPC_LDRQ1#
A58 A22 100K_0804_8P4R_5%
<44> UPD_SMBUS_ALERT# GPIOF2 LDRQ1# IRQ_SERIRQ
B61 B21
DGPU_PWROK GPIOF3/TACH8 SER_IRQ CLK_SIO_14M IRQ_SERIRQ <23,46>
A56 A32
<18,23> DGPU_PWROK VGA_ID GPIOF4/TACH7 14.318MHZ/GPIOM0 EC_32KHZ_ECE5048 PAD~D @ T214
B59 B35
3.3V_RUN_GFX_ON GPIOF5 CLK32/GPIOM2 EC_32KHZ_ECE5048 <46>
A55
<21,49> 3.3V_RUN_GFX_ON TDOCK_BATLOW# GPIOF6
B58
<44> TDOCK_BATLOW# GPIOF7 D_LAD0
B29 GPIOL0 1 2
DLAD0 B28 D_LAD1 D_LAD0 <43>
DLAD1 D_LAD2 D_LAD1 <43> Reserve only @ R3741 100K_0402_5%
B47 A25
M2_SLOT2_PCIE#_SATA A45 GPIOG0/TACH5 DLAD2 A24 D_LAD3 D_LAD2 <43>
SYS_LED_MASK# B48 GPIOG1 DLAD3 B23 D_LFRAME# D_LAD3 <43>
<35,47> SYS_LED_MASK# 5VUSB_OFF GPIOG2 DLFRAME# D_CLKRUN# D_LFRAME# <43> SYS_LED_MASK#
A46 A19 2 1
<44> 5VUSB_OFF DP1_GPU_SEL# GPIOG3 DCLKRUN# D_DLDRQ1# D_CLKRUN# <43>
B <34> DP1_GPU_SEL# B49 B24 R775 10K_0402_5% B
EN_PIC_LDO GPIOG4 DLDRQ1# D_SERIRQ D_DLDRQ1# <43>
A47 A20
<44> EN_PIC_LDO USB_PWR_SHR_VBUS_LFT_EN GPIOG5 DSER_IRQ D_SERIRQ <43> PROCHOT_GATE
B50 1 2
+3.3V_ALW <44> USB_PWR_SHR_VBUS_LFT_EN GC6_THM_ON GPIOG6
A48 R416 100K_0402_5%
<19> GC6_THM_ON GPIOG7/TACH6 BC_INT#_ECE5048
Tell EC don't read GFX Temp.in GC6 A29
BC_INT# BC_DAT_ECE5048 BC_INT#_ECE5048 <46>
B31
High: Read; Low: Don`t read PWR_SRC_ON BC_DAT BC_CLK_ECE5048 BC_DAT_ECE5048 <46>
100K_0402_5%
B13 A30
<44> PWR_SRC_ON GPIOH0 BC_CLK BC_CLK_ECE5048 <46>
1
BT_RADIO_DIS# A13
<38> BT_RADIO_DIS# WWAN_RADIO_DIS# GPIOH1
@ R800
A53
<38> WWAN_RADIO_DIS# SYSOPT1/GPIOH2
B57 A4 RUNPWROK
DGPU_SELECT# SYSOPT0/GPIOH3 PWRGD RUNPWROK <46>
B14
<29,30> DGPU_SELECT# SIO_SLP_WLAN# GPIOH4
A14 B56
<23,40> SIO_SLP_WLAN#
2
USB_PWR_SHR_RHT_EN3# B17 GPIOH5 OUT65

<44> USB_PWR_SHR_RHT_EN3# USB_PWR_SHR_VBUS_RHT_EN1 GPIOH6
B18
VGA_ID <44> USB_PWR_SHR_VBUS_RHT_EN1 GPIOH7 B19 1 2
TEST_PIN R804 1K_0402_1%
B46 +CAP_LDO
CAP_LDO
100K_0402_5%
4.7U_0603_6.3V6K
1
B27
VGA_ID0 VSS 1
R803
C1
EP
C714
Discrete 0 DB Version 0.4
ECE5048-LZY_DQFN132_11X11~D 2
UMA 1
2
+3.3V_ALW
CLK_PCI_5048 +CAP_LDO trace width 20

mils
100K_0402_5%
1
1
10_0402_1%
R805
@ R795
A A
2
LID_CL_SIO# 2 1
LID_CL# <44,47>
R807 10_0402_1%
4.7P_0402_50V8C
0.047U_0402_16V4Z
1 1
@ C713
C716
2 2 Compal Electronics, Inc.

SIO (ECE5048)
LA-C551P 1.0

5 4 3 2 1
5 4 3 2 1
+RTC_CELL
+RTC_CELL
100K_0402_5%
1
100K_0402_5%
1
R819
@ C733
R810
@ C1354 1 2
1 2
1U_0402_6.3V6K
2
1U_0402_6.3V6K
2
DOCK_PWR_SW# 1 2
POWER_SW_IN# 1 2 DOCK_PWR_BTN# <43>
+RTC_CELL R825 10K_0402_5%
POWER_SW#_MB <37,44>
1U_0402_6.3V6K
R811 10K_0402_5% 1
+RTC_CELL_VBAT
1U_0402_6.3V6K
1 2 1
C734
@ R1985 0_0402_5%
SIO_SLP_SUS# SIO_SLP_SUS#_R
0.1U_0402_25V6K
C1352
43K_0402_1% 2 1 R374
SIO_SLP_SUS#_R <23> 2
2
1
C1353
2
D
PN change from SA00006YH00 to SA00006YH90 D
U51
1 2 +3.3V_VTR +RTC_CELL
+3.3V_ALW_U51 PANEL_ID
@ R834 0_0402_5% B64 A10
+3.3V_ALW_U51 VBAT GPIO021/RC_ID1 BOARD_ID
0.1U_0402_25V6K
1U_0402_6.3V4Z
+3.3V_ALW B10
GPIO020/RC_ID2 B8 TCABLE_ID TDOCK_PWR_BTN# 2 1
1 1 GPIO014/GPTP-IN7/RC_ID3 LAN_WAKE# TCABLE_ID <44>
1 2 A22 B27 100K_0402_5% R870
H_VTR GPIO025/UART_CLK LAN_WAKE# <23,35>
C739
HOST_DEBUG_TX POA_WAKE#
C1349
@ R845 0_0402_5% B44 2 1
BC_DAT_ECE5048 GPIO120/UART_TX/V2P_COUT_HI1 PCH_PCIE_WAKE#
0.1U_0402_25V6K
1U_0402_6.3V4Z
1 2 B46 100K_0402_5% R880
2 2 +VTR_ADC GPIO124/GPTP-OUT5/UART_RX/V2P_COUT_LO1 PCH_PCIE_WAKE# <23>
R814 100K_0402_5% 1 1 A58 B26 RUNPWROK
1 2 BC_DAT_ECE1117 VTR_ADC VCC_PWRGD A25 EN_INVPWR RUNPWROK <45>
GPIO060/KBRST/BCM_B_INT# EN_INVPWR <30>
C736
SIO_SLP_S4#
C757
R817 100K_0402_5% B36 +3.3V_ALW
PN change to SD309220180 B3 GPIO101/ECGP_SCLK B37 SIO_SLP_LAN# SIO_SLP_S4# <11,23,37,52,54>
RP5
1 8 PBAT_SMBDAT 2 2 A11 VTR GPIO103/ECGP_MISO B38 SIO_SLP_LAN# <23,40>
2 7 PBAT_SMBCLK A26 VTR GPIO105/ECGP_MOSI A34 PCH_ALW_ON
CHARGER_SMBDAT +3.3V_ALW +3.3V_ALW_U51 VTR GPIO102/BCM_C_INT# SIO_SLP_S3# PCH_ALW_ON <49,58>
3 6 PJP@ B35 A35 SUSACK# 2 1
4 5 CHARGER_SMBCLK A41 VTR GPIO104/SLP_S0# A36 2 1@R802 SIO_SLP_S3# <7,11,23,37,44>
PJP13 0_0402_5% 10K_0402_5% @ R837
1 2 A52 VTR GPIO106 A40 PCH_DPWROK <23> AC_PRESENT 2 1
MSDATA
2.2K_8P4R_5% VTR GPIO116/MSDATA/V2P_COUT_LO/TAP_SEL_STRAP B43 MSCLK 10K_0402_5% R835
UPD_GPU_SMBDAT GPIO117/MSCLK/V2P_COUT_HI PCH_RSMRST# DOCK_TNY_SMB_DAT
10U_0603_6.3V6M
0.1U_0402_25V6K
0.1U_0402_25V6K
0.1U_0402_25V6K
0.1U_0402_25V6K
0.1U_0402_25V6K
0.1U_0402_25V6K
1 2 PAD-OPEN1x1m A45 2 1
GPIO127/A20M B65 PCH_RSMRST# <7>
R829 2.2K_0402_5% SHORT DEFAULT 1 1 1 1 1 1 1 FWP# 2.2K_0402_5% R838
1 2 UPD_GPU_SMBCLK SML1_SMBDATA A5 nFWP DOCK_TNY_SMB_CLK 2 1
<23> SML1_SMBDATA GPIO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA
C781
C1345
C1348
C1355
C777
C780
SML1_SMBCLK
C782
R822 2.2K_0402_5% B6 2.2K_0402_5% R841
<23> SML1_SMBCLK CLK_TP_SIO A37 GPIO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK/GANG_DATA0 B57 BREATH_LED#
2 2 2 2 2 2 2 <48> CLK_TP_SIO DAT_TP_SIO GPIO110/PS2_CLK2/GPTP-IN6 GPIO156/LED1/GANG_DATA1 BAT1_LED# BREATH_LED# <43,47>
B40 B1
<48> DAT_TP_SIO CLK_KBD A38 GPIO111/PS2_DAT2/GPTP-OUT6 GPIO157/LED0 A55 BAT2_LED# BAT1_LED# <47> trace width 20 mils
<43> CLK_KBD DAT_KBD B41 GPIO112/PS2_CLK1A GPIO153/LED2/GANG_DATA4 A1 IMVP_VR_ON_EC BAT2_LED# <47> trace width 20 mils
<43> DAT_KBD CLK_MSE GPIO113/PS2_DAT1A GPIO027/GPTP-OUT1 SIO_SLP_A# IMVP_VR_ON_EC <7>
A39 B28
<43> CLK_MSE DAT_MSE B42 GPIO114/PS2_CLK0A GPIO026/GPTP-IN1 B2 SIO_SLP_A# <23,37,49>
+5V_RUN
<43> DAT_MSE PBAT_SMBDAT GPIO115/PS2_DAT0A GPIO001/ECSPI_CS1/32KHZ_OUT EC_32KHZ_ECE5048 <45>
B59 A8
<50> PBAT_SMBDAT PBAT_SMBCLK A56 GPIO154/I2C1C_DATA/PS2_CLK1B/GANG_DATA5 GPIO015/GPTP-OUT7 B9 RUN_ON ME_SUS_PWR_ACK <23>
PN change to SD309470180 <50> PBAT_SMBCLK GPIO155/I2C1C_CLK/PS2_DAT1B/GANG_DATA6 GPIO016/GPTP-IN8 A9 CV2_ON RUN_ON <46,49>
RP6
DAT_KBD JTAG_TDI GPIO017/GPTP-OUT8 RESET_OUT# CV2_ON <37>
1 8 A51 B39
2 7 DAT_MSE JTAG_TDO B55 GPIO145/I2C1K_DATA/JTAG_TDI GPIO107/NRESET_OUT A44 VCCST_PWRGD_EC 1 RESET_OUT#
2 <7,23> +3.3V_ALW
3 6 CLK_KBD JTAG_CLK B56 GPIO146/I2C1K_CLK/JTAG_TDO GPIO125/GPTP-IN5/PECI_REQUEST#/GANG_BUSY @ R43 0_0402_5% VCCST_PWRGD <7>
4 5 CLK_MSE JTAG_TMS A53 GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK A54 AC_PRESENT @ C787
DOCK_POR_RST# JTAG_RST# B47 GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS GPIO151/GPTP-IN4/GANG_DATA2 B58 SIO_PWRBTN# AC_PRESENT <23> 1 2
JTAG_RST# GPIO152/GPTP-OUT4 SIO_PWRBTN# <7,23>
4.7K_0804_8P4R_5%
FAN1_TACH_EC B22 A3 DOCK_TNY_SMB_DAT 0.1U_0402_25V6
<28> FAN1_TACH_EC GPIO050/FAN_TACH1/GTACH0/GANG_START GPIO003/I2C1A_DATA DOCK_TNY_SMB_DAT <43,44>
5
DOCK_POR_RST# A21 B4 DOCK_TNY_SMB_CLK
<43> DOCK_POR_RST# FAN2_TACH_EC GPIO051/FAN_TACH2/GANG _MODE GPIO004/I2C1A_CLK DOCK_TNY_SMB_CLK <43,44> SIO_SLP_S3#
0.1U_0402_25V6K
B23 A4 1
P
<28> FAN2_TACH_EC
1
PS_ID B24 GPIO052/FAN_TACH3/GTACH1/GANG_ERROR GPIO005/I2C1B_DATA/BCM_B_DAT B5 0_0402_5% 2 1 @ R797 A_ON <49> IN1 4
<50> PS_ID FAN2_PWM_EC GPIO053/PWM0 GPIO006/I2C1B_CLK/BCM_B_CLK SIO_EXT_WAKE# <24> 1.2V_SUS_PWRGD O RUN_ON_AND <53>
C737
A23 B7 SUSACK# 2
<28> FAN2_PWM_EC GPIO054/PWM1/GPWM1 GPIO012/I2C1H_DATA/I2C2D_DATA SUSACK# <23> <52> 1.2V_SUS_PWRGD IN2
G
BIA_PWM_EC B25 A7 ENVDD_PCH U9
<30> BIA_PWM_EC FAN1_PWM_EC GPIO055/PWM2 GPIO013/I2C1H_CLK/I2C2D_CLK/GANG_DATA3 UPD_GPU_SMBDAT ENVDD_PCH <19,30>
A24 B48 SN74AHC1G08DCKR_SC70-5
<28> FAN1_PWM_EC UPD_GPU_SMBDAT <18,44>
3
2 GPIO056/PWM3/GPWM0 GPIO130/I2C2A_DATA/BCM_C_DAT B49 UPD_GPU_SMBCLK
GPIO131/I2C2A_CLK/BCM_C_CLK A47 CHARGER_SMBDAT UPD_GPU_SMBCLK <18,44>
GPIO132/I2C1G_DATA CHARGER_SMBCLK CHARGER_SMBDAT <57>
B50
BC_CLK_ECE5048 A43 GPIO140/I2C1G_CLK B52 SIO_SLP_SUS# CHARGER_SMBCLK <57>
<45> BC_CLK_ECE5048 BC_DAT_ECE5048 B45 GPIO123/BCM_A_CLK GPIO141/I2C1F_DATA/I2C2B_DATA A49 PBAT_PRES# SIO_SLP_SUS# <11,49,58,59>
<45> BC_DAT_ECE5048 BC_INT#_ECE5048 GPIO122/BCM_A_DAT GPIO142/I2C1F_CLK/I2C2B_CLK USH_SMBDAT PBAT_PRES# <44,50,57>
C A42 B53 C
Place close pin <45> BC_INT#_ECE5048 ACAV_IN_NB B20 GPIO121/BCM_A_INT# GPIO143/I2C1E_DATA A50 USH_SMBCLK USH_SMBDAT <28,37>
1 2 MSDATA A21 <57,60> ACAV_IN_NB SIO_SLP_S5# A18 GPIO032/BCM_E_CLK GPIO144/I2C1E_CLK USH_SMBCLK <28,37>
<23,37,44> SIO_SLP_S5# B19 GPIO031/GPTP-OUT2/BCM_E_DAT A59 SYSPWR_PRES 1 2
R869 10K_0402_5% BEEP
<44> BEEP BC_CLK_ECE1117 GPIO030/GPTP-IN2/BCM_E_INT#/GANG_DATA7 SYSPWR_PRES +3.3V_ALW2
100K_0402_5%
RP7 A20 R874 1K_0402_5%
<48> BC_CLK_ECE1117 GPIO047/LSBCM_D_CLK
1
1 8 DOCK_POR_RST# BC_DAT_ECE1117 B21 B62 EC_FPM_EN
2 7 PCH_ALW_ON <48> BC_DAT_ECE1117 BC_INT#_ECE1117 A19 GPIO046/LSBCM_D_DAT/GANG_STROBE BGP0 A64 ACAV_IN EC_FPM_EN <37>
EN_INVPWR <48> BC_INT#_ECE1117 GPIO045/LSBCM_D_INT# VCI_OVRD_IN ACAV_IN <18,57,60>
3 6 A60 ALWON
SIO_EXT_SMI# VCI_OUT POWER_SW_IN# ALWON <51> +3.3V_ALW
R876
4 5 A6 B67
<22> SIO_EXT_SMI# SIO_RCIN# GPIO011/nSMI VCI_IN0# DOCK_PWR_SW#
A27 A63
2
<23> SIO_RCIN# IRQ_SERIRQ A28 GPIO061/LPCPD# VCI_IN1# B63 TDOCK_PWR_BTN#
100K_0804_8P4R_5%
<23,45> IRQ_SERIRQ SER_IRQ VCI_IN2# TDOCK_PWR_BTN# <44>
1
PCH_PLTRST#_EC POA_WAKE#
8.2K_0402_5%
B30 B68
RESET_OUT# <22,38,39,45> PCH_PLTRST#_EC CLK_PCI_MEC LRESET# VCI_IN3# POA_WAKE# <37>
R396
1 2 A29 R866 close to U51 at least
<23> CLK_PCI_MEC LPC_FRAME# B31 PCI_CLK B51 +PECI_VREF
@ R843 8.2K_0402_5%
<23,45> LPC_FRAME# LPC_AD0 LFRAME# VREF_PECI PECI_EC_R
250mils 1 2
+1.0V_RUN
A30 A48 1 2 @ R866 0_0402_5%
<23,45> LPC_AD0 LPC_AD1 LAD0 PECI_DAT H_PECI <7,19>
0.1U_0402_25V6K
B32 R953 33_0402_5% 1
<23,45> LPC_AD1
2
1 2 PCH_RSMRST# LPC_AD2 A31 LAD1 B13 REM_DIODE1_N C1343 1 2 2200P_0402_50V7K
<23,45> LPC_AD2 LPC_AD3 LAD2 DN1_DP1A/THERM REM_DIODE1_P
C740
R892 10K_0402_5% B33 A13
1 2 A_ON <23,45> LPC_AD3 A32 LAD3 DP1_DN1A/VREF_T B14 REM_DIODE2_N +VCC_IO SIO_SLP_S3#
CLKRUN# C1350 1 2 2200P_0402_50V7K
<23,45> CLKRUN# SIO_EXT_SCI# A33 CLKRUN# DN2_DP2A A14 REM_DIODE2_P 2
R432 47K_0402_5% THERMATRIP2#
RUN_ON <24> SIO_EXT_SCI# GPIO100/NEC_SCI DP2_DN2A REM_DIODE3_N
1 2 A15 C1351 1 2 2200P_0402_50V7K
MEC_XTAL1 DN3_DP3A REM_DIODE3_P
MMBT3904WT1G_SC70-3
0.1U_0402_25V6K
R3730 100K_0402_5% A61 B16 1
XTAL1 DP3_DN3A
2
MEC_XTAL2 MEC_XTAL2_R REM_DIODE4_N
C327
2 1 A62 A16 C1346 1 2 2200P_0402_50V7K
G
XTAL2 DN4_DP4A
1
@ R1068 0_0402_5% B17 REM_DIODE4_P C
DP4_DN4A
Q28
B15 PAD~D @ T155 C1343, C1350, C1351, C1346 Place 1 3 1 R399 2 2
VIN A17 VSET_5085 2.2K_0402_5% B 2
S
VSET A12 I_ADP_R 2 1 I_ADP near U51 @ Q370 E
I_ADP <57>
3
+3.3V_ALW VCP B34 THERMATRIP2# R134 4.7K_0402_5% DMN65D8LW-7_SOT323-3
THERMTRIP2# A2 THERMATRIP3#
GPIO002/THERMTRIP3# THSEL_STRAP THERMATRIP3# <18>
B29 1 2
VSS_ADC
GPIO024/THSEL_STRAP H_PROCHOT#
VSS_RO
VR_CAP
A46 R435 0_0402_5%
H_VSS
CLK_PCI_MEC PROCHOT_IN#/PROCHOT_IO# I_BATT H_PROCHOT# <7,57,61,64>
AGND
100K_0402_5%
B61
I_BATT <57>
VSS
V_ISYS0
1
R1981
A57
EP
32 KHz Clock V_ISYS1 <7,14,15,16,17,19> PCH_THERMTRIP#
1
10_0402_1%
@ R885
MEC5085-LZY_DQFN132_11X11
B66
B11
B60
+VR_CAP B12
B54
B18
C1
Y6
MEC_XTAL1 1 2 MEC_XTAL2
2
15mil
Channel Location
2
4.7P_0402_50V8C
27P_0402_50V8J
33P_0402_50V8J
JTAG_RST# 32.768KHZ_12.5PF_Q13FC135000040 THSEL_STRAP 1 2
C292 Place near U51.A48
1 1
PECI_EC_R
C743
4.7U_0603_6.3V6K
R1069 1K_0402_5% 1 2
1 DP1/DN1 CPU
C741
1 @ C292 47P_0402_50V8J
1
OTP
@ C747
2 2
1U_0402_6.3V6K
C779
DP1a/DN1a CPU
1
2
JTAG1 CONN@
@SHORT PADS~D
100_0402_1%
1 2
VR
@
1: Channel 1 will provide Thermistor

C735
R836
Place close pin ESR Readings DP2/DN2 MXM(TOP)

2
A29 <2ohms 0: Channel 1 will provide Diode Readings
2
B DP2a/DN2a M.2 2280 B

2
2
DP3/DN3 DIMM(TOP)
DP4/DN4 WWAN
+3.3V_ALW +3.3V_ALW
VSET_5085
+3.3V_ALW
0.1U_0402_25V6K
R3754 C1465 REV

6.2K_0402_5%
4.3K_0402_5%
R875 C744 REV
1
1
1.33K_0402_1%
1
240K 4700p 12"
R425
R875
240K 4700p X00 EVT

C320
10K_0402_5%
49.9_0402_1%
10K_0402_5%
10K_0402_5%
10K_0402_5%
R3754
130K 4700p 14"
1
+3.3V_ALW
2 130K 4700p X01 DVT1.0 DP1/DN1 for CPU OTP on Q16, place Q16
R864
R858
R859
R860
R861
33K 4700p 15"

2
2
BOARD_ID 33K 4700p X02 DVT1.1 PANEL_ID
close to CPU and C273 close to Q16.
* 4.3K 4700p 17"
1
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
100K_0402_5%
4.3K 4700p X03 DVT1.2 DN1a/DP1a for CPU VR on Q26, place Q26 DP3/DN3 for SODIMM(TOP) on Q14,
2
@ R850
4700P_0402_25V7K
4700P_0402_25V7K
JDEG2
Rest=1.33k, Tp=93degree 2K 4700p *** close to CPU and C339 close to Q26 place Q14 close to SODIMM(TOP) and C272 close
R847
R848
R849
1
1 2 JTAG_TDI
1
2K 4700p X04 DVT2.0 1
2 JTAG_TMS 1K 4700p *** REM_DIODE1_P to Q14 REM_DIODE3_P
C744
C1465
3
1K 4700p X05 DVT2.1
2
3 JTAG_CLK
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
4
4 5 JTAG_TDO 2 2 MMBT3904WT1G_SC70-3
5
* 62K 4700p A00 Pilot 2 1 1
1
@ C339
@ C273
@ C272
6
E
MSCLK Q26 C C
6 7 MSDATA 2
B
2 2
7
8
8 HOST_DEBUG_TX 8.2K 4700p 1 2
B
2
B
9 R862 1 2 0_0402_5% EC5048_TX
C
E Q16 E Q14
EC5048_TX <45>
3
9 10 @ R863 1 2 0_0402_5% SBIOS_TX MMBT3904WT1G_SC70-3 MMBT3904WT1G_SC70-3
10 SBIOS_TX <24> REM_DIODE1_N REM_DIODE3_N
11
GND1 12
GND2 DP2/DN2 for MXM(TOP side) on Q27, place Q27
BOARD_ID rise time is measured from 5%~68%. close to MXM(TOP side) and C291 close to Q27. DP4/DN4 for WWAN on Q15,
ACES_50506-01041-P01 place Q15 close to WiGig and C288 close to
CONN@
DN2a/DP2a for M.2 2280 on Q17, place Q17 Q15 REM_DIODE4_P
CIS link +3.3V_RUN close to M.2 2280 and C340 close to Q17
100P_0402_50V8J
REM_DIODE2_P
OK
10K_0402_5%
100P_0402_50V8J
100P_0402_50V8J
@ C288
1
1
1
@ C291
1 MMBT3904WT1G_SC70-3 1 C
1
RE67
@ C340
E
Q17 C 2
+3.3V_ALW 2
B
2 B
B 2 E Q15
3
CONN@ +3.3V_RUN +3.3V_ALW 2 C 2 E Q27 MMBT3904WT1G_SC70-3
2
3
100K_0402_5%
A JLPDE1 MMBT3904WT1G_SC70-3 A
1
1 CLK_PCI_LPDEBUG RUNPWROK REM_DIODE2_N REM_DIODE4_N

1
10K_0402_5%
RE68
2
2
1
3 LPC_AD0
3
1
LPC_AD1
10_0402_1%
R872
4
4 LPC_AD2
@ R3757
5
2
5 LPC_AD3
QE2B
6
6 7 LPC_FRAME# RUN_ON# 5
2
7 8 PCH_PLTRST#_EC
2
8
6
9 FWP#
4
9 10 CLK_PCI_LPDEBUG
10 CLK_PCI_LPDEBUG <23>
QE2A
2
4.7P_0402_50V8C
10K_0402_5%
2
GND1
11 1
<46,49> RUN_ON
@ C1469
@ R879
12
1
GND2
PROPRIETARY NOTE:
1
ACES_50506-01041-P01 2 Title
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
CIS link TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS
DOCUMENT MAY NOT
KBC (MEC5085)
OK BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL.
1.0
TO ANY THIRD
5 4 3 PARTY WITHOUT DELL'S
2 EXPRESS WRITTEN CONSENT. 1
5 4 3 2 1
HDD LED
+3.3V_RUN
R383
1 2
10K_0402_5%
+3.3V_ALW
Breath LED
10K_0402_5%
1 2
<19> PCH_SATA_LED#
1
D97 RB751S40T1G_SOD523-2
R932
+3.3V_SSD1 1 2
R384 10K_0402_5% Q359
D <39> SLOT3_SATA_LED#
1 2 DMN65D8LW-7_SOT323-3 BREATH_LED TOP view. D
D98 RB751S40T1G_SOD523-2
2
1 2 3 1 1 2 BREATH_WHITE_LED
D
+3.3V_SSD2 Q74B BREATH_WHITE_LED <44>
<43,46> BREATH_LED#
R385 10K_0402_5% DMN66D0LDW-7_SOT363-6 R956 1K_0402_5%
1 2 4 3
<39> SLOT4_SATA_LED#
D99 RB751S40T1G_SOD523-2
G
2
+3.3V_RUN 1 2 +5V_ALW
R387 10K_0402_5% MASK_BASE_LEDS#
5
1 2
<41> SATAE_LED#
D100 RB751S40T1G_SOD523-2
3
1 2 BREATH_LED#_Q
Q74A Q86 R955 1K_0402_1%
<45> MASK_SATA_LED# D62
<45> LED_SATA_DIAG_OUT#
1 2 1 6 2
DDTA114EUA-7-F_SOT323-3
BREATH_LED side view.
RB751S40T1G_SOD523-2
1
SYS_LED_MASK#
1 2 SATA_SIDE_LED
R943 1K_0402_5%
BATT LED
C
LED Circuit Control Table C
SYS_LED_MASK# LID_CL#
BAT2_LED# 1 2 BATT_WHITE_LED
<46> BAT2_LED#
R130 560_0402_5%
Mask All LEDs (Sniffer Function) 0 X
Mask Base MB LEDs (Lid Closed) 1 0
Do not Mask LEDs (Lid Opened) 1 1
BAT1_LED# 1 2 BATT_YELLOW_LED
<46> BAT1_LED#
R131 560_0402_5%
To LED/B Conn
B +3.3V_ALW B
+5V_ALW
@ C778
1 2
0.1U_0402_25V6K
0.1U_0402_10V6K
U58 1
5
SYS_LED_MASK#
C6
1
P
<35,45> SYS_LED_MASK# IN1 MASK_BASE_LEDS# 2
4
LID_CL# 2 O
<44,45> LID_CL# IN2
G
JLED1
Fiducial Mark
3
1
@ FD1 @ H2 @ H7 @ H8 @ H9 @ H11 @ H14 BREATH_LED#_Q 2 1
1 H_3P0 H_2P8 H_3P0 H_3P0 H_3P8 H_3P8 BATT_YELLOW_LED 3 2 2
BATT_WHITE_LED 4 3
FIDUCIAL MARK~D SATA_SIDE_LED 5 4 4
6 5
1
@ FD2 6 6
1 7
G1 8
FIDUCIAL MARK~D G2 9
G3 10
@ FD3 G4
1 @ H16 @ H17 @ H18 @ H19 @ H20 @ H21 @ H22 @ H23 @ H24 @ H26 @ H27 @ H28 @ H29 ACES_50554-00641-001
H_3P0 H_3P8 H_3P0 H_3P8 H_3P0 H_3P0 H_3P0 H_2P0N H_3P0 H_5P2 H_3P3 H_3P3 H_5P2 CONN@
FIDUCIAL MARK~D
A A
@ FD4
CIS link OK
1
FIDUCIAL MARK~D DELL CONFIDENTIAL/PROPRIETARY

@ H32 @ H33 @ H34 @ H35 @ H36 @ H37 @ H38 @ H39 @ H40 @ H41 @ H42 @ H43 @ H44 @ H10
H_3P3 H_1P15 H_1P15 H_3P8 H_3P8 H_3P8 H_3P8 H_3P3 H_3P0 H_3P0 H_1P2 H_1P2 H_2P8 H_2P8X2P0 Compal Electronics, Inc.
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, LED / Screw hole
1
1.0
LA-C551P
5 4 3 2 1
5 4 3 2 1
Touch Pad Keyboard

+3.3V_RUN +3.3V_TP JKBTP1
+3.3V_TP 1
PJP@ <24> KB_DET# 2 1
PJP14 3 2 2
1 2 4 3
5 4 4
4.7K_0402_5%
4.7K_0402_5%
+5V_RUN
6 5
1
D PAD-OPEN1x1m +3.3V_ALW D
7 6 6
RZ18
RZ19
<46> BC_INT#_ECE1117 8 7
<46> BC_DAT_ECE1117 9 8 8
10 9
2
<46> BC_CLK_ECE1117 11 10 10
DAT_TP_SIO 12 11
<46> DAT_TP_SIO +3.3V_TP DAT_TP_SIO 13 12 12
CLK_TP_SIO CLK_TP_SIO 14 13
<46> CLK_TP_SIO 15 14 14
16 15
<22> TOUCHPAD_INTR# 17 16 16
330P_0402_50V8J
EMC@ CZ30
330P_0402_50V8J
EMC@ CZ31
I2C_1_SDA_R 18 17
19 18 18
1
I2C_1_SCL_R
20 19
20 20
2
21
G1 22
G2 23
G3 24
G4
ACES_50559-02001-001
EMI depop CIS link OK
location
+3.3V_TP +3.3V_ALW +5V_RUN
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
1
1
+3.3V_TP +3.3V_TP
@ C1410
@ C1414
@ C1411
2
2
4.7K_0402_5%
4.7K_0402_5%
10K_0402_5%
10K_0402_5%
C C
1
RZ36
RZ37
RZ115
RZ114
Place close to JKBTP1
2
2
I2C_1_SDA @ R3752 1 2 0_0402_5% I2C_1_SDA_R
<24> I2C_1_SDA
I2C_1_SCL @ R3758 1 2 0_0402_5% I2C_1_SCL_R
<24> I2C_1_SCL
B B
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, KB / TP / RSMRST#
LA-C551P 1.0

5 4 3 2 1
5 4 3 2 1
+3.3V_ALW to +3.3V_MXM
+3.3V_M Source +5V_ALW to +5V_MXM
+5V_MXM_PWR +5V_MXM
+3.3V_M_PWR +3.3V_M UZ26
@ UZ2 +5V_ALW
1 14 @ PJP20
@ PJP19 2 VIN1 VOUT1 13 +5V_MXM_PWR 2 1
1 2 1 7 +3.3V_M_PWR 2 1 VIN1 VOUT1 2 1
<46> A_ON +3.3V_ALW VIN VOUT 2 1 1
10U_0603_6.3V6M
C357
@ R878 0_0402_5% 2 8 3 12 JUMP_43X79
VIN VOUT <21,45> 3.3V_RUN_GFX_ON ON1 CT1
10U_0603_6.3V6M
JUMP_43X79
D 1 2 A_ON_R 3 6 4 11 D
<23,37,46> SIO_SLP_A# ON CT 1 +5V_ALW VBIAS GND 2 +3.3V_MXM_PWR +3.3V_MXM
@ C513
@ R877 0_0402_5%
5 10
ON2 CT2
470P_0402_50V7K
4 2 @ PJP21
+5V_ALW VBIAS 2 +3.3V_MXM_PWR
@ C547
5 +3.3V_ALW 6 9 2 1
GND 9 7 VIN2 VOUT2 8 2 1
GND VIN2 VOUT2
10U_0603_6.3V6M
JUMP_43X79
1
470P_0402_50V7K
470P_0402_50V7K
15 2 2 1
GPAD
C764
AOZ1336_DFN8_2X2
C542
C437
EM5209VF_DFN14_3X2
1 1 2
+3.3V_ALW_PCH Source
+3.3V_ALW
+3.3V_ALW_PCH_PWR +3.3V_ALW_PCH +5V_RUN Source +3.3V_RUN Source

+5V_RUN_PWR +5V_RUN
UZ27
@ PJP15 UZ20 PJP22
1 2 1 7 2 1 1 14 +5V_RUN_PWR 2 1
<11,46,58,59> SIO_SLP_SUS# VIN VOUT 2 1 +5V_ALW VIN1 VOUT1
@ R3760 0_0402_5% 2 8 2 13
VIN VOUT VIN1 VOUT1
10U_0603_6.3V6M
10U_0805_10V6K
PAD-OPEN 4x4m
C
1 2 3 6 JUMP_43X79 1 2 RUN_ON_R 3 12 PJP@
C
<46,58> PCH_ALW_ON ON CT 1 <46> RUN_ON ON1 CT1 1
R3759 0_0402_5% @ R881 0_0402_5%
C1445
C514
4 11
+5V_ALW VBIAS GND
470P_0402_50V7K
4 +3.3V_RUN_PWR +3.3V_RUN
+5V_ALW VBIAS 2 2
5 2 5 10
GND 9 ON2 CT2 @ PJP23
C1444
GND 6 9 +3.3V_RUN_PWR 2 1
7 8
1 VIN2 VOUT2
10U_0603_6.3V6M
AOZ1336_DFN8_2X2 JUMP_43X79
1000P_0402_50V7K
470P_0402_50V7K
15 2 2 1
GPAD
C544
C450
C543
EM5209VF_DFN14_3X2
1 1 2
+1.0V_PRIM to +1.0V_RUN
+1.0V_RUN_PWR +1.0V_RUN
UZ23
@ PJP16
1 7 2 1
+1.0V_PRIM VIN VOUT 2 1
2 8
VIN VOUT
10U_0603_6.3V6M
1 JUMP_43X79
RUN_ON 3 6
ON CT
C1424
B B
2
470P_0402_50V7K
4
+5V_ALW VBIAS 1
+1.8V_RUN Source
C1423
5
GND 9
GND
2
AOZ1336_DFN8_2X2 +1.8V_RUN_PWR +1.8V_RUN
UZ22
@ PJP24
1 7 +1.8V_RUN_PWR 2 1
+1.8V_ALW VIN VOUT 2 1
2 8
VIN VOUT
10U_0603_6.3V6M
RUN_ON 3 6 JUMP_43X79
ON CT 1
C767
470P_0402_50V7K
1
C539
4
+5V_ALW VBIAS 2
5
GND 9
GND 2
AOZ1336_DFN8_2X2
+PWR_SRC_MXM MXM_PWR_SRC Source @ PJP17
1 2
+PWR_SRC_MXM Q186 +MXM_PWR +MXM_PWR_SRC
100K_0402_5%
1 8 PAD-OPEN 4x4m
1
2 7
R940
3 6
5 @ PJP18
10U_1206_25V6M
100K_0402_5%
1 2
1
AO4435L_SO8 1
2
R935
PAD-OPEN 4x4m
C776
12/2 draft cost BOM

+MXM_SRC_EN#
2
2
1
A A
20K_0402_5%
0.01U_0402_50V7K
R944
1
C774
1 2
D 2
3.3V_RUN_GFX_ON 2 Q87
G DMN65D8LW-7_SOT323-3
S Title
3
Power Control
5 4 3 2 1
5 4 3 2 1
+COINCELL
EMI Part (47.1) DVT1.2 change item
COIN RTC Battery
EMC@ PL1
1
SMB3025500YA_2P
1 2 PR1
+PWR_SRC +PWR_SRC_MXM DVT2.0 combine H42,H44e to one schematic 1K_0402_5%
+3.3V_RTC_LDO
BOM structure add H42@,H44@
10U_0805_25V6K
0.1U_0603_25V7K
2
1
100U_25V_M
JRTC1
Z4012
1
1
+ 1
PC31
PC30
PC1
+COINCELL 1
2
D 2 D
2
@ @ 2 3
GND
2
4
+RTC_CELL GND
ESD Diodes
different between H42&H44e ACES_50271-0020N-001
PD1
1
BAS40CW_SOT323-3 1
PC2
ESD (47.2) 1U_0603_10V4Z
2
DVT2.1 change item X-build change item
1
EMC@ EMC@ Move to power schematic
PD2 PD3
TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3
EMI Part (47.1)
3
EMC@ PL2 +3.3V_ALW
FBMJ4516HS720NT_2P
1 2
Primary Battery Connector
EMC@ PL6
EMI Part (47.1)
1
FBMJ4516HS720NT_2P
100K_0402_5%
CONN@ PBATT+_C 1 2 PBATT+
PR2
SUYIN_200045GR009M28QZR
9
PR3
2
1 8
2 7 Z4304 4 5
2200P_0402_50V7K
3 6 PBAT_SMBCLK <46>
Z4305 3 6
4 5 PBAT_SMBDAT <46>
Z4306 2 7
5 4 PBAT_PRES# <44,46,57>
1
C 1 8 C
EMC@ PC4
6 3
7 2 PQ1
2
8 1 100_0804_8P4R_5% AO3409_SOT23
9 10 PD5
GND 11 1 2 1 3
S
GND DOCK_TNY_SMBUS_ALRT# <43,44,45>
PBATT1
SDMK0340L-7-F_SOD323-2
G
2
0_0402_5%
GND 1 2
<43,45,60> SLICE_BAT_PRES#
@ PR33
1
PC5
1500P_0402_50V7K
2
+3.3V_ALW
<43> DOCK_PSID 原
6/15 Change PU1 from SA00003DN00 to
SA00001WK00( 2nd source)for ESD issue
PD4,PD6 depop temporarily for cost
，so
2
EMI Part (47.1) @ PR7 @EMC@ PU1
2.2K_0402_5%
2
1 2 PD6 1 6 GPIO_PSID_SELECT <45>
NO IN
PR8
0_0402_5% PESD5V0U2BT_SOT23-3
1
2 5 +5V_ALW
EMC@ PL3 PR9 GND V+
1
BLM15BX102SN1D_2P 33_0402_5%
NB_PSID 2 1 1 3 1 2 NB_PSID_TS5A63157 3 4
S
NC COM PS_ID <46>
PQ2 TS5A63157DCKR_SC70-6
100K_0402_1%
B B
2
FDV301N_G_NL_SOT23-3~D 6/8 add diode for ESD team Matt request
G
2
3
PR10
+5V_ALW
@EMC@
PD4 @ PT1
10K_0402_1%
1
1
C PAD~D
2
PR11
PESD5V0U2BT_SOT23-3 PQ3
1
B MMST3904-7-F_SOT323-3
15K_0402_1%
E3
2
2
PR12
6/8 add diode for ESD team Matt request PR13

1 2
PSID_DISABLE# <45>
1
@ 10K_0402_5%
EMI Part (47.1) DC_IN+ Source

SI7149DP PQ5
EMC@ PL5 +DC_IN +DC_IN_SS
SMB3025500YA_2P 1
1 2 2
3 5
0.022U_0603_50V7K
EMC@ PL4
SMB3025500YA_2P
1 2 +DC_IN
4
3
1M_0402_5%
VZ0603M260APT_0603
100K_0402_5%
10U_0805_25V6K
2
2
PR16
1
PD8
A PJPDC1 1 A
PQ8B
1
PR18
PC14
1000P_0402_50V7K
1 2
1
4.7K_0805_5%
2 3
1
PC9
@ PR20
0.1U_0603_25V7K
2
1
3 4 1 2
EMC@ PC11
DCX124EK-7-F_SC74R-6
SOFT_START_GC <60>
2
4 5
1
@ PR19
DCX124EK-7-F_SC74R-6
5 6
1
2
@EMC@ PC15
1M_0402_5%
10K_0402_5%
2
6 7 +DCIN_JACK
2
7 8
PR22
8 9 5
PQ8A
9 10 AC_DIS <45,60>
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.
2
10 11 Title
11
ACES_50493-0110N-001 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +DCIN
6
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
CONN@
4/29 PQ8 SB000009N00 is X1 code ,replaced to second source SB000009P80 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C551P
5 4 3 2 1
A B C D E
1 1
+3.3V_ALW2 +3.3V_RTC_LDO
PR100 PR101
6.49K_0402_1% 15K_0402_1%
1 2 1 2
PR102 PR104
0_0402_5%
1
10K_0402_1% 10K_0402_1%
@ PR103
1 2 1 2
4.7U_0603_10V6K
1
PC100
2
2
<7> ALW_PWRGD_3V_5V
FB_3V
22.1K_0402_1%
22.1K_0402_1%
+DC1_PWR_SRC
1
PR105
+DC1_PWR_SRC
PR106
FB_5V
+3.3V_ALW
2
PL100
2
1UH_6.6A_20%_5X5X3_M
1 2 PU101
10U_0805_25V6K
2
1
PR107
1
100K_0402_1%
PC102
PC103 @EMC@
10U_0805_25V6K
CS2
VFB2
VREG3
VFB1
CS1
0.1U_0402_25V6
21
2200P_0402_50V7K
PAD
1
SIS412DN-T1-GE3_POWERPAK8-5
3V_5V_EN 6
PC101
2
EN2
14
PC105
1
VO1
5
2 0_0402_5% PR114 2
2
1 2 PGOOD_3V_5V 7 200_0402_1%
PGOOD 19 1 2
PQ100
@
+PWR_SRC @ PR108 VCLK
PQ101
4 UG_3V 10 TPS51285BRUKR_QFN20_3X3
PC109 PR110 DRVH2 16 UG_5V 4
0.1U_0603_25V7K 2.2_0603_5% DRVH1 PR109 PC110
1 2 BST_3V_C 1 2 BST_3V 9 2.2_0603_5% 0.1U_0603_25V7K
VBST2 17 BST_5V 1 2 BST_5V_C 1 2
1
2
3
VBST1
3
2
1
SW2 8
SW2 18 SW1
VREG5
DRVL2
DRVL1
PL101 SW1 PL102
+3VALWP +5VALWP
EN1
VIN
2.2UH_12A_20%_10X10X4_M 3.3UH_PIMB104T-3R3MS_10A_20%
1 2 1 2
3V_5V_EN
11
12
13
20
15
5
5
1 1
FDMC7692S_MLP8-5
FDMC7692S_MLP8-5
1
1
LG_3V LG_5V
+ +
PQ102
PQ103
PC120 PC121
330U_D2E_6.3VM_R25M PR111 PR112 330U_D2E_6.3VM_R25M
4.7_1206_5% 4 4
2 4.7_1206_5% 2
2
2
0.1U_0603_25V7K
1SNUB_5V
SNUB_3V
4.7U_0603_10V6K
1
2
3
3
2
1
1
1
PC118
PC117
2
2
PC114
3 3
1
PC111 680P_0603_50V7K
2
680P_0603_50V7K +DC1_PWR_SRC +5V_ALW2
2
3VALWP
Ripple voltage - 3V_5V_EN
Static load 3% / Dynamic load 5% 5VALWP

Frequency 355kHz PR113
0_0402_5%
Ripple voltage -
TDC 8.12 A 1 2 Static load 3% / Dynamic load 5%
<46> ALWON
Peak Current 11.61 A Frequency 300kHz
OCP current 13.93 A TDC 7.8 A
TYP MAX Peak Current 11.15 A
H/S Rds(on) 24mohm , 30mohm OCP current 13.38 A
L/S Rds(on) 10.8mohm , 13.6mohm TYP MAX
Choke DCR:15 H/S Rds(on) 24mohm , 30mohm
L/S Rds(on) 10.8mohm , 13.6mohm
1U_0603_10V6K
Bulk cap ESR 25mohm

1
@
PC119
@ PJP100 PJP102
Choke DCR Max:11.8mohm
1 2 +3.3V_ALW 1 2
+5VALWP +5V_ALW Choke Ityp:10A / Isat:16A
2
@ +3VALWP
PAD-OPEN 43x118 PAD-OPEN 43x118 Bulk cap ESR 25mohm

@ PJP101 @ PJP103
1 2 1 2
4 4
PAD-OPEN 43x118 PAD-OPEN 43x118

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
+5V_ALW/3.3V_ALW
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C551P
A B C D E
5 4 3 2 1
@
PJP201 0.675Volt +/- 5%
VLDOIN_1.2V 2 1 +1.2V_MEN_P TDC 1.05A
EMI Part (35.33) Peak Current 1.5A
+PWR_SRC @ PJP200
1.2V_B+ PR200 BOOT_1.2V
PAD-OPEN1x1m
OCP Current 1.8A
1 2 1 2
2.2_0603_5%
PAD-OPEN 1x2m~D
DH_1.2V
PC204 @EMC@
PC205 @EMC@
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
+0.6V_P
SIR472DP-T1-GE3_POWERPAK8-5
22U_0805_6.3VAM
1
1
SW_1.2V
PC202
PC203
PC206
D D
5
0.22U_0603_10V7K
1
2
1
DL_1.2V
PC207
@
16
17
18
19
20
PU200
PQ201
PHASE
UGATE
BOOT
VLDOIN
VTT
2
4 21
PAD
15 1
LGATE VTTGND
1
2
3
PR201 14 2
+1.2V_MEN_P PL201 5.11K_0402_1% PGND VTTSNS +V_DDR_REF
1.0UH_PCMB104T-1R0MH_18A_20% 1 2 CS_1.2V
1 2 13 3
PC213 CS RT8207MZQW_WQFN20_3X3 GND
5
1U_0603_10V6K
4.7_1206_5%
PR203 2 1VDDP_1.2V 12 4 +V_DDR_REF
SIRA06DP-T1_POWERPAK-SO8-5
VDDP VTTREF
220U_D2_2VY_R17M
PR202
1 5.1_0603_5%
EMC@
VDD_1.2V
PC201
+ 1 2 11 5 PC209
+1.2V_MEN_P
1 SNUB_1.35V 2
VDD VDDQ
PGOOD
4
PQ202
0.033U_0402_16V7K
TON
2 +5V_ALW PC210 PR210
FB sense trace
FB
S5
S3
1U_0603_10V6K 2.2_0603_5%
2
when FB pull down to GND
680P_0603_50V7K
3
2
1
10
6
2
+3.3V_ALW
EMC@
PC212
@ PC211 220P_0402_50V8J @ PJP203
1 2 2 1
+5V_ALW
2
2 1
1
PR209 JUMP_1x3m
100K_0402_1% PR204
12K_0402_1% @ PJP204
EMI Part (35.33) 1.2V_FB 1 2 +1.2V_MEN_P 2 1 +1.2V_MEM
2
C 1.2V_SUS_PWRGD 2 1 C
JUMP_1x3m
<46> 1.2V_SUS_PWRGD PR205
1M_0402_1%
1
PR206 1.2V_B+ 1 2
1
200K_0402_5% PR207 @
S5_1.2V 20K_0402_1% PJP202
1 2 PC214
<11,23,37,46,54> SIO_SLP_S4#
@.1U_0402_16V7K +0.6V_P 2 1 +0.6V_DDR_VTT
2
PR208
1.2Volt +/- 5%
2
100K_0402_5%
PAD-OPEN1x1m
TDC: 7.5 A <14> 0.6V_DDR_VTT_ON
1 2 S3_1.2V
Peak Current: 11 A
1
@ PC215
OCP current: 13.2A 1U_0402_6.3VX5R
Rds(on): 3.5m ohm(max)
2
Choke DCR 3.5mohm(max)
+1.2V_MEN_P
FB sense trace
B B
Mode S3 S5 +1.35V_MEN +V_DDR_REF +0.675V_P

S5 L L off off off
S3 L H on on off(Hi-Z)
S0 H H on on on
A A

Title
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 1.2VP/0.6VSP
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Size Document Number Rev
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1.0
LA-C551P
5 4 3 2 1
5 4 3 2 1
RUN_ON_AND
RUN_ON_AND <46>
1000P_0402_50V7K
1
1M_0402_1%
PC312
@ PR303
1
@ PJP300
@
+VCC_IOP +VCC_IO
2
1 2
2
PAD-OPEN 43x118
EMC@ PR305 EMC@ PC301

D 4.7_1206_5% 680P_0603_50V7K D
2SNB_0.95V 1
+PWR_SRC @ PJP301 PU300
1 2
2200P_0402_50V7K
+V0.95SP_B+
0.1U_0402_25V6
1 2 8 1 PC302 PR312
IN EN
10U_0805_25V6K
0.1U_0603_25V7K 0_0603_5%
PAD-OPEN 1x2m~D 6 BST_+V0.95SP 1 2 BST_+V0.95SP_C
1 2 PL301
BS
1
PC303
1UH_6.6A_20%_5X5X3_M
SW_+V0.95SP +VCC_IOP
@EMC@ PC311
@EMC@ PC300
9 10 1 2
GND LX
47U_0805_6.3V6M
47U_0805_6.3V6M
22U_0805_6.3VAM
22U_0805_6.3VAM
330P_0402_50V7K
1
1
10_0402_1%
4 FB_+V0.95SP
FB
PC304
PR311
PC305
PC306
PC307
@ PC308
ILMT_0.95V 3 7
+3.3V_ALW
2
ILMT BYP
4.7U_0603_6.3V6K
+3.3V_ALW
4.7U_0603_6.3V6K
2 5
2
0.95V_MP_PWROK PG LDO
1
1K_0402_5%
PC310
1
PC309
PR309
SYX198DQNC_QFN10_3X3
1
2
2
@ PR306 PR307
@
0_0402_5% PR314
1 2 1 2 1 2
+3.3V_ALW VCC_IO_SENSE <11>
2
ILMT_0.95V
@ PR315 36.5K_0402_1% 0_0402_5%
1
1
62K_0402_1%
0_0402_5%
100K_0402_1%
@ PR308
PR310
@
C PR316 C
2
2
1 2
+VCC_IO VSS_IO_SENSE <11>
TDC 3.85A 0_0402_5%
Peak Current 5.5 A
OCP Current 8 A proximal
TYP PR311 0 ohm PR314 10 ohm PR316 10
MAX ohm
Choke DCR 13.0mohm ,
14.0mohm remote
PR311 10 ohm PR314 0 ohm PR316 0
ohm
B B
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +VCC_IO 0.95V
LA-C551P
5 4 3 2 1
A B C D
1 1
@ PJP401
1 2
+2.5V_MEMP 1 2 +2.5V_MEM
JUMP_43X79
+3.3V_ALW
@
PR401
+2.5VSP_ON 1 2 SIO_SLP_S4# <11,23,37,46,52>
0.1U_0402_16V7K
0_0402_5%
1
PC401
2 @ PR400 2
1
100K_0402_5% PR402
@ 1M_0402_5%
Note:Iload(max)=2.5A
2
PU400
9
1 PGND 8
FB SGND
@ PJP400 2 7 PL400
PG EN 1UH_2.8A_30%_4X4X2_F
+3.3V_ALW 1 2 3 6 LX_2.5V 1 2
1 2 IN LX +2.5V_MEMP
68P_0402_50V8J
22U_0603_6.3V6M
4 5
1
JUMP_43X79 PGND NC
4.7_0603_5%
PC400
@EMI@ PR403
1
PC402
PR404
1
22U_0603_6.3V6M
22U_0603_6.3V6M
SY8003DFC_DFN8_2X2
36.5K_0402_1% Rup
PC403
PC404
2
2
2
2
FB_2.5V
1
1
680P_0402_50V7K
@EMI@ PC405
FB=0.6V
Note:Iload(max)=3A PR405
11.5K_0402_1%
Rdown
2
2.5Volt
2
3 TDC 0.63A 3
Peak Current 0.9A

OCP Current 3.5A
Note:
When design Vin=5V, please stuff snubber
to prevent Vin damage
Vout=0.6V* (1+Rup/Rdown)
4 4

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +2.5V_MEM
LA-C551P
A B C D
Note:Use VCCSA_SEL to switch High & Low Level for VID[1]

5 4 3 2 1
6/17 depop modify (5/27 RF team Brian suggest to pop)

Only H44e PR112-4.7
PR111-4.7
PR202-4.7
PR305-4.7
PR504-4.7
PR1804-4.7
(PR504,PR1804 depop)
+3.3V_ALW PC114 680P

@H44@ PR504 @H44@ PC501
4.7_1206_5% 680P_0402_50V7K
PC111 680P
PC212 680P
PC301 680P
PC501 680P
2
H44@ PC1801 680P
D D
PR500 (PC501,PC1801 depop)
100K_0402_1%
H44@ PL500
HCB1608KF-121T30_0603 H44@
1
H44@
PR502 H44@ PR503 PC500 @EMI@ PR504 @EMI@ PC501
<10,56> CPU_ZVM# 2 1 LP#_EDRAMP 100K_0402_5% 2.2_0603_5% 0.1U_0603_25V7K 4.7_1206_5% 680P_0402_50V7K
BST_EDRAMP 1 2 BST_R_EDRAMP 1 2 1 2 1 2
PR501
2
0_0402_5%
H44@
H44@
9
@EMI@ PL500 PU500 PL501
HCB1608KF-121T30_0603 1UH_1277AS-H-1R0N-P2_3.3A_30%
BST
LP#
MODE
VIN_EDRAMP 1 SW_EDRAMP
+PWR_SRC 1 2
VIN SW
8 1 2
+VCC_EDRAM_P
EN_EDRAMP
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
5 12
0.1U_0402_25V6
H44@ H44@
EN VOUT
1
VID1_EDRAM_VR
PC508
PC509
PC505
PC510
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
3 2
C1 PGND H44@
1
VID0_EDRAM_VR
PC502
PC503
PC504
4 11
2
C0 AGND
3V3
100_0402_1%
PG
@
2
PR505
NB681GD-Z_QFN13_2X3
13
10
H44@ H44@ H44@
H44@ H44@
PR506
2
2 1
PR507 VCC_EDRAM_SENSE <10>
<7,56,61,64> IMVP_VR_ON 2 1 0_0402_5%
PR508
+3.3V_ALW 2 1
H44@
0.1U_0402_25V6
0_0402_5%
1
VSS_EDRAM_SENSE <10>
@ PC507
1
H44@ PR510
1 2 PC506 0_0402_5%
1M_0402_1%
+3.3V_ALW
2
1U_0402_6.3V6K
2
C H44@ @ PR509 H44@ H44@ @ PJP500 C
2
100K_0402_1% JUMP_43X79
1 2
+VCC_EDRAM_P 1 2 +VCC_EDRAM
+3.3V_ALW
+VCCEDRAM(+1.00V)
TDC 2.31 A proximal
Peak Current 3.3 A PR505 0ohm PR506 100ohm PR508 100ohm
2
PR511
OCP Current 8 A
10K_0402_1% @ PR512 MAX remote
H44@
10K_0402_1%
Choke DCR 48.0mohm PR505 100ohm PR506 0ohm PR508 0ohm
1
VID0_EDRAM_VR
VID1_EDRAM_VR
2
@
PR513
10K_0402_1% PR514
10K_0402_1%
1
H44@
B B
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, +VCCEDRAM, 1V
LA-C551P 1.0

5 4 3 2 1
5 4 3 2 1
Only H44e
+3.3V_ALW
2
D D
PR1800 H44@
100K_0402_1%
H44@ PL1800
1
HCB1608KF-121T30_0603
PR1802 H44@ PR1803 PC1800 @EMI@ PR1804 @EMI@ PC1801
<10,55> CPU_ZVM# 2 1 LP#_EOPIOP 100K_0402_5% 2.2_0603_5% 0.1U_0603_25V7K 4.7_1206_5% 680P_0402_50V7K
BST_EOPIOP 1 2 BST_R_EOPIOP 1 2 1 2 1 2
PR1801
2
0_0402_5% H44@ H44@
H44@
H44@
9
@EMI@ PL1800 PU1800 PL1801
HCB1608KF-121T30_0603 1UH_1277AS-H-1R0N-P2_3.3A_30%
BST
LP#
MODE
VIN_EOPIOP SW_EOPIOP
+PWR_SRC 1 2 1
VIN SW
8 1 2
+VCC_EOPIO_P
EN_EOPIOP
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
5 12
0.1U_0402_25V6
H44@
EN VOUT H44@ H44@ H44@
1
VID1_EOPIO_VR
PC1808
PC1809
PC1805
PC1810
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
3 2
C1 PGND
1
VID0_EOPIO_VR
PC1802
PC1803
PC1804
4 11 H44@
2
C0 AGND
3V3
100_0402_1%
PG
@
2
PR1805
NB681GD-Z_QFN13_2X3
13
10
H44@ H44@ H44@
H44@
PR1806
2
2 1
PR1807 VCC_EOPIO_SENSE <10>
<7,55,61,64> IMVP_VR_ON 2 1 0_0402_5%
PR1808
+3.3V_ALW 2 1
0.1U_0402_25V6
0_0402_5%
1
VSS_EOPIO_SENSE <10>
@ PC1806
1
H44@ PR1809
1 2 PC1807 0_0402_5%
1M_0402_1%
+3.3V_ALW
2
1U_0402_6.3V6K
2
C H44@ @ PR1810 H44@ H44@ @ PJP1800 C
2
100K_0402_1% JUMP_43X79
1 2
+VCC_EOPIO_P 1 2 +VCC_EOPIO
+3.3V_ALW
+VCCEOPIO(+1.00V)
TDC 2.24 A proximal
Peak Current 3.2 A PR1805 0ohm PR1806 100ohm PR1808 100ohm
2
PR1811
OCP Current 8 A
10K_0402_1% @ PR1812 MAX remote
H44@ 10K_0402_1%
Choke DCR 48.0mohm PR1805 100ohm PR1806 0ohm PR1808 0ohm
1
VID0_EOPIO_VR
<10> CPU_MSM# 2 1 VID1_EOPIO_VR
PR1815
2
0_0402_5% @
H44@ PR1813
10K_0402_1% PR1814
10K_0402_1%
H44@
1
B B
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, +VCCEOPIO, 1V
LA-C551P 1.0

5 4 3 2 1
A B C D
Iada=0~12.3A(240W) +CHAGER_SRC
+PWR_SRC PL700
ADP_I = 40*Iadapter*Rsense 1UH_6.6A_20%_5X5X3_M
2 1
@ PD700 PR701
2 1 +SDC_IN 0.005_1206_1%
EMI Part (47.1)
ES2AA-13-F 1 4 5/19 add circuit for PD
PQ701 SI7149DP
0.1U_0603_25V7K
2 3
1 @
1
2
+DC_IN_SS 5 3
PC700
@ PR703
4/22 add for PD <18> MXM_PWR_LEVEL
1
0_0402_5%
D
SDMK0340L-7-F_SOD323-2~D 2 1 2 PQ702
3
1 1
<57,60> CSS_GC
4
G DMP3056L-7 1P SOT23-3
PD704 CSS_GC_1
1
PR766 @ D S
3
PQ703
PQ1074B
2 1 1 2 2 1 2
+VBUS_DC_SS PR700
0_0402_5% DC_BLOCK_GC <57,60>
G
PQ700
DMP3056L-7 1P SOT23-3 DMP3056L-7 1P SOT23-3 <44> DCIN_ACOK# 5
0_0402_5% PD701
2 S
3
3 1
D
+DOCK_PWR_BAR
4
DOCK_DCIN_IS+ <43>
1
+SDC_IN
6/23 change PD701 PD702 1
PR715
CSSN_1
CSSP_1
PD1010 from SCS00003800 to
20_0402_1%
G
SCS00005400 for vendor
2
3 PQ706
1
1M_0402_5%
+DC_IN_SS
3
PR704 DMP3056L-7 1P SOT23-3
PR713
2
PR769
PQ708B
100_0402_1%
100K_0402_1%
BAT54CW-7-F SOT-323 H_PROCHOT# <7,46,57,61,64>
2 1 3 1 1 2
PD702 DOCK_DCIN_IS- <43>
1
+3.3V_ALW
1M_0402_5%
0_0402_5%
0_0402_5%
2
1
2
PBATT+
@ PR710
@ PR711
PR709
100K_0402_1%
6
4/22 add for PD 12.1_0402_1%
1
PC151
PR768
G
2
6
1 0.1U_0402_10V7K
2 1
PQ1074A
PR712
PQ708A
PC703
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0603_25V7K
2
2
+VBUS_DC_SS 3 PC702 0.1U_0402_25V6 PC704
2
2 1 2 1 2 1 2 @ PR714
<57,60> CSS_GC
1
2 1
@EMC@ PC705
@EMC@ PC706
PC707
PC708
5
BAT54CW-7-F SOT-323 DK_CSS_GC <60>
1
0.1U_0402_25V6
1M_0402_5%
0.01U_0402_25V6
CSSP_2
CSSN_2
1
@ PD703 0_0402_5%
1
1
CSS_GC_1 PR717 1
P
AC Det (typ 2.4V) B ACAV_DOCK_SRC# <43,60>
2
4
PR770
10_1206_5% MM3Z22VST1G_SOD323-2 O
PR767
Max:16.994V +SDC_IN
A
2
PROCHOT_GATE <45>
G
1 2
Typ :16.540V
2
TC7SH08FU_SSOP5~D
1
1M_0402_5%
1
Min :16.098V
294K_0402_1%
4.12K_0603_1%
3
2
2
PR773 PR771 <57,60> DC_BLOCK_GC PC714 PU105
SIR472DP-T1-GE3_POWERPAK8-5
2
1
BQ24780_REGN 1 2
PR719
PC709 PU700
0_0402_5% 0_0402_5% EMI Part (47.1)
PR706
1U_0603_25V6K
ACDRV
ACP
ACN
2 1 +DCIN 28 2.2U_0603_10V6K PQ704
PR772 VCC
2
2
BQ24780_REGN
1 2 PR718 3 24
2
CMSRC REGN
5
100K_0402_1% 49.9K_0402_1% PR765 PC734
2 1 6 2.2_0603_5% 0.047U_0603_50V7
3
2
@ PR727 0_0402_5% ACDET 25 1 2 2 1
2
BTST
PQ1073B
1 2 11
2 1 @ PR729 0_0402_5% SDA
5 1 2 12 26 UGATE_CHG 4
SCL HIDRV
1
PC711 0.1U_0402_25V4Z~D @ PR721 0_0402_5%

PR722 GNDA_CHG 1 2 5
EMI Part (35.33)
4
100K_0402_1% ACOK 27
<46> CHARGER_SMBDAT PHASE +VCHGR
7 PR723
3
2
1
IADP PL701 0.01_1206_1%
<46> CHARGER_SMBCLK
2
8 23 3.3UH_6.5A_20%_7X7X3_M
PR730 IDCHG LODRV LX_CHG 1 2 1
CHG 4
+3.3V_ALW
<18,46,60> ACAV_IN @ PR716 0_0402_5% 1 2 9
4.7_1206_5%
1
1 2 0_0402_5% PMON 2 3
1
<46> I_ADP
1
20K_0402_1%
5.36K_0402_1%
PR720 @ PR726 0_0402_5% 1 2 10 22 LGATE_CHG PQ705
FDMC7692S_MLP8-5
PROCHOT# GND
5
PR758
PR760
1 2 CSOP_1 CSON_1
@EMC@ PC717 @EMC@ PR724

121K_0402_1% PR725
<46> I_BATT 0_0402_5%
100P_0402_50V8J
100P_0402_50V8J
10U_0805_25V5K~D
10U_0805_25V5K~D
10U_0805_25V5K~D
<61> TSENSE_PSYS
2
CMPIN 13 21
2
37.4K_0402_1%
2
CMPIN ILIM
1
SNUB_CHG
PC721
PC720
PC718
PC719
PC715
PR744
CMPOUT 14 4
6
CMPOUT
1
GNDA_CHG 20
680P_0402_50V7K
1
2
SRP
PQ707A
@
@ 15 19
2
GNDA_CHG
2
BATPRES# SRN 2
TB_STAT# <45,57>
3
2
1
<7,46,57,61,64> H_PROCHOT#
16 18
1
@ PR728 0_0402_5% TB_STAT# BATDRV
Current limit <44,46,50> PBAT_PRES#
1 2 29 17 CHG
PWPD BATSRC
Charger :7.8A Vilim=1.56V PC712 PC710 PC713
1
2.74K_0402_1%
PR757 0.1U_0402_25V6 0.1U_0402_25V6 0.1U_0402_25V6
6 Cell (0.8C )
PR764
10K_0402_5% BQ24780S 1 2 1 2 1 2
2 1
Max Boost Charger :7.8A, Vilim=0.39V +3.3V_ALW
GNDA_CHG
@ PJP700 PR761
2
1 2 10_0402_1% GNDA_CHG GNDA_CHG
3 2 1 3
<45,57> TB_STAT#
PAD-OPEN1x1m 5/14 change the circuit for bettary current sense PR762
GNDA_CHG 10_0402_1%
2 1
+DC_IN CMP_REF=2.3V
+DC_IN>17.6V then ACAV_IN_NB high
1
PR737
665K_0402_1%
PR745
100K_0402_1%
2
2 1 CMPIN
1
CMPOUT
PR738 PC737
3M_0402_5% 100P_0402_50V8J
2
@ PR743
2
<46,60> ACAV_IN_NB 2 1
1
0_0402_5%
4
PC741 4
PR740 100P_0402_50V8J
1
10K_0402_1%
2
+3.3V_ALW DELL CONFIDENTIAL/PROPRIETARY

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, PWR_Charger
LA-C551P 1.0

A B C D
5 4 3 2 1
@ PJP800
+1VSP_B+ 2 1
+PWR_SRC
PAD-OPEN 1x2m~D
+3.3V_ALW
2200P_0402_50V7K
10U_0805_25V6K
0.1U_0402_25V6
1
1
EMC@ PC801
EMC@ PC802
PC803
D D
2
5
@ PR800
100K_0402_5%
PQ800
1
4
PC804
PU800 .1U_0603_25V7K
EMI Part (35.33)
BST_+1VSP PR801
1 10 1 2 2 1
3
2
1
PGOOD VBST
PR802 2.2_0603_5%
S0 mode be high level 1 2 TRIP_+1VSP 2 9 UG_+1VSP PL800
TRIP DRVH 1UH_6.6A_20%_5X5X3_M
107K_0402_1%
EN_+1VSP 3 8 SW_+1VSP 1 2
EN SW +1.0V_PRIMP
FB_+1VSP 4 7 +1VSP_5V
VFB V5IN
+5V_ALW
RF_+1VSP 5 6 LG_+1VSP
SI7716ADN-T1-GE3_POWERPAK8-5
TST DRVL 1
1
PR804 1 2
1 2 11 + PC806
<11,46,49,59> SIO_SLP_SUS# TP
0.22U_0402_16V7K
PC805 PR805 @EMC@ 220U_D2_2VY_R17M
1
0_0402_5% TPS51212DSCR_SON10_3X3 1U_0603_10V6K 4.7_1206_5%
1
PQ801
2
PC800
@ PR809 PR806 4
1 2 470K_0402_1%
<46,49> PCH_ALW_ON
2
1
PC807 @EMC@
2
0_0402_5% @
C 1000P_0402_50V7K C
3
2
1
2
PR807
5.11K_0402_1%
1 2
+1.0V_PRIMP
Ripple voltage -
Static load 3% / Dynamic load 5%
1
PR808
12K_0402_1%
Frequency 290kHz
TDC 5.1A
Peak Current 7.33A
2
@
PJP801 OCP current 8.8A
B
+1.0V_PRIMP 1 2 +1.0V_PRIM TYP MAX B
PAD-OPEN 43x118 H/S Rds(on) 24mohm , 30mohm

L/S Rds(on) 13.5mohm , 16.5mohm
Choke DCR 11mohm
Bulk cap ESR 17mohm
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +1.0V_PRIM
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
LA-C551P
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW
+5V_ALW
1
D D
@ PJP900
PAD-OPEN1x1m @ PJP901
1 2
+1.8VSP +1.8V_ALW
1
PC900
2
1U_0402_6.3V6K PAD-OPEN1x1m
2
+1.8VSP_VIN
6
PU900
1
5
VCNTL
7 VIN PC901
POK 4 4.7U_0805_6.3V6K
2
VOUT
@ PR900 3 1.8VSP
0_0402_5%
VOUT
+1.8VSP
1
1 2 +1.8VSP_ON 8 2
<11,46,49,58> SIO_SLP_SUS# EN FB
1
+1.8VSP
GND
9 PR902 PC903
VIN
TDC 0.035 A
1
12.7K_0402_1% 0.01U_0402_25V7K
1
@ PR901 PC902 @EMC@ AP7175SP-13_SO-8EP-8
PC904 Peak Current 0.05A
2
2
22U_0805_6.3V6M
47K_0402_5% .1U_0402_16V7K
OCP Current 5.7 A fix by IC
2
1
2
PR903
10K_0402_1%
C C
2
Vout=0.8V* (1+Rup/Rdown)
B B
A A

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +1.8V_ALW
LA-C551P
5 4 3 2 1
5 4 3 2 1
PD1001
2
SDMK0340L-7-F_SOD323-2~D +DOCK_PWR_BAR
1
PD1101 PR1033 3
1 2
+VBUS_DC_SS 2 1
1
PDS5100H-13_POWERDI5-3~D
0_0402_5% PR1001 PQ1001 SI7149DP
330K_0402_5%
+SDC_IN 1
2
2
5 3
0.47U_0805_25V7K~D
1M_0402_5%
3
PQ1005B
PR1036
PC1001
1
5
1M_0402_5%
2
D D
PR1034
4
6
PQ1005A
2 1 STSTART_DCBLOCK_GC
2
2 PR1002
@
0_0402_5%
1
1M_0402_5%
1
1
PR1037
STSTART_DCBLOCK_GC
PR1035
2
1M_0402_5%
2
PD1002
2
1
PR1003 3
330K_0402_5%
PDS5100H-13_POWERDI5-3~D
1 2 PQ1004 SI7149DP
PBATT+ SI7149DP PQ1003
PQ1002 1
+VCHGR SI4835DDY-T1-E3_SO8 1 2
8 1 2 PBATT_IN_SS 5 3
+PWR_SRC
7 2 3 5
2200P_0402_50V7K
1
6 3 @ PR1004
1K_1206_5%
5
PR1005
0.1U_0402_25V6
0_0402_5%
1
2 1
PC1002
PC1003
4
4
@ PR1006
2
5/8 add circuit for avoiding type C current to flow to battery
1U_0603_25V6K
0_0402_5%
1 2BLK_MOSFET_GC @ @
PC1005
PC1004
C PR1026 1U_0603_25V6K C
PD1103
100_0603_1%
2
2 1 1 2
+VBUS_DC_SS
PQ1072
AO3409_SOT23
SDMK0340L-7-F_SOD323-2
1 3 1
D
PR1007 PR1008 +3.3V_ALW2
1
100_0603_1% 100_0603_1%
1 2 DK_PWR_BAR @ PR1009
100K_0402_5%
+DOCK_PWR_BAR
1
PR1099
G
PD1102 0_0402_5%
2
2
PR1030
2 1 1 2 3301_DC_IN_SS <45,50> AC_DIS 2 1
DSCHRG_MOSFET_GC
2
+DC_IN_SS PR1010
SSM3K7002FU_SC70-3~D
SDMK0340L-7-F_SOD323-2 100_0603_1% 10K_0402_5%
2
PD1100
1
D
PQ1011
PD1010
1 2 CD3301_DCIN 1 2 2
+DC_IN <43,45,50,60> SLICE_BAT_PRES#
PR1011 47_0805_5% G 3
S
3
1
PC1006 SDMK0340L-7-F_SOD323-2 1
DOCK_AC_OFF <43>
2
0.1U_0603_50V4Z @ PR1012 1 2 2
2
0_0402_5% PR1031
P50ALW 1 2 0_0402_5%
36
35
34
33
32
31
30
29
28
<50> SOFT_START_GC +5V_ALW BAT54CW-7-F SOT-323 330K_0402_5%

PU1001 @ PR1032
PR1013 100K_0402_5% @ PR1016 0_0402_5%
DC_IN_SS
PBatt+
NC
CHARGERVR_DCIN
DK_PWRBAR
GND
NC
BLK_MOSFET_GC
DSCHRG_MOSFET_GC
1
1 2 CD_PBATT_OFF 1 2
+3.3V_ALW2 SLICE_BAT_ON <45>
@ PR1017
0_0402_5% @ PR1014
1 2 ACAVDK_SRC 1 2
<43,57> ACAV_DOCK_SRC#
1 27
PR1015 2 DC_IN P50ALW 26 0_0402_5% @ PR1019 1 2
1 2 ERC1 3 SS_GC PBATT_OFF 25 DK_AC_OFF
+SDC_IN 0_0402_5%
4 ERC1 DK_AC_OFF_EN 24 3301_ACAV_IN_NB 1 2 @ PR1020 1M_0402_5%
ACAVDK_SRC ACAV_IN_NB ACAV_IN_NB <46,57> PR1018
100_0603_1% 5 23 0_0402_5%
B CD3301_SDC_IN 6 GND GND 22 DK_AC_OFF_EN 1 2 B
SDC_IN DK_AC_OFF_EN SL_BAT_PRES# DOCK_AC_OFF_EC <45>
7 21
<57> DC_BLOCK_GC ACAVIN 8 DC_BLK_GC SL_BAT_PRES# 20 BLKNG_MOSFET_GC
@ PR1021 P33ALW2 9 ACAV_IN BLKNG_MOSFET_GC 19
EN_DK_PWRBAR
1 2 P33ALW2 NBDK_DCINSS @ PR1023

SS_DCBLK_GC
<18,46,57> ACAV_IN
0_0402_5%
DK_CSS_GC
0_0402_5% 1 2
SLICE_BAT_PRES# <43,45,50,60>
PWR_SRC
CSS_GC
P33ALW
@ PR1022 37
TP CD3301_NBDOCK_DC_IN_SS
ERC3
ERC2
1 2 1 2
GND
+3.3V_ALW2 +NBDOCK_DC_IN_SS
0_0402_5% 0_0402_5%
CD3301BRHHR @ PR1024
10
11
12
13
14
15
16
17
18
@ PR1025
<57> CSS_GC
0.1U_0603_25V7K
0_0402_5%
P33ALW 1 2
ERC2
<57> DK_CSS_GC +3.3V_ALW

1
PC1007
ERC3 @ PR1027
0_0402_5%
EN_DK_PWRBAR 1 2
EN_DOCK_PWR_BAR <45>
2
0.1U_0402_25V6
0.047U_0603_50V7K
1 2
1
STSTART_DCBLOCK_GC 1M_0402_5%
PC1008
PC1009
PR1029 PR1028
100_0603_1%
2
@ 3301_PWRSRC 1 2
+PWR_SRC
A A

Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Selector
1.0
5 4 3 2 1
5 4 3 2 1
Place close to Choke in VCCSA first phase circuit

PR1101 PR1102 PR1199 NA, need confirm
12K_0402_1% 7.5K_0603_1%
@ PC1140 PH1100 1 2 1 2 1 2 +1.0V_VCCST
SW_1PH <65>
PR1100 1000P_0402_50V7K
100_0402_1% 1 2 100K_0402_1%_TSM0B104F4251RZ
100_0402_1%
1
2
1 2 @ PR1106
499_0402_1%
45.3_0402_1%
45.3_0402_1%
1 2 PC1101
PR1103
PR1105
PR1199
PR1104
0_0402_5% @ PR1107 0.1U_0402_25V6
1
1 2 1 2 VSN_1PH PC1102
<11> VSS_SA_SENSE
0.01UF_0402_25V7K
@
2
2
0_0402_5% 1 2 @
PC1103 @DFT@
1
1000P_0402_50V7K PR1109 PC1104 PR1110
1
0_0402_5% 1K_0402_1% 2200P_0402_50V7K PR1112 100_0402_1%
1
1 2 1 2 VSP_1PH PC1106 30K_0402_1% 81205_VR_HOT1 2
<11> VCC_SA_SENSE <65> CSN_1PH H_PROCHOT# <7,46,57,64>
PR1111 +3.3V_RUN
D @ PR1108 D
100_0402_1% PC1100 470P_0402_50V8J
2
1 2 1 2 1000P_0402_50V7K 81205_SCLK 1 2
+VCC_SA 1 2
PWM1_1PH/ICCMAX1 <65>
PR1117
VR_SVID_CLK <7,64>
1
PC1105 49.9_0402_1%
1000P_0402_50V7K PR1116 81205_ALERT 2 1
VR_SVID_ALERT# <7,64>
14.3K_0402_1% PR1114
1 2 10K_0402_1% PR1120
0_0402_5% PR1115 @
PR1119 34.8K_0402_1% 81205_SDIO 1 2PR1113
VR_SVID_DATA <7,64>
2
100_0402_1% PR1118 PC1107 10_0402_1%
PCH_PWROK
1 2 1.5K_0402_1% 6800P_0402_25V7K 1<23,64> 2
+VCC_CORE @ PR1121
1 2 1 2
0_0402_5% 81205_SCLK
1 2 VSP_3PH_A 81205_ALERT 1 2
<12> VCC_SENSE 81205_SDIO IMVP_VR_ON <7,55,56,64>
1 2
2
0_0402_5%
PC1109 PC1108 @ PR1198 PR1124
1000P_0402_50V7K PR1123 15P_0402_50V8J 100_0402_1%
1
1K_0402_1% 1 2
<12> VSS_SENSE
1 2 1 2 VSN_3PH_A VSN_1PH @ PR1126
0_0402_5%
+VCC_GT
PR1125
100_0402_1% 0_0402_5% 1 2
VSP_1PH VCCGT_SENSE <12>
1 2 @ PR1122 1 2
PC1111
1
PC1110 1000P_0402_50V7K
2200P_0402_50V7K PR1127
1K_0402_1%
2
1 2 1 2
VSSGT_SENSE <12>
PR1129
0_0402_5% 100_0402_1%
PU1100 1 2 @ PR1128 1 2
PC1113 PR1130 PC1114 NCP81205MNTXG_QFN52_6X6
53
52
51
50
49
48
47
46
45
44
43
42
41
40
15P_0402_50V8J 49.9_0402_1% 470P_0402_50V8J @DFT@ PC1112
1 2 1 2 1 2 PR1132 2200P_0402_50V7K
VSP_1PH
VSN_1PH
COMP_1PH
ILIM_1PH
CSN_1PH
CSP_1PH
IMON_1PH
PWM_1PH/ICCMAX_1PH
EN
TAB
VR_RDY
SCLK
ALRT#
SDIO
25.5K_0402_1%
PR1133 PR1131 1 2 @DFT@ PR1134 PC1116 PC1117
3.65K_0402_1% 1K_0402_1% PR1135 49.9_0402_1% 470P_0402_50V8J 15P_0402_50V8J
1 2 1 2 1 2 24.9K_0402_1% 1 2 1 2 1 2
PC1118 VSP_3PH_A 1 39 81205_VR_HOT 1 2
PC1115 470P_0402_50V8J VSN_3PH_A 2 VSP_3PH_A VRHOT# 38 PC1120 2 1 1 2 1 2
2200P_0402_50V7K 1 2 3 VSN_3PH_A VSP_3PH_B 37 470P_0402_50V8J PR1136 PR1137 PC1119
DIFFOUT_3PH_A 4 IMON_3PH_A VSN_3PH_B 36 1 2 1K_0402_1% 3.65K_0402_1% 2200P_0402_50V7K
FB_3PH_A 5 DIFFOUT_3PH_A IMON_3PH_B 35 DIFFOUT_3PH_B
C FB_3PH_A DIFFOUT_3PH_B C
COMP_3PH_A 6 34 FB_3PH_B
1 PR1138 2 ILIM_3PH_A 7 COMP_3PH_A FB_3PH_B 33 COMP_3PH_B
Place close to Choke in VCORE CSCOMP_3PH_A ILIM_3PH_A COMP_3PH_B ILIM_3PH_B
12.7K_0402_1% 8 32 1 PR1139 2
first phase circuit CSCOMP_3PH_A ILIM_3PH_B
1
CSSUM_3PH_A @DFT@ 9 31 16.2K_0402_1% CSCOMP_3PH_B

75K_0402_1%
CSSUM_3PH_A CSCOMP_3PH_B
1
CSSUM_3PH_B
PWM1_3PH_A/ICCMAX_3PH_A
PWM1_3PH_B/ICCMAX_3PH_B
PH1101 10 30 PH1102
PR1140
75K_0402_1%
CSREF_3PH_A CSSUM_3PH_B
1000P_0402_50V7K
100P_0402_50V8J
CSP1_3PH_A 11 29
PR1141
CSP1_3PH_A CSREF_3PH_B
100P_0402_50V8J
1
1000P_0402_50V7K
CSP2_3PH_A 12 CSP1_3PH_B
PWM3_3PH_B/ROSC_3PH
PWM2_3PH_B/ROSC_1PH
220K_0402_5%_ERTJ0EV224J 28 220K_0402_5%_ERTJ0EV224J
PC1121
PC1122
CSP2_3PH_A CSP1_3PH_B
1
PC1123 CSP3_3PH_A 13 27 CSP2_3PH_B Place close to Choke in VCCGT first phase circuit
PC1124
PC1125
2
1 2
CSP3_3PH_A CSP2_3PH_B
PWM3_3PH_A/VBOOT
@DFT@ PR1143
TTSENSE_1PH/PSYS
PWM2_3PH_A/ADDR
165K_0402_1%
1 2
2
1
93.1K_0402_1% 0.1U_0402_25V7K PR1145 @DFT@
165K_0402_1%
1
2
TTSENSE_3PH_A
TTSENSE_3PH_B
1 2 PC1126 107K_0402_1%
PR1142
<61,62> SW1_3PH_A 1 2
@DFT@ PR1146 0.1U_0402_25V7K
PR1144
SW1_3PH_B <61,63>
CSP3_3PH_B
2
93.1K_0402_1% PR1147 @DFT@
1 2 107K_0402_1%
<61,62> SW2_3PH_A
2
@DFT@ PR1148 1 2
SW2_3PH_B <61,63>
2
DRON
VRMP
93.1K_0402_1% PR1149 H44@
VCC
1 2 107K_0402_1%
<61,62> SW3_3PH_A 1 2
SW3_3PH_B <61,63>
PR1150
14
15
16
17
18
19
20
21
22
23
24
25
26
1K_0402_1%
+CPU_B+ 1 2 PC1127
CSP3_3PH_B TSENSE_PSYS <57>
0.1U_0402_25V6
CSREF_3PH_A PC1128 2 1 TSENSE_3PH_A PC1129
<62> CSREF_3PH_A
0.01U_0402_50V7K 0.1U_0402_25V6 PR1153
1 2 TSENSE_3PH_B 1 2 24.9K_0402_1% CSREF_3PH_B
1 2 1 2 CSREF_3PH_B <63>
+5V_ALW
1 2
<62,63,65> DRON 4/30 PR1153 change value for pmon request
PR1154 @ PJP1100 PR1151 PR1152
1
2.26K_0402_1% 1 2 2.2_0603_5% 75K_0402_1%
1U_0603_10V6K
1 2 CSP1_3PH_A
PC1130
<61,62> SW1_3PH_A @DFT@
52.3K_0402_1%
1
2
2
PAD-OPEN1x1m
PR1155
PWM1_3PH_B/ICCMAX3B <63>
3.92K_0402_1%
24.9K_0402_1%
97.6K_0402_1%
97.6K_0402_1%
1
1
PC1131
PR1160
PR1156
PR1157
PR1158
PR1159
0.1U_0402_25V6
1
2.26K_0402_1%
PWM2_3PH_B/DOSC1 <63>
2
CSREF_3PH_A CSP1_3PH_B 1 2
<62> PWM1_3PH_A/ICCMAX3A SW1_3PH_B <61,63>
PR1161
2
2.26K_0402_1%
1 2 CSP2_3PH_A PC1132
<61,62> SW2_3PH_A <62> PWM2_3PH_A/ADDR
0.1U_0402_25V6
1
2
B PC1133 CSREF_3PH_B B
0.1U_0402_25V6 PR1162
PWM3_3PH_B/DOSC3 <63>
1
2.26K_0402_1%
CSREF_3PH_A <62> PWM3_3PH_A/VBOOT CSP2_3PH_B 1 2
SW2_3PH_B <61,63>
PR1163
2
2.26K_0402_1% EMI@ PL1100
1 2 CSP3_3PH_A PC1134
<61,62> SW3_3PH_A HCB2012KF-121T50_0805
1 2 0.1U_0402_25V6
1
2
PC1135 EMI@ PL1101 +PWR_SRC CSREF_3PH_B

0.1U_0402_25V6 HCB2012KF-121T50_0805 H44@ PR1164
1
+CPU_B+ 1 2 2.26K_0402_1%
CSREF_3PH_A CSP3_3PH_B 1 2
1 1 SW3_3PH_B <61,63>
TSENSE_3PH_A TSENSE_3PH_B
100U_25V_M
100U_25V_M
2
+ +
PC1142
PC1141
PC1136 H44@
1
1
H42@ PR1170
@ PR1165
@ PR1166
0.1U_0402_25V6
0_0402_5%
0_0402_5%
1
+5V_ALW 2 2 1K_0402_1%
1 2 CSREF_3PH_B
+5V_ALW
Place close to H-side,L-side MOS
Place close to H-side,L-side MOS in VCCGT first phase
1 2
1 2
1
1
in VCORE first phase
1
@ PR1169 PH1103 PR1167 PH1104 PR1168

PHASE DETECTION 1K_0402_1% 61.9K_0402_1% 61.9K_0402_1%
220K_0402_5%_ERTJ0EV224J 220K_0402_5%_ERTJ0EV224J
2
2
2
2
CSP3_3PH_A
A A

Title
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D +VCORE
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Size Document Number Rev
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1.0
LA-C551P
5 4 3 2 1
A
B
C
D
<61>
<61>
<61,62,63,65>
<61,62,63,65>
PC1249
+5V_ALW
1U_0603_10V6K PC1209
+5V_ALW
DRON
1U_0603_10V6K
PWM3_3PH_A/VBOOT
DRON
2 1 1 2
PWM1_3PH_A/ICCMAX3A
2 1 1 2
+5V_ALW
+5V_ALW
PC1258
1U_0603_10V6K PC1212
PR1209
1U_0603_10V6K
PR1200
2 1
5
5
2_0603_5%
2 1
2_0603_5%
3
31
2
4
5
7
6
3
31
2
4
5
7
6
VCC
PWM
PU1202
VCCD
DISB#
CGND
VCC
PWM
SMOD#
+CPU_B+
PU1200
VCCD
DISB#
CGND
ZOD_EN
SMOD#
+CPU_B+
8 1
ZOD_EN
9 GL THWN 8 1
10 GL 9 GL THWN
11 GL 20 10 GL
32 GL VIN 21 11 GL 20
TEST VIN 22 32 GL VIN 21
VIN 23 TEST VIN 22
VIN 24 PC1216 VIN 23
VIN 25 10U_0805_25V6K VIN 24 PC1200
VIN 2 1 VIN 25 10U_0805_25V6K
VIN 2 1
19 28 PC1217
26 PGND GH 10U_0805_25V6K 19 28 PC1201
PGND PGND GH
NCP81382MNTXG_QFN39_4X6
2 1 26 10U_0805_25V6K
PGND
30 2 1
2
BOOT PC1218 30
2
10U_0805_25V6K BOOT PC1202

2 1 10U_0805_25V6K
VSW
VSW
VSW
VSW
VSW
VSW
VSW
PHASEF
PHASED
2 1
VSW
VSW
VSW
VSW
VSW
VSW
VSW
PHASEF
PHASED
PC1219
PR1208
1
2_0603_5%
18
17
16
15
14
13
12
27
29
2 1 2 1 10U_0805_25V6K PC1203
PR1201
1
2_0603_5%
18
17
16
15
14
13
12
27
29
1 2 2 1 2 1 2 1 10U_0805_25V6K
PC1337 1 2 2 1
0.1U_0402_25V6 PC1333
2 1 0.1U_0402_25V6
PR1211
PC1269
PC1338 2 1
PC1250
PR1206
PC1214
2200P_0402_50V7K
2_1206_5%
PC1210
2 1 PC1334
2_1206_5%
2200P_0402_50V7K
2 1
2200P_0603_50V7K
0.22U_0603_25V7-K
2200P_0603_50V7K
4
4
2
1
0.22U_0603_25V7-K
2
1
PL1202
PL1200
3
4
3
4
1
1
0.15UH_PCME064T-R15MS_36A_20%
0.15UH_PCME064T-R15MS_36A_20%
PR1210
10_0402_1%
PR1204
2
10_0402_1%
2
SW3_3PH_A
CSREF_3PH_A
SW1_3PH_A
CSREF_3PH_A
<61>
<61>
+VCC_CORE
+VCC_CORE
<61,62>
<61,62><61>
<61,62,63,65>
3
3
PC1211
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
+5V_ALW
1U_0603_10V6K
DRON
PWM2_3PH_A/ADDR
2 1 1 2
+5V_ALW
PC1213
2 1 2 1 2 1 2 1 2 1 2 1 1U_0603_10V6K
PR1203
2
1
PC1324 PC1306 PC1288 PC1270 PC1259 PC1238 PC1220 2 1

2_0603_5%
1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M

3
31
2
4
5
7
6
2 1 2 1 2 1 2 1 2 1 2 1
2
1
PC1325 PC1307 PC1289 PC1271 PC1260 PC1239 PC1221

VCC
PWM

PU1201
VCCD
DISB#
CGND
SMOD#
+CPU_B+
ZOD_EN
2 1 2 1 2 1 2 1 2 1 2 1 8 1
GL THWN
2
1
9
PC1326 PC1308 PC1290 PC1272 PC1261 PC1240 PC1222 10 GL
1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M 11 GL 20
32 GL VIN 21
2 1 2 1 2 1 2 1 2 1 2 1 TEST VIN 22
VIN
2
1
23
PC1327 PC1309 PC1291 PC1273 PC1262 PC1241 PC1223 VIN 24 PC1204
1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M VIN 25 10U_0805_25V6K
VIN 2 1
2 1 2 1 2 1 2 1 2 1 2 1
2
1
19 28 PC1205
PC1328 PC1310 PC1292 PC1274 PC1263 PC1251 PC1224 26 PGND GH 10U_0805_25V6K
PGND
1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M 2 1

30
2
2 1 2 1 2 1 2 1 2 1 2 1 BOOT PC1206
2
1
10U_0805_25V6K
PC1329 PC1311 PC1293 PC1275 PC1264 PC1242 PC1225 2 1
VSW
VSW
VSW
VSW
VSW
VSW
VSW
PHASEF
PHASED

PC1207
PR1202
1
2_0603_5%
18
17
16
15
14
13
12
27
29
2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 10U_0805_25V6K
2
2
2
1
1 2 2 1
PC1330 PC1312 PC1294 PC1276 PC1265 PC1243 PC1226 PC1335
1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M 0.1U_0402_25V6
2 1
2 1 2 1 2 1 2 1 2 1 2 1
PR1207
PC1215
PC1208
2
1
PC1336
2_1206_5%
PC1331 PC1313 PC1295 PC1277 PC1266 PC1244 PC1227 2200P_0402_50V7K

2 1 2 1 2 1 2 1 2 1 2 1
2200P_0603_50V7K
0.22U_0603_25V7-K
2
1
2
1
PC1332 PC1314 PC1296 PC1278 PC1267 PC1252 PC1228

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2 1 2 1 2 1 2 1 2 1
PL1201
2
1
PC1315 PC1297 PC1279 PC1268 PC1245 PC1229

1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M

3
4
2 1 2 1 2 1 2 1
2
1
PC1316 PC1298 PC1280 PC1246 PC1230

1
1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 10U_0402_6.3V6M 22U_0603_6.3V6M

0.15UH_PCME064T-R15MS_36A_20%
Title
Size
2 1 2 1 2 1 2 1
Date:
2
1
PR1205
PC1317 PC1299 PC1281 PC1247 PC1231

10_0402_1%
2
2 1 2 1 2 1 2 1
2
1
PC1318 PC1300 PC1282 PC1253 PC1232

Document Number
2
1
2 1 2 1 2 1 2 1
PC1233
SW2_3PH_A
PC1319 PC1301 PC1283 PC1254 22U_0603_6.3V6M

Tuesday, August 18, 2015
CSREF_3PH_A
1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 10U_0402_6.3V6M

<61>
2
1
1
1
2 1 2 1 2 1 2 1
PC1234
+VCC_CORE
<61,62>
PC1320 PC1302 PC1284 PC1248 22U_0603_6.3V6M

LA-C551P
1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 10U_0402_6.3V6M

+VCC_CORE
2
1
2 1 2 1 2 1 2 1
Sheet
PC1235
PC1321 PC1303 PC1285 PC1255 22U_0603_6.3V6M
1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 10U_0402_6.3V6M
62
+
2
1
2 1 2 1 2 1 2 1
PC1236
of
PC1322 PC1304 PC1286 PC1256 330U_D2_2.5V_R6M

1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 10U_0402_6.3V6M
+
2
1
2 1 2 1 2 1 2 1
74
PC1237
PC1323 PC1305 PC1287 PC1257 330U_D2_2.5V_R6M
Rev
1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 10U_0402_6.3V6M

1.0
A
B
C
D
A
B
C
D
<61>
<61>
Only H44e
<61,62,63,65>
<61,62,63,65>
PC1457 PC1411
H44@
+5V_ALW
+5V_ALW
1U_0603_10V6K 1U_0603_10V6K
DRON
DRON
PWM3_3PH_B/DOSC3
PWM1_3PH_B/ICCMAX3B
H44@
2 1 1 2 2 1 1 2
+5V_ALW
+5V_ALW
PC1458 PC1412
5
1U_0603_10V6K 1U_0603_10V6K
5
PR1409
PR1400
H44@
2 1 2 1
2_0603_5%
2_0603_5%
3
31
2
4
5
7
6
3
31
2
4
5
7
6
H44@
VCC
VCC
PWM
PWM
PU1402
PU1400
VCCD
VCCD
DISB#
DISB#
CGND
CGND
SMOD#
SMOD#
+CPU_B+
+CPU_B+
ZOD_EN
8 1 8 ZOD_EN 1
9 GL THWN 9 GL THWN
10 GL 10 GL
11 GL 20 11 GL 20
32 GL VIN 21 32 GL VIN 21
TEST VIN 22 TEST VIN 22
VIN 23 VIN 23
VIN 24 PC1436 VIN 24 PC1400
VIN 25 10U_0805_25V6K VIN 25 10U_0805_25V6K
VIN 2 1 VIN 2 1
H44@
19 28 PC1433 19 28 PC1401
26 PGND GH 10U_0805_25V6K 26 PGND GH 10U_0805_25V6K
PGND PGND
2 1 2 1
30 30
2
2
H44@
BOOT PC1434 BOOT PC1402
10U_0805_25V6K 10U_0805_25V6K
2 1 2 1
H44@
VSW
VSW
VSW
VSW
VSW
VSW
VSW
PHASEF
PHASED
VSW
VSW
VSW
VSW
VSW
VSW
VSW
PHASEF
PHASED
PC1437 PC1403
PR1408
PR1401
1
1
2_0603_5%
2_0603_5%
18
17
16
15
14
13
12
27
29
18
17
16
15
14
13
12
27
29
2 1 2 1 10U_0805_25V6K 2 1 2 1 10U_0805_25V6K
1 2 2 1 1 2 2 1
PC1550
0.1U_0402_25V6
PC1554
2 1
0.1U_0402_25V6
H44@
H44@
H44@ H44@ H44@
PR1411
PC1477
PR1406
PC1414
2 1 PC1551
H44@
PC1438
PC1408
2200P_0402_50V7K
2_1206_5%
2_1206_5%
PC1555
2200P_0402_50V7K 2 1
H44@
2 1
4
4
2200P_0603_50V7K
2200P_0603_50V7K
0.22U_0603_25V7-K
0.22U_0603_25V7-K
2
1
2
1
PL1402
PL1400
H44@
3
4
3
4
1
0.15UH_PCME064T-R15MS_36A_20%
0.15UH_PCME064T-R15MS_36A_20%
PR1404
H44@
PR1410
10_0402_1%
2
10_0402_1%
2
SW3_3PH_B
SW1_3PH_B
CSREF_3PH_B
CSREF_3PH_B
+VCC_GT
+VCC_GT
<61>
<61>
<61,63>
<61,63>
<61>
3
3
+VCC_GT
+VCC_GT
+VCC_GT
+VCC_GT
+VCC_GT
+VCC_GT
+VCC_GT
<61,62,63,65>
PC1409
+5V_ALW
2 1 2 1 2 1 2 1 2 1 1U_0603_10V6K
2
1
2
1
DRON
PWM2_3PH_B/DOSC1
PC1532 PC1514 PC1496 PC1478 PC1459 PC1439 PC1416 2 1 1 2

1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
+5V_ALW
2 1 2 1 2 1 2 1 2 1 PC1413
2
1
2
1
1U_0603_10V6K
PR1403
PC1533 PC1515 PC1497 PC1479 PC1460 PC1440 PC1417

1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 2 1
2_0603_5%
2 1 2 1 2 1 2 1 2 1
3
31
2
4
5
7
6
2
1
2
1
PC1534 PC1516 PC1498 PC1480 PC1461 PC1441 PC1418

1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
VCC
PWM
PU1401
VCCD
DISB#
CGND
SMOD#
+CPU_B+
2 1 2 1 2 1 2 1 2 1
ZOD_EN
2
1
2
1
8 1
PC1535 PC1517 PC1499 PC1481 PC1462 PC1442 PC1419 9 GL THWN
1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 10U_0402_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 10 GL
11 GL 20
2 1 2 1 2 1 2 1 2 1 2 1 32 GL VIN 21
TEST VIN
2
1
22
PC1536 PC1518 PC1500 PC1482 PC1463 PC1443 PC1420 VIN 23
1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M VIN 24 PC1404
VIN 25 10U_0805_25V6K
2 1 2 1 2 1 2 1 2 1 2 1 VIN 2 1
2
1
PC1537 PC1519 PC1501 PC1483 PC1464 PC1444 PC1421 19 28 PC1405

1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M 26 PGND GH 10U_0805_25V6K
PGND
2 1
2 1 2 1 2 1 2 1 2 1 2 1 30
2
BOOT
2
1
PC1406
2
2
PC1538 PC1520 PC1502 PC1484 PC1465 PC1445 PC1422 10U_0805_25V6K

VSW
VSW
VSW
VSW
VSW
VSW
VSW
PHASEF
PHASED
2 1 2 1 2 1 2 1 2 1 2 1 PC1407
PR1402
1
2_0603_5%
18
17
16
15
14
13
12
27
29
2
1
2 1 2 1 10U_0805_25V6K
PC1539 PC1521 PC1503 PC1485 PC1466 PC1446 PC1423 1 2 2 1
PC1552
2 1 2 1 2 1 2 1 2 1 2 1
0.1U_0402_25V6
2
1
PR1407
PC1415
2 1
PC1410
PC1540 PC1522 PC1504 PC1486 PC1467 PC1447 PC1424

PC1553
2_1206_5%

2200P_0402_50V7K
2 1
2 1 2 1 2 1 2 1 2 1 2 1
2
1
2200P_0603_50V7K
0.22U_0603_25V7-K
PC1541 PC1523 PC1505 PC1487 PC1468 PC1448 PC1425

2
1

2 1 2 1 2 1 2 1 2 1 2 1
2
1
PL1401
PC1542 PC1524 PC1506 PC1488 PC1469 PC1449 PC1426

3
4
2 1 2 1 2 1 2 1 2 1 2 1
Title
Size
2
1
Date:
PC1543 PC1525 PC1507 PC1489 PC1470 PC1450 PC1427

1
0.15UH_PCME064T-R15MS_36A_20%
2 1 2 1 2 1 2 1 2 1 2 1
2
1
PC1544 PC1526 PC1508 PC1490 PC1471 PC1451 PC1428

PR1405

10_0402_1%
2
2 1 2 1 2 1 2 1 2 1 2 1
Document Number
2
1
PC1545 PC1527 PC1509 PC1491 PC1472 PC1452 PC1429

Tuesday, August 18, 2015
2 1 2 1 2 1 2 1 2 1 2 1
2
1
1
1
+VCC_GT
PC1546 PC1528 PC1510 PC1492 PC1473 PC1453 PC1430

CSREF_3PH_B
SW2_3PH_B
LA-C551P
+VCC_GT
2 1 2 1 2 1 2 1 2 1 2 1
2
1
Sheet
<61>
PC1547 PC1529 PC1511 PC1493 PC1474 PC1454 PC1431

<61,63>

63
2
1
+
2 1 2 1 2 1 2 1 2 1 2 1
PC1549
PC1548 PC1530 PC1512 PC1494 PC1475 PC1455 330U 2.5V M D2 LESR6M

of
1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 10U_0402_6.3V6M 10U_0402_6.3V6M

2
1
+
2 1 2 1 2 1 2 1 2 1 PC1435
330U 2.5V M D2 LESR6M
74
PC1531 PC1513 PC1495 PC1476 PC1456

2
1
+

Rev
PC1432
1.0
330U 2.5V M D2 LESR6M

A
B
C
D
5 4 3 2 1
H44@
5/8 PR1600 from 28.7K to 27K ohm for vendor request PR1601
Only H44e 8.25K_0402_1%
1 2 81210_SWN
PR1600 place
27K_0402_1% H44@ close
1 2 PR1602
PC1600 15K_0402_1% PH1600 to Choke
470P_0402_50V8J 1 2 1 2 81210_SENSE_RETURN
1 2
H44@ H44@ 100K_0402_1%_TSM0B104F4251RZ
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
1 2 +CPU_B+
1
D H44@ PC1690 @ D
PC1601
PC1604
PC1605
PC1602
PR1603 4700P_0402_25V7K PR1604
2_0603_5% 1 2 6.19K_0402_1%
2
PC1643
PC1644
+5V_ALW 2 1 1 2
PC1603
0.01UF_0402_25V7K PC1607
PC1606 H44@ 1000P_0402_50V7K
1U_0603_10V6K
H44@ 81210_ILIM 1
H44@ 2
1 2
81210_COMP H44@ H44@ H44@ H44@ H44@
1 2 1 2
H44@
PR1605
81210_VSN PC1608 H44@
H44@ 81210_VSP 0.015U_0402_16V7K 1.5K_0402_1%
<7,55,56,61> IMVP_VR_ON PR1606 H44@ 1 2H44@
10K_0402_1%
H44@ PR1607 1 2 +5V_ALW PC1609
100_0402_1% 15P_0402_50V8J
<7,46,57,61> H_PROCHOT# 2 1 H44@ PL1600
H44@ PR1608 0.47UH_MMD05CZR47M_12A_20%
41
40
39
38
37
36
35
34
33
32
31
10_0402_1% H44@ 81210_SW1 1 4
<7,61> VR_SVID_DATA 1 2 +VCC_GTU
IOUT
ILIM
CSP
COMP
VSP
PSYS
GND
EN
VCC
CSN
VSN
H44@ PR1609 PR1610 2 3
1
0_0402_5% 150K_0402_1%
<7,61> VR_SVID_ALERT# 1 2 1 30 81210_ADDR/VBOOT 1 2 PC1610
H44@ PR1611 2 VR_HOT# DOSC/ADDR/VBOOT 29 81210_TSENSE 2200P_0603_50V7K
1 2
49.9_0402_1% 3 SDIO TSENSE 28 81210_IMAX
1 2
ALERT# IMAX H44@
2
<7,61> VR_SVID_CLK 1 2 4 27 +5V_ALW
SCLK PVCC
100K_0402_1%_TSM0B104F4251RZ
5 26 PR1612 H44@ PR1613 H44@ PR1614 81210_SENSE_RETURN
6 PGND PGND 44 10K_0402_1% 2_1206_5%
<23,61> PCH_PWROK VR_RDY GL 0_0402_5%
1
C 7 25 H44@
C
VIN PU1600 GL
1
+CPU_B+ BST1 8 24 PC1611
2 1
2
BST NCP81210MNTWG_QFN40_5x5 GL
61.9K_0402_1%
470P_0402_50V8J
PC1642 9 4.7U_0402_6.3V6M 81210_SWN
2
GH
1
0.1U_0402_25V7K 10 23
2
SW SW
2
PC1612
PR1616
22 H44@ H44@
SW
1
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PH1601
PC1642 place close to IC 21 H44@
SW
VIN
VIN
VIN
VIN
VIN
H44@ PR1615
1
2_0603_5%
2
81210_SW1
11
12
13
14
42
15
16
17
18
19
20
43
2
PC1613
0.22U_0603_25V7-K H44@
H44@ 2 1 +CPU_B+
H44@ place close to IC
H44@
H44@
+VCC_GTU
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
PR1620 PC1614 1 H44@1 1 1 1 1 1 1
1
PC1615
PC1616
PC1617
PC1618
PC1619
PC1620
PC1621
PC1622
PC1623
PC1624
PC1625
PC1626
100_0402_1% 1000P_0402_50V7K
1 2 1 2
2
PR1617 2 2 2 2 2 2 2 2
1K_0402_1%
H44@ 1 H44@ 2 81210_VSN
<12> VSSGTX_SENSE
1
PC1627
B 1000P_0402_50V7K PR1618 H44@ H44@ H44@ H44@ H44@ H44@ H44@ H44@ H44@ H44@ H44@ H44@ B
H44@
2
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
866_0402_1% 1
470U_X_2VM_R6M
81210_VSP
PC1628
PC1629
PC1630
PC1631
PC1632
PC1633
PC1634
PC1635
PC1636
PC1637
PC1638
PC1639
1 2
<12> VCCGTX_SENSE +
PC1641
H44@ PR1619
866_0402_1%
2
1 2 1 2
PR1621 2
H44@
100_0402_1% PC1640 5/8 PR1618,PR1619 from 1K to 866 ohm for vendor request
1 2
+VCC_GTU 1000P_0402_50V7K
H44@ H44@
H44@ H44@ H44@ H44@ H44@ H44@ H44@ H44@ H44@ H44@ H44@ H44@
H44@ H44@
A A

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +VCC_GTX
5 4 3 2 1
5 4 3 2 1
InputCapacitor:
10uF_0805_X5R_25V
2200P_0402_50V7K
2210U_0805_25V6K
30 0.1U_0402_25V6
+CPU_B+
1
10U_0805_25V6K
PC1700
24 PC1701
+5V_ALW
2
PC1707
PC1708
PR1701
2 1 2_0603_5%
20
21
23
25
28
1
2
PR1700 PU1700
D D
2_0603_5% PC1703
THWN
VIN
VIN
VIN
VIN
VIN
VIN
GH
BOOT
0.22U_0603_25V7-K
1
6
1
VCC
29
PHASED
1U_0603_10V6K
1
PC1702
27
PHASEF
1U_0603_10V6K
7
2
VCCD
1
PC1704
PL1700
0.47UH_MMD05CZR47M_12A_20%
2
12 1 4
5 NCP81382MNTXG_QFN39_4X6 VSW 13 +VCC_SA
CGND VSW 14 2 3
VSW 15
VSW 16
4 VSW 17 CSN_1PH <61>
<61> PWM1_1PH/ICCMAX1 PWM VSW 18
VSW
1
2
<61,62,63> DRON DISB# PC1705
2200P_0603_50V7K SW_1PH <61>
1 2
+5V_ALW 31
ZOD_EN
C C
PR1702
PGND
PGND
3 2_1206_5%
TEST
SMOD#
GL
GL
GL
GL
2
+VCC_SA
8
9
10
11
32
19
26
220U_D2_2.5VY_R9M
1
PC1706
+
2
Total VCORE Output
Capacitor:
8 X 22uF_0603_X5R
B B
A A

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +VCC_SA
5 4 3 2 1
5 4 3 2 1
C551_H42 component C551_H44e component

@H42@ H42@ H42@ H42@ @H44@ H44@ H44@ H44@
PR1153 PR1135 PR1109 PR1132 PR1153 PR1135 PR1109 PR1132
38.3K_0402_1% 22.6K_0402_1% 1.43K_0402_1% 24.3K_0402_1% 30.1K_0402_1% 24.9K_0402_1% 1K_0402_1% 25.5K_0402_1%
D D
H42@ H42@ H42@ H42@ H44@ H44@ H44@ H44@

PR1138 PR1152 PR1145 PR1147 PR1138 PR1152 PR1145 PR1147
14.3K_0402_1% 43.2K_0402_1% 56.2K_0402_1% 56.2K_0402_1% 12.7K_0402_1% 75K_0402_1% 107K_0402_1% 107K_0402_1%
H42@ H42@ H42@ H44@ H44@ H44@

PR1143 PR1146 PR1148 PR1143 PR1146 PR1148
82.5K_0402_1% 82.5K_0402_1% 82.5K_0402_1% 93.1K_0402_1% 93.1K_0402_1% 93.1K_0402_1%
C C
B B
A A

Title
PWR_table
1.0
LA-C551P
5 4 3 2 1
5 4 3 2 1
+1.0V_PRIM
5 VCCPRIM_1P0 PCH SIO_PWRBTN# 7

Timing Diagram for S5 to S0 mode DCPDSW_1P0
VCCMPHY_1P0
VCCMPHYPLL_1P0
VCCAPLL_1P0
PWRBTN#
RSMRST#
PCH_RSMRST#
6
VCCCLK1~5 SIO_SLP_SUS#
SLP_SUS#
5
SIO_SLP_S5#
SLP_S5#
SIO_SLP_S4#
8
SLP_S4# 9
SIO_SLP_S3#
+3.3V_ALW +3.3V_ALW_DSW SLP_S3#
+VCC_CORE 3 VCCDSW_3P3 SIO_SLP_A#
CPU VCC SLP_A#
+1.0VS_VCCIO
+3.3V_SPI 5 +3.3V_ALW_PCH SIO_SLP_LAN#
10
VCCHDA SLP_LAN#
D H_VCCST_PWRGD VCCIO VCCSPI D
11 VCCST_PWRGD VCCPRIM_3P3
VCCPGPPA~E
SLP_WLAN#/GPD9
SIO_SLP_WLAN#
+VCC_GTU VCCRTCPRIM RESET_OUT#
H_PWRGD
VCCGTX
5 +1.8V_PRIM SYS_PWROK
15
14 PROCPWRGD +VCC_GT VCCPGPPG
VCCATS PCH_PWROK
PCH_PWROK
VCCGT
+RTC_CELL 13
+1.2V_MEM VCCRTC VCCST_PWRGD
VDDQ +1.0V_PRIM
5 +1.0V_PRIM
VCCST_PWRGD
11
DDR_PG_CTRL +1.0V_VCCST 9 SIO_SLP_S4# VCCPRIM_CORE
11 DDR_VTT_CNTL VCCST TPS22961 PROCPWRGD
H_CPUPWRGD
14
+1.0V_VCCSTG PCH_PLTRST#
VCCSTG 17 PLTRST#
+VCC_SA
VCCSA 11
+VCC_SFR_OC DGPU_PWR_EN DGPU_PEX_RST#
PCH_DPWROK GPP_D13 MXM
VCCPLL_OC
4 DSW_PWROK
16
+VCC_VDDQ_CLK
VDDQC
+3.3V_ALW
+LCDVDD APL3512ABI
ENVDD_PCH
EDP_VDDEN 11
+PWR_SRC DGPU_PWROK
GPP_D18
+1.0V_PRIM SIO_SLP_SUS# +3.3V_ALW
5 TPS51212DSCR
SIO_SLP_LAN# DGPU_HOLD_RST#
+3.3V_ALW 10 +3.3V_LAN EM5209VF SLP_LAN# GPP_D10
PLTRST#
TC7SH08FU
PLTRST_GPU#
5 +1.8V_PRIM
SY8032ABC
C C
Power Button
SIO 5048 1BAT 2AC

10 SIO_SLP_WLAN#
10 ADAPTER
+PWR_SRC
+5V_ALW ALWON
+5V_ALW2
RUN_ON
EC 5085
+5V_ALW
+3.3V_RUN +5V_RUN +5V_HDD
EM5209VF TPS51225CRUKR +3.3V_RTC_LDO
CCD_OFF +3.3V_ALW2
+CAMERA_VDD DMG2301U +3.3V_ALW BATTERY
+3.3V_ALW
EM5209VF +3.3V_RUN +3.3V_HDD
PCH_RSMRST#
+3.3V_ALW
+3.3V_RUN
6
11
DGPU_PWROK 11 EM5209VF
APL5930 +1.5V_RUN 4 PCH_DPWROK PCH_ALW_ON +3.3V_ALW_PCH 5
+PWR_SRC
RESET_OUT#
+3.3V_ALW @SIO_SLP_WLAN# TLV62130 +1.0VS_VCCIO 15 @SIO_SLP_A#
10 +3.3V_WLAN EM5209VF AUX_EN_WOWL 5 SIO_SLP_SUS#

+3.3V_ALW
B
9 SIO_SLP_S4#
10 Pop option B
A_ON
SIO_SLP_S5#
EM5209VF +3.3V_M +3.3V_SPI
8
SIO_SLP_LAN#
9 +3.3V_ALW
10 SIO_SLP_S3# SUS_ON
EM5209VF +3.3V_SUS
SIO_SLP_A#
+PWR_SRC +PWR_SRC
11 EN_INVPWR
19
+VCC_SA IMVP_VR_ON
FDC654P-G +BL_PWR_SRC
12 +VCC_CORE NCP81205MNTXG
+VCC_GT
9 +PWR_SRC
13 PCH_PWROK
SIO_SLP_S4#
+1.2V_MEM
+PWR_SRC VDDQ
RT8207MZ VTT
DDR
+VCC_EDRAM +0.6V_DDR_VTT
+VCC_EOPIO SYX198DQNC
+PWR_SRC 0.6V_DDR_VTT_ON
11
+VCC_GTU NCP81210MNTWG
BC BUS
A A

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Power Sequence
1.0
LA-C551P
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R.

List )
Item Page# Title Date
Request Owner
Issue Description Solution Description Rev.
D Add RH343,RH344,RZ75,TPM PWR rail change to +3.3V_ALW_PCH D
1 22,37,49 HW 12/6/2014 compal reserve SPI and TPM PWR rail optional ,add @RH348 to +3.3V_M power rail option for +3.3V_1.8V_SPI. X01(0.2)
+3.3V_ALW_PCH or +3.3V_M.
2 37,46 HW 12/6/2014 compal GPIO MAP:Gen7_GPIO1211 U51.B62 change netname from POA_EN to EC_FPM_EN and U51.A9 change X01(0.2)
netname from SUS_ON to CV2_ON for follow GPIO MAP
3 45 HW 12/6/2014 compal Avoid backdrive to +3.3V_RUN. R3740.2(UPD_SMBUS_ALERT#) PWR rail change from +3.3V_RUN to +3.3V_ALW. X01(0.2)
48 HW 12/6/2014 compal TP I2C interface reserve 0ohm add R3752,R3758 X01(0.2)
4
28,35 HW 12/9/2014 compal symbol link CIS normal CPN update U8 symbol for SA00007ZW00,update U31 symbol for SA000081G0L X01(0.2)
5
24 HW 12/9/2014 AMD aviod incorrect behavior when system w/AMD Reserve a pull up 10k(RH345) to +3.3V_ALW_PCH close to PCH side on X01(0.2)
6 MXM cards GPU_EVENT#
7 25,30 HW 12/10/2014 compal add "+" on PWR trace netname and others no "+" add netname +DCPRTC on CH68.1,change netname +3.3V_CAM_EN# to X01(0.2)
3.3V_CAM_EN#
8 38 HW 12/10/2014 compal symbol CPN and Value not match. change C1176,C1402 PN to SGA00002B00,and depop C1402 X01(0.2)
9 30 HW 12/11/2014 compal align BC change Q24 main source change Q24 to SB00000QP00 X01(0.2)
C C
10 23 HW 12/15/2014 RF RF request change CH268 from 0.01uF to 22pF X01(0.2)
11 45,46 HW 12/17/2014 compal Gen7_GPIO1211 remove R851,R852,R853,R854,change netname CPU_ID to GPIOL0,U51.A40 to X01(0.2)
MSDATA,U51.B43 to MSCLK,U51.B46 to PCH_PCIE_WAKE#,U46.A64 to
ME_FW_EC,U46.A8 to USB_PWR_SHR_LFT_EN#
12 19,42,41 HW 12/19/2014 compal SATA express HDD function issue-PCIE13~16 lane SATA express interface change to PCIE14(match HDD port1),PCIE13(match X01(0.2)
reverse HDD port0),UH1.AG39 change to HDD_DET#,UH1.AD35 to SATA_EXP_IFDET.
13 46 HW 12/23/2014 compal reserve for next-gen EC that use the Intel add R862,R863,change netname GPP_C9 to SBIOS_TX X01(0.2)
chipset UART TXD for the SBIOS Serouts
14 46 HW 12/29/2014 compal SB339045100 EOL change Q28 to SB000008P00 X01(0.2)
15 22 HW 12/30/2014 compal solve TPM PLTRST leakage add RH346 and depop RH187,RH196, change U638.5 to_3.3V_ALW_PCH X01(0.2)
16 6,39,35, HW 12/30/2014 compal same Value a CPN on Board PEG 0.22UF AC CAP(CC1~CC64) and SSD 0.22UF AC X01(0.2)
47,22,7,36 CAP(CN83,CN85~CN88,CN91,CN92,CN95,CN97)change from SE00000R700 to
SE095224K00
U15,U58,U638,UC4 change from SA007080120 to SA007080180
Q327 change from SB00000ST00 to SB00000UO00
B T156 change from SP050006P00 to SP050006Y00 B
17 21 HW 12/30/2014 compal DG1.0 RTC Crystal MAX ESR is 50Kohm YH1 change to SJ10000LV00 X01(0.2)
18 42 HW 12/30/2014 compal HDD SATA/PCIE repeater change to GEN3 chip UN8,UN9 change from PS8555 to PS8558(SA00008DT00),CN75,CN71 change to X01(0.2)
0.01uF,CN70,CN63,CN69,CN76,CN64,CN72,CN79,CN65,CN74,CN80,CN66,CN81
change to 0.22uF,remove CN77,CN68,CN82,CN78,add RH99~RH111,RH114~RH130
19 23 HW 12/31/2014 compal MOW Rev1.0-To enable Direct Connect Interface RH329 change to 150kohm(SD028150380) and pop it,reserve RH347 pull up X01(0.2)
(DCI),a 150K pull up resistor will need to be to +3.3V_RUN,add RH353,@QH5
added to PCHHOT# pin.
20 37 HW 01/05/2015 compal System will shut down as soon as system power add DZ3,RZ76,RZ72,RZ73.change JUSH1.9 from +5V_ALW2 to +5V_ALW, X01(0.2)
on with FPM and RFID/NFC testing result is JUSH1.10 from +3.3V_ALW2 to +5V_ALW2,JUSH1.25 from GND to +3.3V_ALW2,
failed JUSH1.26 from GND to +PWR_SRC.
21 39 HW 01/06/2015 compal no business with vender-KEMET change C619 from SGA00000N00 to SGA00002B00 X01(0.2)
A A
Title
EE P.I.R -01
1.0
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R.

List )
Item Page# Title Date
Request Owner
Issue Description Rev.
Solution Description
D D
22 15,17 HW 01/06/2015 compal CONN LIST1124 change JDIMM2 to ADDR0106-P005A, JDIMM4 to ADDR0107-P005A X01(0.2)
23 46 HW 01/06/2015 compal Board ID change R875 to 130Kohm(SD028130380) X01(0.2)
24 28 HW 01/08/2015 compal USH SMBUS PULL UP when wo/ USH/B remove R3738,R3739,Q366 BS AAC@(let them always pop w/USH or wo/USH) X01(0.2)
25 21 HW 01/08/2015 compal Crystal EA change CH13,CH14 from 22pF to 15pF, X01(0.2)
C743 from 22pF to 27pF, C741P from 22pF to 33pF
26 18,20,30 HW 01/08/2015 compal cost saving change U17,UC3 from SA00003Y000 to SA000046R00,U33 from SA00003AR00 to X01(0.2)
SA00006Y800 and add @R42,change Q21 from SB000009K10 to SB000010C00
27 46 HW 01/08/2015 compal EC5085 change CPN change U51 to SA00006YH60 X01(0.2)
28 22 HW 01/09/2015 compal ADD PWR net on pin16 of JSPI1 netname is +3.3V_SPI_RWR on JSPI1.16 X01(0.2)
29 22 HW 01/09/2015 compal PLTRST group change balance before AND GATE add RH349,@RH350,change RH210.1 to PCH_PLTRST#,RH337.1 to X01(0.2)
30 and after PCH_PLTRST#_AND,RH195.1 to PCH_PLTRST#
31 24 BIOS 01/13/2015 compal AMI BIOS Bidirection debug remove dummy net PCH_NFC_RST,add RH351,RH352 PU to +3.3V_ALW_PCH and
add @RH354,@RH355 PU to +3.3V_RUN on UH1.AR39,UH1.AR45,add JUART1 X01(0.2)
32 14 HW 01/14/2015 compal MOW rev1.0 ww02- recommended not to install depop CD16
any capacitor on DDR Reset signal (DRAMRST) X01(0.2)
C 33 28 HW 01/19/2015 compal resevrve AAC SMBUS control from PCH add R38,R39,@R40,@R41,and R40.2 connect to UH1.AT42, R41.2 connect C
to UH1.AR38 X01(0.2)
34 47 ME 01/19/2015 compal Screw hole Add H42,H43,H44
X01(0.2)
35 10,11 HW 01/20/2015 intel VENDER suggestion remove RC218,@RC219,@RC311
X01(0.2)
36 47 HW 01/20/2015 COMPAL LED limit current R value change R955 to 2.21k, R956 to 3k, R130 to 1.8k, R131 to 560
X01(0.2)
31,32 HW 01/20/2015 COMPAL DOCK DP1,DP2 EA pop R119,R121(PEQ=8.5dB),RV29,RV35(PEQ=8.5dB)
37
X01(0.2)
38 37 HW 01/21/2015 COMPAL TPM improve S3 support and back drive issue Add RZ78,@RZ79,@RZ77,@RZ80,QZ2,RZ82,change U637.1 to
+3.3V_ALW_PCH,U637.8 to +U637_TPM,U637.12 to NC X01(0.2)
39 7 HW 01/26/2015 COMPAL Solving for when system force shut down,it add @R43,@RC327,UC5,UC6
can't power on with power botten between 1 X01(0.2)
minute.
40 35 HW 03/18/2015 COMPAL LAN EA change L63~L70 to 0ohm(R63~R70) X02(0.3)
B B
546717_SKL_PCH_H_EDS_R1_2(add a 1K PD for add RH356,RH357 pull down to GND
41 20 HW 03/18/2015 COMPAL USB2_VBUSSENSE and USB2_ID, if the signal is X02(0.3)
not used.Else it impacts Intel DCI test with
warm boot)
DOCK E-SATA signal reverse SWAP SATA_PTX_C_DRX_P1 to JDOCK1.60(C699.1),SATA_PTX_C_DRX_N1 to
42 43 HW 03/18/2015 COMPAL JDOCK1.62(C700.1) X02(0.3)
43 37 HW 03/18/2015 COMPAL reserve @RZ111 for modern standby,RZ112 for add @RZ83 connect to SIO_SLP_S0#,RZ112 between PCH_SPI_CS#2_R and
TPM detect issue. QZ2.2 X02(0.3)
44 46 HW 03/18/2015 COMPAL material lack change R374 from 0603 to 0402 X02(0.3)
45 30 HW 03/18/2015 COMPAL for AAC function Pop R40,R41, De-pop R38, R39 X02(0.3)
46 18 HW 03/18/2015 COMPAL solve never detect Hot plug event input at add R71,C1470,D95,R72change U14.1,U25.1,U27.1 from DGPU_PWROK to
Optimus GPU off DGPU_PEX_RST#_D,remove @C95,@C96 X02(0.3)
A 47 24 HW 03/18/2015 COMPAL reserve DIMM TYPE selection add RC329 X02(0.3) A
Title
EE P.I.R -02
1.0
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List )

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
D D
48 47 HW 03/18/2015 COMPAL material lack change R374 from 0603 to 0403 X02(0.3)
49 46 HW compal Board ID
03/18/2015 change R875 to 33Kohm X02(0.3)
50 47 HW 03/18/2015 compal screw hole Remove H15 X02(0.3)
51 7 HW 03/18/2015 compal XDP working De-pop RC314,RC315,add RC330 X02(0.3)
52 44 HW 03/18/2015 compal Keep VBUS PWR stable change JIO2.17 from +PWR_SRC to +VBUS_DC_SS X02(0.3)
53 7,23 HW 03/18/2015 compal backdrive and DG1.0 change RC315.1,RH312.1,RH314.1,RH315.1 from +1.0V_VCCSTG to X02(0.3)
+1.0V_VCCST
54 24,30 HW 03/18/2015 compal IR camera detect pin for verb table add GPP_A23 to IR_CAM_DET# and connect to JEDP1 pin26,add R366 pull X02(0.3)
up to +3.3V_RUN
55 47 HW 03/18/2015 compal LED luminance adjust R956 to 1k, R130 to 1k, R131 to230, R943 to 1k, R955 to 1k X02(0.3)
C C
56 38 HW 04/21/2015 compal reserve SIM detection design add RZ113 between SIM pin1(JSIM1) to WWAN pin58(JNGFF2) X03(0.4)
57 48 HW 04/21/2015 compal TP module add damping R,PU and new touchpad Depop R3752,R3758,add RZ114,RZ115 pull up to +3.3V_TP X03(0.4)
support PS2(in DOS),I2C bus(in OS)
58 45 HW 04/24/2015 compal BITS211484: Left IO/B USB port 1 can't charge add RE72,RE73,RE74,RE75,RE76 pull up to +3.3V_ALW. X03(0.4)
smart mobile device under S3/S4/S5
59 45 HW 04/27/2015 DELL AAC update BOM for mic change C1420 and C365 from 0.1uf to 2.2uF. X03(0.4)
60 28 HW 04/27/2015 broadcom USH reset by BCM58102 depop RH359 X03(0.4)
61 18 HW 05/18/2015 NVIDIA add test pad on DVI_HPD of MXM Add T217 on DVI_HPD X03(0.4)
62 46 HW 05/18/2015 NVIDIA common EC code change U51 from SA00006YH60 to SA00006YH30. X03(0.4)
63 47 HW 05/18/2015 compal HDD active LED behavior for PCIe M.2 SSD add D97,D98,D99,and add R383 PU to +3.3V_RUN,R384 PU to+3.3V_SSD1, X03(0.4)
B
module R385 PU to +3.3V_SSD2 B
63 48 HW 05/21/2015 compal BOM change for Touchpad function pop CZ30,CZ31 and change them to 330pF X03(0.4)
63 44,45 PWR 05/21/2015 compal TBT PD power support change JIO1.36 from GND to DCIN_ACOK#,and add PROCHOT_GATE on U46.A61 X03(0.4)
64 45 BIOS 05/21/2015 compal EC detect for AR/B or non AR/B change JIO1.34 from GND to PD_ACE_DET#,and add it on U46.A60 and X03(0.4)
RE77 PU to +3.3V_ALW
65 46 HW 05/22/2015 compal board ID change R875 from 33Kohm to 4.3Kohm X03(0.4)
66 41,47 HW 05/22/2016 compal HDD active LED behavior for SATA EXPRESS HDD add U639,R386,D100,and add R387 PU to +3.3V_RUN X03(0.4)
67 26 HW 05/22/2016 compal reserve 0.1uF for 5.76G noise add @CH269 X03(0.4)
68 44 HW 06/15/2016 compal GPIO pin can direct PU/PD no need serise R to change R388 from 10kohm to 0ohm X04(0.5)
limilt current
A A
68 44 HW 06/15/2016 compal QS CPU no need PD on SPI0_IO3 for boot depop RH334 X04(0.5)
Title
EE P.I.R -03
1.0
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List )

Request
D D
69 18 HW 06/15/2016 compal MXM3.1 SPEC remove @R6,@R1979,change JMXM1 pin268,pin270 to +3.3V_MXM X04(0.5)
70 19,45 HW 06/15/2016 compal reserve GPIO pin for tell EC don't read GFX connect RH342.1 to U46.A48,remove R3749 X04(0.5)
Temp.in GC6
71 45 HW 06/15/2016 compal PROCHOT_GATE initial status add @R415 PU to +3.3V_ALW,R416 PD to GND X04(0.5)
46 HW 07/05/2015 compal power on/off sequence tCPU05/tPLT18/tCPU03 add U9,@C787 for tCPU05 and tPLT18,add RC331,CC273 for tCPU03,add X05(0.6)
72 and global reset issue @Q370,R435 for global reset
73 37 HW 07/05/2015 compal TPM DS3 support change U637.1 from +3.3V_ALW_PCH to +3.3V_ALW X05(0.6)
74 46 HW 07/05/2015 compal Board ID change R875 from 2kohm to 1kohm X05(0.6)
75 42 HW 07/29/2015 compal SATA IEMT CTLE(change RX EQ from level 1 to 2) pop RN130 A00(1.0)
76 41 HW 07/29/2015 compal SATA PWR supply for over loading pop C404,change C403 for 0.1uF to 22uF,and pop it. A00(1.0)
77 11 HW 07/31/2015 compal VCCPLL_OC power gate requirement for Deep depop RC302,add UZ30,@RC330,@CZ95,@CZ96,CZ97,UC7,@CZ98 A00(1.0)
Sleep support
C change RC135.1,RH312.1,RH314.1,RH315.1 from +1.0V_VCCST to C
78 7,23 HW 08/07/2015 compal backdrive and CPU EDS0.95 +1.0V_VCCSTG A00(1.0)
79 46 HW 08/03/2015 compal Board ID change R875 from 1kohm to 62kohm A00(1.0)

80 22,35,46 HW 08/07/2015 compal MP component CPN change UH1 to SA00009602L,U31 to SA000081G1L,U51 to SA00006YH90 A00(1.0)
81 7,23,28,44,49 HW 08/13/2015 compal MP BOM change depop R3739,R3738,R40,R41,U8,C31~C36,R23~R30,C141,C143,C365 A00(1.0)
,C1420,R373,R375,R414,R410,R413,R411,R361,R362(drop AAC),
SW1,SW2,R3728,UZ28,C513,C547,pop RC301
B B
A A
Title
EE P.I.R -03
1.0
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List )Page 1

Request
D Item Page# Title Date Owner Issue Description Solution Description Rev. D
1 P57 POWER 1/6 COMPAL BQ24780 IFAULT LOW latch off 1. PC702 chagne to 0.1uF
2. PC704 change to 0.01uF PR02
1. PU101 change to TPS51285B

2 P51 POWER 1/6 COMPAL PU101 change to TPS51285B 2. PC100/PC118 chagne to 4.7uF
3. add PR114 PR02
4. PR105 change to 29.4k ohm
3 P64 POWER 1/19 COMPAL VCC_GTU sense Add PR1620/PR1621 100ohm PR02
C
1. PR1109 change to 1.43k ohm C
2. PR1137/PR1133 change to 3.65k ohm

4 P61 POWER 1/28 COMPAL VCORE parameter adjust 3. PC1121/PC1124 change to 100pF
for vendor request 4. PR1132 change to 25.5k ohm
5. PC1123/PC1125 change to 0.1uF
6. PC1104 change to 2200pF PR02
7. PR1112 change to 30k ohm
8. PC1107 change to 6800pF
10. PR1152 change to 75k ohm
change unmount PC215 change to numount

5 P52 POWER 3/18 COMPAL for HW request(power sequence) PR03
B B
6 P53 POWER 3/18 COMPAL Add RC

for HW request(Power sequence) Add PR317/PC312 PR03
7 P57 POWER 3/18 COMPAL change to connect RENG for Add PD703 in IC RENG pin PR03
BATTERY reverse input protection
change VCC_GTU parameter PR1604 change to 6.19k ohm PR03

8 P64 POWER 3/18 COMPAL for Vendor request add PC1690 to 4700p F
P57 Add circuit to prevent Add PD704/PR766~PR770/PQ708 PR03
9 POWER 3/24 COMPAL +SDC_IN oscillation Add PD1101/1033~PR1037/PQ1005
P60
A A
Security Classification Compal Secret Data Compal Electronics, Inc.

2013/10/01 2015/07/08 Title
Issued Date Deciphered Date
PWR-PIR
Size
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. Page

D Item Page# Title Date List ) Owner
Request
Issue 2 Solution Rev. D
Description Description
10 P61 POWER 3/26 COMPAL Add PR1170 for CPU H LINE-42 Add PR1170 PR03
4/29 COMPAL change CHARGER parameter PR744 change to 37.4k ohm PR03
11 P57 POWER for Vendor request
Add circuit to detect Add PQ1073(SB00000DH00)

12 P57 POWER 4/30 COMPAL /PR771(SD028000080) PR04
type C current
,PR772(SD034100380)
,PR773(SD028000080)
C 13 P61 POWER 4/30 COMPAL change VCORE parameter

for Vendor request 、PR1153 change to 30.1k ohm(H44e)
38.3kohm(H42)
PR04 C
Add PD1102/PD1103(SCS0340L010)
14 P60 POWER 5/8 COMPAL Add circuit for avoiding type C /PR1026 100ohm(SD014100080) PR04
current to flow to battery
15 P57 POWER 5/14 COMPAL Change the charger ILIM circuit

PR758 from 18K to 20K PR760
from 3.16K to 5.36K and PR764
、 PR04
for current sense
from 20K to 2.74K
16 P57 POWER 5/19 COMPAL Add circuit for the PD Add PC151(SE102104K00)/ PR04
PQ1074(SB00000DH00)/
PU105(SA007080120)
B B
17 P50 POWER 6/8 COMPAL Add diodes for ESD team Add PD4/PD6(SCA00000T00) PR05
request
18 P50 POWER 6/15 COMPAL Change PU1 for ESD issue Change PU1 from SA00003DN00 PR05
to SA00001WK00/ depop PD4/PD6
19 P61 POWER 6/23 COMPAL change VCORE parameter PR1153 change to 24.9k PR05
for IPCC solution ohm(SD034249280)
20 P52 POWER 7/6 For tCPU05 (VDDQ 1.2V to Depop PC312/PR303 Remove PR317
COMPAL VCCIO 1.0V) add one AGATE Change EC netname(to HW) from
P53 PR06
7408 and control by SIO_SLP_S3# to RUN_ON_AND
SIO_SLP_S3# and Pop PR209
A
1.2V_SUS_PWRGD(for HW ) Add offpagethe for 1.2V_SUS_PWRGD A

2013/10/01 2015/07/08 Title
PWR-PIR
Size
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List )Page 3

Request
21 P58 POWER 8/3 COMPAL Add circuit control line for 1.pop PR804
2. add line PCH_ALW_ON and PR10
D dirty shutdown issue D
PR809 0 ohm(depop)
3.depop PC800
C C
B B
A A

2013/10/01 2015/07/08 Title
PWR-PIR
Size
5 4 3 2 1

LA-C551P (AAPB0) 2015-08-18, Rev 1.0 (A00)

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LA-C551P (AAPB0) 2015-08-18, Rev 1.0 (A00)

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A B C D E

REV : 1.0 (A00)

TB@ : Thunderbolt function

Layout Dell logo

mDP mDP DDI3 DP_D P.6~13

USB3 Port 1 USB 3.0 Repeater

SDXC P.6 PI3L720ZHEX SSD

Date: Tuesday, August 18, 2015 Sheet 2 of 74

Port 1 Left Side JUSB1 Lane 3 MMI(Card reader)

Port 2 M.2 Slot-2 (WWAN/LTE/HCA) Lane 4 10/100/1G LOM

Port 3 Right Side JUSB1 Lane 5~8 TBT-Alpine Ridge

Port 4 Right Side JUSB2 Lane 9~12 SSD 2280

Port 5 Right Side JUSB3 Lane 13 M.2 Slot-2 (WWAN/LTE/HCA)

Port 6 Docking Lane 15~16 HDD SATA-Express

Date: Tuesday, August 18, 2015 Sheet 3 of 74

SIO_SLP_SUS# TPS51212 SIO_SLP_S4# TPS22967

+3.3V_RUN +LCDVDD +1.8V_ALW +2.5V_MEM

Date: Tuesday, August 18, 2015 Sheet 5 of 74

Date: Tuesday, August 18, 2015 Sheet 6 of 74

BP19 CFG14 @XDP@ RC315 0_0402_5%

BH31 BT19 CFG15 2

VR_SVID_DATA RC158 499_0402_1% PROCHOT# CFG[16] BP22 CFG19

XDP_OBS1 @ RC312 1 2 0_0402_5% XDP_OBS1_R

BM31 @ RC313 0_0402_5%

PLTRST_CPU# BP35 PROCPWRGD BT28 CPU_XDP_TDO

<46> IMVP_VR_ON_EC IN1 IMVP_VR_ON

Date: Tuesday, August 18, 2015 Sheet 7 of 74

Date: Tuesday, August 18, 2015 Sheet 8 of 74

Compal Electronics, Inc.

BK17 VCCOPC PAD~D @ T1 D1 BM33 T26 @ PAD~D

Date: Tuesday, August 18, 2015 Sheet 10 of 74

+VCC_GT +VCC_SA +1.2V_MEM

+1.0V_VCCSTG source +1.0V_VCCSTG

VIN2 +5V_ALW 7 6 +1.0V_VCCST_UZ18 2 1 1 2

<23,37> SIO_SLP_S0# IN1 4

RC331 0_0402_5% UC1

Date: Tuesday, August 18, 2015 Sheet 11 of 74

PLACE CAP BACKSIDE ?

AR32 N13 U31

AR35 AH37 N31 U34

Date: Tuesday, August 18, 2015 Sheet 12 of 74

All VREF traces should

0_0402_5% 0_0402_5% 0_0402_5% 213 214

DDR_A_DQS#6 219 VSS77 VSS78 220

DIMM2 0 0 0 229 230

@ RD30 @ RD29 @ RD28 231 232

239 DQ56 VSS87 240 DDR_A_DQS#7 NC VCC @ CD144 0.1U_0402_25V6

Date: Tuesday, August 18, 2015 Sheet 14 of 74

JDIMM2 STD Type H=4

+V_DDR_REFCA_A DDR_A_BA1 145 146 DDR_A_MA10

161 162 T52 @ PAD~D

DIMM Select +3.3V_RUN +3.3V_RUN +3.3V_RUN

DDR_A_D40 191 192

0_0402_5% 0_0402_5% 0_0402_5% DDR_A_D45 195 196

201 DM5_n/DBI5_n DQS5_t 202

DIMM2_SA1 +3.3V_RUN_DIMM2 205 DQ46 DQ47 206

SA0 SA1 SA2 207 208

DIMM2 211 212

@ RD35 @ RD36 @ RD31 213 214

DDR_A_DQS6 221 DQS6_c DM6_n/DBI6_n 222

Date: Tuesday, August 18, 2015 Sheet 15 of 74

JDIMM3 STD Type H=5.2

DIMM Select +3.3V_RUN +3.3V_RUN +3.3V_RUN DQ38 VSS61 DDR_B_D37