Overview of Power Integrity Solutions On Package and PCB: Decoupling and EBG Isolation

O ve r vie w o f P o w e r I nt e gr i t y S o lut io ns o n
P a c k a ge a nd P C B : D e c o up l i n g a nd EB G I s o la t io n. P age |1
CHAPTER 1
INTRODUCTION
POWER DISTRIBUTION NETWORK (PDN) design

has become one of the major concerns in designing high-speed circuits or mixed-
signal systems in recent years [1]-[4]. The challenge is expected to increase in next
decade, as electronic systems are driven in the direction of faster digital speed, higher
integration with RF circuits, and higher throughput of data communication [5].
Table 1.1:Trend of high-performance microprocessors predicted by the International

Technology Roadmap of Semiconductors (ITRS).
YEAR INTERCONNECT ON-CHIP POWER MAXIMUM

PITCH(nm) CLOCK(GHz) SUPPLY(V) POWER
DENSITY(watts/mm)
2010 45 5.9 1.1 0.96
2012 36 6.8 1.0 1.11
2014 28 7.9 1.0 1.17
2016 22.5 9.2 0.9 1.07
2018 17.9 10.7 0.9 1.19
2020 14.2 12.4 0.8 1.24
2022 11.3 14.3 0.8 1.73
Dept. of Electronics & Communication Govt. College of Engineering,Kannur

Table1.1 shows the trend of high-performance

microprocessors predicted by the International Technology Roadmap of
Semiconductors (ITRS) in 2008 for the next decade [6]. As the interconnect pitch
decrease to 11.3 nm in 2022, the power and on-chip clock speed are expected to
increase to 14.3 GHz with a corresponding decrease of the power supply level to 0.8
V and a corresponding increase of the maximum power density to 1.73 (W/mm2 ).
These trends imply that the demands of fast transient currents above the gigahertz
range will significantly increase for IC with lower dc power levels. The PDN noise
above gigahertz will be expected to be serious because the distributed and parasitic
effects of the PDN become dominant at higher frequencies. The power integrity (PI)
design will be more challenging due to the wider bandwidth of the noise energy on
the PDN with a smaller noise margin in the dc power level.
The coupling between the PDN and the high-speed
signal channels will be another main source of PDN noise [7]-[10]. It is predicted that
the speed of the point-to-point differential signals for chip-to-board peripheral buses
will be 40 Gb/s in the next decade [6], [9] .The gigahertz-band noise caused by the
differential via transition between the power/ground planes, the crossing of the
reference plane discontinuities like slots and the unbalanced discontinuities on the
connectors will couple to the PDN [10]. The noise will either degrade the PI or
become a source of radiated emission [or electromagnetic interference (EMI) [10].
Three main issues could result from poor PDN design.
They are signal integrity (SI) issue, EMI issues, and platform interference [also called
RF interference (RFI)] issues. SI has shown to be strongly correlated to the PI
because the pull- up or pull-down capability of the transistors is dependent on their dc
bias level. The SI in terms of jitter and the eye opening of high-speed signals will be
degraded by the fluctuated (or the noisy) dc power level [1], [2]. The PDN noise can
also propagate through the package or printed circuit board (PCB) and be the source
of EMI. The radiation is through the antenna- like structures, such as the I/O cables,
chassis slots, connectors, or heat sinks. The RFI issue is the sensitivity (or throughput)
degradation for the RF communication circuits caused by the near-field interference

due to the PDN noise. It is expected to be a challenging problem for the high-density
integration of RF and digital circuits in a compact package or system boards [12]-[14].
There are two possible ways to reduce PDN noise. The
first priority way is keeping the PDN impedance very low in a wide frequency range,
except at dc, by employing shunt capacitors, which can be in-chip, package, or PCB
levels[15]-[28]. Ideally, it is the most effective approach to reduce PDN noise
because the low impedance PDN can immediately provide the required transient
currents to the switched transistors, and at the same time, eliminate the noise from
spreading throughout the whole PDN. However, practically, decoupling capacitors
are band-limited for providing a low-impedance path between the power and ground
due to the inevitable series inductance in the implementation of the capacitor. The
decoupling capacitors will become inductive and ineffective in reducing the PDN
noise above the self- resonance frequency. In this scenario, the isolation approach that
keeps part of the PDN at high impedance is another way to mitigate the PDN noise
propagation. The typical isolation approaches include etched slots on power or
ground planes, a π filter with beads, or electromagnetic band gap (EBG) structures.
This approach is effective to prevent the PDN noise from coupling throughout the
whole PDN and is useful in solving some EMI and RFI problems, but it is s hort of
providing the transient current to the switched transistors due to the inherent series
high impedance on the PDN.

CHAPTER 2
STRUCTURE OF A MULTILAYER PCB
A structure of a multilayer printed circuit board

includes a power layer, a ground layer, and a dielectric layer. The dielectric layer is
located between the power layer and the ground layer. The dielectric layer has a
relative permittivity and a relative permeability, wherein the product of the relative
permittivity and the relative permeability substantially decreases along with an
increase in frequency within a frequency range.
A VIA (Vertical Interconnect Access) is a vertical

electrical connection between different layers of conductors in a printed circuit board.
It consists of two pads, in corresponding positions on different layers of the board that
are electrically connected by a hole through the board.
Fig.2.1: Multilayer PCB with VIA connection.

The hole is made conductive by electroplating, or is

lined with a tube or a rivet. High-density multilayer PCBs may have microvias: blind
vias are exposed only on one side of the board, while buried vias connect internal
layers without being exposed on either surface. Thermal vias carry heat away from
power devices and are typically used in arrays of about a dozen.
A via consists of:
1. Barrel — conductive tube filling the drilled hole

2. Pad — connects each end of the barrel to the component, plane or trace
3. Antipad — clearance hole between barrel and no-connect metal layer
In integrated circuit design, a via is a small opening in

an insulating oxide layer that allows a conductive connection between different
layers. A via on an integrated circuit is often called a through-chip via. A via
connecting the lowest layer of metal to diffusion or poly is typically called a
"contact".

CHAPTER 3
FUNDAMENTAL CONCEPTS OF POWER INTEGRITY
3.1. POWER DISTRIBUTION NETWORKS:

Power distribution network covers largest part of PCB
and rapidly switching current flow through it.
Fig.3.1.1: Typical computer system and corresponding PDN’s

Fig.3.1.1 shows a typical computer/communication circuit system and the
corresponding PDNs. The CPU, memory circuits, and the RF communication system
in package (SiP) are the three main parts of the system.
Fig.3.1.2: Conceptual circuit model of a simple signal path from a transmitter to a

receiver IC and their corresponding PDN.

The PDN from the transistor level to the system level

can be mainly described by three kinds of elements, shunt capacitors, series inductors,
and distributed transmission lines.
The shunt capacitors are the key element to keep the
PDN at low impedance and to provide the necessary transient current.
The effective series inductance (ESL) of the capacitor
causes an ideal short-circuit at the self-resonant frequency (SRF). The capacitor will
become inductive above the SRF. In general, the decoupling capacitors on-chip,
package, or PCB levels can response to the transient current in the frequency band of
above gigahertz, several hundred megahertz to gigahertz, and kilohertz to megahertz,
respectively, because the ESL is increased from pico henry (pH) on the chip level to
several nano henry (nH) on the PCB level.
The other two elements, series inductor and the
transmission line, are the parts that cause PDN noise because they will impede the
transient current demand from a switched tra nsistor. The electrically short
power/ground interconnects from chip to PCB, such as the bonding wires that connect
from the chip pads to the package substrate or the soldering balls that connect the
package to the PCB are described by the series inductor. The distributed
power/ground traces or planes on the package or PCB are described by the
transmission lines.
3.2. MECHANISM OF PDN NOISE GENERATION:
As shown in Fig.3.1.2, there are two main mechanisms

for explaining PDN noise generation. The first is the transistor transient current
passing through the series inductor of the PDN. The induced voltage variation (ΔV =
L(di/dt)) on the power or ground nets will be enhanced as many transistors are

switched simultaneously. The second mechanism is the voltage fluctuation caused by

the standing wave or the cavity resonance on the distributed power/ground traces or
planes. This power/ground bounce noise (GBN) can couple throughout the distributed
PDN and degrade the PI of the circuits that share the same PDN. As shown in
Fig.3.1.2, the PDN resonance can be excited through the interaction of the signal
traces and the PDN, such as the via transition through the power/ground planes or a
signal passing through the etched power/ground planes.
3.3. PDN PERFORMANCE EVALUATION:
The impedance parameter and the scattering parameters

are two different ways to evaluate the PDN performance. The Z-parameter in terms of
self- impedance Z11 (or target impedance) and transfer impedance Z21 is generally used
to evaluate the low impedance PDN with decoupling capacitors. However, the S-
parameter in terms of insertion loss (S21 ) is often employed to evaluate the high
impedance part of the PDN with the isolation solutions. As shown in Fig.3.1.2, the
target impedance (Z11 ) is a useful parameter to relate the active circuits design with
the PI design by [16]
Zt =ΔV /50% Imax Eqn(3.3.1)
where ΔV is the allowed power supply ripple for the

active circuits and Imax is the maximum transient current demanded from circuits.
Ideally, if the PDN can be designed to satisfy the criterion Z11 < Zt in all frequency
bands of interest, the circuit can work well and be stable. However, in reality, it is a
strict criterion that is not easy, and sometimes, not necessary to satisfy. The reasons
are the target impedance based on Eqn(3.3.1) will be very small for future high-
performance circuits. It is not easy to achieve in practical PDN design. Another point
is that the target impedance should be frequency dependent due to the allowed
voltage variation ΔV and the transient current demand for the active circuits are

frequency dependent. How to define a suitable specification for the frequency-

dependent target impedance profile is another challenge for both circuit and PDN
designers, but it is not the focus of this paper. However, it is clear that keeping the
PDN impedance as low as possible in a wide frequency range, is helpful for avoiding
SI and electromagnetic compatibility (EMC) issues. Discussing all possible solutions
for reducing the PDN impedance is one of the main purposes of this paper.
Another important parameter to evaluate the low
impedance PDN is the transfer impedance Z21 . This parameter can describe how large
is the voltage perturbation induced from the transient current excitation at port 1 to
the other part of the PDN at port 2, as shown in Fig.3.1.2. Similarly, keeping Z21 as
low as possible in a wide frequency range is helpful for reducing the PDN noise
propagation.

P a c k a ge a nd P C B : D e c o up l i n g a nd EB G I s o la t io n. P a g e | 10
CHAPTER 4
DECOUPLING CAPACITORS
4.1. POWER/GROUND PLANES:
Planes for power and ground levels are commonly used

for the PDN in multilayer packages or PCBs. The static capacitance formed between
the power and ground planes provide ―natural‖ decoupling capacitors at low
frequency. However, as frequency increases, the planes structure becomes a parallel
plate waveguide with cavity resonances at resonant frequencies. The resonance
effects will cause an increase of the self and transfer impedance, which enhances the
coupling of PDN noise.
Fig.4.1.1: Typical example of the power/ground plane structure for package and
PCB.
Fig.4.1.1 shows a typical example of the power/ground plane structure for a package
and PCB. There is the ball grid array (BGA) package of 2.7 cm × 2.7 cm mounted on

a test PCB of 10 cm × 8 cm through 32 solder balls of 670 μm diameter. The BGA

package consists of four copper layers with a total substrate thickness of 350 μm. The
inner two layers are ground and power layers with 150 μm spacing. A two layer PCB
with substrate thickness 700 μm is the power and ground planes on the PCB. The
dielectric constant (DK) of the BGA and PCB is 4.3.
Fig.4.1.2: Measured |S21 | for three different PDN combinations.
Fig.4.1.2 shows the measured |S21 | for three different

PDN combinations. The combinations are the package only, PCB only, and the PCB
with package attached. The PDN of the package behaves as a pure capac itor for
frequencies up to 2 GHz, because the first cavity resonance occurs above 2.8 GHz
due to its small size. In this frequency range, the noise coupling on the package
significantly decreases as the frequency is increased. For the PCB planes only, there
are several noise coupling peaks occurring at 0.76, 0.95, 1.22, 1.52, and 1.79 GHz.
These peaks correspond to the resonant cavity modes TM10 , TM01 , TM11 , TM20 , and
TM21 , respectively. Comparing these two cases, the PCB planes provide better noise

suppression below approximately 0.7 GHz than the package planes only due to the
larger parallel-plate capacitance. At higher frequencies, the PCB planes have higher
noise coupling than the package planes because of the larger resonant cavity with
lower resonance frequencies.
With the package mounted on the PCB, the noise
coupling seen on the package shows interactions between the package and PCB. As
shown in Fig.3.1.2, the PDN behavior is derived by the two shunted capacitors (CPCB
= 0.38 nF for PCB and Cpkg = 0.23 nF for package) at frequencies below0.4 GHz. At
frequencies above 0.4 GHz, there are four peaks. The first peak at 0.58 GHz could be
explained as the parallel resonance of the capacitance of the package and PCB, and
the equivalent inductance (Leff = 0.48 nH) of the interconnection between the
package and PCB. The next three peaks in |S21 | are due to the cavity resonance
coupling (or interaction) between the PCB and the package. Because the power noise
fed through the package excites the resonant TM01 and TM11 modes inside the PCB,
the energy of the resonant modes is coupled to the BGA packages through the solder
balls and results in the second and third peaks, respectively.
The last peak in |S21 | at 1.45 GHz is due to the higher
order TM20 mode on the PCB cavity [7],[13]. Damping the resonant peak by
reducing the Q- factor of the cavity is a way to reduce the noise coupling on the plane-
typed PDN. Using the conductive layer with inherent skin loss or a magnetic material
coating on the power/ground planes have been shown to be effective in reducing the
target impedance of the PDN near the resonant frequencies. Because the resonance
results from the reflection at the power/ground planes edge, another way to reduce the
Q-factor of the cavity is providing loss at the edge of the power/ground planes. The
loss can be obtained by using the dissipated edge termination combining series R and
C, where C is for blocking dc, or by using absorbing material with large magnetic
loss at microwave frequencies. Besides providing loss at the board edge, it has been
shown that the Q- factors can be reduced by putting coupled resistive terminations at
suitable positions of the PDN. Another interesting way to reduce the PDN impedance
at the resonant frequencies is employing the effective series resistor (ESR) of the

surface mounted technology (SMT) decoupling capacitors. The optimum ESR (RN)
for N uniformly distributed capacitors on the PCB board can be decided by
RN = NQh/2πεr ε0A Eqn(4.1.1)
where A is the area of the power/ground planes, h is the

substrate thickness between power and ground planes, εr is the relative permittivity of
the substrate, and Q is the desired quality factor. In general, Q ≈ 1 for smooth
impedance profile at those resonant frequencies. It is effective only as the ESL
impedance is smaller than the RN.
4.2. SMT CAPACITORS:

Adding ceramic SMT capacitors on a package or PCB
is the common way to reduce the PDN impedance. Because there is inevitable series
ESL of the capacitor as they are mounted on the substrate, the decoupling capacitor
will become inductive and be short of providing the transient current to the switched
IC. This phenomenon can be seen for the aforementioned package and PCB planes
structures, shown in Fig.4.1.1, with an additional eight SMT capacitors of 100 nF
mounted on the PCB.
Fig.4.2.1: Corresponding |S21 | for the combined PDN with and without Capacitors.

The locations of the capacitors can be referred to

Fig.4.2.1 which shows the corresponding |S21 | for the combined PDN with and
without capacitors. The |S21 | for the case with decoupling capacitors is significantly
decreased below approximately 200 MHz, because there is a transfer impedance zero
at approximately 23 MHz, which results from the series resonance of the decoupling
capacitors and their ESL. However, in the frequency range between 200 and 500
MHz, the PDN with eight capacitors on the PCB has a noise peak at approximately
400 MHz. The reason could be the parallel resonance of the ESL of the decoupling
capacitor and the shunting capacitance of the PCB and package. Above 500 MHz, the
noise coupling behavior is similar to the case without SMT capacitors on the PCB. It
implies that the SMT capacitors are not able to provide the displacement current at
higher frequency due to the ESL. Decreasing the connection inductance between the
chip power/ground pads to the decoupling capacitors, which include the traces, pads,
vias, and the ESL of the decoupling capacitor, is important for enhancing their
effective bandwidth.
Several approaches have been reported to reduce these
inductances. The intuitive way is putting the SMT capacitors as close as possible to
the chips with shorter power/ground traces [15]. It has been proved that putting the
capacitors on the package substrate have lower PDN impedance over a wider
frequency range compared to putting on the PCB due to a smaller length for the
power/ground interconnects. The connection inductance can be further reduced using
a package technology called the capacitor inside the substrate, which can put the
discrete capacitor just beneath the chip with lower ESL. Another way to reduce the
connection inductance is using multiple identical capacitors in parallel [16], [19], [21].
The effective bandwidth could be further enhanced by parallel capacitors with
different capacitor values, but the unwanted antiresonance occurred due to the parallel
LC resonance [16], [21]. It is associated with the circuit that one capacitor has
become inductive and the other one is still capacitive. The antiresonance peaks can be
reduced by using the low-Q-controlled ESR decoupling capacitors or using the annual

embedded resistor on the package substrate to increase the ESR of the decoupling
capacitors [20].
For multilayer package or PCB, SMT capacitors are
commonly connected to the power/ground planes. The space between the power and
ground planes could affect the PDN noise suppression capability for the SMT
capacitors [17], [18], [22], [26].
Fig.4.2.2: Multilayer package or PCB, SMT capacitors are commonly connected

to the power/ground planes. (a) Small (<10 mils). (b) Not small (>30 mils).
When the space is small as shown in Fig.4.2.2(a), the

small loop area and wide power/ground conductors causes the contribution of the
planes to the overall connection inductance to become negligible compared to the
parasitic inductance of the interconnects between the capacitor and the planes. The
locations of the decoupling capacitors are not critical below the SRF because their
performance is dominated by the connection inductance to the planes. However, if the
spaces between the power and ground planes are not small, the local decoupling
phenomenon by placing the capacitors very close to the active device power/ground

pin can be seen because the planes inductance and the mutual inductance between the
vias going through the planes cannot be ignored[17],[18],[23]. As shown in
Fig.4.2.2(b), the reduction of the transfer impedance between two ports on the PDN
can be derived as [22],[24],[27]
Δ|Z21 |≈ −20 log10 [((1 − k) + L3/L2)/ (1 + L3/L2)] Eqn(4.2.1)

where k is the mutual magnetic coupling coefficients
between the local decoupling capacitors and IC vias, L3 is the interconnection
inductance above the planes, which is comprised of the capacitor vias above the
planes pair, the traces, and the ESL of the capacitor, and L2 is the partial inductance
of the capacitor via between the power and ground planes. As shown in Eqn(4.2.1),
two factors play an important role in reducing the PDN transfer impedance, i.e., the
ratio L3/L2 and the coupling coefficient k. The decrease of the transfer impedance
Δ|Z21 | can be enhanced by decreasing L3/L2 and increasing k. It implies that the
effective local decoupling may be achieved when the spaces between the power and
ground planes are large and the vias are very close with strong magnetic coupling. It
is worth noting that the local decoupling effect is still valid at frequencies above the
SRF and is a broadband behavior.
Fig.4.2.3: Transfer impedance Z21 for a simulated local decoupling example on a 10 ×

12 inch two-layer PCB with space between power and ground planes equal to 35 mil.

Fig.4.2.3 shows a simulated local decoupling example

on a 10 × 12 inch two layer PCB with a space between power and ground planes of
35 mil. A SMT decoupling capacitor of 1 μF, an ESL of 0.5 nH, and an ESR of 0.3 Ω,
is movable with a distance of s from port 1. The transfer impedance Z21 is plotted in
Fig.4.2.3 with three different s (10, 100, and 800 mil) for frequencies below 1 GHz.
The transfer impedance decrease is approximately frequency independent with about
a 3–6 dB reduction compared to the case of s = 100 and 800 mil.
Another approach to reduce the target or transfer

impedance of a PDN is, employing the optimization method [24],[28] .A generic
algorithm has been used to optimize the locations and the values of the SMT
decoupling capacitors mounted on the power/ground planes. An efficient core PDN
simulator, such as cavity model or the multiple layer finite-difference method, is
required to efficiently decide the optimum capacitor design.
4.3. EMBEDDED CAPACITORS:
Embedded capacitors are another way to enhance the

effective bandwidth of the PDN. They are broadly classified into two categories. One
is the planar embedded capacitor that is fabricated on the whole power/ground planes
pair with a very thin dielectric substrate between the planes. It can be in package or
on the PCB level. The other type is the discrete embedded thick film (or thin film)
capacitors. These can be embedded inside the package substrate and the capacitor size
is small because a very high DK material, say reaching 3000, could be used. The
PDN noise suppression performance for these two types of embedded capacitors is
decided mainly by the thickness and the DK of the dielectric layer. A thinner
dielectric and higher DK have lower PDN impedance. Another advantage of the
embedded capacitor is lower ESL compared to the conventional SMT capacitors.
Because the embedded capacitor scan be located just
beneath the IC, only through hole (or buried) vias are needed to connect the IC to the

capacitor. The SRF of the embedded capacitors can be shifted to higher frequencies
due to the decrease of the ESL. It has been reported that the embedded capacitors can
efficiently reduce the PDN noise in the gigahertz range. Although the fabrication cost
of the embedded capacitor is higher, it could partially replace the SMT capacitors and
saves package or PCB area.

CHAPTER 5
ISOLATION USING SLOTS OR FILTER
Using isolation slots is a common way to suppress PDN

noise. A complete segmentation employing surrounding slots on either the power or
ground planes can achieve significant PDN noise isolation, but it lacks a dc
connection [13]. In some applications, keeping the same dc level between the two
sides of the slots is important. A narrow conducting trace (called bridges) connecting
two sides of the PDN could provide the good dc reference, but the isolation
performance is degraded in low-frequency range [13].
Fig.5.1: (a) Typical four-layer PCB of 10 cm × 8 cm. (b) Noise is coupled from the
PDN at port 1 to the signal trace at port 2 through the via.

Fig.5.1 (a) shows a typical four- layer PCB of 10 cm × 8

cm. The power and ground planes are on layer two and three with a space of 1 mm.
There are three terminated 50 Ω transmission lines of 4 cm length with via transition
from the top to bottom layers at the center of the line. As shown in Fig.5.1 (a), an
isolation slot of 4 cm × 4 cm with a bridge of 4 mm width is designed both on the
power and ground planes. The noise coupled from the PDN at port 1 to the signal
trace at port 2 through the via is shown in Fig.5.1 (b). The case of continuous power
and ground planes without the slots is also shown in Fig.5.1 (b) for comparison. 3-D
finite difference time domain (FDTD) simulation is used to verify the accuracy of the
measurements. It is found that the isolation slots could result in about 10 dB PDN
coupled noise reduction on average from 800 MHz to 3 GHz, except at the resonance
frequencies at 1.3 and 1.9 GHz. However, the noise coupling is significantly
enhanced at frequencies below 0.7 GHz due to the isolation slot and the bridge. The
coupling peak at about 400 MHz could be explained by the resonance on a longer
path formed by the isolated area and the bridge. The SI and EMI performance will be
significantly degraded if the signal crosses the etched slots on the reference plane.
Special care is generally required.
Using a π filter, consisting of one SMT ferrite bead in

series and two SMT decoupling capacitors in parallel, to replace the bridge on the
isolation slots, is another approach to suppress PDN noise [35]. It has been
demonstrated that this method can efficiently reduce the PDN noise from dc to high
frequencies. The dc connection between the two sides of the slot is achieved by the
ferrite bead, and the noise isolation can be enhanced by the π filter in the frequency
range, where these SMT components are still effective.
The aforementioned isolation approaches have been

widely used in practical packages or PCB designs due to their simplicity in
implementation, but there are two drawbacks. One is that they provide the local

isolation. The isolation is effective only for the area surrounded by the slots. The
cavity resonance still occurs between the power and ground planes and could degrade
the isolation effectiveness. The other one is that the isolation level (or insertion loss)
is not very high because there is capacitive coupling between the two sides of the slot
at high frequencies. A high isolation level is required in a highly integrated package
or PCB system, especially, with RFI issues.

CHAPTER 6
EBG STRUCTURES
6.1. MODELS:
EBG structures applied on the PDN could be one of the

possible solutions for the problems faced by the conventional isolation approaches.
The basic idea of an EBG PDN is creating a 2-D periodic structure on the whole or
partial power and/or ground planes. The inherent stopband within which the parallel-
plate modes cannot propagate will appear on the periodic structures. Ideally, the
isolation level can approach infinity, as there are infinite number cells. However, in
reality, it has been shown that only a few cells can achieve high insertion loss (over
30 dB) for well-designed EBG structures on a PDN.
Fig.6.1.1: Two typical EBG structures. (a) Mushroom type. (b) Coplanar type.

Fig.6.1.1 (a) and Fig.6.1.1 (b) shows two typical EBG

structures of mushroom type and coplanar type, respectively [36]-[38], [40]. As
shown in Fig.6.1.1 (a), the mushroom shaped unit cells are periodically embedded
between the power and ground planes. The pads between two planes are connected to
one of the planes through the vias. Three metal layers at a minimum are required to
implement this type of PDN. The additional layer and the vias increase the fabrication
cost. A series LC resonator formed between the power and ground planes could
intuitively explain the mechanism of the PDN noise suppression [36], [37].
Fig.6.1.2: One-dimensional model for (a) mushroom type, and (b) coplanar type.

The capacitor C is provided by the thin substrate

between the top layer and the pad on the second layer, and the inductor is provided
mainly by the long and thin via connecting the pad and the bottom layer. As the PDN
noise is close to the resonance frequency of this series resonator, the noise is shorted
to ground and suppressed. The bandwidth of the stop band will be broadened for
cascading more unit cells. Fig.6.1.2 (a) shows a 1-D equivalent circuit model for the
unit cell. The parallel plate between the top and bottom layers is modeled by Lp3 and
Cp4. A parallel LC of Lv1 and Cp3 describe the parallel plate between the pad
(second layer) and the ground (bottom layer) and the shorting via. A π- model for Lp1,
Cp2, and Cp1 describes the parallel plate between the power layer (top layer) and the
pad (second layer) with the mutual inductive coupling Lp2. This mutual coupling Lp2
is the same with the self- inductance of the pad because they have the same
overlapping area with layer three under the assumption of thin substrate layer. It is
noted that Cp1 = 2Cp2 because of symmetry. The lower side and upper side cutoff
frequencies ( fL and fH ) for the 1-D mushroom-type EBG can be derived as
fL =(1/2π)*[2/ 2Cp1 (Lp1 + Lp3 + 2Lv1 )]1/2 Eqn (6.1.1)
fH =(1/4π)*[ 2(((Lp2/Lv1) + 4) −((((Lp2/Lv1 )2 + 16)))1/2 /Cp3Lp2] Eqn(6.1.2)
The coplanar EBG approach of designing periodic

patterns directly on the power or ground planes the power plane) is shown in
Fig.6.1.1 (b). The pattern is built by periodic square patches that connect to their
adjacent patches by thin bridges. The bridge location could also be designed close to
the corner of the square pad like alternating impedance EBG. It does not require an
additional metal layer and the vias for the coplanar EBG structure, but the power
plane is periodically etched by slots and will degrade the SI for the signal traces
referred to such patterned planes. Basically, the coplanar EBG structure behaves like
a low-pass filter with a large shunt capacitor C and large series inductance L that is
provided by the patches and the bridges, respectively. The 1-D model for one unit cell
is shown in Fig.6.1.2 (b). The bridge inductance is Lb. The square pad is modeled as

two cascading π- models, which are described by Lp1, Cp1, and Cp2, where Cp1 =
2Cp2. The lower side and upper side cutoff frequencies (fL and fH ) for a 1-D
coplanar EBG can be derived as
fL =(1/2π)*(2/((Cp1 + 2Cp2 )Lb))1/2 Eqn(6.1.3)
fH =(1/2π)*(1/(Cp2 Lp1))1/2 Eqn(6.1.4)
which correspond to the cutoff frequency of the low-

pass filter and the first resonance frequency of the patches, respectively .
6.2. DISPERSION DIAGRAM FOR AN EBG STRUCTURE:
Fig.6.2.1:Two-dimensional dispersion diagram for mushroom-type EBG.
EBG structures applied in PDNs are commonly 2-D.

The aforementioned 1-D equivalent model and corresponding derived cutoff
frequencies are only an approximation, but they are useful to understand the
mechanism of the band rejection behavior.

2-D dispersion diagram calculated by full- wave

methods can provide the most rigorous stop band behavior. All modes are solved for
the unit cell with the boundary conditions satisfying the Bloch theory. The frequency
ranges in which no modes can propagate in any direction are considered as the stop
band. Fig.6.2.1 shows the 2-D dispersion diagram for the mushroom with the same
unit cell size of 20 mm. The via length, pad size, and substrate thickness between top
and second layers are 0.875, 15, and 0.125 mm, respectively. The dispersions
diagrams only for first two modes are simulated by a full-wave tool high- frequency
structure simulator. The stop band is marked in Fig.6.2.1. The inset of Fig.6.2.1
shows the irreducible Brillouin zone for the square unit cell. The dispersion curves
are plotted along the phase vector of Γ–X–M–Γ. The dispersion diagram for the
planar EBG can be seen in.
6.3. PROGRESS OF EBG STRUCTURES APPLIED TO PDN:
Recently, two main research efforts are emphasized for

EBG structures applied to PDN noise suppression. One is stop band bandwidth
enhancement because of switching noise from digital circuits covering a wide
frequency band [36]-[38], [40] .The other is miniaturization techniques due to the
trend of system in package. The progress of these two research directions will be
discussed for both types of EBG structures, respectively.
An intuitive approach to broaden the stop band or
reduce the structure size of the mushroom EBG is increasing the capacitance (C)
between the pads on the second layer to the top planes. Using a thin- film high DK
substrate between the top and second layers can significantly increase the capacitance.
As shown in Eqn(6.1.1) and Eqn(6.1.2), fL can be decreased as the C is increased but
fH is not changed too much. The main drawback of this approach is high material and
fabrication cost. Another way to enhance the bandwidth is by cascading two or more
EBG structures with different unit cell periods that have different stop bands [40].

The different EBG configurations can be cascaded either

horizontally [40] or vertically. The mushroom EBG structure could be miniaturized
by increasing the equivalent inductance between second and the bottom layers, but
the stop band bandwidth generally becomes narrower. It could also be understood by
Eqn(6.1.3) and Eqn(6.1.4) that fL and fH are both reduced as L is increased. The
inductance can be increased by using a spiral via between the second and bottom
layers [37] and/or using spiral pads on the second layer. For coplanar EBG structures,
the bandwidth enhancement or the unit cell size reduction could be achieved by
increasing the bridge inductance (Lb ). As shown in Eqn(6.1.3) and Eqn(6.1.4), fL can
be reduced by increasing Lb while fH is kept almost the same. The inductance can be
increased by using an L-shaped [43] or Meander Bridge that has a longer length of
the bridge. Another idea for increasing the bridge inductance is replacing the bridge
by a SMT lumped inductor. It could significantly reduce fL by using a large lumped
inductor with additional component cost.
Fig.6.3.1: Top and side views of the GSPL structure with the geometrical
notations being denoted.

A Ground Surface Perturbation Lattice (GSPL)

embedded between the power and ground planes has been shown to have a good
effect on enlarge the stop band for the coplanar L-bridged EBG structure [56].
Fig.6.3.1 shows the top and side views of the GSPL structure with the geometrica l
notations being denoted. It has a larger stop band and therefore a band of frequencies
will be suppressed.
Fig.6.3.2 shows the measured noise insertion loss (S21 )

for three different EBG structures, mushroom, L-bridged, and GSPL, applied on the
same PDN with dimensions of 60 mm × 60 mm. The unit cell size for these three
EBG structures is 20 mm × 20 mm, and their detailed geometrical dimensions are
shown in Table5.1.
Fig.6.3.2: Noise insertion loss (S21 ) for three different EBG structures: mushroom,
L-bridged, and GSPL.

It is clearly seen that the stop band bandwidth is 0.42, 3,

and 4.57 GHz, respectively. The mushroom-shaped EBG has smallest bandwidth and
the GSPL has the widest one under the same fabrication limitation.
Table 6.3.1: Geometrical Parameter of GSPL,L-bridge and Mushroom types.
GSPL(nm) L-bridge(nm) Mushroom

a 20 p 19.4 a 20 p 19.4 a 20
W 15 g1 0. 1 g2 0.2 g1 0.1 w 15
t1 0.125 g2 0.2 g3 0.2 t1 0.125
t2 0.875 g3 0.2 e 0.6 t2 0.875
l 18.2 e 0.6 L 18.2
All aforementioned approaches design the periodic

structure on the metal layers using etched slots. SI and EMI problem below or above
stop band could be caused for the high-speed signals traces passing through the
discontinuous reference planes. Another idea of creating a periodic structure on the
dielectric substrate has been shown effective in forming the stop band on the PDN. A
photonic crystal power layer that periodically embeds high DK rods between the
power and ground planes, has demonstrated good noise suppression performance [46],
[57]. This approach keeps the power and ground planes continuous, and will improve
both the power and signal integrity behavior. High fabrication and material costs are
the challenges of this technique.

CHAPTER 7
CONCLUSION
Noise on PDNs of high-speed or mixed-signal circuits

is one of the main challenges for PI and EMC design. This paper describes the
fundamental concepts for PI design on a package or PCB. The possible solutions for
PI based on decoupling and isolation concepts have been reviewed. The decoupling
techniques including the planes structure, surface- mounted technology decoupling
capacitors, and embedded capacitors have been discussed. The isolation approach that
keeps part of the PDN at high impedance also has been reviewed. Besides the typical
isolation approaches such as the etched slots and filter, the new isolation concept
using electromagnetic band gap structures have also been discussed.

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APPENDIX




Overview of Power Integrity Solutions On Package and PCB: Decoupling and EBG Isolation

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POWER DISTRIBUTION NETWORK (PDN) design

Table 1.1:Trend of high-performance microprocessors predicted by the International

YEAR INTERCONNECT ON-CHIP POWER MAXIMUM

Dept. of Electronics & Communication Govt. College of Engineering,Kannur

Table1.1 shows the trend of high-performance

Dept. of Electronics & Communication Govt. College of Engineering,Kannur

Dept. of Electronics & Communication Govt. College of Engineering,Kannur

A structure of a multi- layer printed circuit board

A VIA (Vertical Interconnect Access) is a vertical

Fig.2.1: Multilayer PCB with VIA connection.

Dept. of Electronics & Communication Govt. College of Engineering,Kannur

The hole is made conductive by electroplating, or is

A via consists of:

1. Barrel — conductive tube filling the drilled hole

In integrated circuit design, a via is a small opening in

Dept. of Electronics & Communication Govt. College of Engineering,Kannur

3.1. POWER DISTRIBUTION NETWORKS:

Fig.3.1.1: Typical computer system and corresponding PDN’s

Fig.3.1.2: Conceptual circuit model of a simple signal path from a transmitter to a

Dept. of Electronics & Communication Govt. College of Engineering,Kannur

The PDN from the transistor level to the system level

3.2. MECHANISM OF PDN NOISE GENERATION:

As shown in Fig.3.1.2, there are two main mechanisms

Dept. of Electronics & Communication Govt. College of Engineering,Kannur

switched simultaneously. The second mechanism is the voltage fluctuation caused by

3.3. PDN PERFORMANCE EVALUATION:

The impedance parameter and the scattering parameters

Zt =ΔV /50% Imax Eqn(3.3.1)

where ΔV is the allowed power supply ripple for the

Dept. of Electronics & Communication Govt. College of Engineering,Kannur

frequency dependent. How to define a suitable specification for the frequency-

Dept. of Electronics & Communication Govt. College of Engineering,Kannur

4.1. POWER/GROUND PLANES:

Planes for power and ground levels are commonly used

Dept. of Electronics & Communication Govt. College of Engineering,Kannur

a test PCB of 10 cm × 8 cm through 32 solder balls of 670 μm diameter. The BGA

Fig.4.1.2: Measured |S21 | for three different PDN combinations.

Fig.4.1.2 shows the measured |S21 | for three different

Dept. of Electronics & Communication Govt. College of Engineering,Kannur

Dept. of Electronics & Communication Govt. College of Engineering,Kannur

RN = NQh/2πεr ε0A Eqn(4.1.1)

where A is the area of the power/ground planes, h is the

4.2. SMT CAPACITORS:

Dept. of Electronics & Communication Govt. College of Engineering,Kannur

The locations of the capacitors can be referred to

Dept. of Electronics & Communication Govt. College of Engineering,Kannur

Fig.4.2.2: Multilayer package or PCB, SMT capacitors are commonly connected

When the space is small as shown in Fig.4.2.2(a), the

Dept. of Electronics & Communication Govt. College of Engineering,Kannur

Δ|Z21 |≈ −20 log10 [((1 − k) + L3/L2)/ (1 + L3/L2)] Eqn(4.2.1)

Fig.4.2.3: Transfer impedance Z21 for a simulated local decoupling example on a 10 ×

Dept. of Electronics & Communication Govt. College of Engineering,Kannur

Fig.4.2.3 shows a simulated local decoupling example

Another approach to reduce the target or transfer

4.3. EMBEDDED CAPACITORS:

Embedded capacitors are another way to enhance the

Dept. of Electronics & Communication Govt. College of Engineering,Kannur

Dept. of Electronics & Communication Govt. College of Engineering,Kannur

Using isolation slots is a common way to suppress PDN

Dept. of Electronics & Communication Govt. College of Engineering,Kannur

Fig.5.1 (a) shows a typical four- layer PCB of 10 cm × 8