A32 - Concevez Des Systemes Reels, Rapidement, Avec NI LabVIEW Et NI myRIO

27/03/2014
ni.com
NI myRIO
Design Real Systems, Fast
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Agenda
• Overview of NI myRIO
• Introduction to LabVIEW
• Connecting NI myRIO
• Introduction to LabVIEW Real-Time
• Introduction to LabVIEW FPGA
• Resources and Next Steps
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Overview of NI myRIO
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From Core Concepts to System Design
Controls Mechatronics
Final
Year
Design
Embedded
Robotics
Systems
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NI myRIO
Enclosed
Feature Rich
Protective Casing
Ecosystem
Board-Only
Optimized for Cost
• No Wi-Fi
• No myDAQ connector
Integrate into a Larger Project
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NI myRIO Product Overview: Front View
XILINX Zynq SoC
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What is Zynq?
I/O
PCI Bus
AXI
Processor FPGA I/O
Specialty I/O
Traditional Implementation
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667 MHz Dual-Core ARM Cortex-A9 processor

28K Logic Cells (Artix-7)
Xilinx ZYNQ 80 DSP slices, 16 DMA channels
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92 Billion calculations per second
Why Zynq Matters in Education
•Smaller Size, Lower Power
•667 MHz Dual-Core ARM Cortex-

A9 Processor
•Artix-7 FPGA, 28k logic cells
•16 DMA Channels
•NI Linux Real-Time
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Why Zynq Really Matters in Education
Leading Industry
Grade Technology
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NI myRIO Product Overview: Front View
User Defined LEDs
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Back View
Built-in Accelerometer
Mounting Holes
Getting Started
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Top View
Connection to PC
USB Port Power
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NI myRIO Expansion Port (MXP)
Identical Connectors
4 AI MXP A MXP B
6 DIO 2 AO 1 UART
1 SPI
1 Quad Encoder
1 I2C
3 PWMs
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NI miniSystems Port (MSP)

Side
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Introduction to NILabVIEW
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Graphical System Design

A platform-based approach for measurement and control
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Data Flow
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LabVIEW Getting Started Window
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LabVIEW Getting Started Window
Additional support, tutorials, and explanations can all

be found using the links here. These are specifically
tailored to NI myRIO users.
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Create a Project
• Click the Create Project
button
• Select Blank Project.
• Click Finish.
• To save the project:

• File >> Save
• Select the desired directory
and choose a meaningful
name.
• Remember, two LabVIEW
projects cannot share the
same directory.
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Group Activity
• Create and save a LabVIEW project.
Group Activity
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Project Explorer
• Find, access, and organize
project files
• Deploy or download files

to targets
• Manage code for build

options
• Executables, installers, and
zip files
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Parts of a VI
VIs have three main components:
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Parts of a VI – Front Panel
The front panel is

constructed using
controls (inputs)
and indicators
(outputs).
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Parts of a VI – Block Diagram
Front panel object

appear as
terminals on the
block diagram.
This is where
“programming” is
done in LabVIEW.
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Parts of a VI – Icon/Connector Pane
Icons and connector panes are necessary to use a VI as a

subVI.
o A subVI is a VI that appears on the block diagram of another VI.
o A subVI is similar to a subroutine or function in a text-based
programming language.
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Exercise 1 – Building a LabVIEW VI in Windows

Temperature conversion from Fahrenheit to Celsius.
Group Activity
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NI myRIO Hardware Setup
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Group Activity
• Plug in and power the NI myRIO.
• Power the NI myRIO with the AC to DC adaptor included in the
device’s packaging or a similarly rated power source.
• Connect the NI myRIO with a Male Type A – to – Male Type B

USB Cable.
• Click “Launch the Getting Started Wizard”
• Follow the prompts in the Getting Started Wizard
Group Activity
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Introduction to LabVIEW Real-Time
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What is Real-Time?
• Real-time does not always mean real fast
• Real-time means absolute reliability
• Hard Real-time systems have timing constraints
that must be met to avoid failure
• Determinism is the timing reliability of the
system
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Critical Applications to Consider
Event Response Closed-Loop Control Critical Tests
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When General Purpose OSs Fall Short

• Design for fairness and user responsiveness vs.
strictly prioritizing tasks
• Focus on multitasking instead of maximum reliability /
uptime
• Not the result of bad products, only certain design
goals
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Key Careabouts for Critical Applications
• Jitter: execution time variability of a given operation or

application
2.8
Mean = 2.03 ms
2.1 2.1
2 Jitter
1.9
Execution 1.3
Time (ms)
Iterations
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Key Careabouts for Critical Applications
• Determinism: a condition that is met if an operation or

application has bounded jitter
Bound (for hard

2.8 real-time
Mean = 2.03 ms systems)
2.1 2.1
2 Jitter
1.9
Execution 1.3
Time (ms)
…n
Iterations
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Running Real-Time Code – Modes

• “Real-Time Code” typically refers to VI’s running on a
target that are at processor level (non-FPGA).
• RT code can be run in two modes.

• Stand-alone
• Interactive Front Panel Mode
• In both modes, the code is deployed to the target (NI

myRIO) and is running on the NI myRIO processor.
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Exercise 2 – Investigate and Run Main.vi

• Create a project based on the myRIO project template.
• Open main.vi
• Features to understand:
• Flat Sequence Structure
• Wait (ms) function (loop refresh rate)
• Accelerometer Express VI
Group Activity
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NI myRIO Express VIs - Overview

• Express VIs are special VIs that allow the user to configure their settings
when placed on the block diagram.
• This avoids having to wire controls/constants to terminals taking up time and
block diagram space.
• NI myRIO has a palette of express VI that can be found by right-clicking on

the block diagram and navigating to myRIO.
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NI myRIO Express VIs - Configuration

• When an Express VI is placed on the block diagram, a
configuration dialog box opens.
This is the Digital
Input Express VI.
More I/O
channels can be
accessed by
selecting Add Relevant
Channel. configuration
options are
shown in this
LabVIEW space.
generates G-code
with View Code.
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NI myRIO Express VIs – G-Code

• If the View Code button is selected in the configuration
dialog, LabVIEW will generate a window like this:
Copy to Clipboard
allows the user to
copy this code
into their VI if they
want to customize
options
programmatically.
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Exercise 3 – Create RT code for NI myRIO

• Expand the functionality of the default Main.vi in the
default myRIO project.
• Features to learn:
• Creating space on the block diagram and resizing.
• Shift-Registers
• Boolean Palette Functions
• myRIO LED Express VI
Group Activity
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Introduction to LabVIEW FPGA
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FPGA Technology
Programmable
Interconnects
Logic
Blocks
I/O Blocks
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FPGAs are Dataflow Systems
E F
Implementing
Logic on FPGA: A
B
F = {(A+B)CD} ⊕ E C
D
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FPGAs are Dataflow Systems

Implementing Logic on FPGA: F = {(A+B)CD} ⊕ E
LabVIEW FPGA Code E F
A
B
C
D
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FPGAs are Parallel Dataflow Systems

E F
A
B
C
D
Z
W X Y
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LabVIEW FPGA vs. VHDL
66 Pages ~4000 lines
I/O with DMA

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Why Are FPGAs Useful?

• True Parallelism – Provides parallel tasks and
pipelining
• High Reliability – Designs become a custom

circuit
• High Determinism – Runs algorithms at

deterministic rates down to 25 ns (faster in many
cases)
• Reconfigurable – Create new and alter existing

task-specific personalities
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LabVIEW FPGA: How does it work?
Xilinx ISE
Compiler
Xilinx
FPGA
LabVIEW VI VHDL Bitfile Chip
LabVIEW LabVIEW
FPGA FPGA
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LabVIEW Programming and myRIO
Real-Time Reconfigurable
User Interface Processor FPGA
LabVIEW LabVIEW Real- LabVIEW FPGA

Time
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Exercise 4 – Exploring the NI myRIO FPGA Shipping

Personality
• Explore the FPGA shipping functionality on NI myRIO.
Group Activity
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Instructor Demo
Customizing the FPGA
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Optional Instructor Demo

• Programming the Processor with C
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Resources and Next Steps
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NI myRIO Kits | ni.com/myrio
Starter Mechatronics Embedded

LEDs & switches DC gear motors/encoders RFID reader kit
7-segment display H-bridge driver Numeric keypad
Potentiometer Accelerometer LED matrix
Thermistor Triple-axis gyro Digital potentiometer
Photo resistor Infrared proximity sensor Character LCD
Hall effect Ambient light sensor Digital temp sensor
Microphone/Speaker Ultrasonic range finder EEPROM
Battery holder Compass
DC motor Hobby servo motors
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NI myRIO | Courseware
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C Support for NI myRIO – ni.com/myrio/c-support
•Processor Programming
•Eclipse IDE
•C/C++ Support
•Free
•One Installer from ni.com
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Learn More About Programming NI myRIO
ni.com/learn-myrio
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Learn More About Programming NI myRIO
ni.com/community/myrio
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A32 - Concevez Des Systemes Reels, Rapidement, Avec NI LabVIEW Et NI myRIO

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27/03/2014

• Introduction to LabVIEW Real-Time

• Introduction to LabVIEW FPGA

• Resources and Next Steps

From Core Concepts to System Design

Integrate into a Larger Project

NI myRIO Product Overview: Front View

XILINX Zynq SoC

667 MHz Dual-Core ARM Cortex-A9 processor

Why Zynq Matters in Education

•Smaller Size, Lower Power

•667 MHz Dual-Core ARM Cortex-

•Artix-7 FPGA, 28k logic cells

•16 DMA Channels

•NI Linux Real-Time

Why Zynq Really Matters in Education

NI myRIO Product Overview: Front View

User Defined LEDs

USB Port Power

NI myRIO Expansion Port (MXP)

NI miniSystems Port (MSP)

Graphical System Design

LabVIEW Getting Started Window

LabVIEW Getting Started Window

Additional support, tutorials, and explanations can all

• To save the project:

• Deploy or download files

• Manage code for build

Parts of a VI – Front Panel

The front panel is

Parts of a VI – Block Diagram

Front panel object

Parts of a VI – Icon/Connector Pane

Icons and connector panes are necessary to use a VI as a

Exercise 1 – Building a LabVIEW VI in Windows

NI myRIO Hardware Setup

• Connect the NI myRIO with a Male Type A – to – Male Type B

• Click “Launch the Getting Started Wizard”

• Follow the prompts in the Getting Started Wizard

Introduction to LabVIEW Real-Time

Critical Applications to Consider

Event Response Closed-Loop Control Critical Tests

When General Purpose OSs Fall Short

Key Careabouts for Critical Applications

• Jitter: execution time variability of a given operation or

Key Careabouts for Critical Applications

• Determinism: a condition that is met if an operation or

Bound (for hard

Running Real-Time Code – Modes

• RT code can be run in two modes.

• In both modes, the code is deployed to the target (NI

Exercise 2 – Investigate and Run Main.vi

NI myRIO Express VIs - Overview

• NI myRIO has a palette of express VI that can be found by right-clicking on

NI myRIO Express VIs - Configuration

NI myRIO Express VIs – G-Code

Exercise 3 – Create RT code for NI myRIO

Introduction to LabVIEW FPGA

FPGAs are Dataflow Systems

FPGAs are Dataflow Systems

LabVIEW FPGA Code E F

FPGAs are Parallel Dataflow Systems