Chapter 8

Current-mode Control

© H. Wang, Power Management and High-speed I/O in CMOS Systems Ch.8 Current-mode Control 1/26
 Buck converter with PCM control

peak-current-mode control (PCM)

© H. Wang, Power Management and High-speed I/O in CMOS Systems Ch.8 Current-mode Control 2/26
 Boost converter with PCM control

© H. Wang, Power Management and High-speed I/O in CMOS Systems Ch.8 Current-mode Control 3/26
 Waveforms of constant-frequency, PCM control

 The clock sets the

latch and turns the
transistor on at the
beginning of the cycle
Ts. The comparator
resets the latch and
turns the transistor off
when the inductor
current iL reaches the
control current iC .

© H. Wang, Power Management and High-speed I/O in CMOS Systems Ch.8 Current-mode Control 4/26
 Voltage Mode vs Current Mode

 Control
 VM: output voltage (through duty cycle)
 CM: output current (through inductor current or switch current)
 Loop
 VM: Single loop
 CM: Two loops
 The key feature of current mode control is that the inner loop
changes the inductor into a voltage-dependent current source at
frequencies lower than the crossover frequency of the current loop.
 The action of the current loop is similar to that of a sample-and-
hold circuit, which is a nonlinear, time-varying system.

© H. Wang, Power Management and High-speed I/O in CMOS Systems Ch.8 Current-mode Control 5/26
 Two Categories of CM

 Constant-frequency
 peak-current-mode control (PCM)
 valley-current-mode control (VCM)
 PWM conductance control with triangle-wave compensation
 average-current-mode control (ACM)
 Variable-frequency
 constant on-time
 constant off-time
 hysteretic

© H. Wang, Power Management and High-speed I/O in CMOS Systems Ch.8 Current-mode Control 6/26
 Features of CM
 CM control exhibits a feedforward control feature.
 CM control behaves approximately as a first-order system.
 Maximum current is limited cycle by cycle.
 It is easy to connect converters with CM in parallel.
 CM control is a perfect solution to transformer imbalance in
symmetrical converters.
 A disadvantage of PCM control is its inherent instability of the
inner current loop when D > 0.5, resulting in subharmonic
oscillations.
 CM control needs a current sensor (eg.sensing resistor) which
may cause extra power loss.

© H. Wang, Power Management and High-speed I/O in CMOS Systems Ch.8 Current-mode Control 7/26
 Steady-state waveforms for CCM.

M 1 DTs  M 2 (1  D )Ts

M2 D

M1 1  D

© H. Wang, Power Management and High-speed I/O in CMOS Systems Ch.8 Current-mode Control 8/26
 Instability of Closed-current Loop
 Small perturbation
in iL(0).

 The inner current

loop is stable if

M1  M 2

D  0.5

© H. Wang, Power Management and High-speed I/O in CMOS Systems Ch.8 Current-mode Control 9/26
 Waveforms of inductor current

 Steady-state
(solid line) and
stable inner current loop
perturbed
(dashed line)

marginally stable current loop

unstable current loop

© H. Wang, Power Management and High-speed I/O in CMOS Systems Ch.8 Current-mode Control 10/26
 Slope Compensation

Implementation of slope compensation

Current adder Voltage adder

© H. Wang, Power Management and High-speed I/O in CMOS Systems Ch.8 Current-mode Control 11/26
 Slope Compensation
iL 0  GE  GF  FE  ( M 1  M 3 )dTs

E iL1  BC  AC  AB  ( M 2  M 3 )dTs
F

G iL1 M 2  M 3
a   1     for convergence.
 iL 0 M 1  M 3

M 2  M 3  M1  M 3
M 2  M1  2M 3

M 2  M1
Stablity conditon:   M 3 
2

© H. Wang, Power Management and High-speed I/O in CMOS Systems Ch.8 Current-mode Control 12/26
 Slope Compensation
M 2  M1
Stablity conditon:   M 3 
2

 The condition of stability at any

duty cycle D is given by

M2
M3 
2
 Optimum slope compensation
(dead-beat control)

M3  M2

© H. Wang, Power Management and High-speed I/O in CMOS Systems Ch.8 Current-mode Control 13/26
 Sample-and-hold Effect on Current Loop
 Natural Response of
Inductor Current to Small
Perturbation in Closed-
current Loop
(自由响应)

iln ( k  1)  ailn ( k )

M2  M3
where,     a 
M1  M 3

© H. Wang, Power Management and High-speed I/O in CMOS Systems Ch.8 Current-mode Control 14/26
 Sample-and-hold Effect on Current Loop
 Forced Response of
Inductor Current to Step
Change in Control Voltage
in Closed-current Loop
(强迫响应)

1 a
ilf ( k  1)  vc ( k  1)
Rs

Read the textbook for the

derivation.

© H. Wang, Power Management and High-speed I/O in CMOS Systems Ch.8 Current-mode Control 15/26
 Sample-and-hold Effect on Current Loop
 Transfer Function of Closed-current Loop in z-Domain

Total response

1 a
il ( k  1)  iln ( k  1)  ilf ( k  1)  ailn ( k )  vc ( k  1)
Rs

il ( z ) 1  a z
H icl ( z )  
vc ( z ) Rs z  a

© H. Wang, Power Management and High-speed I/O in CMOS Systems Ch.8 Current-mode Control 16/26
 Current Loop in s-Domain
 Using the definition of the z–transform z = esTs and multiplying the
result by the zero-order hold transfer function, we obtain the inductor
current in the s-domain.
il ( s ) 1  a e sTs  1 1 1
H icl ( s )   
vc ( s ) Rs sTs e  a Rs
sTs
2i
 s 
2

1  
i  i 
where,
i  12 f s
3  1 a 
i   
2 1 a 
For a < 1, the two poles are in the LHP, and the closed-current loop is stable.
For a = 1, ξi = 0, and the closed-current loop is unstable, causing steady-state
oscillations.
For a > 1, ξi < 0, and the current loop is unstable, causing growing oscillations.

© H. Wang, Power Management and High-speed I/O in CMOS Systems Ch.8 Current-mode Control 17/26
 Bode plot of Hicl for selected values of a

f / fs f / fs

© H. Wang, Power Management and High-speed I/O in CMOS Systems Ch.8 Current-mode Control 18/26
 Step response of the inductor current iL to a step
change in Vc = 0.01V at a = 0.7.

© H. Wang, Power Management and High-speed I/O in CMOS Systems Ch.8 Current-mode Control 19/26
 Error Voltage-to-duty Cycle Transfer Function

It will be shown in subsequent chapters that

il ( s ) 1  a e sTs  1 TmsTpi
H icl ( s )   
vc ( s ) Rs sTs e sTs  a 1  TmsTpi Rs

© H. Wang, Power Management and High-speed I/O in CMOS Systems Ch.8 Current-mode Control 20/26
 Loop Gain of Current Loop

v fi ( s )
Ti ( s )   TmsTpi Rs  ...
vei ( s )

© H. Wang, Power Management and High-speed I/O in CMOS Systems Ch.8 Current-mode Control 21/26
 Closed-loop Transfer Function of Current Loop

d ( s) Tms T
Ticl ( s )    ms  ...
vc ( s ) 1  TmsTpi Rs 1  Ti

© H. Wang, Power Management and High-speed I/O in CMOS Systems Ch.8 Current-mode Control 22/26
 Voltage Loop of PWM Converters
with Current-mode Control

Current-mode control block diagram of

PWM converters without feedforward
Block diagram of the power
gains.
stage of PWM converters

© H. Wang, Power Management and High-speed I/O in CMOS Systems Ch.8 Current-mode Control 23/26
 Closed-voltage Loop Transfer Function

vo TcTicl Tp
Tcl  
vr vi  io  0
1  TcTicl Tp 

© H. Wang, Power Management and High-speed I/O in CMOS Systems Ch.8 Current-mode Control 24/26
 Closed-loop Audio Susceptibility

© H. Wang, Power Management and High-speed I/O in CMOS Systems Ch.8 Current-mode Control 25/26
 Closed-loop Output Impedance

© H. Wang, Power Management and High-speed I/O in CMOS Systems Ch.8 Current-mode Control 26/26