U.S.

6,854,067 (“Kutz”)

U.S. Patent 6,854,067 (“Kutz”), with a priority date of October 30, 2000, is directed to a method
and system dynamically controlling microcontroller power. The method and system configures a
microcontroller power state, senses its condition, and determines its suitability status,
communicates that status between a power on reset (“PORˮ) circuit and a processor, controls
certain microcontroller functions accordingly, and dynamically programs power related
functions.

U.S. Patent 5,754,436 (“Walsh”), with a priority date of December 22, 1994, discloses a
computer power management system for a computer having a clock, said system including a
plurality of sampling circuits responsive to different system activity levels and producing system
activity signals representative of the system activity levels; circuitry responsive to the system
activity signals that supplies weighted activity output signals; filter circuitry that responds to the
weighted activity output signals to produce control signals representative of directions to pulse-
width modulate the computer clock.

U.S. Patent 5,745,375 (“Reinhardt”), with a priority date of September 29, 1995, discloses a
power control circuit and method for reducing consumption by an electronic device; said power
control circuit comprising a controller, clock generation circuit, and power supply circuit; the
controller signals the power supply circuit and clock generation circuit to perform voltage and
frequency scaling.

U.S. Patent 6,144,569 (“Rodriguez”), with a priority date of February 29, 2000, is directed to a
power cut detection and recovery system. The system provides for restoration of operation of an
electronic device after disconnection or interruption of the power supply to the device, including
a terminal for monitoring voltage, and may include a POR circuit to restart the device in a
controlled manner.

W/O 01/23977 (“Huang”), with a priority date of September 29, 1999, discloses a power
management PC expansion card controller that includes power on reset circuitry to reset power
management enable registers during a reset period. The controller supports advanced power
management specifications without modification that could have been used in current computer
systems at the time.

A sample claim chart comparing the Kutz patent to the Walsh, Reinhardt, Rodriguez, and Huang
references is provided below.

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US 6,854,067 (“Kutz”)
Claim 1 preamble: In a
microcontroller with an embedded
processor, a switched mode pump
power supply and power on reset
circuit, a method of dynamically
controlling a plurality of power stability
functions for said microcontroller, said
method comprising:
US 5,754,436 (“Walsh”)
US 5,745,375 (“Reinhardt”)
U.S. 6,144,569 (“Rodriguez”)
W/O 01/23977 (“Huang”)
Reinhardt discloses a “power cut detection and recovery
system (36) provides for the recovery of an electronic
apparatus (20) in response to a momentary interruption in
the voltage level of a power supply (46) coupled to that
apparatus. The system includes a level detecting circuit (80)
coupled to the power supply (46) for monitoring the voltage
supplied to the apparatus (20). The system further includes
internal reference supply circuits (86) that provide voltage
and current references to operate the apparatus (20). A
power cut monitor and reference control circuit (84) is
coupled to the level detecting circuit (80) and is capable of
causing the internal reference supply circuits (86) to remain
enabled upon the detection of a momentary cut in the
externally Supplied power (46). A second level detecting
circuit (90), dependent on the internal reference supply
circuits (86), and the power cut monitor and reference
control circuit (84) are coupled to an under voltage monitor
and recovery circuit (88) that can cause the apparatus (20) to
restart upon the recovery of the voltage level to a value
above a predetermined level. By maintaining the internal
reference supply circuits (86) in an enabled State, the
apparatus (20) is able to restart in its pre-interruption state if
the voltage level remains above a POR level.” Reinhardt,
Abstract.
Claim 1 of Reinhardt discloses “[a] power control circuit
adapted for use by an electronic device comprising . . . a
power circuit that provides a power supply signal having a
scalable voltage to the electronic device; and a controller
coupled to . . . said power supply circuit, said controller
generates a first and second signal in response to an event in
order to dynamically control power usage by the electronic
device, the power usage is capable of being (i) reduced by
decreasing the frequency of the clock signal followed by the
voltage of the power supply signal or (ii) increased by
increasing the voltage followed by the frequency. See
Reinhardt at 7:10-24.
Reinhardt further discloses that “[a]nother advantage
provided by the power control circuit is that it encourages
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Claim 1a: supplying a power state to
said microcontroller from said switched
mode pump power supply, wherein said
processor and said power on reset
circuit are interconnectedly coupled,
and wherein said switched mode pump
power supply is interconnectedly
coupled with said power on reset circuit
the implementation of full-frequency, full-voltage electronic
devices within power sensitive hardware products rather
than configuring the electronic device to function if a worst-
case condition occurs. Instead, the electronic device relies on
voltage and frequency scaling to dynamically configure the
electronic device based on its various conditions at the time.
Thus, the overall performance of the product implementing
the electronic device is enhanced. Yet another advantage is
to enable companies to reduce their inventories of electronic
devices dedicated to either laptop or desktop systems by
eliminating the need for electronic devices calibrated to have
a specific voltage and operating frequency, but rather
dynamically calibrating the voltage and frequency of the
electronic device based on the current conditions
experienced by the electronic device.” Reinhardt at 2:10-27.
Rodriguez discloses a “[p]ower management integrated
circuit 36 can include a power on reset (POR) circuit. The
function of the power on reset circuit is to restart the
electronic apparatus in a controlled manner after an
interruption in power.” Rodriguez at 4:9-12.
Huang discloses a “power management PC card controller
(20) that includes power on reset circuitry (30) to reset
power management enable registers (50), thereby ensuring
that the PME registers (50) correctly identify the power
management capabilities of the controller (20). Once the
PME registers (50) are reset, an instruction may be provided
to change the state of the registers (50) from a default state
to a power management support state. Additionally, the
controller (20) includes blocking circuitry (38) to block
conventional reset signals (18) from resetting the power
management and proprietary registers (22) from being reset.
The controller (20) supports advanced power management
specifications without requiring additional pinouts.” Huang,
Abstract.
Claim 1 of Reinhardt discloses “[a] power control circuit
adapted for use by an electronic device comprising . . . a
power circuit that provides a power supply signal having a
scalable voltage to the electronic device; and a controller
coupled to . . . said power supply circuit, said controller
generates a first and second signal in response to an event in
order to dynamically control power usage by the electronic
device, the power usage is capable of being (i) reduced by
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and responsive to signals therefrom;
Claim 1b: sensing a power state
condition of said power state;
Claim 1c: determining a suitability
status of said power state condition;
decreasing the frequency of the clock signal followed by the
voltage of the power supply signal or (ii) increased by
increasing the voltage followed by the frequency. See
Reinhardt at 7:10-24.
Huang discloses that “the present invention includes power
on reset (POR) circuitry 30 that generates a reset signal Rl
(34) to reset the PME registers 50, based on a signal
available during power on periods. In the preferred
embodiment, the POR circuitry generates the reset signal 34
based on the AUXVCC signal, defined by the ACPI
specification. This signal is preferable since it does not
change state once a reset period is over.” Huang at 6:26-31.
Claim 4 of Walsh discloses “[a] process for power
management of a computer system having a clock,
comprising the steps of: sampling different system activity
levels and producing system activity signals representative
of the system activity levels; supplying weighted activity
output signals adjustably weighting the system activity
levels.” See Walsh at 203:5-11.
Huang discloses a “cardbus controller that includes power
on reset circuitry to reset power management enable (PME)
registers during a reset period, thereby ensuring that these
registers correctly identify the power management
capabilities of the controller.” Huang at 3:27-30.
Claim 4 of Walsh discloses “[a] process for power
management of a computer system having a clock,
comprising the steps of . . . continually filtering the weighted
activity output signals to produce a series of duty-cycle-
related control signals.” See Walsh at 203:5-6, 12-16.
Claim 5 of Walsh further discloses that “[t]he process of
claim 4 wherein said filtering step includes: computing a
criterion function value as a function of the system activity
levels; and updating the duty-cycle-related control signal
based on the criterion function value.” See Walsh at 203:17-
22.
Claim 6 of Walsh further discloses that “[t]he process of
claim 4 wherein said filtering step includes: computing
successive criterion function values as a function of the
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Claim 1d: communicating said
suitability status between said power on a first and second signal in response to an event in order to
reset circuit and said processor;
Claim 1e: controlling certain functions
of said microcontroller accordingly.
system activity levels over time; and updating the duty-
cycle-related control signal based on an average of criterion
function values.” See Walsh at 203:23-28.
Claim 7 of Walsh further discloses that “[t]he process of
claim 4 wherein said filtering step includes: computing a
criterion function value as a function of the system activity
levels; updating the duty-cycle-related control signal based
on the criterion function value when that value lies in a
predetermined range.” See Walsh at 203:29-35.
Huang discloses a “cardbus controller that includes power
on reset circuitry to reset power management enable (PME)
registers during a reset period, thereby ensuring that these
registers correctly identify the power management
capabilities of the controller.” Huang at 3:27-30.
Claim 1 of Reinhardt discloses a “controller [that] generates
dynamically control power usage by the electronic device.”
See Reinhardt at 7:17-20.
Huang discloses “a PC card controller, comprising power
management enable (PME) registers, a trigger signal that
changes state when power is first applied to the power
management enable registers, and power on reset circuitry
that receives the trigger signal and generates a first reset
signal to reset the PME registers when power is first applied
to the PME registers.” Huang at 4:4-8.
Reinhardt discloses “controlling power consumption of at
least one electronic device through both voltage and
frequency scaling.” Reinhardt at 3:7-9.
Reinhardt further describes “[r]eferring to FIG. 3, one
embodiment of a power control circuit employed within a
computer system to control power consumption by an
electronic device (e.g., a microprocessor) is illustrated.
Although the electronic device is shown as a microprocessor
because of its reputation of being one of the main power
consuming chips within a computer system, the power
control circuit is capable of controlling power consumption
by other types of electronic devices such as controllers.”
Reinhardt at 4:3-11.
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Claim 3 of Huang discloses “said PME registers being reset
to a default state and generating a control signal indicative of
said default state, and said PME registers adapted to receive
an instruction to change from a default state to a different
state and generating a control signal indicative of said
different state.” Huang at 11:13-16.

Claim 7 of Walsh discloses that “[t]he process claim 4

wherein said filtering step includes . . . updating the duty-
cycle-related control signal based on the criterion function
value when that value lies in a predetermined range; and
halting the system when the criterion function value lies
outside the range in one direction and running the system
with 100% duty cycle clock when the criterion function
value lies outside the range in the other direction.” See
Walsh at 203:29-30, 33-40.

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