Microsoft Word - HDLMANUAL - NEW2017

BMS EVENING COLLEGE OF ENGINEERING
BANGALORE-560019
DEPARTMENT OF ELECTRONICS AND COMMUNICATION
HDL LAB MANUAL
B.E., V Semester
[As per Choice Based Credit System (CBCS) scheme]
Subject Code 15ECL58/17ECL58

CONTENTS
PROGRAMS:
PART-A
1. Write a Verilog code to realize all the logic gates
2. Write a Verilog program for the following Combinational logic designs

a) 2 to 4 Decoder
b) 8 to 3 Encoder (Encoder with and without Priority)
c) 8 to 1 MUX
d) 4 bit Binary to Gray
e) Multiplexer, De-multiplexer, Comparator
3. Write a VHDL and Verilog Code to describe the functions of a full adder using three modeling styles
4. Write a Verilog code to model 32 - BIT ALU using the schematic diagram shown below:
 ALU should use combinational logic to calculate an output based on the four bit op-code input.
 ALU should pass the result to the out bus when enable line is high and tri-state the out bus when the
enable line is low.
 ALU should decode the 4-bit op-code according to the example given below:
5. Develop a Verilog code for the following flip-flops: SR, D, JK & T flip-flops.
6. Design a 4-bit Binary, BCD Counters (Synchronous Reset and Asynchronous Reset) and Any Sequence
Counters, using Verilog code.
PART-B
INTERFACING
1. Write VHDL/Verilog code to display messages on an alpha numeric LCD display.
2. Write VHDL/Verilog code to interface Hex key Pad and display the key code on seven segment display.
3. Write VHDL/Verilog code to control speed, direction of DC and Stepper Motor.
4. Write VHDL/Verilog code to accept analog signal, Temperature sensor and display the data on LCD or
Seven segment displays.
5. Write VHDL/Verilog code to generate different waveforms (Sine, Square, Triangle, Ramp etc.,) using
DAC – Change the frequency.
6. Write VHDL/Verilog code to Simulate Elevator operation.
Followed by Model Viva questions

INTRODUCTION
1. Double click on Vivado 2014.4 icon
2. Double click on create new project option

3. Click Next.
4. Give project name and select the project location, click next
5. Select RTL project Click Next
6. Click on Create File, select the target language, simulator language and source type as
Verilog.
7. Enter the name for the source file to be created. Click Next.
8. Select the board details as mentioned in the above slide to implement the application
code on the Artix-7 Board. Click Next.
9. Define a module, module name is the name of the source file created (step 7)
10. Give the name for the I/O port to use in the source file. Choose the direction as input
or output or inout.
11. If the I/O ports are vector select bus, specify the the size of the vector by specifying
the LSB and MSB value. For ex: for an input of 4-bits LSB=0 and MSB=3.
12. In the Sources pane, double-click the gates.v entry to open the file in text mode on
13. Click on Run Simulation > Run Behavioral Simulation under the Project Manager tasks of
the Flow Navigator pane. You will see a simulator output similar to the one shown below
14. Synthesize the Design Step. Synthesize the design with the Vivado synthesis tool and
analyze the Project Summary output. Click on Run Synthesis under the Synthesis tasks of the
Flow Navigator pane. The synthesis process will be run on the counter.v file (and all its
hierarchical files if they exist). When the process is completed a Synthesis Completed dialog
will appear. In The Flow Navigator, under Synthesis (expand Synthesized Design if
necessary), click on Schematic to view the synthesized design in a schematic view.
Fig: Synthesized design’s schematic view
15. In the Sources pane, open the Constraints folder and double-click the basys3.xdc entry to
open the file in text mode. Click on I/O ports in Schematic to view the pin design in a
schematic view define the pin locations of the input switches and lines the pin locations of
the output LEDs
16. Implement the Design Implement the design with Default settings and analyze the
Project Summary output. Click on Run Implementation under the Implementation tasks of
the Flow Navigator pane. The implementation process will be run on the synthesized design.
When the process is completed an Implementation Completed dialog box with three options
will be displayed.
a. Select Open implemented design and click OK as we want to look at the implemented
design in a Device view tab. In the Netlist pane, select one of the nets and notice that the
net displayed in the X1Y1 clock region in the Device view tab (you may have to zoom in
to see it).
b. When the Implementation process is completed Select Generate the Bitstream. The
bitstream generation process will be run on the implemented design.
17. When the process is completed a Bitstream Generation Completed dialog box with
three options will be displayed.
[Generate the Bitstream and Verify Functionality Connect the board and power it ON. Make
sure that the Micro-USB cable is connected to the JTAG PROG connector and Make sure
that the board is set to use USB power (via the Power Select jumper)]
a. Select the Open Hardware Manager option and click OK. The Hardware Manager
Window will open indicating “unconnected” status. Click on the Open target link.
b. Click Next to see the Hardware Server Settings form
c. Click Next with the Hardware Target selected. The JTAG cable which uses the Xilinx_tcf
should be detected and identified as a hardware target. It will also show the hardware devices
detected in the chain
d. Click Next and then Finish.

18. The Hardware Session status changes from Unconnected to the server name and the
device is highlighted
19. Select the device and verify that the counter.bit is selected as the programming file in the
General tab.
Dept of Electronics and Communication Engg. V-Sem, HDL-Lab
Figure. Programming file
20. Click Program to program the FPGA
21. Verify the functionality by flipping switches and observing the

output on the LEDs (Refer to the logic diagram).
22. When satisfied, power OFF the board.
23. Close the hardware session by selecting File > Close Hardware Manager.
24. Click OK to close the session.
25. Close the Vivado program by selecting File > Exit and click OK
VHDL VHINX PROJECT NAVIGATOR TOOL TUTORIAL

XILINX PROJECT NAVIGATOR TOOL TUTORIAL
ECE Dept. BMS Evening College of Engineering 1

PART-A
EXPERIMENT NO. 1
Write a Verilog code to realize all the logic gates
AIM: To write a Verilog Code to realize all the Logic gates.
THEORY: The gate is a digital circuit with one or more input voltages but only one output
voltage. By connecting the different gates in different ways, we can build circuits that
perform arithmetic and other functions. Logic gates are the basic elements that make up a
digital system. The Electronic gate is a circuit that is able to operate on a number of binary
inputs in order to perform a particular logic function. The types of gates available are the
NOT, AND, OR, NAND, NOR, EXCLUSIVE-OR, and EXCLUSIVE-NOR.
LOGIC GATES AND TRUTH TABLE:
a a a
a a h=a^b
f=~(a&b) g=~(a!b)
a
d=a&b e=a!b 7400 b
7402
b 7486
c=~a 7408
7404 b b 7432 b
Input NOT AND OR NAND NOR XOR
a b c=~a d=a&b e=a|b f=~(a&b) g=~(a|b) h=a^b

0 0 1 0 0 1 1 0
0 1 1 0 1 1 0 1
1 0 0 0 1 1 0 1
1 1 0 1 1 0 0 0
VERILOG CODE
module basic_gates (a,b,c,d,e,f,g,h);

input a,b;
output c,d,e,f,g,h;
assign c=~a;
assign d=a&b;
assign e=a|b;
assign f=~(a&b);
assign g=~(a|b);
assign h=a^b;
endmodule

UCF File
NET "a" LOC = "<input pin numbers>" ;(to be referred from datasheet)
NET "b" LOC = "<input pin numbers>" ;
NET "c" LOC = "<output pin numbers>" ;
NET "d" LOC = "<output pin numbers>";
NET "e" LOC = "<output pin numbers>" ;
NET "f" LOC = "<output pin numbers>";
NET "g" LOC = "<output pin numbers>";
NET "h" LOC = "<output pin numbers>";

EXPERIMENT NO. 2
Write a Verilog program for the following Combinational logic designs
2 (a) 2 to 4 DECODER
AIM: To write a Verilog Code to realize 2 to 4 DECODER.
THEORY:
A decoder is a combinational circuit that converts binary information from n input
lines to a maximum of 2n unique output lines. A binary code of n bits is capable of
representing up to 2n distinct elements of the coded information.
A 2-to-4-line decoder, the two inputs are decoded into four outputs, each output
representing one of the minterms of the 2-input variables. A 2-to-4 decoder can be used for
decoding any 2 –bit code to provide 4-outputs, one for each element of the code.
BLOCK DIAGRAM
LOGIC DIAGRAM

TRUTH TABLE
Selector Output
Enable X(1) X(0) Y(3) Y(2) Y(1) Y(0)
0 X X Z Z Z Z
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
VERILOG CODE
module decoder2to4(x,enable,y);
input enable;
input [1:0] x;
output reg [3:0] y;
always @(x,enable)
begin
if (enable==1'b1)
begin
case(x)
2'b00:y = 4'b0001;
2'b01:y = 4'b0010;
2'b10:y = 4'b0100;
2'b11:y = 4'b1000;
endcase
end
else
y=4'bZZZZ;
end
endmodule
2 (b) 8 to 3 ENCODER
AIM: To write a Verilog Code to realize 8 to 3 Encoder (Encoder with and without
Priority)
THEORY:
An encoder is a digital function that produces a reverse operation from that of
decoder. An encoder has 2n (or less) input lines and n output lines. The output lines generate
the binary code for 2n input variables. The encoder assumes that only one input line can be
equal to 1 at any time. Otherwise the circuit has no meaning. If the encoder has 8 inputs and
could have 28 = 256 possible input combinations.

PRIORITY ENCODER:
These encoders establish an input priority to ensure that only the highest priority line
is encoded. For example 8-to-3-line priority encoder the inputs are a(0) ,a(1) ,…….a(7).
If the priority is given to an input with higher subscript number over one with a lower
subscript number, then if both a(2) and a(5) are logic-1 simultaneously , the output will be
101 because a(5) has higher priority over a(2).
BLOCK DIAGRAM
ENCODER WITHOUT PRIORITY
TRUTH TABLE
Inputs Output
En a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2
0 x X X x x x x x z z z
1 0 0 0 0 0 0 0 1 1 1 1
1 0 0 0 0 0 0 1 0 1 1 0
1 0 0 0 0 0 1 0 0 1 0 1
1 0 0 0 0 1 0 0 0 1 0 0
1 0 0 0 1 0 0 0 0 0 1 1
1 0 0 1 0 0 0 0 0 0 1 0
1 0 1 0 0 0 0 0 0 0 0 1
1 1 0 0 0 0 0 0 0 0 0 0
VERILOG CODE
module encoder_without(en,a,b);
input en;
input[0:7]a;
output reg[2:0]b;
always @ (en,a)
begin
if (en==1'b1)
begin

case (a)
8'b 00000001 :b=3'd7;
8'b 00000010 :b=3'd6;
8'b 00000100 :b=3'd5;
8'b 00001000 :b=3'd4;
8'b 00010000 :b=3'd3;
8'b 00100000 :b=3'd2;
8'b 01000000 :b=3'd1;
8'b 10000000 :b=3'd0;
default:b=3'bZZZ;
endcase
end
else
b=3'bZZZ;
end
endmodule
ENCODER WITH PRIORITY

TRUTH TABLE
Inputs Output
en a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2
0 x x x x x x x x z z z
1 X X X X X X X 1 1 1 1
1 X X X X X X 1 0 1 1 0
1 X X X X X 1 0 0 1 0 1
1 X X X X 1 0 0 0 1 0 0
1 X X X 1 0 0 0 0 0 1 1
1 X X 1 0 0 0 0 0 0 1 0
1 X 1 0 0 0 0 0 0 0 0 1
1 1 0 0 0 0 0 0 0 0 0 0
VERILOG CODE
module encoder_with(en,a,b);
input en;
input [0:7] a;

output reg [2:0] b;
always @(en,a)
begin
if(en==1’b1)
casex(a)
8'bXXXXXXX1:b=3'd7;
8'bXXXXXX10:b=3'd6;
8'bXXXXX100:b=3'd5;
8'bXXXX1000:b=3'd4;
8'bXXX10000:b=3'd3;
8'bXX100000:b=3'd2;
8'bX1000000:b=3'd1;
8'b10000000:b=3'd0;
endcase
else
b=3'dZZZ;
end
endmodule
2 (c) 8 to 1 MULTIPLEXER
AIM: To write a Verilog Code to realize 8 to 1 Multiplexer
THEORY: A digital multiplexer is a combinational circuit that selects binary information

from one of many input lines and directs it to a single output line. A multiplexer is also called
as data selector, since it selects one of many inputs and steers the binary information to the
output line. The selection of particular input line is controlled by a set of selection lines.
Normally there are 2n input lines and n selection lines whose bit combinations determine
which input is selected.
BLOCK DIAGRAM: TRUTH TABLE:
I(0)
Selector O/P
I(1) S2 S1 S0 Y
I(2)
0 0 0 I(0)
I(3)
y 0 0 1 I(1)
I(4) 8:1 0 1 0 I(2)
MUX
I(5) 0 1 1 I(3)
I(6) 1 0 0 I(4)
I(7) 1 0 1 I(5)
1 1 0 I(6)
s(2) s(0) 1 1 1 I(7)
s(1)

VERILOG CODE
module mux8to1(i, y, s);

input [7:0] i;
output reg y;
input [2:0] s;
always @ (s,i)
begin
case (s)
3'd0: y = i[0];
3'd1: y = i[1];
3'd2: y = i[2];
3'd3: y = i[3];
3'd4: y = i[4];
3'd5: y = i[5];
3'd6: y = i[6];
default:y = i[7];
endcase
end
endmodule
2(d) BINARY TO GRAY CODE CONVERSION
AIM: To write a Verilog Code to realize 4-bit Binary to Gray Conversion
THEORY: A Gray code represents each number in the sequence of integers as a binary
string of length N in an order such that adjacent integers have Gray code representations that
differ in only one bit position. The advantage of the gray code is that only one bit will change
as it proceeds from one number to the next. To obtain gray code, one can start with any bit
combination by changing only one bit from 0 to 1 or 1 to 0 in any desired random fashion, as
long as two numbers do not have identical code assignments.
CIRCUIT DIAGRAM
b(0) b(1) b(2) b(3)

g(3)
g(2)
7486
g(1)
7486
g(0)
7486

TRUTH TABLE
BCD-I/P Gray-Code-O/P
b(3) b(2) b(1) b(0) g(3) g(2) g(1) g(0)
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
VERILOG CODE
module bintogrey(b,g);
input [3:0] b;
output [3:0] g;
wire [3:0] g;
assign g[3] = b[3];

assign g[2:0] = b[3:1] ^ b[2:0];
endmodule
2(e) 2:1 MULTIPLEXER
AIM: To write a Verilog Code to realize 2 to 1 Multiplexer
THEORY: Multiplexer (MUX) is a digital switch which connects data from one of n sources
to the output. A number of select inputs determine which data source is connected to the
output.
A 2 to 1 line multiplexer is shown in figure below, A & B are two inputs. En is enable.
Enable is used to enable or disable the multiplexer. Selection line S are decoded to select a
particular input. Y is a output which selects any one of the input depending on the select
lines. The truth table for the 2:1 mux is given in the table below.

BLOCK DIAGRAM TRUTH TABLE
En
Input Output
A SEL En Y
2:1
Y X 1 0
MUX
0 0 A
B
1 0 B
SEL
VERILOG CODE
module MUX2_1 (A, B, SEL, En, Y);

input A, B, SEL, En;
output Y;
reg Y;
always @ (SEL, A, B, En)
begin
if (En == 0 & SEL == 1)
begin
Y = B;
end
else if (En == 0 & SEL == 0)
Y = A;
else
Y = 1'bz;
end
endmodule
2(e) 1: 8 DE-MULTIPLEXER
AIM: To write a Verilog Code to realize 1 to 8 De-Multiplexer
THEORY: A de-multiplexer is a circuit that receives the information on a single line and
transmits this information on one of 2n possible output lines. The selection of specific output
lines is controlled by the values of n selection lines. For 1: 8 de-multiplexers, the single input
variable has a path to all the eight outputs, but the input information is directed to only one of
the 8 output lines.

BLOCK DIAGRAM
TRUTH TABLE
Selector Output
I S2 S1 S0 y7 y6 y5 y 4 y3 y2 y1 y0
1/0 X X X Z Z Z Z Z Z Z Z
1/0 0 0 0 Z Z Z Z Z Z Z 1/0
1/0 0 0 1 Z Z Z Z Z Z 1/0 Z
1/0 0 1 0 Z Z Z Z Z 1/0 Z Z
1/0 0 1 1 Z Z Z Z 1/0 Z Z Z
1/0 1 0 0 Z Z Z 1/0 Z Z Z Z
1/0 1 0 1 Z Z 1/0 Z Z Z Z Z
1/0 1 1 0 Z 1/0 Z Z Z Z Z Z
1/0 1 1 1 1/0 Z Z Z Z Z Z Z
VERILOG CODE
module Demux1to8 (i, y, s);

input i;
output reg [7:0] y;
input [2:0] s;
always @ (s,i)
begin
case (s)
3'd0: y[0] = i;
3'd1: y[1] = i;
3'd2: y[2] = i;
3'd3: y[3] = i;
3'd4: y[4] = i;
3'd5: y[5] = i;
3'd6: y[6] = i;
default: y[0] = i;
endcase
end
endmodule
2(e) 4-BIT COMPARATOR
AIM: To write a Verilog Code to realize 4-Bit Comparator
THEORY: A comparator is a combinational circuit that compares two numbers, A and B,

and then determines their relative magnitudes. The comparison of two numbers is an
operation that determines if one number is greater than, less than or equal to the other
number. The outcome of the comparison is specified by three binary variables that indicate
whether A > B, A = B, A < B.
COMPARATOR TABLE
inputs Comparator o/p

a b agb aeb alb
100
1000 0 1 0
0
011
1000 0 0 1
1
100
0111 1 0 0
0
VERILOG CODE
module comparator(a,b,x,y,z);
input [3:0] a, b;
output reg x, y, z;
always @(a , b)
begin
x = 1'b0;
y = 1'b0;
z = 1'b0;
if(a < b)
x = 1'b1; //when a is less than b then x is high
else if(a == b)
y = 1'b1; //when a is equal to b then y is high
else if(a > b)
z = 1'b1; //when a is greater than b then z is high
end
endmodule

EXPERIMENT NO. 3
Write a VHDL and Verilog Code to describe the functions of a full adder using three
modeling styles
AIM: Write a VHDL/ Verilog code to describe the functions of a FULL ADDER using
Following modeling styles.
i) Dataflow description
ii) Behavioral description
iii) Structural description
THEORY: A combinational circuit that performs the addition of two bits is called a half
adder. One that performs the addition of three bits (two significant bits and a previous carry)
is a Full adder.
The most basic arithmetic operation is the addition of two binary digits. This simple
addition consists of four possible elementary operations namely 0 + 0 = 0, 0 + 1 = 1, 1 + 0 =
1, 1 + 1 = 10.The first three operations produce a sum whose length is one digit, but when
both augend and addend bits are equal to 1, the binary sum consists of two digits. The higher
significant bit is called carry.
a half Adder1 half Adder2

b sum
a
p p
cin
b 7486
sum
7486
s1
q
7408
7408
s2 carry
r
carry
7432
Cin
q
s3
Truth Table:
Inputs output
A b Cin Sum carry

0 0 0 0 0
0 0 1 1 0
1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

1) FULL ADDER IN DATAFLOW METHOD
VHDL CODE:
library ieee;
use ieee.std_logic_1164.all;
entity fa_dataflow is
port (a,b,cin : in bit;
sum, carry : out bit );
end fa_dataflow;
architecture Behavioral of fa_dataflow is

begin
sum<= a xor b xor cin;
carry<= ( a and b) or (b and cin) or (cin and a);
end Behavioral;
VERILOG CODE:
module full_adder_dataflow (a,b,cin,sum,carry);

input a,b,cin;
output sum,carry;
assign sum =a ^ b ^ cin;
assign carry =(a&b) | (b&cin) | (cin&a);
endmodule
2) FULL ADDER IN BEHAVIORAL METHOD
VHDL CODE:
library ieee;
entity fa_behav is
Port ( a,b,cin : in std_logic;
sum,carry : out std_logic);
end fa_behav;
architecture Behavioral of fa_behav is

begin
process (a,b,cin)
begin
sum<= a xor b xor cin;
carry<= (a and b) or (b and cin) or (cin and a);
end process;
end Behavioral;
VERILOG CODE :
module fa_behav (a,b,cin,sum,carry);

input a,b,cin;
output sum,carry;
reg sum,carry;
always @ (a,b,cin)
begin
sum=a^b^cin;
carry=(a&b)|(b&cin)|(cin&a);
end
endmodule
3) FULL ADDER USING STRUCTURAL DESCRIPTION
VHDL CODE:
library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity full_adder is
Port ( a, b, cin : in std_logic;
sum, cout : out std_logic);
end full_adder;
architecture structural of full_adder is

component xor_3
port (a,b,cin : in std_logic;
sum : out std_logic);
end component;
component and_2
port (x,y : in std_logic;
z : out std_logic);
end component;
component or_3
port (x,y,z : in std_logic;
cout : out std_logic);
end component;
signal s1,s2,s3:std_logic;
begin
u0:xor_3 port map(a,b,cin,sum);
u1:and_2 port map(a,b,s1);
u2:and_2 port map(b,cin,s2);
u3:and_2 port map(cin,a,s3);
u4:or_3 port map(s1,s2,s3,cout);
end structural;
--LOW LEVEL MODULE--
library ieee;
entity and_2 is
Port ( x,y : in std_logic;
z : out std_logic);
end and_2;
architecture Behavioral of and_2 is
begin
z<=x and y;
end Behavioral;
library ieee;
entity or_3 is
Port ( x,y,z : in std_logic;
Cout : out std_logic);
end or_3;
architecture Behavioral of or_3 is
begin
cout<=x or y or z;
end Behavioral;
library ieee;

entity xor_3 is
Port ( a,b,cin : in std_logic;
sum : out std_logic);
end xor_3;
architecture Behavioral of xor_3 is

begin
sum<=a xor b xor cin;
end Behavioral;
FULL ADDER USING TWO HALF ADDERS IN STRUCTURAL METHOD
VHDL CODE :
library ieee;
entity full_adder_struct is
port ( a,b,cin : in bit;
sum, carry : out bit);
end full_adder_struct;
architecture behavioral of full_adder_struct is

component half_adder
port ( a,b : in bit;
sum, carry : out bit);
end component;
component or_gate
port ( a,b : in bit;
e : out bit);
end component;
signal p,q,r: bit;
begin
u1: half_adder port map (a, b, p, q);
u2: half_adder port map (p, cin , sum, r);
u3: or_gate port map (q, r, carry );
end behavioral;
----------LOW LEVEL MODULE------------

library ieee;
entity half_adder is
Port ( a : in std_logic;
b : in std_logic;
sum : out std_logic;
carry : out std_logic);
end half_adder;
architecture Behavioral of half_adder is

begin
sum<= a xor b;
carry<= a and b;
end Behavioral;
----------LOW LEVEL MODULE----------

library ieee;
entity or_gate is
Port ( a : in std_logic;
b : in std_logic;
e : out std_logic);
end or_gate;
architecture Behavioral of or_gate is

begin
e<= a or b;
end Behavioral;
VERILOG CODE:
module full_adder_struct (a,b,cin,sum,carry);

input a,b,cin;
output sum,carry;
wire p,q,r;
half_adder A1 (a,b,p,q);
half_adder A2 (p,cin,sum,r);
or (carry,q,r);
endmodule
module half_adder (a,b,sum0,carry0);
input a,b;
output sum0,carry0;
xor (sum0,a,b);
and (carry0,a,b);
endmodule

EXPERIMENT NO. 4
Write a Verilog code to model 32 - BIT ALU
AIM: Write a model for 32bit ALU using schematic diagram shown below
THEORY: The arithmetic logic unit (ALU) is a digital circuit that calculates an arithmetic
operation (like an addition, subtraction, etc.) and logic operations (like XOR, AND, NOT
etc.,) between two numbers. The ALU is a fundamental building block of the central
processing unit of a computer.
Many types of electronic circuits need to perform some type of arithmetic operation,
so even the circuit inside a digital watch will have a tiny ALU that keeps adding 1 to the
current time, and keeps checking if it should beep the timer, etc...
Block diagram Truth Table
b (32) a( 32)
Enable Opcode- Input- a (32) Input- b (32) output -y
(4) (32)
0 X X X Z…….ZZZZ
1 0000 …….00001000 …….00000001 …….0000
op (4)
1001
Arithmetic y
(32) -Logic 1 0001 …….00001000 …….00000001 …….0000
0111
Unit
Enable (ALU) 1 0010 …….00001000 …….00000001 …….0000
1000
1 0011 …….00001000 …….00000001 …….1111
0111
1 0100 …….00001000 …….00000001 …….0000
0000
1 Others …….00001000 …….00000001 …….XXXX
XXXX
VERILOG CODE
module alu(a,b,opcode,enable,y, prod);

input [31:0] a,b;
input enable;
input [3:0] opcode;
output [31:0] y;
output [63:0] prod;
reg [31:0] y;
reg [63:0] prod;
always @ (a,b,enable,opcode)
begin
if(enable==1)
begin
case(opcode)
4'b0000 : y=a+b;
4'b0001 : y=a-b;
4'b0010 : prod=a[31:0]*b[31:0];
4'b0011 : y=~a;
4'b0100 : y=a&b;
4'b0101 : y=a|b;
4'b0110 :y=~(a&b);
4'b0111 :y=~(a|b);
4'b1000 :y=(a^b);
default :y=32'bx;
endcase
end
else
y=32'bZ;
end
endmodule
4-bit ALU
Verilog code
module alu(a,b,opcode,enable,y, prod);
input [3:0] a,b;
input enable;
input [3:0] opcode;
output reg [4:0] y;
output reg [7:0] prod;
always @ (a,b,enable,opcode)
begin
if(enable==1)
begin
case(opcode)
4'b0000 : y=a+b;
4'b0001 : y=a-b;
4'b0010 : prod=a[3:0]*b[3:0];
4'b0011 : y=~a;
4'b0100 : y=a&b;
4'b0101 : y=a|b;
4'b0110 :y=~(a&b);
4'b0111 :y=~(a|b);
4'b1000 :y=(a^b);
default :y=5'bx;
endcase
end
else
y=5'bz;

end
endmodule

EXPERIMENT NO. 5
Develop a Verilog code for the following flip-flops: SR, D, JK & T flip-flops.
5 (a) SR FLIP-FLOP
AIM: Develop the VHDL code for SR flip-flop.
THEORY: The basic flip-flop is an asynchronous sequential circuit. The RS flip-flop

consists of a basic NOR flip-flop and two AND gates. The outputs of the two NAND gates
remain at ‘0’ as long as the clock pulse is ‘0’, regardless of the S and R input values. When
the clock pulse goes to ‘1’, the information from the S and R inputs is allowed to reach the
basic flip-flop. The set state is reached with with S = 1 and R = 0 and Clock pulse = 1. To
change it to clear state the inputs must be S = 0, R = 1 and Clock pulse = 1. When both S
= R = 1, the occurrence of the clock pulse causes both outputs to go to 0.
Circuit diagram: Truth Table:
s s1
3 clk S R Q Qbar
1 q
1 0 0 Hold
clk 1 1 0 1 0
1 0 1 0 1
2 qn 1 1 1 z z
4
r r1 0 x x Hold
VERILOG CODE
module SR_FF (sr, clk, q, qb);

input [1:0] sr;
input clk;
output reg q, qb;
always @ (posedge clk)
begin
case (sr)
2'b00 : q = q ;
2'b01 : q = 1’b0 ;
2'b10 : q = 1’b1 ;
2'b11 : q = 1’bZ ;
endcase
qb =~ q;
end
endmodule

5 (b) D-FLIP FLOP
AIM: Develop the Verilog code for D flip-flop.
THEORY: A flip-flop is a binary cell capable of storing one bit of information. A flip-flop
circuit has two outputs, one for the normal value and one for the compliment of bit stored in
it. A flip-flop circuit can maintain a binary state indefinitely until directed by an input signal
to switch states. The major difference between various flip-flops is in number of inputs they
possess and in the manner in which the inputs affect the binary state.
The D flip-flop receives the designation from its ability to transfer data into a flip-
flop. It’s basically an RS flip-flop with an inverter in the R input. This type of flip-flop
sometimes called as D- latch.
Block diagram: Truth Table:
Clk D Q Qb
D D-Flip q 1 1 1 0
Flop 1 0 0 1
0 X X Hold
clk qb
VERILOG CODE
module dff (d,clk,q,qb);

input d,clk;
output reg q,qb;
always @ (d,clk)
begin
if(clk==1)
begin
q=d;
qb=~d;
end
end
endmodule
5(c) T-FLIP FLOP

AIM: Develop the Verilog code for T flip-flop.
THEORY: The T flip-flop is a single input version of the JK flip-flop. The T flip-flop is
obtained from JK flip-flop if both the inputs are tied together. The designation T comes from
the ability of the flip-flop to toggle. Regardless of the present state, it assumes the
complement state when the clock pulse occurs while input T is logic is 1.

Block diagram: Truth Table:
T Q Qn
0 0 1
D Q 0 1 0
T 1 0 0
T-FF
1 1 1
CLK
Qn
VERILOG CODE
module tff(clk,t, q,qb);

input clk,t;
output reg q=1’b0;
output reg qb;
wire sclk;
reg [22:0]clkdiv;
always @ (posedge(clk))
begin
clkdiv= clkdiv+1;
end
assign sclk= clkdiv[22];
always @ (posedge sclk)
begin
case(t)
1'b0 : q = q;
1'b1 : q =~q;
endcase
qb=~q;
end
endmodule
5(d) JK- FLIP FLOP
AIM: Develop the Verilog code for T flip-flop.
THEORY: A JK flip-flop is a refinement of the RS flip-flop in that the indeterminate state of

the RS flip-flop is defined in the JK flip-flop. Inputs J and K behave like inputs S and R to set

and clear the flip-flop. The JK flip-flop behaves like an RS flip-flop except when both J and
K are equal to 1. When both J and K are 1, the clock pulse is transmitted through one AND
gate only-the one whose Q=1, the output of upper AND gate becomes 1, upon application of
clock pulse, and the flip-flop is cleared. If Q’ is 1, the output of lower AND gate becomes a
1, and the flip-flop is set.
CLK J K Q Qb
J
Q 1 0 0 Hold
1 0 1 0 1
CLK J K- FF
1 1 0 1 0
Qb
K 1 1 1 Qb Q
VERILOG CODE
module jkff(jk,q,qb,clk);
input [1:0]jk;
input clk;
output reg q,qb;
wire sclk;
reg [22:0]clkdiv;
begin
clkdiv= clkdiv+1;
end
assign sclk= clkdiv[22];
always @ (posedge(sclk))
begin
case (jk)
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
2'b11:q=~q;
endcase
qb=~q;
end
endmodule

EXPERIMENT NO. 6
Design a 4-bit Binary, BCD Counters (Synchronous Reset and Asynchronous
Reset) and Any Sequence Counters, using Verilog code.
AIM: Design a 4-bit BCD COUNTER with synchronous reset and asynchronous
Reset.
THEORY: A counter is a register capable of counting the number of clock pulses arriving at
its clock input. There are two types of counters, synchronous and asynchronous. In
synchronous counter the common clock input is used to connect all the flip-flops and they are
clocked simultaneously. In Asynchronous counters the external clock pulse clocks the first
flip-flop and then each successive flip-flop is clocked by the output of previous flip-flop.
BCD stands for Binary Coded Decimal. A BCD counter has four outputs usually
labeled A, B, C, D. By convention A is the least significant bit, or LSB. In other words, the
counter outputs follow a binary sequence representing the decimal numbers 0-9.... this is why
its called as binary coded decimal counter.
Clock Reset Current Next

q3 q2 q1 qo state state
1 1 xxx 0000
1 0 0000 0001
1 0 0001 0010
Synchronous 1 0 0010 0011
BCD-Counter
1 0 0011 0100
1 0 0100 0101
1 0 0101 0110
1 0 0110 0111
Reset CLK 1 0 0111 1000
1 0 1000 1001
0 x 1001 0000
BCD-COUNTER PROGRAM WITH ASYNCHRONOUS RESET
VERILOG
module count(sclk,reset,q);
input sclk;
output reg [3:0]q;
always @ (posedge(clk) or posedge(reset))

begin
if (reset==1)
q = 4'b0000;
else if (q==4'b1001)
q = 4'b000;
else
q=q+1;
end
endmodule
WITH CLOCK DIVISION -

VERILOG
input sclk;
output reg [3:0]q;
wire clk;
reg [20:0]clkdiv;
begin
clkdiv=clkdiv+1;
end
assign clk= clkdiv[20];
begin
if (reset==1)
q = 4'b0000;
q = 4'b0000;
else
q=q+1;
end
endmodule
BCD-counter program with asynchronous reset to run on simulator
VERILOG
input sclk;
output reg [3:0]q;

begin
if (reset==1)
q = 4'b0000;
q = 4'b000;
else
q=q+1;
end
endmodule
DESIGN A 4-BIT BINARY COUNTER

q3 q2 q1 qo
Clock Reset Current state Next state
1 1 xxx 0000
Counter 1 0 0000 0001
1 0 0001 0010
1 0 0010 0011
1 0 0011 0100
1 0 0100 0101
1 0 0101 0110
Reset CLK 1 0 0110 0111
1 0 0111 1000
1 0 1000 1001
1 0 1001 1010
1 0 1010 1011
1 0 1011 1100
1 0 1100 1101
1 0 1101 1110
1 0 1110 1111
1 x 1111 0000
BINARY-COUNTER PROGRAM WITH SYNCHRONOUS RESET
VERILOG CODE
input sclk;
output reg [3:0]q;
wire clk;
reg [20:0]clkdiv;
begin
clkdiv=clkdiv+1;
end
begin
if (reset==1)
q = 4'b0000;
else
q=q+1;

end
endmodule
ANY-SEQUENCE COUNTER (SEQUENCE 3-4-8-9-11-15-0) WITH

SYNCHRONOUS RESET
VERILOG CODE
input sclk;
output reg [3:0]q = 4’d3; //counter is inialized to starting value i,e 3
wire clk;
reg [20:0]clkdiv;
begin
clkdiv=clkdiv+1;
end
begin
if (reset==1)
q = 4'b0000;
else
begin
case (q)
4’d3: q = 4’d4;
4’d4: q = 4’d8;
4’d8: q = 4’d9;
4’d9: q = 4’d11;
4’d11: q = 4’d15;
4’d15: q = 4’d3;
default: q = 4’d3;
endcase
end
end
endmodule
UP/DOWN COUNTER WITH SYNCHRONOUS RESET
Verilog
module count(sclk,ud,reset,q);
input sclk,ud;
output reg [3:0]q;
wire clk;
reg [20:0]clkdiv;
begin
clkdiv=clkdiv+1;
end
begin
if (reset==1)
q = 4'b0000;
else if (ud==1)
q=q+1;
else
q=q-1;
end
endmodule

PART-B
INTERFACING EXPERIMENTS
EXPERIMENT NO. 1
SEVEN-SEGMENT DISPLAY INTERFACE
THEORY: 7-Segment display can display the digits 0-9 and the hex extension (A-F). A
signal-character displays bring out leads for 7-segments & the common elect code (Common
cathode & common anode). Here in FPGA/CPLD board to interface one 7-segment LED
display whose elements are connected to any I/O pins of the FPGA/CPLD.
Here we can consider common-anode 7-segment LED displays. The user can then ON by
driving associated signal low.
LED 7 SEGMENT DISPLAY DIAGRAM
TRUTH TABLE:
INPUT OUTPUT
BCD LED
0000 1111110
0001 0110000
0010 1101101
0011 1111001
0100 0110011
0101 1011011
0110 1011111
0111 1110000
1000 1111111
1001 1111011
1010 1110111
1011 0011111
1100 1001110
1101 0111101
1110 1001111
1111 1000111

EXPERIMENT NO. 1A
PROGRAM TO DISPLAY HDLH ON SEVEN SEGMENT
VHDL
library ieee;
entity segment1 is
port ( header6 : out std_logic_vector(3 downto 0);
header7 : out std_logic_vector(6 downto 0);
sclk : in std_logic );
end segment1;
architecture prp of segment1 is
signal clkdiv : std_logic_vector(20 downto 0):="000000000000000000000";
signal state : std_logic_vector(1 downto 0);
signal clk1 : std_logic;
begin
process(sclk)
begin
if( rising_edge(sclk)) then
clkdiv <= clkdiv + 1;
end if;
clk1 <= clkdiv(13);
end process ;
process (clk1)
begin
if( rising_edge(clk1)) then
state <= state + 1;
end if;
end process ;
process (state)
begin
case state is
when "00" => header7<="1110110"; header6 <= "1110"; -- 'H'
when "01" => header7 <="1011110";header6 <= "1101"; -- 'D'
when "10" => header7 <="0111000";header6 <= "1011"; -- 'L'
when others => header7 <="1110110";header6 <= "1110"; --‘H’
end case ;
end process;
end prp;
EXPERIMENT NO. 1B
PROGRAM FOR BCD TO SEVEN SEGMENT DISPLAY
VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SEVSEG is
Port ( sclk : in std_logic;
q : inout std_logic_vector(3 downto 0);
header6 :out std_logic_vector(3 downto 0);
led : out bit_vector(6 downto 0));
end SEVSEG;
architecture Behavioral of SEVSEG is

signal count:std_logic_vector(3 downto 0):="0000";
signal clkdiv:std_logic_vector(22 downto 0):="00000000000000000000000";
signal clk1:std_logic;
begin
process (sclk)
begin
if(rising_edge(sclk)) then
clkdiv<=clkdiv+1;
end if;
end process;
clk1 <=clkdiv(22);
process (clk1)
begin
if (rising_edge(clk1)) then
if (count="1001") then
count<="0000";
else
count<=count+1;
end if;
end if;
end process;
q<=count;
process(q)
begin
case q is
when "0000"=>led<="0111111";
when "0001"=>led<="0000110";
when "0010"=>led<="1011011";
when "0011"=>led<="1001111";
when "0100"=>led<="1100110";
when "0101"=>led<="1101101";
when "0110"=>led<="1111100";
when "0111"=>led<="0000111";
when "1000"=>led<="1111111";
when "1001"=>led<="1100111";
when others=>led<="0000000";
end case;
header6<="0000";
end process;
end Behavioral;

EXPERIMENT NO. 2A
STEPPER MOTOR
AIM: Write the VHDL code to control speed and direction of Stepper Motor
THEORY: Stepper motors are electromechanical devices, which convert a digital pulses in
mechanical rotation, that provide accurate incremental rotation. The most common stepper
motor uses four windings for a four-phase operation. A typical four-phase motor driving
circuit is shown in Figure using an FPGA to generate the sequence logic. The clock (CLK)
input synchronizes the logic and determines the speed of rotation. The motor advances one
step per clock period; the angle of rotation of the shaft will depend on the particular motor.
To determine the clock period, consider that the stepper motor torque increases as frequency
decreases. The direction (DIR) control input changes the sequence at the outputs (PH1 to
PH4) to reverse the motor direction.
CIRCUIT DIAGRAM:
VDD
A
B
C
D
VHDL
entity stepmot1 is
port(dir : in std_logic;
rst : in std_logic;
step_signal : inout std_logic_vector(3 downto 0);
sclk : in std_logic);
end stepmot1;
architecture Behavioral of stepmot1 is
signal clkdiv : std_logic_vector(20 downto 0);

signal step_clk : std_logic;
begin
process(sclk)
begin
if(rising_edge(sclk)) then
clkdiv <= clkdiv+1;
end if;
step_clk <= clkdiv(12);
end process;
process(step_clk,rst,dir)
begin
if(rst = '1') then

step_signal <="0110";
elsif rising_edge(step_clk) then
if dir = '1' then ------------------------clockwise
case step_signal is
when "0110"=>step_signal<="1010";
when "1010"=> step_signal<="1001";
when others => null;
end case;
else ---------------------------anticlockwise
case step_signal is
when "0101" => step_signal<= "1001";
when "1001" => step_signal <= "1010";
when "1010" => step_signal<= "0110";
when "0110"=> step_signal <= "0101";
when others=> null;
end case;
end if;
end if;
end process;
end Behavioral;
EXPERIMENT NO. 2b
DC MOTOR INTERFACE
AIM: Write the VHDL code to control speed of DC Motor
VHDL
entity dcmotor is
Port ( str,dir : in STD_LOGIC;
pwm_out : out STD_LOGIC;
out_dc : out STD_LOGIC_VECTOR (1 downto 0));
end dcmotor;
architecture Behavioral of dcmotor is

begin
process(str,dir)
begin
if dir='1' and str='1' then
out_dc<="10";
pwm_out<='1';
elsif dir='0' and str='1' then
out_dc<="01";
pwm_out<='1';
else
out_dc<="00";
pwm_out<='0';
end if;
end process;
end Behavioral;

EXPERIMENT NO. 3
ELEVATOR PROGRAM USING LEDS
VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity elevator is
Port ( fl_req : in STD_LOGIC_VECTOR (2 downto 0);
Clk : in STD_LOGIC;
fl_disp : out STD_LOGIC_VECTOR (7 downto 0));
end elevator;
architecture Behavioral of elevator is

signal curr_fl :STD_LOGIC_VECTOR (2 downto 0):="000";
signal clk1 : STD_LOGIC;
begin
process(clk)
variable x :STD_LOGIC_VECTOR (22 downto 0);
begin
if rising_edge(clk) then
x:=x+1;
end if;
clk1<=x(22);
end process;
process(fl_req,curr_fl,clk1)
begin
if rising_edge(clk1) then
if (fl_req<curr_fl) then
curr_fl<=curr_fl-1;
elsif (fl_req>curr_fl) then
curr_fl<=curr_fl+1;
else
curr_fl<=curr_fl;
end if;
end if;
end process;
process(curr_fl)

begin
case (curr_fl)is
when "000"=>fl_disp<="00000001";
when "001"=>fl_disp<="00000010";
when "010"=>fl_disp<="00000100";
when "011"=>fl_disp<="00001000";
when "100"=>fl_disp<="00010000";
when "101"=>fl_disp<="00100000";
when "110"=>fl_disp<="01000000";
when "111"=>fl_disp<="10000000";
when others=>null;
end case;
end process;
end Behavioral;

Model Viva questions
What is FPGA :Field Programmable Gate Array, an array of logic gates whose configuration
can be programmed by the customer.
Explain FPGA design flow :

The ISE design flow comprises the following steps: design entry, design synthesis, design
implementation. Design verification, which includes both functional verification and timing
verification, takes places at different points during the design flow.
What is the difference between VHDL and Verilog?
VHDL, intended as a specification langauge, is very exact in its nature and hence very
verbose.
Verilog, intended as a simulation langauge, it much closer to C in style, in that it is terse and
elegant to write but requires much more care to avoid nasty bugs. VHDL doesn't let you get
away with much; Verilog assumes that whatever you wrote was exactly what you intended to
write. If you get a VHDL architecture to compile, it's probably going to approximate to the
function you wanted. For Verilog, successful compilation merely indicates that the syntax
rules were met, nothing more. VHDL has some features that make it good for system-level
modelling, whereas Verilog is much better than VHDL at gate-level simulation.
Can I use VHDL for the analog part of a design?
Yes, there is a VHDL Analogue and Mixed Signal language (VHDL-AMS), based on VHDL
93, which allows modeling of both analogue and digital in the same language.
Difference b/n FPGA and CPLD

FPGA-Field Programmable Gate Array and CPLD-Complex Programmable Logic Device--
both are programmable logic devices made by the same companies with different
characteristics.
"A Complex Programmable Logic Device (CPLD) is a Programmable Logic Device with
complexity between that of PALs (Programmable Array Logic) and FPGAs, and architectural
features of both. The building block of a CPLD is the macro cell, which contains logic
implementing disjunctive normal form expressions and more specialized logic operations".
FPGA have special routing resources to implement binary counters,arithmetic functions like
adders, comparators and RAM. CPLD don't have special features like this.
FPGA can contain very large digital designs, while CPLD can contain small designs only.The
limited complexity (<500>
Speed: CPLDs offer a single-chip solution with fast pin-to-pin delays, even for wide input
functions. Use CPLDs for small designs, where "instant-on", fast and wide decoding, ultra-
low idle power consumption, and design security are important (e.g., in battery-operated
equipment).

Security: In CPLD once programmed, the design can be locked and thus made secure. Since
the configuration bit stream must be reloaded every time power is re-applied, design security
in FPGA is an issue.
Power: The high static (idle) power consumption prohibits use of CPLD in battery-operated
equipment. FPGA idle power consumption is reasonably low, although it is sharply
increasing in the newest families.
Difference b/n FPGA and ASIC
An ASIC is an APPLICATION SPECIFIC INTEGRATED CIRCUIT. The design of this IC

depends upon the specific application for which is going to be used. But in case of FPGA,
these are
FIELD PROGRAMABLE GATE ARRAY. These ICs have programmable logic circuit
inside it. So it can be programmed in field itself according to the requirement of application.
No prior knowledge of application is required. Nowadays FPGAs are more popular than
ASIC.
What is Synthesis?
Synthesis is the stage in the design flow which is concerned with translating your VHDL
code into gates - and that's putting it very simply! First of all, the VHDL must be written in a
particular way for the target technology that you are using. Of course, a synthesis tool doesn't
actually produce gates - it will output a netlist of the design that you have synthesised that
represents the chip which can be fabricated through an ASIC or FPGA vendor.
Difference b/n functions and procedures
Function always returns a value. Procedure may or may not return a value.
Functions can be called in SQL statements. Procedure can not be called in an SQL statement.
Difference b/n D-latch and D flip-flop
D-latch is level Triggering and D Flip Flop is Edge triggering. latch can have a clock.
difference is that for a latch the output can follow input(like a buffer) if latch is in "pass"
state, else if the clock input is such that the its in "latch"state then output is preserved.
Whereas, flip-flop output only changes at the clock edge(rising or falling depending upon
type of flop)
latch-it consists of both enable and clock.flip flop-it consists of only clock and no enable is
present for flip
flop.
what s difference b/w blocking and non blocking assignments?

ans: 1.blocking stmt
these stmt blocks the other stmt from being executed.ie first these stmt gets executed
before it lets other stmt execute.
2.Non blocking stmt : these stmt executes all parallely.with designated delays.

what s racing condition?
when s=1 and r=1, then both the signals fight against each other to determine the output.if
this occurs output of the FF is not determined.
what's diffrence b/w mealy and moore ckt?
mealy
it has less number of states.
it more prone to noise.
moore
it has more number of states.
it is less prone to noise.
how will u write d ff using variables alone?(VHDL question)

using signals we can write D FF
which universal gate do u prefer(NAND or NOR)? Why?

NAND gate , it takes less power
what determines drive strength of a gate?

width of the gate determines drive strength of the gate.
what s clock skew?

when clock s routed through the chip it is subjected to parasitic capacitance, so the current
is absorbed by the circuit, so clock is delayed by some amount. Which is called clock skew.
skew-- means delay
eqn:- r1+r1*c1+r1(c1+c2)+... like that
how to reduce the frequency by half?
just put a T FF. if u put a T FF u reduce the freq by half. if u put 2 power n FF, u reduce
the frequency by n times.
what's difference b/w signals and variables in vhdl

1. Signals are used to connect the design components and must carry the information between
current statements of the design. On the other hand, variables are used within process to
compute certain values. Variables must be declared inside a process
2. A variable changes instantaneously when the variable assignment is executed. On the other
hand, a signal changes a delay after the assignment expression is evaluated. If no delay is
specified, the signal will change after a delta delay. This has important consequences for the
updated values of variables and signals.
what's difference b/w reg and wire in verilog
Whenever the simulator need storage to evaluate the value a registe is used. It is obvious
when you sample relative to clock. But combinatorial logic within an always process need to
be declared as process as well.
Nets, which connect modules use wire declaration. Same is for combinatorial, which are
assigned values by the assign value.
What is the difference between transport and inertial delays ?

VHDL provides for two types of delays - transport delays and inertial delays.
The transport delay, which is used to model the delay introduced by wiring. With transport
delay any pulse of small width is propagated to the output. The transport delay is especially
useful for modeling delay line drivers, wire delays on PC board, and on path delays on ASIC.
The inertial delay, which is the default delay type for VHDL, is used to model propagation
delay of gates and other devices. Inertial delay do not propagate short pulses from the input to
the output i.e. if a gate has an ideal inertial delay T, the input signal is delayed by time T, but
any pulse with a width less than T is rejected.
What are the different State machine Styles ? Which is better ? Explain disadvantages and
advantages.
What is the difference between === and == ?
What is the difference between unary and logical operators ?
What is the difference between tasks and functions ?
What are setup time and hold time constraints ?

Setup time :F/F input must be stable for a certain amount of time before the active edge of
the clock
Hold time : F/F input must be stable for a certain amount of time after the active edge of the
clock
What is static timing analysis?
Write the syntax for case statement ?
Expand UCF?
What are the different kinds of test benches?
Define test bench in vhdl ?
Define VHDL modules?

The general structure of VHDL module is an entity description and an architecture
description. The entity description consists of a declaration of all of the input and output
signals,and the architecture declaration specifies the internal operation of the module
Explain the various steps in synthesis?
Mention different styles of VHDL modeling?
Difference between bit, std_logic , std_logic_vector?
What is the difference between case x and case statements?
What is the difference between $monitor and $display?

What is the difference between compiled, interpreted, event based and cycle based
simulators?
What is code coverage and what are the different types of code coverage that one does ?
What is CPLD: CPLD are known to have short pin-to-pin delays, and can accept wide i/p’s,
but have relatively high power consumption and fewer f/f’s compared to FPGA’s
What is JTAG :Joint Test Action Group, older name for IEEE1149.1 Boundary scan, a
method to test PC board and ICs
K-map :a graphical tool for minimizing SOP or POS logic functions( useful for upto 6 logic
variables)
1. What does VHDL stands for?

2. Which IEEE standard describes the VHDL language?
3. List the three popular Hardware languages.
4. Which are the different levels of abstraction that can be specified using VHDL?
5. List the different design units of VHDL.
6. Which are the mandatory design units to write VHDL code?
7. Which are the different modes of port declaration?
8. Which are the valid characters for identifier declaration?
9. Which are the different classes of operators?
10. Where do you write the concurrent statements?
11. Where do you write the sequential statement?
12. In which model process statement appears?
13. What is the importance of sensitivity list in process statement?
14. Is VHDL Case sensitive?
15. Does VHDL support multi dimensionnel arrays?
16. Can combinational circuits be coded inside the process?
17. Does VHDL support operator overloading?
18. Is it possible to write multiple entities for a single architecture?
19. Is it possible to write multiple architectures for a single entity?
20. Where we declare the variable?
21. Write device configuration for CPLD and FPGA Used in your Lab.
22. Expand CPLD and FPGA.

23. Differentiate sequential and concurrent statement.
24. List the different types of wait statements.
25. How you model your program using wait statement?
26. What are the different modeling styles in VHDL?
27. What is the difference between the bit and std_logic?
28. What is the difference between the variable and signals?
29. Name the different VHDL objects.
30. Name the different data types used in VHDL.
31. Explain the VHDL term (i) Entity, (ii) Architecture, (iii) Configuration, (iv) Package,
(v) Driver, (vi) Process, (vii) Attribute, (viii) Generic and (ix) Bus.
32. Write the general syntax for Case, LOOP, Architecture Configuration, package,
Process, Exit.
33. Differentiate between Procedure and Function
34. Explain attribute, event, range
35. How to detect signal edge using attribute?
36. What is synthesis?
37. What is simulation?
38. Differentiate between syntax error and semantic error.
39. Is other clause necessary in VHDL case statement? why?
40. What are the inputs required for synthesis?
41. Which architecture description you preferred? Why?
42. Which Tool you used for simulation?
43. Which Tool you used for synthesis?
44. xc3s400pq208-4what 3S stands for? what 400 stands for? what pq208 stands for?
45. xc3s400pq208-4 what xc stands for? what -4 stands for?
46. What is the difference between CPLD and FPGA?
47. What is the difference between synchronous and asynchronous reset?
48. What is the basic element of memory?
49. What do you mean by latch?
50. How you model latch in VHDL?
51. What is the difference between synchronous and asynchronous counter?
52. What is the difference between backend and front-end?
53. Expand ASIC.
54. Expand JTAG.
55. Expand ISE

56. Which IEEE standard supports JTAG?
57. What information is present in .Bit File?
58. What do you mean by configuration?
59. Which file used to configure the CPLD?
60. Which file used to configure the FPGA?

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BMS EVENING COLLEGE OF ENGINEERING

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

HDL LAB MANUAL

Subject Code 15ECL58/17ECL58

1. Write a Verilog code to realize all the logic gates

2. Write a Verilog program for the following Combinational logic designs

1. Write VHDL/Verilog code to display messages on an alpha numeric LCD display.

3. Write VHDL/Verilog code to control speed, direction of DC and Stepper Motor.

6. Write VHDL/Verilog code to Simulate Elevator operation.

Followed by Model Viva questions

1. Double click on Vivado 2014.4 icon

2. Double click on create new project option

d. Click Next and then Finish.

Figure. Programming file

20. Click Program to program the FPGA

21. Verify the functionality by flipping switches and observing the

22. When satisfied, power OFF the board.

24. Click OK to close the session.

VHDL VHINX PROJECT NAVIGATOR TOOL TUTORIAL

ECE Dept. BMS Evening College of Engineering 1

AIM: To write a Verilog Code to realize all the Logic gates.

LOGIC GATES AND TRUTH TABLE:

Input NOT AND OR NAND NOR XOR

a b c=~a d=a&b e=a|b f=~(a&b) g=~(a|b) h=a^b

module basic_gates (a,b,c,d,e,f,g,h);

ECE Dept. BMS Evening College of Engineering 2

ECE Dept. BMS Evening College of Engineering 3

ECE Dept. BMS Evening College of Engineering 4

Enable X(1) X(0) Y(3) Y(2) Y(1) Y(0)

ECE Dept. BMS Evening College of Engineering 5

ENCODER WITHOUT PRIORITY

ECE Dept. BMS Evening College of Engineering 6

ENCODER WITH PRIORITY

ECE Dept. BMS Evening College of Engineering 7

THEORY: A digital multiplexer is a combinational circuit that selects binary information

BLOCK DIAGRAM: TRUTH TABLE:

ECE Dept. BMS Evening College of Engineering 8

module mux8to1(i, y, s);

2(d) BINARY TO GRAY CODE CONVERSION

AIM: To write a Verilog Code to realize 4-bit Binary to Gray Conversion

b(0) b(1) b(2) b(3)

ECE Dept. BMS Evening College of Engineering 9

assign g[3] = b[3];

2(e) 2:1 MULTIPLEXER

AIM: To write a Verilog Code to realize 2 to 1 Multiplexer

ECE Dept. BMS Evening College of Engineering 10

BLOCK DIAGRAM TRUTH TABLE

module MUX2_1 (A, B, SEL, En, Y);

AIM: To write a Verilog Code to realize 1 to 8 De-Multiplexer

ECE Dept. BMS Evening College of Engineering 11

module Demux1to8 (i, y, s);

2(e) 4-BIT COMPARATOR

AIM: To write a Verilog Code to realize 4-Bit Comparator

THEORY: A comparator is a combinational circuit that compares two numbers, A and B,

inputs Comparator o/p

ECE Dept. BMS Evening College of Engineering 13

a half Adder1 half Adder2

A b Cin Sum carry