Chapter-4

(12 Marks )

Microprocessor: 8086 and Modern

Microprocessors
 Introduction to Microprocessor

● A microprocessor is a multipurpose, clock driven

electronic component that is used by computer to
do it’s work.

● It accepts binary information as input, processes

it according to instruction stored in its memory
and provides results as output.

● It is just like central processing unit(CPU) on a

single integrated circuit.
Input(binary data) Microprocessor Output

Memory

Fig. A Programmable Machine

 Evolution of Microprocessor &
Types :-
The microprocessor operates in binary digits 0 and 1
also known as bits.

1) 4-Bit Microprocessors

2) 8-Bit Microprocessors

3) 16-Bit Microprocessors

4) 32-Bit Microprocessors

5) 64-Bit Microprocessors
 Salient Features of 8086 Microprocessor :-
1. It is 16 bit Microprocessor(i.e. it can read or write or
perform arithmetic and logical operations on 16-bit
data at a time).
2. It has a 16-bit data bus and 20-bit address bus.
Hence it can access upto (2^20=1MB) memory
location.
3. Operating Clock Frequencies are 5 MHz, 8 MHz or 10
MHz.

4. Operate in maximum and minimum mode to

achieve high performance level.

5. Supports 24 addressing modes.

 Salient Features of 8086 Microprocessor :-
6. Provides 256 software interrupts and 2 hardware
interrupts.

7. Provide 6 byte instruction queue for Pipelining of

instruction execution.

8. Arithmetic operation can be performed on 8-bit or

16-bit signed and unsigned data including multiplication
and division.

9. It has multiplexed address and data bus AD0- AD15

and A16 – A19 are multiplexed with status signals.
 Salient Features of 8086 Microprocessor :-
10. It requires +5V power supply.

11. A 40 pin dual in line package.

12. Supports Multiprogramming and segmentation.

Pin Diagram of 8086 Microprocessor :-
 AD0-AD15 (Bidirectional) : Address/Data bus.

These are low order address bus. They are multiplexed

with data lines.

Whenever the ALE=1 these pins carry the address, when

the ALE=0 it carry the data.

A16-A19 (Output) : High order address bus.

These are multiplexed with status signals S3,S4,S5 and
S6(A16/S3, A17/S4, A18/S5, A19/S6 )

When ALE=1 these pins carry the address and when

ALE=0, they carry the status lines.
 AD0-AD15 (Bidirectional) : Address/Data bus.

These are low order address bus. They are multiplexed

with data lines.

Whenever the ALE=1 these pins carry the address, when

the ALE=0 it carry the data.

A16-A19 (Output) : High order address bus.

These are multiplexed with status signals S3,S4,S5 and
S6(A16/S3, A17/S4, A18/S5, A19/S6 )

When ALE=1 these pins carry the address and when

ALE=0, they carry the status lines.
BHE / S7(Active Low)/S7 (Output):
Bus High Enable/Status.

When BHE is low it indicates that AD15-AD8 are involved

in data transfer.
S7 always remain high.

RD (Read) (Active Low) :

●
The signal is used for read operation.
●
It is an output signal. It is active when low.

READY: This is the acknowledgment from the slower I/O

device or memory.

When high it indicates that peripheral device is ready to

transfer data.
 INTR-Interrupt Request:

This is a level triggered interrupt request input and is

checked during the last clock cycles of each instruction to
determine the availability of the request.

NMI –Non Maskable Interrupt:

• It is an edge triggered input which causes a Non-maskable
interrupt.
• The non-maskable interrupt input is a hardware interrupt.
• It cannot be disabled by software.
INTA: Interrupt acknowledge.
●
It is active LOW Signal.
●
When microprocessor receive INTR signal, processor
complete m/c cycle and acknowledge the interrupt by
generating this signal.

MN/MX:MINIMUM(Active high)/MAXIMUM(Active Low:

This pin signal indicates what mode the processor is to
operate in.

RQ/GT1, RQ/GT0 : REQUEST/GRANT:

●
These pins are bidirectional.

●
RQ/GT0 have higher priority than RQ/GT1.
●

After receiving request on these lines, CPU sends

acknowledge signal on the same lines.
RESET (Input) : RESET:
It is system reset. When this signal goes high, the
processor enter into reset state.

LOCK:
● Its an active low pin.

● When LOCK is active LOW, it indicates that other

system bus masters are not to allowed to gain control of
the system bus.

TEST :-
It is an active low pin.
This signal is used to test the status of math co-processor
8087.
Vcc – Power Supply ( +5V D.C.)

GND – Ground
QS1, QS0 (Queue Status):-
These signals indicate the status of the internal 8086
instruction queue according to the table shown below:
QS1 QS0 Status
0 0 No Operation

0 1 First Byte of Op Code from Queue

1 0 Empty the Queue

1 1 Subsequent Byte from Queue

DT / R :- Data Transmit/Receive:
This output pin is used to decide whether data is
transmitted or received by microprocessor.

DT / R =1 indicates transmitting the data

DT / R =0 indicates processor receives data.

DEN :- Data Enable((Active Low)

-This signal informs the transceiver that
the microprocessor is ready to send or receive the data.
-This signal indicates the availability of valid data over
the address/data lines.
M / IO :-(Memory / Input Output)
● The signal on this pin indicates a memory or I/O
operation.

If M / IO =1, then microprocessor is performing memory

related operation.
if M / IO =0 then microprocessor is performing I/O related
operation.

ALE :( Address Latch Enable): Active High

Signal
It indicate the availability of valid address on AD0-
AD15.
WR: (WRITE) :-Active Low Signal
This is active low signal issued by processor to write data
to memory or I/O depending on the status of M / IO signal.

HOLD: Active High Signal

When another master device needs the use of address,
data and control bus, it sends a HOLD request to the
processor through this line.

HLDA (Hold Acknowledge) :-

The processor receiving the hold request will issue HLDA
as an acknowledgment
S0, S1 and S2 :- Active Low Status Signals
These status signals reflect the type of operation being carried
out by the processor and required by the bus controller.

S2 S1 S0 Status
0 0 0 INTA
0 0 1 I/O Read
0 1 0 I/O Write
0 1 1 HALT
1 0 0 Opcode Fetch
1 0 1 Memory Read
1 1 0 Memory Write
1 1 1 Passive
Block Diagram of 8086 Microprocessor

OR

Architecture of 8086 Microprocessor

Draw the labeled architecture of 8086
8086 has two blocks :BIU (Bus Interface Unit) and
EU (Execution Unit)

Functions of BIU :-
● The BIU performs all bus operations such as instruction

fetching, reading and writing operands for memory and

calculating the addresses of the memory operands.

● The instruction bytes are transferred to the instruction

queue.

● BIU contains Instruction queue, Segment registers,

Instruction pointer, and Address adder.
● BIU controls the address, data and control buses.
● It provides a full 16 bit bidirectional data bus and 20 bit
address bus.
● The bus interface unit is responsible for performing all
external bus operations.

Functions of Execution Unit(EU) :-

● EU executes instructions from the instruction system byte
queue.
● EU contains Control circuitry, Instruction decoder, ALU,
Pointer and Index register, Flag register.
● The Execution unit is responsible for decoding and
executing all instructions.
● During the execution of the instruction, the EU tests the
status and control flags and updates them based on the
results of executing the instruction.

● EU has a 16 bit ALU, which can perform arithmetic and

logical operations on 8 bit as well as 16 bit data.
Instruction Queue:-
● The BIU fetches(takes)up to six instruction bytes from

the memory and stores these pre-fetched bytes in a first

–in first out register set called Queue.

● When the execution unit is ready for the execution of the

instruction ,instead of fetching the byte from the
memory ,it reads the byte from the Queue.

● The processor doesn't have to wait for the next

instruction to be fetched as it is already made available in
the queue registers. Thus, the speed of operation is
enhanced.
● This pre fetching of next instruction while another
instruction is still being executed is known as pipelining.
General-purpose Registers:
● There are eight 8-bit general-purpose registers: AL, AH,
BL, BH, CL, CH, DL and DH. These can be used for
temporary storage of 8-bit data.

● They can also be used for storage for 16-bit data words
as groups: AX register (AH and AL), BX register (BH and
BL),CX register (CH and CL) and DX register (DH and
DL).
Other Registers:
● The other four registers are referred to as index /
pointer registers such as SP, BP, SI and DI.
● They are Stack Pointer register , Base Pointer register,
Source Index register and Destination Index registers.
ALU(Arithmetic and Logical Unit): -
ALU is used to perform arithmetic and logical
operations on 8 bit as well as 16 bit data.

Address generator: -
This unit is used to generate 20 bit physical address
by adding 16 bit logical address displacement with
base address.

Instruction Decoder:-
This unit is used to decode or convert the
instructions and provides signals to various units in
the EU.
Segment Registers of 8086:-
BIU has 4 segment registers of 16 bits each i.e

CS(Code Segment) register

DS (Data Segment) register
SS(Stack Segment) register and
ES(Extra Segment) register

These registers are used to point/address particular memory

location in memory.
CS(Code Segment) :-CS register is used to address/point a
memory location in the code segment of the memory where
opcode of program is stored.

Data Segment(DS) : DS register points to the data segment

of the memory where the data is stored.

Extra Segment (ES): ES register is used to address the

segment which is additional data segment.

Stack Segment (SS) : SS Register is used to point Stack

location in stack segment of the memory and used to store
data temporarily on the stack
Flag Register :-
● This register is also called status register.

● It is a 16 bit register which contains 6 status flags and 3

control flags. So, only nine bits of the 16 bit register are
defined and the remaining seven bits are undefined.

● The Flag register contains

Carry flag
Parity flag
Auxiliary carry flag
Zero flag
Sign flag
Trap flag
Interrupt flag
Direction flag and overflow flag
CF,PF,AF,ZF,SF,OF are the status flags and the TF,IF and
DF are the control flags.
1. Carry flag(CF): This flag is set when there is a carry out
of MSB in case of addition or a borrow in case of
subtraction.

2. Parity flag(PF): This flag is set to 1 if the lower byte of

the result contains even numbers of 1s.

3. Auxiliary carry flag (AF): This is set if there is a carry

from the lowest nibble, i.e. bit three during addition or
borrow for the lowest nibble i.e. bit three during
subtraction.

4. Zero Flag(ZF): This flag is set, if the result of the

computation or comparison performed by the previous
instruction is zero.
5. Sign Flag(SF) : This flag is set, when the result of any
computation is negative.
 
6.Trap Flag(TF):If TF=1, the CPU automatically generates
an internal interrupt after each instruction. This flag is
used for debugging of program.

7.Interrupt Flag(IF): If this flag is set, the maskable

interrupt INTR of 8086 is enabled and if it is zero ,the
interrupt is disabled.

If IF=1, the CPU will recognize external interrupt request.

8.Direction Flag (DF): This bit is specially for string
instructions.
If this flag bit is ‘0’, the string is processed beginning from
the lowest address to the highest address, Otherwise, the
string is processed from the highest address towards the
lowest address.

9.Over flow Flag(OF): This flag is set, if the result of a

signed operation is large enough to accommodate in a
destination register.
Memory Segmentation in 8086:-
What is segmentation?
It is the process in which the main memory of computer is
divided into different segments and each segment has it’s own
base address.
Memory Segmentation in 8086:-
Advantages of Segmentation :-

●
It is used to increase the execution speed of computer
system.

●
Programs and data can be stored separately.

●
Segmentation allows two processes to share data.
Physical Memory address Generation :-
***Explain the concept of physical address calculation with
suitable diagram and example.**

- The address associated with any instruction or data byte

is only 16-bit called as Effective Address/Offset/
Displacement/ Logical Address.

- The logical addresses are used to calculate physical

address

- The address generated by BIU is 20-bit called as

Physical address

Physical address = ( Segment base address *10H ) +

Offset address.
 Physical Memory address Generation :-

Calculate the physical address generated by:

i) 4370 : 561E

4 370 0 - Segment Base Address

+ 561E - Offset Address

4 8 D1 E – Physical Address

Physical Address = 48D1E H

 Physical Memory address Generation :-

Calculate the physical address generated by:

ii) CS:7A32 IP: 0028

7 A 3 2 0 - Segment Base Address

+ 0 0 2 8 - Offset Address
7 A3 4 8 – Physical Address

HW
iii)DS:A000H BX:2000H
iv)CS:1000H IP:2000H
V) CS:69FAH IP:834CH
Vi) DS:C239H SI:8ABCH
Vii)CS:1200H IP:DE00H
Viii) DS:1F00H BX:1A00H
● The contents of the following registers are:
CS = 1111 H
DS = 3333 H
SS = 2526 H
IP = 1232 H
SP = 1100 H
DI = 0020 H
Calculate the corresponding physical
addresses for the address bytes in CS, DS
and SS.
●
 Concepts of Pipelining :-
● Fetching the next instruction while the current instruction
is executing is called as pipelining.
● Because of this execution time will be reduced.
● Ultimately it improves the execution speed of the
processor.
● In pipelined processor, fetch, decode and execute
operations are performed in parallel.
● In 8086, pipelining is implemented by providing 6 byte
instruction queue where 6 one byte instructions can be
stored well in advance and then one by one instruction
goes for decoding and execution.
● In this way 8086 perform fetch, decode and execute
operation in parallel.
 Advantages of Pipelining :-
● Pipelining enables many instructions to be executed at the
same time.
● It allows execution to be done in fewer clock cycles.
● Speed up the execution speed of the processor.
● More efficient use of processor.
 CISC Processor :-
● CISC stands for Complex Instruction Set Computer
● Features of CISC Processors:
1. CISC chips have complex instructions.
2. CISC processors have a variety of instructions
3. CISC machines generally make use of complex addressing modes.
4. CISC processors have variable length instructions
5. Easier compiler design
6. CISC processors are having limited number of registers.
7. Intel uses CISC Chips.
Examples of CISC processors are:
Intel 386, 486, Pentium, Pentium Pro, Pentium II, Pentium III etc.
 RISC Processor :-
● RISC stands for Reduced Instruction Set Computer
● Features of RISC Processors:
1. RISC processors use a small and limited number of instructions.
2. RISC processors consume less power and have high performance.
3. Each instruction is very simple and consistent.
4. RISC processors use simple addressing modes.
5. RISC instruction is of uniform fixed length.
6. Large Number of Registers.
7. Apple uses RISC chips.
Examples of RISC processors are: IBM RS6000, MC88100 ,DEC’s
Alpha 21064, 21164 and 21264 processors.
 Compare CISC and RISC Processors :-
●

Sr. No. Parameter RISC CISC

1 Instruction Set Few instructions in More instructions in

instruction set instruction set

2 Data Types Few Data types More Data types

3 Addressing Mode Few Addressing Modes More Addressing Modes

4 Registers Large number of general Small number of general

purpose registers purpose registers and
several special purpose
registers.

5 Architecture Type Load / Store architecture No Load / Store

architecture

6 Opearation Single-cycle opearation Multi-cycle opearation

7 Design Hardwired control Micro-coded control

8 Instruction Format Fixed length instruction Variable length instruction

format format
Compare features of Microprocessor 8086 with Pentium
processor III on the basis of following parameters :
 Memory size
 Address bus/ data bus width
 Clock speed (MHz)
 Modes of operation
 ALU

Sr. Parameter 8086 Pentium Processor III

No.
1 Memory size 1MB 512KB Cache
Memory
2 Address bus/ data 20bit / 16bit 32 bit / 64 bit
bus width
3 Clock speed (MHz) 5MHZ, 8MHZ, 10MHZ 800 MHZ
4 Modes of operation Maximum and
Minimum mode
5 ALU 01 02
Question :-Write use of index registers, base
pointer and instruction pointer.
Index Registers:-
● The Index registers are used as general purpose registers as

well as for holding the offsets. These index registers are

specifically used in string manipulations.
● There are usually two types of index registers such as Source

Index Register(SI) and Destination Index Register(DI). Both

are 16-bit registers.
● Source Index register(SI) is generally used to store the offset

of source data in data segment .

● Destination Index register(DI) used to store the offset of

destination data in data or extra segment.

Instruction Pointer(IP) :
It is a 16-bit register which always points to the next instruction
to be executed within the currently executing code segment.
Question :-Write use of index registers, base
pointer and instruction pointer.
Pointer Registers:-
● There are two 16 bit pointer registers: Stack Pointer (SP) and

Base Pointer (BP)

● SP(Stack Pointer) : This is the 16-bit register. It points to the

program stack in stack segment.

● BP(Base Pointer): BP is also the 16-bit register. It holds the

offsets of data segment