Microprocessor term paper

ECE 212:- Microprocessor

TOPIC – Design of Handshaking mode of 8255 with

8086.

Submitted To : Ms. Kamal Preet

Submitted By : Manish Kumar
Roll No : A16
Section : B1802
Registration No : 10801901
Acknowledgement

First and foremost I would like to thank my teacher who has assigned me this
term paper to bring out my creative capabilities.

I express my gratitude to my parents for being a continuous source of

encouragement and for all their financial aid given to me.

I would like to thank to acknowledge the assistance provided to me by the library

staff of Lovely Professional University.

My heartfelt gratitude to my friends, cousins for helping me to complete my work

in time.
 Contents

1) Introduction
2) Operational mode of 8255

3) Control word Format

4) Low speed two way Handshaking

5) High speed two way Handshaking

 Introduction
The Intel8255 Programmable Peri
pheral Interface chip is a
peripheral chip originally
developed for the Intel
8085 microprocessor, and as such
is a member of a large array of
such chips, known as the MCS-85
Family. This chip was later also
used with the Intel 8086 and its
descendants
This chip is used to give the CPU
access to programmable
parallel I/O, and is similar to other
such chips like the Motorola 6520
PIA(Peripheral Interface
Adapter) . The 8255 is widely
used not only in many
microcomputer/microcontroller
systems especially Z-80
based, home computers such
as SV-328and all MSX, but also in
the system board of the best
known original IBM-PC, PC/XT,
PC/jr, etc. and clones, along with
numerous homebuilt
computer computers such as
the N8VEM.
The 8255 has 24 input/output pins
in all. These are divided into three
8-bit ports. Port A and port B can
be used as 8-bit input/output ports.
Port C can be used as an 8-bit
input/output port or as two 4-bit
input/output ports or to produce
handshake signals for ports A and
B.
The three ports are further
grouped as follows:
1. Group A consisting of port
A and upper part of port
C.
2. Group B consisting of port
B and lower part of port
C.
Eight data lines (D0 - D7) are
available (with an 8-bit data
buffer) to read/write data into the
ports or control register under the
status of the " RD" (pin 5) and 
WR" (pin 36), which are active
low signals for read and write
operations respectively. The
address lines A1 and A0 allow to
successively access any one of the
ports or the control register as
listed below:
A1 A0 Function
0 0 port A
0 1 port B

1 0 port C
1 1 control register
The control signal "' CS" (pin 6)
is used to enable the 8255 chip. It
is an active low signal, i.e.,
when  CS = '0' , the 8255 is
enabled. The RESET input (pin
35) is connected to a system (like
8085, 8086, etc. ) reset line so that
when the system is reset, all the
ports are initialised as input lines.
The control register or the control
logic or the command word
register is an 8-bit register used to
select the modes of operation and
input/output designation of the
ports.
Operational modes of 8255
There are two main operational
modes of 8255:
1. Input/output mode
2. Bit set/reset mode
Input/output mode
There are three types of the
input/output mode which are as
follows:
Mode 0
In this mode, the ports can be used
for simple input/output operations
without handshaking. If both port
A and B are initialized in mode 0,
the two halves of port C can be
either used together as an
additional 8-bit port, or they can
be used as individual 4-bit ports.
Since the two halves of port C are
independent, they may be used
such that one-half is initialized as
an input port while the other half
is initialized as an output port. The
input/output features in mode 0
are as follows:
1. O/p are latched.
2. I/p are buffered not
latched.
3. Port do not have
handshake or interrupt
capability.
Mode 1
When we wish to use port A or
port B for handshake input or
output operation, we initialize that
port in mode 1 (port A and port B
can be initialized to operate in
different modes, i.e., for e.g., port
A can operate in mode 0 and port
B in mode 1). Some of the pins of
port C function as handshake
lines.
For port B in this mode
(irrespective of whether is acting
as an input port or output port),
PC0, PC1 and PC2 pins function
as handshake lines.
If port A is initialized as mode 1
input port, then, PC3, PC4 and
PC5 function as handshake
signals. Pins PC6 and PC7 are
available for use as input/output
lines.
The mode 1 which supports
handshaking has following
features:
1. Two ports i.e. port A and B
can be use as 8-bit i/o
port.
2. Each port uses three lines
of port c as handshake
signal and remaining two
signals can be function as
i/o port.
3. Interrupt logic is
supported.
4. Input and Output data are
latched.
Mode 2
Only group A can be initialised in
this mode. Port A can be used
for bidirectional handshake data
transfer. This means that data can
be input or output on the same
eight lines (PA0 - PA7). Pins PC3
- PC7 are used as handshake lines
for port A. The remaining pins of
port C (PC0 - PC2) can be used as
input/output lines if group B is
initialized in mode 0. In this mode,
the 8255 may be used to extend
the system bus to a
slave microprocessor or to transfer
data bytes to and from a floppy
disk controller.
Bit set/reset (BSR) mode
Control word format
Input/output mode format
 The figure shows the
control word format in the
input/output mode. This mode
is selected by making D7 =
'1' .
 D0, D1, D3, D4 are for
lower port C, port B, upper
port C and port A respectively.
When D0 or D1 or D3 or D4
are "SET", the corresponding
ports act as input ports. For
e.g., if D0 = D4 = '1', then
lower port C and port A act as
input ports. If these bits
are "RESET", then the
corresponding ports act as
output ports. For e.g., if D1 =
D3 = '0', then port B and upper
port C act as output ports.
 D2 is used for mode
selection for group B (Port B
and Lower Port C). When D2
= '0', mode 0 is selected and
when D2 = '1', mode 1 is
selected.
 D5, D6 are used for mode
selection for group A (Upper
Port C and Port A). The format
is as follows:
D6 D5 mode
0 0 0
0 1 1 BSR mode. This mode is
1 X 2
Example: If port B and upper
port C have to be initialised as
input ports and lower port C and
port A as ouput ports (all in mode
0), what is the control word?
1. Since it is an input/ouput
mode, D7 = '1'.
2. Mode selection bits, D2,
D5, D6 are all '0' for mode
0 operation.
3. Port B should operate as
input port, hence, D1 = '1'.
4. Upper port C should
also be an input port,
hence, D3 = '1'.
5. Port A has to operate
output port, hence, D4 =
'0'.
6. Lower port C should
also operate as output port,
hence, D0 = '0'.
Applying the corresponding
values to the format in
input/output mode, we get the
control word as "8A (hex)"
BSR mode format
 The figure shows the
control word format in
selected by
making D7='0'.
 D0 is used for bit set/reset.
When D0= '1', the port C
bit selected (selection of
a port C bit is shown in
the next point) is SET,
when D0 = '0', the port C
bit is RESET.
 D1, D2, D3 are used to
select a particular port C
bit whose value may be
altered using D0 bit as
mentioned above. The
selection of the port C
bits are done as follows:
 3. PC5 has to be selected,
hence, D3 = '1', D2 = '0',
D3 D2 D1 Bit/pin of port C selected D1 = '1'.
4. PC5 has to be set,
0 0 0 PC0 hence, D0 = '1'.

0 0 1 PC1

0 1 0 PC2
Low-Speed Two-Way
Handshaking
0 1 1 PC3

For this application note, low-

1 0 0 PC4 speed data transfers relate to data
that is transferred at a rate less
than 1 million samples per second
1 0 1 PC5 (1 MS/s).

1 1 0 PC6
1 1 1 PC7
 D4, D5, D6 are not used.
Example: If the 5th bit (PC5)
of port C has to be "SET",
then what is the control
word?
1. Since it is BSR
mode, D7 = '0'.
2. Since D4, D5, D6 are
not used, assume them to
be '0'.
8255/82C55 Mode
This is the most common
handshaking protocol. Common
applications include interfacing to
parallel digital I/O peripherals
such as BCD-compatible panel
meters and communication/control
of test equipment. All Lab/1200
Family, DIO-24/96, and MIO-16D
boards use an 8255 or 82C55 PPI.
In this application note 8255 and
82C55 PPIs will be referred to
simply as 8255. Although the
6533 Family can emulate the 8255
protocol, the following discussion
relates to the actual 8255
handshaking and not to the 8255
emulation mode of the 6533. Each
8255 chip contains three 8-bit
ports (PA, PB, and PC). When the
8255 is configured for a
handshaking operation, lines in
Port C are used to control the data
transfer operation.
8255 -- Mode 1, Strobed Input
A low signal in the STB* line
causes the 8255 to load data into
the input latch. The 8255 outputs a
high signal on the IBF line to
indicate that data has been loaded
into the input latch. When the IBF
lines goes back to low, the
peripheral device can then place a
low signal on the STB* line to
load new data into the input latch
of the 8255.
8255 -- Mode 1, Strobed Output
The two control lines that are used
in strobed output operations are
ACK* and OBF*. The ACK* line
is an input controlled by the
peripheral device that is
handshaking with the 8255. The
OBF* is an output line controlled
by the 8255. The 8255 device
places a low signal on the OBF*
line to indicate that data has been
written to the port. The peripheral
device places a low signal on the
ACK* line to indicate that the data
written by the 8255 has been
accepted. The peripheral device
then sets the ACK* signal back to
high when it is ready to accept
new data.
8255 -- Mode 2, Bidirectional
Bus
Only Port A on the 8255 PPI can
be configured for a bidirectional
mode. Two main lines of port C
are used to control handshaking of
port A -- ACK* and STB*.

When you want to configure the

port as output, both ACK* and
STB* are initially high. When the
ACK* line goes low, data will be
driven to Port A as long as the
ACK* line is low. As soon as the
ACK* line goes high again, Port
A goes back to a high impedance
mode, and thus the pattern you
just wrote will no longer be
present.
More than one digital port can be
grouped together so that more
digital data can be transferred at a
time, such as 16-bit data transfers
with two ports instead of 8-bit data
transfers with one port. For 8255-
based devices that perform
handshaking, all the STB* lines
must be connected together for
digital input. Only the IBF* line of
the last port should be connected
to the peripheral device.

Handshaking More than One

Port or More than One 8255 PPI

Figure 6. Digital Scanning Output

Group Handshaking Connections

When performing digital output

handshaking on more than one
8255 port, connect only the ACK*
and OBF* handshaking signals of
the last port.
High-Speed Two-Way
Handshaking -- Asynchronous
There are two main categories of
high-speed handshaking --
synchronous and asynchronous.
The synchronous protocols use a
shared clock between transmitter
and receiver to perform the block
transfer. High-speed handshaking
in this application note refers to
data transfers faster than 1 MS/s.
While the DIO-32F DAQ devices
implement all the following modes
(except 8255 emulation and burst
mode), they cannot handshake
data at high speeds. Sustained
transfer rates is typically less than
400 kwords/s with the driver
software (1 word = 16 bits).
Level-ACK, Leading-Edge Pulse,
Long Pulse, and Trailing-Edge
Pulse 
These protocols are recognized
only by the DIO-32F and the 6533
Family DAQ devices. Two control
lines are used to handshake the
data transfers: ACK and REQ. The
DAQ device (6533 or DIO-32F)
controls the ACK signal and the
peripheral device controls the
REQ signal.
Level-ACK Mode
In level-ACK mode, the DAQ
device asserts the ACK signal
when ready for a transfer and
holds the ACK signal level until
an active-going edge occurs on the
REQ line. After the REQ edge
occurs, the 6533 device deasserts
the ACK signal until ready for
another transfer.

8255 Emulation

8255 emulation mode is available

only on 6533 devices. This mode
handshakes in a manner
compatible with the 8255 PPI. The
6533 device emulation mode is a
superset of the 8255 handshaking
protocol. The 6533 device can
perform back-to-back transfers
much faster than a true 8255-
based device. If the peripheral
device needs more time, you can
configure the 6533 device to add a
data settling delay between
transfers. The 6533 device can use
8255 emulation with 8, 16, or 32-
bit data paths.
 pulse mode, a programmable
delay is used to increase the
minimum width of the pulse rather
than delaying the ACK pulse. In
long-pulse mode you can
handshake with 8255 emulation
mode, if you set the ACK and
REQ signals to active low. If you
want to use long-pulse to
handshake with an actual 8255,
make sure to select an adequate
minimum pulse width for your
8255. A data-settling time of 500
ns is sufficient for any current
8255. 
Leading-Edge Mode
In leading-edge mode, the DAQ
device and the peripheral device
send each other pulses on the
ACK and REQ lines. The leading
edge of the ACK or REQ pulse
indicates that the DAQ device or
peripheral device is ready for a
transfer. In input mode, the DAQ
device sends an ACK pulse when
ready to receive data. After
receiving at least the leading edge
of the ACK pulse, the peripheral
devices can strobe data into the
DAQ device by asserting the REQ
signal. In output mode, the DAQ
device sends an ACK pulse after
driving output data to indicate
new, valid output data. The  Long-Pulse Mode Input
peripheral device can latch the
data on the falling or rising edge
of the ACK signal, or at any time
before returning a REQ pulse, thus
requesting additional data. 

Long-Pulse Mode
Long-pulse mode is a variant
of leading-edge mode. The only
difference is the effect of a data
settling delay, if used. In long-
 Burst Mode
The burst-mode handshaking
protocol is used only by 6533
Family DAQ devices. This
handshaking mode is a
synchronous, or clocked protocol.
Common applications include
electronic and logic testing, board
and chip verification, pattern
detection, and high-speed
communication/data transfer with
ATE (automated test equipment).
In burst mode, three control lines
are used for data transfers -- REQ,
ACK, and PCLK. The data
transmitter and receiver share a
clock signal over the PCLK
Long-Pulse Mode Output
control line. The 6533 device
controls the state of the ACK line,
Trailing-Edge Mode
and the peripheral device controls
In trailing-edge mode, the DAQ
the state of the REQ line.
device and peripheral device send
each other pulses on the ACK and
REQ lines. The trailing edge of
the ACK or REQ pulse indicates
that the DAQ device or peripheral
device is ready for a transfer.

Input Burst Mode Transfer

Example

Trailing-Edge Mode Input

High-Speed Two-Way
Handshaking -- Synchronous
Output Burst Mode Transfer
Example

When performing a burst-mode

input operation with an external
PCLK, data will be latched on the
falling edge of PCLK. With all
other data transfer functions and
PCLK directions, data is latched
on the rising edge of PCLK.