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CSE211 - Updated New IP Aug 2015
CSE211 - Updated New IP Aug 2015
Course Code Course Title Course Planner Lectures Tutorials Practicals Credits
CSE211 COMPUTER ORGANIZATION AND DESIGN 13742::Mandeep Singh 3.0 1.0 0.0 4.0
Course Orientation 1 :DISCIPLINE KNOWLEDGE, 7 :COMPETITIVE EXAMINATION(Higer Education)
TextBooks
Sr No Title Author Edition Year Publisher Name
T-1 COMPUTER SYSTEM MORRIS MANO 3rd 2007 PRENTICE HALL
ARCHITECTURE
Reference Books
Sr No Title Author Edition Year Publisher Name
R-1 COMPUTER ORGANIZATION CARL HAMACHER, 5th 2011 MCGRAW HILL EDUCATION
ZVONKO VRANESIC,
SAFWAT ZAKY
R-2 COMPUTER ARCHITECTURE A HENNESSY,J.L,DAVID 4th 2006 PEARSON
QUANTITATIVE APPROACH A PATTERSON, AND
GOLDBERG
R-3 COMPUTER ORGANISATION P. PAL CHOUDHURI 2nd 2003 PRENTICE HALL
AND DESIGN
R-4 COMPUTER SYSTEM JOHN P.HAYS 3rd 1998 MCGRAW HILL EDUCATION
ARCHITECTURE
R-5 COMPUTER ORGANIZATION WILLIAM STALLINGS 8th 2004 PRENTICE HALL
AND ARCHITECTURE-
DESIGNING FOR PERFORMANCE
Other Reading
Relevant Websites
Sr No Web address (only if relevant to the course) Salient Features
RW-1 http://www.cs.uwm.edu/classes/cs458/Lecture/HTML/ch01s06.html Flip-Flops
Virtual Labs
Sr No VL (only if relevant to the course) Salient Features
VL-1 http://www.softpedia.com/get/Others/Home-Education/CEDAR-Logic-Simulator.shtml CEDAR Logic Simulator
VL-2 http://sourceforge.net/projects/circuit/files/latest/download Simulations
VL-3 http://sourceforge.net/projects/qucs/files/latest/download?source=rw_dlp_t5 Simulations
Basics Of Digital RW-5 Introduction of boolean i. Understand the Demonstration A simple finite
Electronics(boolean algebra) AV-1 algebra basic concept of with simulator. state machine
VL-3 boolean algebra. for the soda
ii. Employ Boolean machine
algebra to describe
the function of logic
circuits.
Lecture 2 Basics Of Digital AV-1 Describing about i. Understand about Demonstration A digital circuit
Electronics(map VL-1 boolean function and boolean algebra and with simulator. can be designed
simplification) boolean expressions can map simplification to control the
be simplified using map ii. Analysis and movement of an
simplification design of digital elevator.
circuits.
Basics Of Digital T-1:1 RW-1 i. Introduction of i. Learn about Demonstration Usage for S- R
Electronics(Flip flops) R-1:1 AV-1 combinational circuits. combinational and with simulator Flip Flop would
R-2:1 VL-1 ii. Flip Flop and its Flip Flop be a simple
R-3:1 types. ii. Understand the security system.
R-4:1 design and Usages of R is hooked up
R-5:1 Flip Flop to a key to arm
it and a trigger
or switch on a
door or window
is hooked up to
S to set it off.
Week 1 Lecture 3 Basics Of Digital T-1:2 AV-1 Introduction to i. Understand circuits Demonstration Wireless remote
Electronics(Decoder and VL-1 integrated circuits and design by with simulator. control system :
Encoder) Decoders and Encoder interconnection of When using a
various gates. wireless remote
ii. Formation of control system it
larger decoders by is desirable to
combining two or have a way of
more small decoders filtering out or
ignoring those
unwanted
signals to
prevent false
data from being
received.
A simple way to
accomplish this
is to use an
encoder IC at
the transmitter
and a decoder
IC at the
receiver. The
encoder
generates serial
codes that are
automatically
sent three times
and must be
received at least
twice before
data is accepted
as valid by the
decoder circuit.
Week 2 Lecture 4 Basics Of Digital AV-1 Introduction to i. Understand circuits Demonstration Wireless remote
Electronics(integrated VL-1 integrated circuits and design by with simulator. control system :
circuits) Decoders interconnection of When using a
various gates. wireless remote
ii. Formation of control system it
larger decoders by is desirable to
combining two or have a way of
more small decoders filtering out or
ignoring those
unwanted
signals to
prevent false
data from being
received.
A simple way to
accomplish this
is to use an
encoder IC at
the transmitter
and a decoder
IC at the
receiver. The
encoder
generates serial
codes that are
automatically
sent three times
and must be
received at least
twice before
data is accepted
as valid by the
decoder circuit.
Basics Of Digital T-1:2 AV-1 Lecture orientation Design of integrated Demonstration Traffic Light
Electronics(Multiplexers and VL-2 about multiplexer and circuit package by with simulator. Control with
De multiplexers) demultiplexer two or more decoders and
multiplexer. multiplexers are
used for sharing
of a data
transmission
line by a number
of signals,
selection control
on a home
stereo unit.
Week 2 Lecture 5 Register Transfer and Micro T-1:4 Discussion on Bus and i. Understand transfer Discussion with Digital
Operations(Bus and Memory Memory Transfers, Bus between Processor image. computer.
Transfer) selection and three - registers through
state bus buffers buses
ii. Understand
transfer between
Processor
register and memory
through buses
Register Transfer and Micro T-1:4 Discussion on Bus and i. Understand transfer Discussion with Digital
Operations(Register transfer Memory Transfers, Bus between Processor image. computer.
and register transfer selection and three - registers through
language) state bus buffers buses
ii. Understand
transfer between
Processor
register and memory
through buses
Week 2 Lecture 5 Basics Of Digital AV-1 Introduction to i. Understand circuits Demonstration Wireless remote
Electronics(integrated VL-1 integrated circuits and design by with simulator. control system :
circuits) Decoders interconnection of When using a
various gates. wireless remote
ii. Formation of control system it
larger decoders by is desirable to
combining two or have a way of
more small decoders filtering out or
ignoring those
unwanted
signals to
prevent false
data from being
received.
A simple way to
accomplish this
is to use an
encoder IC at
the transmitter
and a decoder
IC at the
receiver. The
encoder
generates serial
codes that are
automatically
sent three times
and must be
received at least
twice before
data is accepted
as valid by the
decoder circuit.
Lecture 6 Register Transfer and Micro T-1:4 RW-4 Operations are Learn about the 16 Peer learning
Operations(Logic Micro performed on the binary Logical micro-
Operations) data stored in the operations.
register
Week 3 Lecture 7 Register Transfer and Micro T-1:4 AV-1 Serial data transfer of i. Understand about Peer learning
Operations(Shift Micro data and arithmetic logic data transfer.
Operations) unit ii. Understand about
data processing
operations.
iii. Understand the
design of arithmetic
logic unit
Week 3 Lecture 7 Basics Of Digital AV-1 Discussion on register i. Understand the data Demonstration Buffer storage
Electronics(registers) VL-2 and register with parallel processing tasks with images e.g. video
Load performed by memory for
registers. graphics cards
ii. Understand the
working of clock
pulse of registers in
the system.
iii. Understand of
Load input : The load
input in the register
determines the action
taken with each clock
pulse.
Control Unit(Micro T-1:7 OR-1 Discussion on hardwired Learn about how to Demonstration
programmed controls.) AV-1 control Unit design a control Unit with images
Lecture 18 MCQ,Test1
Week 7 Lecture 19 Central Processing Unit AV-1 CISC variable length Learn the CISC and Peer learning Earlier when
(Manipulation) instructions in RISC Architecture most computer
multiple cycles programming
was done in
assembly
language,
instruction set
architecture was
considered the
most important
part of computer
architecture,
because it
determined how
difficult it was
to obtain
optimal
performance
from the system.
Week 7 Lecture 19 Central Processing Unit AV-1 CISC variable length Learn the CISC and Peer learning Earlier when
(Reduced instruction set instructions in RISC Architecture most computer
computer) multiple cycles programming
was done in
assembly
language,
instruction set
architecture was
considered the
most important
part of computer
architecture,
because it
determined how
difficult it was
to obtain
optimal
performance
from the system.
Central Processing Unit AV-1 CISC variable length Learn the CISC and Peer learning Earlier when
(Complex instruction set instructions in RISC Architecture most computer
computer) multiple cycles programming
was done in
assembly
language,
instruction set
architecture was
considered the
most important
part of computer
architecture,
because it
determined how
difficult it was
to obtain
optimal
performance
from the system.
SPILL OVER
Week 7 Lecture 20 Spill Over
Lecture 21 Spill Over
MID-TERM
Week 8 Lecture 22 Control Unit(control Discussion on hardwired Learn about how to Demonstration
memory) control Unit design a control Unit with images
Week 8 Lecture 22 Control Unit(address Discussion on hardwired Learn about how to Demonstration Traffic manager
sequencing) control Unit design a control Unit with images
Week 10 Lecture 28 Input-Output Organization T-1:11 AV-1 Introduction to input Understand the the Discussion with
(Peripheral devices) output mode of images
subsystem of a communication
computer between the central
system and out side
environment
Input-Output Organization T-1:11 AV-1 Introduction to input Understand the the Discussion with
(Input output interface) output mode of images
subsystem of a communication
computer between the central
system and out side
environment
Input-Output Organization AV-1 Introduction to input- Understand the the Discussion with
(Peripheral Devices) output subsystem of a mode of images
computer communication
between the central
system and out side
environment
Input-Output Organization AV-1 Introduction to input- Understand the the Discussion with
(Input Output Interface) output subsystem of a mode of images
computer communication
between the central
system and out side
environment
Lecture 29 Input-Output Organization T-1:11 RW-3 Discussion on Learn about source Discussion with
(Priority interrupt) AV-1 asynchronous Data and destination images
transfer between initiated data transfer
independent units
Input-Output Organization T-1:11 RW-3 Discussion on Learn about source Discussion with
(Data transfer schemes) AV-1 asynchronous Data and destination images
transfer between initiated data transfer
independent units
Lecture 30 MCQ,Test2
Week 11 Lecture 31 Input-Output Organization Discussion on types Learn about types of Discussion Data Sharing
(modes of data transfer) of data transfer schemes data transfer Methods
techniques
means how to
transfer
data from memory to
processor and input
output devices
Input-Output Organization T-1:11 AV-1 Discussion on DMA i. Understand the Demonstration and
(Program control and used when multiple concept of Direct discussion
interrupts) bytes are to be memory
transferred between access to memory for
memory and IO devices data transfers
ii. Learn how DMA
used when multiple
bytes are
to be transferred
between memory and
IO
devices
iii. Learn DMA Data
transfer mechanism
between
I/O devices and
system memory with
the least
processor
intervention using
DMAC
Input-Output Organization T-1:11 AV-1 Discussion on DMA i. Understand the Demonstration and
(Direct memory access used when multiple concept of Direct discussion
transfer) bytes are to be memory
transferred between access to memory for
memory and IO devices data transfers
ii. Learn how DMA
used when multiple
bytes are
to be transferred
between memory and
IO
devices
iii. Learn DMA Data
transfer mechanism
between
I/O devices and
system memory with
the least
processor
intervention using
DMAC
Week 11 Lecture 31 Input-Output Organization T-1:11 AV-1 Discussion on DMA i. Understand the Demonstration and
(Input/Output processor.) used when multiple concept of Direct discussion
bytes are to be memory
transferred between access to memory for
memory and IO devices data transfers
ii. Learn how DMA
used when multiple
bytes are
to be transferred
between memory and
IO
devices
iii. Learn DMA Data
transfer mechanism
between
I/O devices and
system memory with
the least
processor
intervention using
DMAC
Lecture 32 Memory Unit(High speed T-1:12 Describing about i. Learn three levels Discussion with
memories) Argument register of hierarchy of cache, image.
Match RAM/ROM and
Logic etc secondary storage
ii.Learn about content
addressable memory
Memory Unit(Cache T-1:12 Describing about i. Learn three levels Discussion with
memory) Argument register of hierarchy of cache, image.
Match RAM/ROM and
Logic etc secondary storage
ii.Learn about content
addressable memory
Memory Unit(Associative T-1:12 Describing about i. Learn three levels Discussion with
memory) Argument register of hierarchy of cache, image.
Match RAM/ROM and
Logic etc secondary storage
ii.Learn about content
addressable memory
Memory Unit(Memory T-1:12 Describing about i. Learn three levels Discussion with
hierarchy) Argument register of hierarchy of cache, image.
Match RAM/ROM and
Logic etc secondary storage
ii.Learn about content
addressable memory
Week 11 Lecture 33 Memory Unit(Processor Vs T-1:12 Argument register Argument register Discussion with Contentaddressa
Memory speed) Match Match image. ble
Logic etc Logic etc memory is often
used in
computer
networking
devices. For
example, when a
network switch
receives a data
frame from one
of its ports, it
updates an
internal table
with the frame's
source MAC
address and the
port it was
received on. It
then looks up
the destination
MAC address in
the table to
determine what
port the frame
needs to be
forwarded to,
and sends it out
on that port. The
MAC address
table is usually
implemented
with a binary
CAM so the
destination port
can be found
very quickly,
reducing the
switch's latency.
Week 11 Lecture 33 Memory Unit(Inter leave) T-1:12 Argument register Argument register Discussion with Contentaddressa
Match Match image. ble
Logic etc Logic etc memory is often
used in
computer
networking
devices. For
example, when a
network switch
receives a data
frame from one
of its ports, it
updates an
internal table
with the frame's
source MAC
address and the
port it was
received on. It
then looks up
the destination
MAC address in
the table to
determine what
port the frame
needs to be
forwarded to,
and sends it out
on that port. The
MAC address
table is usually
implemented
with a binary
CAM so the
destination port
can be found
very quickly,
reducing the
switch's latency.
Memory Unit(main Discussion on Memory Learn three levels of Discussion USB Flash
memory) and its types hierarchy of cache, Drives
RAM/ROM and
secondary storage
Week 12 Lecture 34 Memory Unit(auxiliary Describing about Learn about content Discussion with Contentaddressa
memory) Argument register addressable memory image. ble
Match memory is often
Logic etc used in
computer
networking
devices. For
example, when a
network switch
receives a data
frame from one
of its ports, it
updates an
internal table
with the frame's
source MAC
address and the
port it was
received on. It
then looks up
the destination
MAC address in
the table to
determine what
port the frame
needs to be
forwarded to,
and sends it out
on that port. The
MAC address
table is usually
implemented
with a binary
CAM so the
destination port
can be found
very quickly,
reducing the
switch's latency.
Memory Unit(Virtual T-1:12 Discussion on page Learn about how to Discussion with
memory) table ,memory mapping manage memory images.
table space and address
space
Memory Unit(Memory T-1:12 Discussion on page Learn about how to Discussion with
management.) table ,memory mapping manage memory images.
table space and address
space
Lecture 35 Introduction to Parallel T-1:9 AV-1 Simultaneous data Learn about Discussion
Processing(parallel processing task to processor with
processing) increase the speed of multiple functional
computer system. units.
Week 12 Lecture 35 Introduction to Parallel T-1:9 AV-1 Simultaneous data Learn about Discussion
Processing(Pipelining) processing task to processor with
increase the speed of multiple functional
computer system. units.
Memory Unit(Cache Discussion on types of Learn about basic Peer learning
Memory) mapping techniques in concepts of cache
cache memory memory
Lecture 36 MCQ,Test3
Week 13 Lecture 37 Introduction to Parallel T-1:13 Discussion on i. Learn about how to Discussion
Processing(Inter processor arbitration logic and transfer information
arbitration) mutual exclusion between
multiprocessor
components.
ii. Learn about
synchronization
Introduction to Parallel T-1:13 Discussion on i. Learn about how to Discussion
Processing(Inter processor arbitration logic and transfer information
communication) mutual exclusion between
multiprocessor
components.
ii. Learn about
synchronization
Introduction to Parallel T-1:13 Discussion on i. Learn about how to Discussion
Processing arbitration logic and transfer information
(Synchronization.) mutual exclusion between
multiprocessor
components.
ii. Learn about
synchronization
Lecture 38 Introduction to Parallel T-1:13 AV-1 Discussion on system To understand Discussion with
Processing(Interconnection bus interconnect multiprocessor images
structures) network system
interconnects using
system and
time shared buses
Introduction to Parallel T-1:13 AV-1 Discussion on system To understand Discussion with
Processing(Characteristics bus interconnect multiprocessor images
of multiprocessors) network system
interconnects using
system and
time shared buses
Lecture 39 Introduction to Parallel AV-1 Discussion on system To understand Discussion with
Processing(Interconnection bus interconnect multiprocessor images
Structures) network system
interconnects using
system and
time shared buses
Week 13 Lecture 39 Latest technology and trends RW-10 Intel has said the first Understand the new Demo with Images
in computer architecture RW-11 solid-state drives to use technology for and Presentation
(multi-cores processor.) its new 3D Xpoint memory and storage
memory technology will devices
ship next year, under a
new brand called Intel
Optane.
SPILL OVER
Week 14 Lecture 41 Spill Over
Lecture 42 Spill Over
Week 15 Lecture 43 Spill Over
Lecture 44 Spill Over
Lecture 45 Spill Over
Total :- 10 20
Test2 To check the subject Will be covering syllabus from lecture 16 to lecture 27. All Individual On the basis of 9 / 10
understanding and questions should be of 5 marks each or in multiples of 5. answer attempted
learning ability of by student
the students.
MCQ1 To ensure Will be covering syllabus from lecture 1 to lecture 33. Individual No. of answers 10 / 12
understanding of the correctly marked by
concepts and check student (25%
the student's negative marking
progress for incorrect
answers)
Plan for Tutorial: (Please do not use these time slots for syllabus coverage)
Tutorial No. Lecture Topic Type of pedagogical tool(s) planned
(case analysis,problem solving test,role play,business game etc)
Tutorial1 Problem Solving on Encoders and Decoders, Logic Gates and Flip- Problem Solving
Flops
Tutorial2 Problems based on Bus and Memory transfer and Arithmetic and Problem Solving
shift Micro operations
Tutorial3 Problem Solving on Register transfer and Register transfer Problem Solving
language and Instruction Codes
Tutorial4 Problem Solving on Control Timing Signals and Instruction Cycle Problem Solving
Tutorial5 Problem Solving on Memory Reference Instructions and Input Problem Solving
Output interrupt
Tutorial6 Problem Solving on program and Micro Program Control, Problem Solving
Tutorial7 Problem Solving on Data Transfer, Manipulation and Addressing Problem Solving
Modes
After Mid-Term
Tutorial8 Problem Solving on Addition, Subtraction Algorithm, Multiplication Problem Solving
and Division Algorithm
Tutorial9 Problem Solving on Fixed, Floating Point Arithmetic and Priority Problem Solving
Interrupt
Tutorial10 Problem Solving on Data Transfer Schemes, Program Control and Problem Solving
Interrupts
Tutorial11 Problem Solving on Direct Memory Access and Memory Hierarchy Problem Solving
Tutorial12 Problem Solving on Cache Memory, Associative Memory and Problem Solving
Virtual Memory
Tutorial13 Problem Solving on Memory Management and Pipelining Problem Solving
Tutorial14 Problem Solving on Interconnection Structure, Inter processor Problem Solving
Arbitration and Synchronization