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Cse 2105 Set 1
Cse 2105 Set 1
1 a) For the timing diagram in Figure, synthesize the function f (x1, x2, x3) in the simplest sum- 5
of-products form.
2 a) Use K mapping to design a logic circuit that has three inputs, A, B, and C, and whose 8
output will be HIGH only when a majority of the inputs are HIGH.
b) What is a don’t-care condition? 2
3 a) A full adder can be implemented in many different ways. Figure shows how one may be 6
constructed from two half adders. Construct a function table for this arrangement, and
verify that it operates as a FA.
b) Show the logic levels at each input and output of the following figure, when EC 16 is added 5
to 4316.
4 a) 7
In the circuit of Figure, inputs A, B, and C are all initially LOW. Output Y is supposed to go
HIGH only when A, B, and C go HIGH in a certain sequence. Determine the sequence that
will make Y go HIGH.
b) Which register function (load or shift) will be performed on the next clock if in = 0 and out 5
= 1? What data value will be input when clocked?
7 a) What will be the logic output of a TTL NAND gate that has all of its inputs unconnected? 3
b) What are two acceptable ways to handle unused inputs to an AND gate? 4
c) What is power-supply decoupling? Why is it used? 3