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Digital ASIC IC Design GP Roadmap
Digital ASIC IC Design GP Roadmap
ROADMAP
Required Knowledge
- Principles [Logic, MP, DSP, Digital Electronics, VLSI]
- HDL [Verilog]
- ASIC Design Flow
- RTL
- RTL Verification (Testbench, etc.)
- Synthesis [Goals, Constraints, Tools, Static Timing Analysis (STA)]
- Place and Route (PnR)
- Tools
- Scripting [TCL or Perl] (A Plus)
Schedule Overview
Approx. Time: 1.5 Months (6 Weeks) to finish two parallel sub tracks.
• Practical:
• Digital ASIC Design with Verilog- Dr. Paul Franzon
• Digital VLSI Design (RTL to GDS) - Dr. Adam Teman
• Introduction to Digital ASIC Design - VLSI School [Quizzes&Assignments]
• Theoretical Basis:
• FPGA Prototyping with Verilog Examples
• Principles of VLSI RTL Design: A Practical Guide
• The Art of Hardware Architecture
• Constraining Designs for Synthesis and Timing Analysis
• Digital IC Design Courses - Dr. Hesham Omran
Sources
• Important before Starting:
• Digital Design Career Overview
https://gofile.io/d/OFFpE8
• ASIC vs FPGA Comparison
http://www.signoffsemi.com/asic-vs-fpga//
• Digital ASIC IC Design Flow
https://prezi.com/view/fjnKPHNDRw9jC5Bihzeh/
• ModelSim Tutorials [ModelSim PE Student Edition]
https://www.mentor.com/company/higher_ed/modelsim-student-edition
https://www.youtube.com/watch?v=9mpRF6bAY1g
https://www.youtube.com/watch?v=t4LcbG5tnHY&t=307s
• Videos Playlists:
• Digital ASIC Design with Verilog - Dr. Paul Franzon
https://www.youtube.com/playlist?list=PLfGJEQLQIDBN0VsXQ68_FEYyqcym8CTDN
• Digital VLSI Design (RTL to GDS) - Dr. Adam Teman
http://www.eng.biu.ac.il/temanad/digital-vlsi-design/
https://www.youtube.com/playlist?list=PLZU5hLL_713x0_AV_rVbay0pWmED7992G
• Introduction to Digital ASIC Design - VLSI School
https://vlsi-school.thinkific.com/courses/101
• Digital IC Design Courses - Dr. Hesham Omran
https://www.youtube.com/playlist?list=PLMSBalys69yzvAKErDt7tT7O-iIKPlOCP
https://www.youtube.com/playlist?list=PLMSBalys69yxoIjeZ2Q3fxs69cGCU14B1
https://www.youtube.com/playlist?list=PLMSBalys69yw1tSoF42QW9jbbC0-UeCAy
• Textbooks:
• FPGA Prototyping by Verilog Examples
https://drive.google.com/file/d/1MplwouwD9kBATaWpdpEskm0p_bOR84PJ/view?usp=sharing
• Principles of VLSI RTL Design: A Practical Guide
https://drive.google.com/file/d/1WZL6uToBzi5Fex-g_OQIMvkYHOxCyZxM/view?usp=sharing
• The Art of Hardware
https://drive.google.com/file/d/16Y2_6JcJX_qwsHLnZz-p3Ut68k0PSU7k/view?usp=sharing
• Constraining Designs for Synthesis and Timing Analysis
https://drive.google.com/file/d/1GcLNzbxiZwvyCZKdSJdeMwso8G8_p3Ia/view?usp=sharing
• Practicing on Projects:
• FPGA 4 Students - Verilog Projects
https://www.fpga4student.com/p/verilog-project.html?m=1
• ASIC World - Verilog Projects
http://www.asic-world.com/verilog/index.html
Schedule (Week by Week)
• Week 1
Day Tasks
6
• Week 3
Day Tasks