PicoSoC: How we created a RISC-V based ASIC

processor using a full open-source foundry targeted

RTL-to-GDS flow, and how you can, too!

Tim Edwards
Mohamed Kassem
efabless Corporation
San Jose, CA

Clifford Wolf 7th RISC-V Workshop

Symbiotic EDA
November 2017
Vienna, Austria
 PicoChip: A full-chip ASIC implementation of the PicoRV32 "PicoSoC"

RISC-V CPU source: Clifford Wolf’s "PicoRV32" (available from github, efabless IP catalog)
• CPU core: PicoRV32 (RISC-V)
• Reference design: PicoSoC
• Reference implementation: hx8kdemo (iCE40-HX8K Lattice Semi FPGA)
• Firmware/Software: gcc (riscv32 cross-compiler to .hex file target)

Open Source Synthesis Toolchain: qflow (opencircuitdesign.com)

• Synthesis: yosys / ABC
• Static Timing Analysis: vesta
• Placement: graywolf
• Routing: qrouter
• Layout: magic
• DRC: magic
• LVS: netgen
• Verilog simulation: iverilog Design Platforms
• Cosimulation: ngspice and iverilog • efabless.com "Open Galaxy" server (development version)
• Mask generation: magic • efabless.com "CloudV" cloud-based synthesis and simulation environment

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 PicoChip: A full-chip ASIC implementation of the PicoRV32 "PicoSoC"

PicoSoC example components:

UART (“simpleuart”)

Demo testbench uses the UART for ASCII input/output

SPI memory controller (“spimemio")

Implements (Q)SPI bus master for external SPI flash memory

Scratchpad SRAM memory:

Demo uses 256 word scratchpad External components:

SPI flash memory (up to four channels QSPI)

Pre-loaded ("$readmemh" in simulation) with firmware from (gcc-) compiled .hex file

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 Comparison of FPGA and full-chip ASIC implementations

For ASIC, add padframe and Power-on-reset (POR). SRAM is generated by memory compiler from the foundry.

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 Software and Hardware Verification Flows

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 Software - Hardware Co-Simulation
Picochip verilog testbench simulation Exercising GPIO

Open Source toolchain

Firmware: gcc
Simulation: iverilog
Waveforms: gtkwave

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 Software - Digital - Analog Co-Simulation

• ngspice analog and xspice

waveforms (pad I/O). 

•Boot sequence followed by

GPIO bit toggle.

• Verilog (iverilog)
testbench stimulus digital
signals.

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 PicoChip: Synthesized PicoSoC, 1k x 32 SRAM, and padframe

PicoSoC core 1mm x 1mm

(19,051 logic standard Analog

cells, 15,022 wires)

Core limited with 32 GPIO

pins, UART, IRQ, clock, and
flash QSPI

Fabrication process: 0.18 μm

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 How you can, too: Design on efabless Platform

efabless platform components:

1.IP catalog with community and

vendor IP for "try before buy" and
project cloning.

2. Toolbox for access to design tools

on cloudV and Open Galaxy

3. Knowledge Base with tutorials,

webinars, and other documents to
help the designer.

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 Verilog Code from IP Catalog

1. Each IP catalog entry has a page

giving a summary description, specs,
features, and a way to obtain the IP
directly or for use in a design.

2. IP catalog entries may be open

source (free to copy, modify, and use,
or closed source, with licensing options
available to the designer.

3. Catalog entries are "Soft IP" (verilog)

or "Hard IP" (schematic or layout),
with other types under consideration.

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 efabless’ CloudV-based
Design Environment

1. "Soft IP" from the catalog can be

viewed in cloudV.

2. The cloudV tool can simulate

verilog source and testbenches,
and synthesize to a foundry
process target digital library.

3. Synthesized netlists can be

exported to the efabless Open
Includes synthesis
Galaxy platform.
frontend and
simulation

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 efabless’ Open Galaxy Design Environment
1. Hard IP" from the IP catalog can
be viewed in Open Galaxy as an
imported project or can be used
in a new or existing project.

2. Verification through mixed-

signal cosimulation

3. Synthesized netlists from

cloudV can be imported

as a project and taken through
backend

synthesis to a completed layout.

4. backend synthesis

5. Designs can be verified through

DRC, LVS, STA, and mixed-mode
simulation.

6. Custom ASIC layout with

foundry memory and I/O pads
Includes synthesis backend, layout, mixed-signal
(abstracted)
functional characterization, DRC, and LVS.
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 PicoSoC: How we created a RISC-V based ASIC processor using a full open-
source foundry targeted RTL-to-GDS flow, and how you can, too!

ASIC SoC design flow:

1.Get verilog source IP from catalog or other source such as github
2.Create digital SoC core and testbench and verify through simulation on CloudV
3.Synthesize digital SoC core on CloudV
4.Place and route digital SoC core on Open Galaxy
5.Create ASIC layout on Open Galaxy
6.Verify through functional mixed-mode cosimulation, DRC, and LVS on Open Galaxy
7.Fabricate on foundry target through efabless

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 Thank You!

To start your design online visit

efabless.com

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