Half Adder:

Gate Level Verilog Code for Half Adder:

module HalfAdder(a,b,s,c);
input a,b;
output s,c;
wire s,c;
xor (s,a,b);
and (c,a,b);
endmodule

Dataflow level Verilog Code for Half Adder:

module fulladder
input a,b;
output s,c;
assign s=a^b;
assign c=a&b;
endmodule

Test Bench Verilog Code:

`timescale 1ns / 1ns
module ha_test();
reg a,b;
wire s,c;
HalfAdder h1(.a(a),.b(b),.s(s),.c(c));
initial
begin
a=1'b0; b=1'b0;
#100;
a=1'b0; b=1'b1;
#100;
a=1'b1; b=1'b0;
#100;
a=1'b1; b=1'b1;
#100;
end
endmodule

Simulation Wave form:

Printed Output from Transcript window:
# 0The value of a=0 b=0 s=0 c=0

# 100The value of a=0 b=1 s=1 c=0

# 200The value of a=1 b=0 s=1 c=0

# 300The value of a=1 b=1 s=0 c=1

Full adder:
Gate Level Verilog Code for Full adder:

module halfadder(s,c,a,b);

input a,b;

output s,c;

xor(s,a,b);

and(c,a,b);

endmodule

module Fulladder(S,Cout,A,B,Cin);

input A,B,Cin;

output S,Cout;

wire w1,w2,w3;

halfadder h1(w1,w2,A,B);
halfadder h2(S,w3,w1,Cin);

or(Cout,w2,w3);

endmodule

Dataflow level Verilog Code for Full adder:

module fulladder(a,b,cin,s,cout);
input a,b,cin;
outut s,cout;
assign s=a^b^cin;
assign cout(a & b)| cin&(a&b);
endmodule

Test Bench Verilog Code:

`timescale 1ns / 1ns
module fa_test();
reg A,B,Cin;
wire S,Cout;
Fulladder h1(.A(A),.B(B),.Cin(Cin),.S(S),.Cout(Cout));
initial
begin
$monitor($time, "The value of A=%b B=%b Cin=%b S=%b Cout=%b",A,B,Cin,S,Cout);
A=1'b0; B=1'b0; Cin=1'b0;
#20;
A=1'b0; B=1'b0; Cin=1'b1;
#20;
A=1'b0; B=1'b1; Cin=1'b0;
#20;
A=1'b0; B=1'b1; Cin=1'b1;
#20;
A=1'b1; B=1'b0; Cin=1'b0;
#20;
A=1'b1; B=1'b0; Cin=1'b1;
#20;
A=1'b1; B=1'b1; Cin=1'b0;
#20;
A=1'b1; B=1'b1; Cin=1'b1;
#20;
end
endmodule

Simulation Wave form:

Printed Output from Transcript window

# 0The value of A=0 B=0 Cin=0 S=0 Cout=0

# 20The value of A=0 B=0 Cin=1 S=1 Cout=0

# 40The value of A=0 B=1 Cin=0 S=1 Cout=0

# 60The value of A=0 B=1 Cin=1 S=0 Cout=1

# 80The value of A=1 B=0 Cin=0 S=1 Cout=0

# 100The value of A=1 B=0 Cin=1 S=0 Cout=1

# 120The value of A=1 B=1 Cin=0 S=0 Cout=1

# 140The value of A=1 B=1 Cin=1 S=1 Cout=1

Gate Level Verilog Code for Half Substractor:

module HalfSub(a,b,d,br);
input a,b;
output d,br;
wire d,br;
xor (d,a,b);
not (x,a);
and (br,x,b);
endmodule
Dataflow level Verilog Code for Half Subtractor
module HalfSubstractor(a,b,d,br);
input a,b;
output d,br;
xor(d,a,b);
assign br=(~a&b);
endmodule

Test Bench Verilog Code:

`timescale 1ns / 1ns
module hs_test();
reg a,b;
wire d,br;
HalfSub h1(.a(a),.b(b),.d(d),.br(br));
initial
begin
$monitor($time, "The value of a=%b b=%b d=%b br=%b",a,b,d,br);
a=1'b0; b=1'b0;
#100;
a=1'b0; b=1'b1;
#100;
a=1'b1; b=1'b0;
#100;
a=1'b1; b=1'b1;
#100;
end
endmodule
Simulation Wave form:

Printed Output from Transcript window

# 0The value of a=0 b=0 d=0 br=0

# 100The value of a=0 b=1 d=1 br=1

# 200The value of a=1 b=0 d=1 br=0

# 300The value of a=1 b=1 d=0 br=0

Gate Level Verilog Code for full Subtractor:

module full_subtractor(A,B,C,diff,borr);
input A,B,C;
output diff,borr;
wire x,n2,z,n1;
xor s1(x,A,B);
not s3(n2,x);
not s4(n1,C);
and s5(y,n1,B);
xor s2(diff,A,x);
and s6(z,n2,A);
or (borr,y,z);
endmodule
Dataflow level Verilog Code for full Subtractor
module FullSubstractor(A,B,C, diff,borr);
input A,B,C;
output  diff,borr;
assign difference=(A^B^C);
assign bout=(~A&B)|(~A&C)|(B&C);
endmodule

Test Bench Verilog Code:

`timescale 1ns / 1ns
module fs_test();
reg A,B,C;
wire diff,borr;
full_subtractor h1(.A(A),.B(B),.C(C),.diff(diff),.borr(borr));
initial
begin
$monitor($time, "The value of A=%b B=%b borr=%b diff=%b borr=%b",A,B,C,diff,borr);
A=1'b0; B=1'b0; C=1'b0;
#20;
A=1'b0; B=1'b0; C=1'b1;
#20;
A=1'b0; B=1'b1; C=1'b0;
#20;
A=1'b0; B=1'b1; C=1'b1;
#20;
A=1'b1; B=1'b0; C=1'b0;
#20;
A=1'b1; B=1'b0; C=1'b1;
#20;
A=1'b1; B=1'b1; C=1'b0;
#20;
A=1'b1; B=1'b1; C=1'b1;
#20;
end
endmodule
Simulation Wave form:

Printed Output from Transcript window

0The value of A=0 B=0 borr=0 diff=0 borr=0

# 20The value of A=0 B=0 borr=1 diff=0 borr=0

# 40The value of A=0 B=1 borr=0 diff=1 borr=1

# 60The value of A=0 B=1 borr=1 diff=1 borr=0

# 80The value of A=1 B=0 borr=0 diff=0 borr=0

# 100The value of A=1 B=0 borr=1 diff=0 borr=0

# 120The value of A=1 B=1 borr=0 diff=1 borr=1

# 140The value of A=1 B=1 borr=1 diff=1 borr=1

Gate Level Verilog Code for MUX21:

module mux_21(Y, D0, D1, S);

output Y;
input D0, D1, S;
wire a1, b1, Sbar;
and (a1, D1, S), (b1, D0, Sbar);
not (Sbar, S);
or (Y, a1, b1);

endmodule
Dataflow level Verilog Code for MU21:
module m21(D0, D1, S, Y);
output Y;
input D0, D1, S;
assign Y=(S)?D1:D0;
endmodule
Test Bench Verilog Code:
`timescale 1ns / 1ns
module mux_test();
reg D0,D1,S;
wire Y;
mux_21 h1(.D0(D0),.D1(D1),.S(S),.Y(Y));
initial
begin
$monitor($time, "The value of D0=%b D1=%b S=%b Y=%b",D0,D1,S,Y);
D0=1'b1; D1=1'b0; S=1'b0;
#100;
D0=1'b0; D1=1'b1; S=1'b0;
#100;
D0=1'b0; D1=1'b0; S=1'b0;
#100;
D0=1'b0; D1=1'b1; S=1'b0;
#100;
D0=1'b1; D1=1'b0; S=1'b0;
#100;
D0=1'b1; D1=1'b1; S=1'b0;
#100;
end
endmodule
Simulation Wave form:

Printed Output from Transcript window

0The value of D0=1 D1=0 S=0 Y=1

# 100The value of D0=0 D1=1 S=0 Y=0

# 200The value of D0=0 D1=0 S=0 Y=0

# 300The value of D0=0 D1=1 S=0 Y=0

# 400The value of D0=1 D1=0 S=0 Y=1

# 500The value of D0=1 D1=1 S=0 Y=1

Gate Level Verilog Code for Half Adder:

module mux41(a,b,c,d,s0,s1,y);
input a,b,c,d,s0,s1;
output y;
wire i1,i2,i3,i4,i5,i6;
not (i1,s0);
not (i2,s1);
and (i3,i1,i2,a);
and (i4,i1,s1,b);
and (i5,s0,i2,c);
and (i6,s0,s1,d);
or (y,i3,i4,i5,i6);
endmodule

Dataflow level Verilog Code for Half Subtractor

module mux41 (a,b,c,d,s0,s1,y);
input a,b,c,d,s0,s1;
output y;
wire i1,i2,i3,i4,i5,i6;
assign i1=~s0;
assign i2=~s1;
assign i3=i1&i2&a;
assign i4=i1&s1&b;
assign i5=s0&i2&c;
assign i6=s0&s1&d;
assign y=i3|i4|i5|i6;
endmodule

Test Bench Verilog Code:

`timescale 1ns / 1ns
module mux41_test();
reg a,b,c,d,s0,s1;
wire y;
mux41 h1(.a(a),.b(b),.c(c),.d(d),.s0(s0),.s1(s1),.y(y));
initial
begin
$monitor($time, "The value of a=%b b=%b c=%b d=%b,s0=%b, s1=%b, y=
%b",a,b,c,d,s0,s1,y);
a=1'b1; b=1'b0; c=1'b0; d=1'b0; s0=1'b0; s1=1'b0;
#100;
a=1'b0; b=1'b1; c=1'b0; d=1'b0; s0=1'b0; s1=1'b1;
#100;
a=1'b0; b=1'b0; c=1'b1; d=1'b0; s0=1'b1; s1=1'b0;
#100;
a=1'b1; b=1'b0; c=1'b0; d=1'b0; s0=1'b1; s1=1'b1;
#100;

end
endmodule
Simulation Wave form:

Printed Output from Transcript window

# 0The value of a=1 b=0 c=0 d=0,s0=0, s1=0, y=1

# 100The value of a=0 b=1 c=0 d=0,s0=0, s1=1, y=1

# 200The value of a=0 b=0 c=1 d=0,s0=1, s1=0, y=1

# 300The value of a=1 b=0 c=0 d=0,s0=1, s1=1, y=0

Gate Level Verilog Code for Half Adder:

module DEMUX_1_to_2(s,d,y1,y0);
input s,d;
output y0,y1;
not(sn,s);
and(y0,sn,d);
and(y1,s,d);
endmodule
Dataflow level Verilog Code for Half Subtractor
module DEMUX_1_to_2(s,d,y1,y0);
assign sn = ~ s;
assign y0 = sn & d;
assign y1 = s & d;
endmodule

Test Bench Verilog Code:

`timescale 1ns / 1ns
module demux12_test();
reg s,d;
wire y0,y1;
DEMUX_1_to_2 h1(.s(s),.d(d),.y0(y0),.y1(y1));
initial
begin
$monitor($time, "The value of s=%b d=%b y0=%b y1=%b",s,d,y0,y1);
s=1'b0; d=1'b1;
#100;
s=1'b1; d=1'b1;
#100;
s=1'b0; d=1'b0;
#100;

end
endmodule
Simulation Wave form:

Printed Output from Transcript window

0The value of s=0 d=1 y0=1 y1=0

# 100The value of s=1 d=1 y0=0 y1=1

# 200The value of s=0 d=0 y0=0 y1=0

Gate Level Verilog Code for Half Adder:

module demux_1_to_4(d,s0,s1,y0,y1,y2,y3);
input s1,s0,d;
output y0,y1,y2,y3;
not(s1n,s1),(s0n,s0);
and(y0,d,s0n,s1n);
and(y1,d,s0,s1n);
and(y2,d,s0n,s1);
and(y3,d,s0,s1);
endmodule
Dataflow level Verilog Code for Half Subtractor
module DEMUX_1_to_4(s1,s0,d,y3,y2,y1,y0);
assign sn0 = ~ s0;
assign sn1 = ~ s1;
assign y0 = sn0 & sn1 & d;
assign y1 = sn0 & s1 & d;
assign y2 = s0 & sn1 & d;
assign y3 = s0 & s1 & d;
endmodule

Test Bench Verilog Code:

`timescale 1ns / 1ns
module demux12_test();
reg s0,s1,d;
wire y0,y1,y2,y3;
demux_1_to_4 h1(.s0(s0),.s1(s1),.d(d),.y0(y0),.y1(y1),.y2(y2),.y3(y3));
initial
begin
$monitor($time, "The value of s0=%b s1=%b d=%b y0=%b y1=%b",s0,s1,d,y0,y1);
s0=1'b0; s1=1'b0; d=1'b1;
#100;
s0=1'b0; s1=1'b1; d=1'b1;
#100;
s0=1'b1; s1=1'b0; d=1'b1;
#100;
s0=1'b1; s1=1'b1; d=1'b1;
#100;

end
endmodule

Simulation Wave form:

Printed Output from Transcript window

0The value of s0=0 s1=0 d=1 y0=1 y1=0

# 100The value of s0=0 s1=1 d=1 y0=0 y1=0

# 200The value of s0=1 s1=0 d=1 y0=0 y1=1

# 300The value of s0=1 s1=1 d=1 y0=0 y1=0

Gate Level Verilog Code for Half Adder:

module Encoder(d0,d1,d2,d3,d4,d5,d6,d7,a,b,c);
input d0,d1,d2,d3,d4,d5,d6,d7;
output a,b,c;
or(a,d4,d5,d6,d7);
or(b,d2,d3,d6,d7);
or(c,d1,d3,d5,d7);
endmodule

Dataflow level Verilog Code for Half Subtractor

module encoder();
input d0,d1,d2,d3,d4,d5,d6,d7;
output a,b,c;
assign a=d4 | d5 | d6 | d7;
assign b=d2 | d3 | d6 | d7;
assign c=d2 | d4 | d6 | d7;
endmodule

Test Bench Verilog Code:

`timescale 1ns / 1ps
module encodertest();
reg d0,d1,d2,d3,d4,d5,d6,d7;
wire a,b,c;
Encoder h1(
.d0(d0),
.d1(d1),
.d2(d2),
.d3(d3),
.d4(d4),
.d5(d5),
.d6(d6),
.d7(d7),
.a(a),
.b(b),
.c(c)
);
initial
begin
$monitor($time, "The value of d0=%b d1=%b d2=%b d3=%b d4=%b d5=%b d6=%b d7=%b
a=%b b=%b c=%b",d0,d1,d2,d3,d4,d5,d6,d7,a,b,c);
d0=1'b1; d1=1'b0; d2=1'b0; d3=1'b0; d4=1'b0; d5=1'b0; d6=1'b0; d7=1'b0;
#100;
d0=1'b0; d1=1'b1; d2=1'b0; d3=1'b0; d4=1'b0; d5=1'b0; d6=1'b0; d7=1'b0;
#100;
d0=1'b0; d1=1'b0; d2=1'b1; d3=1'b0; d4=1'b0; d5=1'b0; d6=1'b0; d7=1'b0;
#100;
d0=1'b0; d1=1'b0; d2=1'b0; d3=1'b1; d4=1'b0; d5=1'b0; d6=1'b0; d7=1'b0;
#100;
d0=1'b0; d1=1'b0; d2=1'b0; d3=1'b0; d4=1'b1; d5=1'b0; d6=1'b0; d7=1'b0;
#100;
d0=1'b0; d1=1'b0; d2=1'b0; d3=1'b0; d4=1'b0; d5=1'b1; d6=1'b0; d7=1'b0;
#100;
d0=1'b0; d1=1'b0; d2=1'b0; d3=1'b0; d4=1'b0; d5=1'b0; d6=1'b1; d7=1'b0;
#100;
d0=1'b0; d1=1'b0; d2=1'b0; d3=1'b0; d4=1'b0; d5=1'b0; d6=1'b0; d7=1'b1;
#100;

end
endmodule
Simulation Wave form:
Printed Output from Transcript window

0The value of d0=1 d1=0 d2=0 d3=0 d4=0 d5=0 d6=0 d7=0 a=0 b=0 c=0

# 100The value of d0=0 d1=1 d2=0 d3=0 d4=0 d5=0 d6=0 d7=0 a=0 b=0 c=1

# 200The value of d0=0 d1=0 d2=1 d3=0 d4=0 d5=0 d6=0 d7=0 a=0 b=1 c=0

# 300The value of d0=0 d1=0 d2=0 d3=1 d4=0 d5=0 d6=0 d7=0 a=0 b=1 c=1

# 400The value of d0=0 d1=0 d2=0 d3=0 d4=1 d5=0 d6=0 d7=0 a=1 b=0 c=0

# 500The value of d0=0 d1=0 d2=0 d3=0 d4=0 d5=1 d6=0 d7=0 a=1 b=0 c=1

# 600The value of d0=0 d1=0 d2=0 d3=0 d4=0 d5=0 d6=1 d7=0 a=1 b=1 c=0

# 700The value of d0=0 d1=0 d2=0 d3=0 d4=0 d5=0 d6=0 d7=1 a=1 b=1 c=1

Gate Level Verilog Code for Decoder 2:4:

module decoder_2_to_4(a0,a1,en,d0,d1,d2,d3);
input a0,a1,en;
output d0,d1,d2,d3;
not(an0,a0),(an1,a1);
and(d0,an0,an1,en);
and(d1,an0,a1,en);
and(d2,a0,an1,en);
and(d3,a0,a1,en);
endmodule
Dataflow level Verilog Code for Half Subtractor
module decoder_2_to_4(EN, A0, A1, D0, D1, D2, D3);
input EN, A0, A1;
output D0, D1, D2, D3;
assign D0 =(EN & ~A1 & ~A0);
assign D1 =(EN & ~A1 & A0);
assign D2 =(EN & A1 & ~A0);
assign D3 =(EN & A1 & A0);
endmodule
Test Bench Verilog Code:
`timescale 1ns / 1ns
module decoder24_test();
reg a0,a1,en;
wire d0,d1,d2,d3;
decoder_2_to_4 h1(.a0(a0),.a1(a1),.en(en),.d0(d0),.d1(d1),.d2(d2),.d3(d3));
initial
begin
$monitor($time, "The value of a0=%b a1=%b en=%b d0=%b d1=%b d2=%b d3=
%b",a0,a1,en,d0,d1,d2,d3);
a0=1'b0; a1=1'b0; en=1'b1;
#100;
a0=1'b0; a1=1'b1; en=1'b1;
#100;
a0=1'b1; a1=1'b0; en=1'b1;
#100;
a0=1'b1; a1=1'b1; en=1'b1;
#100;

end
endmodule
Simulation Wave form:

Printed Output from Transcript window:

0The value of a0=0 a1=0 en=1 d0=1 d1=0 d2=0 d3=0

# 100The value of a0=0 a1=1 en=1 d0=0 d1=1 d2=0 d3=0

# 200The value of a0=1 a1=0 en=1 d0=0 d1=0 d2=1 d3=0

# 300The value of a0=1 a1=1 en=1 d0=0 d1=0 d2=0 d3=1

Gate Level Verilog Code for Half Adder:

Dataflow level Verilog Code for Half Subtractor

Test Bench Verilog Code:

Simulation Wave form:

Printed Output from Transcript window: