CMOS Inverter Fabrication Steps

1. First mask defines N-well. The process begins with the creation of an n-
well on a bare p-type silicon wafer. The wafer is first oxidized to form SiO2
layer on the wafer surface. The Oxide layer is patterned using
photolithography process to define the n-well. Ion implantation or
diffusion is used to produce the n-well. The remaining oxide is etched
with hydrofluoric acid to leave the bare wafer with the n-well in the
appropriate place.

2. The transistor gates are formed next. These consist of polycrystalline

silicon, generally called polysilicon, over a thin layer of oxide. The thin
oxide is grown in a furnace. Then the wafer is placed in a reactor with
silane gas (SiH4) and heated again to grow the polysilicon layer through a
process called chemical vapor deposition. The polysilicon is heavily doped
to form a reasonably good conductor. The resulting cross-section is shown
in Figure.
3. The n+ regions are introduced for the transistor active area and the n-well
contact. A protective layer of oxide is formed and patterned with the n-
diffusion mask to expose the areas where the dopants are needed to
form the n+ regions using ion implantation. The polysilicon gate over the
nMOS transistor blocks the diffusion so the source and drain are
separated by a channel under the gate. This is called a self-aligned
process because the source and drain of the transistor are automatically
formed adjacent to the gate without the need to precisely align the
masks. Finally, the protective oxide is stripped.

4. The process is repeated for the p-diffusion mask to form source and drain
of PMOS in the n-well, as well as substrate p+ contact region for NMOS.

5. The field oxide is grown to insulate the wafer from metal and patterned
with the contact mask to leave contact cuts where metal should attach to
diffusion or polysilicon.

6. Finally, alluminum is sputtered over the entire wafer, filling the contact
cuts as well using metallization process. The metal is patterned with the
metal mask and plasma etched to remove metal everywhere except
where wires should remain.
Cross sectional views
Set of masks used
Top view of the CMOS inverter