Sequential Logic

Counters and Registers

Counters
 Introduction: Counters
 Asynchronous (Ripple) Counters
 Asynchronous Counters with MOD number < 2n
 Asynchronous Down Counters
 Cascading Asynchronous Counters

Serial In/Serial Out Shift Registers 1

 Sequential Logic
Counters and Registers

 Synchronous (Parallel) Counters

 Up/Down Synchronous Counters
 Designing Synchronous Counters

Serial In/Serial Out Shift Registers 2

 Lecture 13: Sequential Logic
Counters and Registers
Registers
 Introduction: Registers
 Simple Registers
 Registers with Parallel Load

 Using Registers to implement Sequential Circuits

 Shift Registers
 Serial In/Serial Out Shift Registers
 Serial In/Parallel Out Shift Registers
 Parallel In/Serial Out Shift Registers
 Parallel In/Parallel Out Shift Registers

Serial In/Serial Out Shift Registers 3

 Lecture 13: Sequential Logic
Counters and Registers

 Bidirectional Shift Registers

 An Application – Serial Addition
 Shift Register Counters
 Ring Counters
 Johnson Counters

 Random-Access Memory (RAM)

Serial In/Serial Out Shift Registers 4

Introduction: Counters
 Counters are circuits that cycle through a specified
number of states.
 Two types of counters:
 synchronous (parallel) counters
 asynchronous (ripple) counters

 Ripple counters allow some flip-flop outputs to be

used as a source of clock for other flip-flops.
 Synchronous counters apply the same clock to all
flip-flops.

Serial In/Serial Out Shift Registers 5

Asynchronous (Ripple) Counters
 Asynchronous counters: the flip-flops do not change
states at exactly the same time as they do not have a
common clock pulse.
 Also known as ripple counters, as the input clock
pulse “ripples” through the counter – cumulative
delay is a drawback.
 n flip-flops  a MOD (modulus) 2n counter. (Note: A
MOD-x counter cycles through x states.)
 Output of the last flip-flop (MSB) divides the input
clock frequency by the MOD number of the counter,
hence a counter is also a frequency divider.

Serial In/Serial Out Shift Registers 6

Asynchronous (Ripple) Counters
 Example: 2-bit ripple binary counter.
 Output of one flip-flop is connected to the clock input
of the next more-significant flip-flop.
HIGH

J Q0 J Q1
CLK C C
Q0
K K

FF0 FF1

CLK 1 2 3 4

Q0 Timing diagram
Q0 0 1 0 1 0 00  01  10  11  00 ...
Q1 0 0 1 1 0

Serial In/Serial Out Shift Registers 7

Asynchronous (Ripple) Counters
 Example: 3-bit ripple binary counter.
HIGH

J Q0 J Q1 J Q2
CLK C Q0 C Q1 C
K K K
FF0 FF1 FF2

CLK 1 2 3 4 5 6 7 8

Q0 0 1 0 1 0 1 0 1 0

Q1 0 0 1 1 0 0 1 1 0

Q2 0 0 0 0 1 1 1 1 0

Recycles back to 0

Serial In/Serial Out Shift Registers 8

Asynchronous (Ripple) Counters
 Propagation delays in an asynchronous (ripple-
clocked) binary counter.
 If the accumulated delay is greater than the clock
pulse, some counter states may be misrepresented!

CLK 1 2 3 4

Q0

Q1

Q2
tPHL (CLK to Q0) tPHL (CLK to Q0)
tPLH (Q0 to Q1) tPHL (Q0 to Q1)
tPLH
(CLK to Q0) tPLH (Q1 to Q2)

Serial In/Serial Out Shift Registers 9

Asynchronous (Ripple) Counters
 Example: 4-bit ripple binary counter (negative-edge
triggered).
HIGH
Q0 Q1 Q2 Q3
J J J J
CLK C C C C
K K K K
FF0 FF1 FF2 FF3

CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Q0

Q1

Q2

Q3

Serial In/Serial Out Shift Registers 10

 n
Asyn. Counters with MOD no. < 2
 States may be skipped resulting in a truncated
sequence.
 Technique: force counter to recycle before going
through all of the states in the binary sequence.
 Example: Given the following circuit, determine the
counting sequence (and hence the modulus no.)
C B A
Q J Q J Q J
All J, K CLK CLK CLK
inputs Q K Q K Q K
CLR CLR CLR
are 1
(HIGH). B
C

Serial In/Serial Out Shift Registers 11

Asynchronous Down Counters
 So far we are dealing with up counters. Down
counters, on the other hand, count downward from
a maximum value to zero, and repeat.
 Example: A 3-bit binary (MOD-23) down counter.
1
Q0 Q1 Q2
J Q J Q J Q 3-bit binary
CLK C C C up counter
Q' K Q' K Q'
K

1
Q0 Q1 Q2
J Q J Q J Q 3-bit binary
CLK C C C down counter
Q' K Q' K Q'
K

Serial In/Serial Out Shift Registers 12

Asynchronous Down Counters
 Example: A 3-bit binary (MOD-8) down counter.
000
001 111
1
Q0 Q1 Q2
J Q J Q J Q 010 110
CLK C C C
Q' K Q' K Q'
K
011 101
100

CLK 1 2 3 4 5 6 7 8

Q0 0 1 0 1 0 1 0 1 0

Q1 0 1 1 0 0 1 1 0 0

Q2 0 1 1 1 1 0 0 0 0

Serial In/Serial Out Shift Registers 13

Synchronous (Parallel) Counters
 Synchronous (parallel) counters: the flip-flops are
clocked at the same time by a common clock pulse.
 We can design these counters using the sequential
logic design process (covered in Lecture #12).
 Example: 2-bit synchronous binary counter (using T
flip-flops, or JK flip-flops with identical J,K inputs).
Present Next Flip-flop
state state inputs
00 01 A1 A0 A1+ A0+ TA1 TA0
0 0 0 1 0 1
11 10 0 1 1 0 1 1
1 0 1 1 0 1
1 1 0 0 1 1

Serial In/Serial Out Shift Registers 14

Synchronous (Parallel) Counters
 Example: 2-bit synchronous binary counter (using T
flip-flops, or JK flip-flops with identical J,K inputs).
Present Next Flip-flop
state state inputs
A1 A0 A1+ A0+ TA1 TA0 TA1 = A0
0 0 0 1 0 1
0 1 1 0 1 1 TA0 = 1
1 0 1 1 0 1
1 1 0 0 1 1

A0 J A1
J Q Q
C C
Q' K Q'
K

CLK

Serial In/Serial Out Shift Registers 15

Synchronous (Parallel) Counters
 Example: 3-bit synchronous binary counter (using T
flip-flops, or JK flip-flops with identical J, K inputs).
Present Next Flip-flop
state state inputs
A2 A1 A0 A2+ A1+ A0+ TA2 TA1 TA0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1
A1 A1 A1

1 1 1 1 1 1 1
A2 1 A2 1 1 A2 1 1 1 1

A0 A0 A0
TA2 = A1.A0 TA1 = A0 TA0 = 1
Serial In/Serial Out Shift Registers 16
Synchronous (Parallel) Counters
 Example: 3-bit synchronous binary counter (cont’d).
TA2 = A1.A0 TA1 = A0 TA0 = 1

A2 A1 A0

Q Q Q
J K J K J K
CP
1

Serial In/Serial Out Shift Registers 17

Synchronous (Parallel) Counters
 Note that in a binary counter, the nth bit (shown
underlined) is always complemented whenever
011…11  100…00
or 111…11  000…00
 Hence, Xn is complemented whenever
Xn-1Xn-2 ... X1X0 = 11…11.
 As a result, if T flip-flops are used, then
TXn = Xn-1 . Xn-2 . ... . X1 . X0

Serial In/Serial Out Shift Registers 18

Synchronous (Parallel) Counters
 Example: 4-bit synchronous binary counter.
TA3 = A2 . A1 . A0
TA2 = A1 . A0
TA1 = A0
TA0 = 1

1 A1.A0 A2.A1.A0

A0 J A1 J A2 J A3
J Q Q Q Q
C C C C
Q' K Q' K Q' K Q'
K

CLK

Serial In/Serial Out Shift Registers 19

Synchronous (Parallel) Counters
 Example: Synchronous decade/BCD counter.
Clock pulse Q3 Q2 Q1 Q0
Initially 0 0 0 0
1 0 0 0 1 T0 = 1
2 0 0 1 0
3 0 0 1 1 T1 = Q3'.Q0
4 0 1 0 0
5 0 1 0 1 T2 = Q1.Q0
6 0 1 1 0
7 0 1 1 1 T3 = Q2.Q1.Q0 + Q3.Q0
8 1 0 0 0
9 1 0 0 1
10 (recycle) 0 0 0 0

Serial In/Serial Out Shift Registers 20

Introduction: Registers
 An n-bit register has a group of n flip-flops and some
logic gates and is capable of storing n bits of
information.
 The flip-flops store the information while the gates
control when and how new information is transferred
into the register.
 Some functions of register:
 retrieve data from register
 store/load new data into register (serial or parallel)
 shift the data within register (left or right)

Serial In/Serial Out Shift Registers 21

Simple Registers
 No external gates.
 Example: A 4-bit register. A new 4-bit data is loaded
every clock cycle.
A3 A2 A1 A0

Q Q Q Q
D D D D
CP

I3 I2 I1 I0

Serial In/Serial Out Shift Registers 22

Registers With Parallel Load
 Instead of loading the register at every clock pulse,
we may want to control when to load.
 Loading a register: transfer new information into the
register. Requires a load control input.
 Parallel loading: all bits are loaded simultaneously.

Serial In/Serial Out Shift Registers 23

Registers With Parallel Load
Load'.A0 + Load. I0
Load
D Q A0
I0

D Q A1
I1

D Q A2
I2

D Q A3
I3

CLK
CLEAR

Serial In/Serial Out Shift Registers 24

Using Registers to implement
Sequential Circuits
 A sequential circuit may consist of a register
(memory) and a combinational circuit.
Next-state value

Register Combin-
Clock ational
circuit
Inputs Outputs

 The external inputs and present states of the register

determine the next states of the register and the
external outputs, through the combinational circuit.
 The combinational circuit may be implemented by
any of the methods covered in MSI components and
Programmable Logic Devices.
Serial In/Serial Out Shift Registers 25
Shift Registers
 Another function of a register, besides storage, is to
provide for data movements.
 Each stage (flip-flop) in a shift register represents
one bit of storage, and the shifting capability of a
register permits the movement of data from stage to
stage within the register, or into or out of the register
upon application of clock pulses.

Serial In/Serial Out Shift Registers 26

Shift Registers
 Basic data movement in shift registers (four bits are
used for illustration).

Data in Data out Data out Data in

(a) Serial in/shift right/serial out (b) Serial in/shift left/serial out

Data in Data in
Data in

Data out
Data out
(c) Parallel in/serial out (d) Serial in/parallel out
Data out
(e) Parallel in /
parallel out

(f) Rotate right (g) Rotate left

Serial In/Serial Out Shift Registers 27

Serial In/Serial Out Shift Registers
 Accepts data serially – one bit at a time – and also
produces output serially.

Serial data Q0 Q1 Q2 Q3 Serial data

D Q D Q D Q D Q
input output
C C C C

CLK

Serial In/Serial Out Shift Registers 28

Serial In/Serial Out Shift Registers
 Application: Serial transfer of data from one register
to another.

SI SO SI SO
Shift register A Shift register B

Clock CP
Shift control

Clock

Shift Wordtime
control

CP
T1 T2 T3 T4

Serial In/Serial Out Shift Registers 29

Serial In/Serial Out Shift Registers
 Serial-transfer example.

Timing Pulse Shift register A Shift register B Serial output of B

Initial value 1 0 1 1 0 0 1 0 0
After T1 1 1 0 1 1 0 0 1 1
After T2 1 1 1 0 1 1 0 0 0
After T3 0 1 1 1 0 1 1 0 0
After T4 1 0 1 1 1 0 1 1 1

Serial In/Serial Out Shift Registers 30

Shift Register Counters
 Shift register counter: a shift register with the serial
output connected back to the serial input.
 They are classified as counters because they give a
specified sequence of states.
 Two common types: the Johnson counter and the
Ring counter.

Serial In/Serial Out Shift Registers 31

SIPO register

Serial In/Serial Out Shift Registers 32

Parallel in serial out shift register

Serial In/Serial Out Shift Registers 33

PIPO register

Serial In/Serial Out Shift Registers 34

Applications of Registers
 Shift register is used as Parallel to serial converter, which
converts the parallel data into serial data. It is utilized at the
transmitter section after Analog to Digital Converter (ADC)
block.
 Shift register is used as Serial to parallel converter, which
converts the serial data into parallel data. It is utilized at the
receiver section before Digital to Analog Converter (DAC) block.
 Shift register along with some additional gate(s) generate the
sequence of zeros and ones. Hence, it is used as sequence
generator.
 Shift registers are also used as counters. There are two types
of counters based on the type of output from right most D flip-
flop is connected to the serial input. Those are Ring counter and
Johnson Ring counter.

Serial In/Serial Out Shift Registers 35

Ring Counter
 ‘N’ bit Ring counter performs the similar operation. But, the only
difference is that the output of rightmost D flip-flop is given as input of
leftmost D flip-flop instead of applying data from outside. Therefore, Ring
counter produces a sequence of states (pattern of zeros and ones) and it
repeats for every ‘N’ clock cycles.
 The block diagram of 3-bit Ring counter is shown in the following figure.

Serial In/Serial Out Shift Registers 36

Serial In/Serial Out Shift Registers 37
Serial In/Serial Out Shift Registers 38
 Therefore, the following operations take place for every positive edge of clock
signal.
 Serial input of first D flip-flop gets the previous complemented output of third flip-
flop. So, the present output of first D flip-flop is equal to the previous
complemented output of third flip-flop.
 The previous outputs of first and second D flip-flops are right shifted by one bit.
That means, the present outputs of second and third D flip-flops are equal to the
previous outputs of first and second D flip-flops.

Serial In/Serial Out Shift Registers 39

Random Access Memory (RAM)
 A memory unit stores binary information in groups of
bits called words.
 The data consists of n lines (for n-bit words). Data
input lines provide the information to be stored
(written) into the memory, while data output lines
carry the information out (read) from the memory.
 The address consists of k lines which specify which
word (among the 2k words available) to be selected
for reading or writing.
 The control lines Read and Write (usually combined
into a single control line Read/Write) specifies the
direction of transfer of the data.

Serial In/Serial Out Shift Registers 40

Random Access Memory (RAM)
 Block diagram of a memory unit:
n data
input lines
n

k
k address lines Memory unit
2k words
n bits per word
Read/Write

n data
output lines

Serial In/Serial Out Shift Registers 41

Random Access Memory (RAM)
 Content of a 1024 x 16-bit memory:

Memory address
binary decimal Memory content

0000000000 0 1011010111011101
0000000001 1 1010000110000110
0000000010 2 0010011101110001
: : :
: : :
1111111101 1021 1110010101010010
1111111110 1022 0011111010101110
1111111111 1023 1011000110010101

Serial In/Serial Out Shift Registers 42

Random Access Memory (RAM)
 The Write operation:
 Transfers the address of the desired word to the address
lines
 Transfers the data bits (the word) to be stored in memory to
the data input lines
 Activates the Write control line (set Read/Write to 0)

 The Read operation:

 Transfers the address of the desired word to the address
lines
 Activates the Read control line (set Read/Write to 1)

Serial In/Serial Out Shift Registers 43

Random Access Memory (RAM)
 The Read/Write operation:
Memory Enable Read/Write Memory Operation
0 X None
1 0 Write to selected word
1 1 Read from selected word

 Two types of RAM: Static and dynamic.

 Static RAMs use flip-flops as the memory cells.
 Dynamic RAMs use capacitor charges to represent data.
Though simpler in circuitry, they have to be constantly
refreshed.

Serial In/Serial Out Shift Registers 44

Random Access Memory (RAM)
 A single memory cell of the static RAM has the
following logic and block diagrams.

Select

Select
R

Input S Q Output Input BC Output

Read/Write
Read/Write

Logic diagram Block diagram

Serial In/Serial Out Shift Registers 45

Facts of tables

Serial In/Serial Out Shift Registers 46

Serial In/Serial Out Shift Registers 47
Serial In/Serial Out Shift Registers 48
End of segment

Serial In/Serial Out Shift Registers 49