Th3F-1

A GaN/Diamond HEMTs with 23 W/mm for Next Generation

High Power RF Application
Won Sang Lee#1, Kyung Won Lee$2, Seung Hyun Lee$3, Kevin Cho$4, Samuel Cho$5
#
RFHIC US Corp, USA
$
RFHIC Corp, Republic of Korea
1
wslee@rfhic.com, kwlee@rfhic.com, 3leesh@rfhic.com, 4kevin.cho@rfhic.com, 5drcho@rfhic.com
2

Abstract— This work demonstrated a successful fabrication of power GaN/Diamond HEMTs results will be addressed, and
4” GaN/Diamond HEMTs incorporated with Inner Slot Via Hole characteristics of On-wafer Load pull measurement of
process. The RF device parameters were measured On-wafer GaN/Diamond Transistor will be discussed.
Load pull measurement. The power density of 23.2 W/mm at Vds
= 100 V is obtained at a wafer level at 2 GHz pulse power II. FABRICATION AND MEASUREMENT
measurements.
Keywords— GaN/Diamond, HEMTs, Slot Via Hole, On-wafer A. 4” GaN/Diamond epitaxial wafer
Load-pull measurement, RF power amplifiers.
A manufacturing process procedure, exclusive technology
I. INTRODUCTION holded by RFHIC, for GaN/Diamond epitaxial wafer are shown
in Fig. 1. The process for epitaxal wafer manufacturing is as
III-Nitride High Electron Mobility Transistors (HEMTs)
follows: Si substrate and transition layer included buffer layer
technology for RF application has been of critical importance
are removed, 35 nm thick intermediate layer is deposited onto
for commercial and military applications, 50V CW applications
exposed GaN epitaxial layer and 120 um thick CVD Diamond
with greater than 10W/mm saturated output power density are
layer is deposited onto the intermediate layer and finally
fairly common. A discrete transistor with higher than 100V S-
temporary carrier is removed.
band 200W has been demonstrated recently [1].
However, the long-term reliable operation of GaN at high
power has been facing unique challenges originating from the
simultaneously high electric field and high temperature within
a small volume of a HEMTs [2]. With the ever-increasing
operating voltage and power, heat dissipation became the key
technological barrier hindering future progress of GaN-based
RF transistors.
Mitigating self-heating using a CVD Diamond cap has Fig. 1. Manufacturing process procedure of GaN/Diamond epitaxial wafer.
resulted in about 20% lower device temperature at an expense
of additional process complexity in order to integrate the heat
spreading close to the 2DEG channel [3]. On the other front,
advances in CVD Diamond technology make synthetic
diamond an ideal substrate for GaN devices due to its excellent
thermal conductivity (up to 20W/cmK). In the past few years,
with the improvement in microwave CVD Diamond synthesis
process, researchers in Raytheon and TriQuint successfully
demonstrated enhanced thermal and RF performance on
GaN/Diamond HEMTs, reducing the operating junction
temperature by 40-45 % and tripling the areal RF power density
compared to that of GaN/SiC [4][5]. Similarly, GaN/Diamond
technology had produced an excellent electrothermal
performance by integrating GaN/Si with CVD Diamond grown
on the N-polar backside [6]. Such advances in thermal Fig. 2. Map of TBR (Unit: m2K/GW) for 120 um thickness 4 inch
management have demonstrated that GaN/Si HEMTs have the GaN/Diamond epitaxial wafer
potential to operate reliably at a very high power density (> 10
W/mm). But most of the work was R&D based activity for GaN
HEMTs as well as GaN/Diamond HEMTs. The propose of this A TBR of GaN/Diamond epitaxial wafer measured using
work is to develop a production level process using fully Thermo-Reflectance measurement method. In Fig. 2, map of
automated 4” foundry fabrication facility (Fab) and to improve TBR for 120 um thick 4” GaN/Diamond epitaxial wafer is
RF characteristics of GaN/HEMT bare die as well as a shown. The within wafer TBR uniformity is of the order of
packaged device. In this paper, the development status of high

978-1-7281-1309-8/19/$31.00 © 2019 IEEE 1395 2019 IEEE/MTT-S International Microwave Symposium

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±10%, with wafer to wafer TBR average uniformity of the
measurement of less than ±15%, for all process lot.
B. 0.5 um GaN/Diamond HEMTs
A 4” GaN/Diamond HEMT epitaxial wafer was produced
by RFHIC and processed at a foundry Fab using standard
existing 4” toolset as in GaN/SiC and GaN/Si production.
The typical 4” GaN/Diamond epitaxial wafer has a
thickness from 110 um to 130 um. Specially developed wafer
bonding process effectively controlled BOW and Warpage
during the wafer process. A stiff carrier with strong bonding
media is necessary to let these tools accept 4” GaN/Diamond
epitaxial wafers. Especially, at gate lithography (0.5 um)
process using Stepper, wafer bowing and poor thickness Fig. 4. 4 inch 0.5 um GaN/Diamond HEMTs wafer
uniformity presented extraordinary challenges.
A damage-free Inner Slot Via Hole process recipe was
successfully developed for GaN/Diamond HEMTs using a
Laser Drilling process. This unique process was made on 80 um
Source pad incorporated with round shape 20 um dia. hole.

Fig. 5 Inner Slot Via Hole shape on Source pad

Fig. 3 Standard GaN/Diamond HEMTs process Flow

Using a standard GaN/SiC HEMTs process procedure, 0.5
um GaN/Diamond HEMTs was fabricated with high
temperature ohmic alloying, SiN deposition, implant isolation
defining the active layer, gate formation involving a gate SiN
etch and gate metal deposition, and anneal. Then 2nd SiN layer
is deposited to passivate the gates. M1 interconnect, 3rd SiN
layer, air bridge, and final passivation are followed to complete
GaN/Diamond HEMTs wafer surface. Fig. 3 illustrates the
simplified process flow. A 0.5 um GaN/Diamond HEMT
basically followed these standardized production level process
route incorporated with Inner Slot Via Hole process. In Fig. 4,
4” GaN/Diamond HEMTs wafer is shown a front side process
and a back side process completion in standard 4" foundry Fab.
As shown Fig. 5, Inner Slot Via Hole was controlled by
taper characteristics during Laser Drilling process in order to
increase Au plating process yield.
C. On-wafer Load pull measurement
On-wafer- probing load pull measurement was conducted
on 4” GaN/Diamond HEMT wafer. To acquire a more accurate
measurement of the device, combination of using PNA-X, high
power load pull tuner and eliminating the 2nd harmonics was
the key. Even though the use of the diamond substrate can
greatly enhance the thermal performance of GaN HEMT device,
pulse signal was used instead of a continuous wave for the
measurement due to heat dissipation limit for On-wafer testing.
III. MEASUREMENT RESULTS
The On-wafer Load pull measurement results of 4”
GaN/Diamond HEMT are shown in Fig. 6.
The RF characteristics in Fig. 6 show Pin vs Gain, Pout, and
Power Added Efficiency (PAE) measurement using a 300 um
gate width two fingers device measured at 2 GHz with 100 V

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drain voltage. 50 us pulse width, 10% duty is the signal
conditions used for this measurement. To find the optimum
impedance, fundamental and 2nd harmonic were eliminated
during the Load pull measurement. Saturated output power is
41.3 dBm which calculates the power density to be 22.5 W/mm.

Fig. 8. IR thermal signatures of packaged 2 X 300 um GaN/Diamond HEMTs

at Pd = 12 W

The channel temperature of packaged 2 X 300 um

Fig. 6. On-wafer Load pull measurement results of 4 inch 2 X 300 um (0.6
mm total gate width) GaN/Diamond HEMTs wafer measured after front side
wafer process completion.
In 0.6 mm GaN/Diamond HEMTs revealed RF power
saturated at 41.3 dBm, corresponding to a world record of 22.5
W/mm in power density.
GaN/Diamond HEMTs was 152.39 OC at gate area and most of
active area revealed lower than 120 OC.
The Load pull measurement results of packaged 10F X 200
um GaN/Diamond HEMTs at pulsed (10 % duty cycle)
condition are shown Fig. 9. Peak output power is 45.6 dBm
which calculated the power density to be 18.1 W/mm at Vds =
80 V.

Fig. 7. On-wafer Load pull measurement results of 4 inch 10 X 50 um (0.5 mm

total gate width) GaN/Diamond HEMTs wafer measured after Inner Slot Via
Hole process completion. Fig. 9. Load pull measurement results of 10 X 200 um (2 mm total gate width)
GaN/Diamond HEMTs measured after assembly process completion.

Fig. 7 shows the output power at 2 GHz for a 10 fingers 50

Characteristics of Pout appears to be slightly increased at
um long device. The bias is set at 100 V and 15 % Idss. The
Vds applied up to 100 V due to peak gain decreased. RFHIC
pulse width is 50 us and duty cycle is 10 %.
has investigating items about an active area optimization for
In the aforementioned conditions, the power saturated at
large periphery device and an assembly technology to improve
40.6 dBm, corresponding to State-of-Art record of 23.2 W/mm.
power density at Vds = 100 V.
IR (Infrared) microscope was used to evaluate the thermal
characteristics of the packaged 2 X 300 um GaN/Diamond
HEMTs. Fig. 8 shows the channel temperature of the packaged
2 X 300 um GaN/Diamond HEMTs at Vds = 100 V, Idq = 120
mA (Pd = 12 W) condition.

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 IV. CONCLUSION
RFHIC continue to make significant progress in
GaN/Diamond HEMTs manufacturing technology, including
production level assembly process development. On 4”
GaN/Diamond HEMTs wafer, we obtained 41.3 dBm from
2X300 um device and 40.6 dBm 10X50 um device from a 2
GHz On- wafer Load pull test when biased at 100 V and 15 %
Idss. To our knowledge, this is the world record in terms of RF
output power density among GaN/SiC HEMTs as well as even
GaN/Diamond HEMTs.

REFERENCES
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