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    This document summarizes a research paper that proposes a new 10T SRAM cell design for low power and high speed applications. The proposed cell uses Virtual Ground and Forward Body Biasing techniques to achieve lower power dissipation during hold mode and higher read performance. Simulation results show the new 10T cell has significantly improved read current and delay compared to 6T, 8T, 9T, and 10T SRAM cells, while maintaining similar write delay and write noise margin. The proposed cell is estimated to achieve up to 82% improvement in read current and 72% higher read noise margin compared to other cell designs.

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    This document summarizes a research paper that proposes a new 10T SRAM cell design for low power and high speed applications. The proposed cell uses Virtual Ground and Forward Body Biasing techniques to achieve lower power dissipation during hold mode and higher read performance. Simulation results show the new 10T cell has significantly improved read current and delay compared to 6T, 8T, 9T, and 10T SRAM cells, while maintaining similar write delay and write noise margin. The proposed cell is estimated to achieve up to 82% improvement in read current and 72% higher read noise margin compared to other cell designs.

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    17 views2 pages

    Design of 10T SRAM Cell For Low Power and High-Speed Applications

    Uploaded by

    GS EKTA
    This document summarizes a research paper that proposes a new 10T SRAM cell design for low power and high speed applications. The proposed cell uses Virtual Ground and Forward Body Biasing techniques to achieve lower power dissipation during hold mode and higher read performance. Simulation results show the new 10T cell has significantly improved read current and delay compared to 6T, 8T, 9T, and 10T SRAM cells, while maintaining similar write delay and write noise margin. The proposed cell is estimated to achieve up to 82% improvement in read current and 72% higher read noise margin compared to other cell designs.

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    Design of 10T SRAM Cell for Low Power and High-Speed Applications

    Article · January 2017

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    3 authors, including:

    Nikhil Saxena Amit Singh Rajput


    University of Cincinnati Chhattisgarh Swami Vivekananda Technical University
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    Home > Vol 8, No 2 (2017) > Gupta
    Open Access Subscription or Fee Access

    Design of 10T SRAM Cell for Low Power and High Speed
    Applications
    Rajat Gupta, Amit S. Rajput, Nikhil Saxena

    Abstract

    Abstract
    This paper presents techniques for designing a low-power and higher read speed Static
    Random Access Memory (SRAM) cell. The cell achieves low power dissipation due to Virtual
    Ground (VGND) scheme and provides higher read performance due to Forward Body Biasing
    (FBB). Design metrics of the proposed SRAM cell was studied and compared with that of CON
    6T, CON D10T, TG 8T, 9T, and ST-10T SRAM cells. It was observed that the proposed design
    shows significant improvements in read current, read delay over 6T, TG 8T, 9T, ST- 10T.
    However, write delay and WSNM of proposed cell is significantly same as that of CON 6T and
    read decoupled SRAM cells but its RSNM is similar to read decoupled SRAM cells. Proposed
    SRAM cell has simulated at 45 nm technology PTM files for estimating its design metrics by
    using HSPICE circuit simulator. The proposed design achieves 27%/36%/82%/32%/26%
    improvement in TRA as compared to 6T/CON D10T/9T/TG 8T/ST- 10T. An improvement of
    66%/55%/72% in RSNM was observed as compared to 6T/TG8T/ST- 10T. The proposed
    design consumes 39%/19%/22% less power during hold mode @ VDD =0.7 V as compared
    to CON D10T/9T/ ST-10T.

    Keywords: FBB and VGND techniques, read current, read delay, RSNM, WSNM

    Cite this Article


    Gupta R, Rajput AS, Saxena N. Design of 10T SRAM Cell for Low Power and High Speed
    Applications. Journal of Electronic Design and Technology. 2017; 8(2): 16–27p.

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