VISVESVARAYA NATIONAL INSTITUTE

OF TECHNOLOGY NAGPUR

VLSI DESIGN
MTECH 2021-23
CMOS DIGITAL VLSI LAB

ASSIGNMENT 4
Submitted by

Rutvik Patel
MT21MVD022
 Question :- Simulate 3 Input Nand Gate and Find Tpdr,Tpdf,Tcdf,Tcdr. Do
theoretical Calculations. Use 180nm Technology.

1. Rising Propagation delay :-

 Code:-
3ip nand
.include cmosedu_models1.txt
vdd 4 0 dc 1.8
va 1 0 dc 1 pulse (0 1.8 0 5n 5n 0.1u 0.2u)
vb 2 0 dc 1 pulse (0 1.8 0 5n 5n 0.1u 0.2u)
vc 3 0 dc 1 pulse (0 1.8 0 5n 5n 0.1u 0.2u)
mp0 5 1 4 4 MOSP w=1.4um l=180nm
mp1 5 2 4 4 MOSP w=1.4um l=180nm
mp2 5 3 4 4 MOSP w=1.4um l=180nm
mn0 5 1 6 6 MOSN w=0.8um l=180nm
mn1 6 2 7 7 MOSN w=0.8um l=180nm
mn2 7 3 0 0 MOSN w=0.8um l=180nm
.control
tran 1ps 0.8us
plot v(3) v(5)
meas tran tpdr trig v(3) val=0.5 fall=1 targ v(5) val=0.5 rise =1
.endc
.end

 Tprd:-
 Output:-

 Calculation:-
2. Falling Propagation delay :-
 Code:-
3ip nand
.include cmosedu_models1.txt
vdd 4 0 dc 1.8
va 1 0 dc 1 pulse (0 1.8 0 5n 5n 0.1u 0.2u)
vb 2 0 dc 1 pulse (0 1.8 0 5n 5n 0.1u 0.2u)
vc 3 0 dc 1 pulse (0 1.8 0 5n 5n 0.1u 0.2u)
mp0 5 1 4 4 MOSP w=1.4um l=180nm
mp1 5 2 4 4 MOSP w=1.4um l=180nm
mp2 5 3 4 4 MOSP w=1.4um l=180nm
mn0 5 1 6 6 MOSN w=0.8um l=180nm
mn1 6 2 7 7 MOSN w=0.8um l=180nm
mn2 7 3 0 0 MOSN w=0.8um l=180nm
.control
tran 1ps 0.8us
plot v(3) v(5)
meas tran tpdf trig v(3) val=0.5 rise=1 targ v(5) val=0.5 fall =1
.endc
.end

 Tpfd:-
 Output:-

 Calculation:-
3. Rising Contamination delay :-
 Code:-
3ip nand
.include cmosedu_models1.txt
vdd 4 0 dc 1.8
va 1 0 dc 1 pulse (0 1.8 0 5n 5n 0.1u 0.2u)
vb 2 0 dc 1 pulse (0 1.8 0 5n 5n 0.1u 0.2u)
vc 3 0 dc 1 pulse (0 1.8 0 5n 5n 0.1u 0.2u)
mp0 5 1 4 4 MOSP w=1.4um l=180nm
mp1 5 2 4 4 MOSP w=1.4um l=180nm
mp2 5 3 4 4 MOSP w=1.4um l=180nm
mn0 5 1 6 6 MOSN w=0.8um l=180nm
mn1 6 2 7 7 MOSN w=0.8um l=180nm
mn2 7 3 0 0 MOSN w=0.8um l=180nm
.control
tran 1ps 0.8us
plot v(1) v(5)
meas tran tcdr trig v(1) val=0.5 fall=1 targ v(5) val=0.5 rise =1

.endc
.end
 Tcrd:-
 Output:-

 Calculation:-
4. Falling Contamination delay :-
 Code:-
3ip nand
.include cmosedu_models1.txt
vdd 4 0 dc 1.8
va 1 0 dc 1 pulse (0 1.8 0 5n 5n 0.1u 0.2u)
vb 2 0 dc 1 pulse (0 1.8 0 5n 5n 0.1u 0.2u)
vc 3 0 dc 1 pulse (0 1.8 0 5n 5n 0.1u 0.2u)
mp0 5 1 4 4 MOSP w=1.4um l=180nm
mp1 5 2 4 4 MOSP w=1.4um l=180nm
mp2 5 3 4 4 MOSP w=1.4um l=180nm
mn0 5 1 6 6 MOSN w=0.8um l=180nm
mn1 6 2 7 7 MOSN w=0.8um l=180nm
mn2 7 3 0 0 MOSN w=0.8um l=180nm
.control
tran 1ps 0.8us

plot v(1) v(5)

meas tran tcdf trig v(1) val=0.5 rise=1 targ v(5) val=0.5 fall =1
.endc
.end

 Tcfd:-
 Output:-

 Calculation:-

 Conclusion:-
1.We have analysed the 3 input NAND gate circuit in ngspice. The calculated
parameters graphically are:
tpdf= 0.226nm;
tpdr= 0.22nm;
tcdf =0.136 nm;
tcdr= 0.0574nm;
2. It is observed that the gate has equal resistance pulling up and down, the
delays are not quite equal because of the capacitances on the internal nodes.