ASSIGNMENT 7

ANALOG VLSI DESIGN LAB

NAME:YATENDRA CHAUHAN
ENROLL:MT20MVD014
Q1:-Determine the gain, magnitude, and phase shift of the amplifier shown in
Fig.21.8. Using an AC SPICE simulation, verify your hand calculations. The bias
circuit is used to bias the amplifier at the operating point seen in Table 9.1, that is, at a
drain current of 20 |xA. The big resistor and capacitor set the DC bias point but don't
affect the AC operation of the circuit.

Code
.include cmosedu_models.txt
.option scale=1u
*.dc Von 0 5 1m
.AC DEC 100 10MEG 100G
**.op

VDD VDD 0 DC 5
Vs Vs 0 DC 0 AC 1
Rs Vs Vss 100k
M1 Vout Vin 0 0 N_1u L=2 W=10
M2 Vout Vout VDD VDD P_1u L=2 W=30

Rbig Vbias4 Vin 1G

Cbig Vss Vin 1u
Xbias VDD Vbias1 Vbias2 Vbias3 Vbias4 Vhigh Vlow Vncas Vpcas bias
.subckt bias VDD Vbias1 Vbias2 Vbias3 Vbias4 Vhigh Vlow Vncas Vpcas

MN1 Vbias2 Vbiasn 0 0 N_1u L=2 W=10

MN2 Vbias1 Vbiasn 0 0 N_1u L=2 W=10
MN3 Vncas Vncas vn1 0 N_1u L=2 W=10
MN4 vn1 Vbias3 vn2 0 N_1u L=2 W=10
MN5 vn2 vn1 0 0 N_1u L=2 W=10
MN6 Vbias3 Vbias3 0 0 N_1u L=10 W=10
MN7 Vbias4 Vbias3 Vlow 0 N_1u L=2 W=10
MN8 Vlow Vbias4 0 0 N_1u L=2 W=10
MN9 Vpcas Vbias3 vn3 0 N_1u L=2 W=10
MN10 vn3 Vbias4 0 0 N_1u L=2 W=10

MP1Vbias2 Vbias2 VDD VDD P_1u L=10 W=30

MP2Vhigh Vbias1 VDD
MP3Vbias1 Vbias2 Vhigh
MP4vp1 Vbias1 VDD
MP5Vncas Vbias2 vp1 VDD
MP6vp2 Vbias1 VDD
MP7Vbias3 Vbias2 vp2VDD
MP8vp3 Vbias1 VDD
MP9Vbias4 Vbias2 vp3VDD
MP10 vp4 vp5 VDD
MP11 vp5 Vbias2 vp4
MP12 Vpcas Vpcas vp5
VDD P_1u L=2 W=30
VDD P_1u L=2 W=30
VDD P_1u L=2 W=30
P_1u L=2 W=30
VDD P_1u L=2 W=30
P_1u L=2 W=30
VDD P_1u L=2 W=30
P_1u L=2 W=30
VDD P_1u L=2 W=30
VDD P_1u L=2 W=30
VDD P_1u L=2 W=30

MBM1 Vbiasn Vbiasn 0 0 N_1u L=2 W=10

MBM2 Vbiasp Vbiasn Vr 0 N_1u L=2 W=40
MBM3 Vbiasn Vbiasp VDD VDD P_1u L=2 W=30
MBM4 Vbiasp Vbiasp VDD VDD P_1u L=2 W=30

Rbias Vr 0 6.5k

MSU1 Vsur Vbiasn 0 0 N_1u L=2 W=10

MSU2 Vsur Vsur VDD VDD P_1u L=100 W=10
MSU3 Vbiasp Vsur Vbiasn 0 N_1u L=1 W=10

*#destroy all
*#run
*#plot 20*log(mag(vout/vs))
*#set units=degrees
*#plot ph(vout/vs)
.ends
.end
Output
Design a beta multiplier for 10u A of current

For different different current at the output of beta multiplier we

have to choose different resistance value which may conduct the
same current .
For 10u A of current we calculated resistance value of 8.83K ohm.

Netlist

.include cmosedu_models.txt
VDD VDD 0 DC 5
Vop Vop 0 DC 0
Von VDD Von DC 0
Vmeas1 Vmeas1 0 DC 0
Vmeas2 Vmeas2 0 DC 0
M1 Vbiasn Vbiasn Vmeas1 0 N_1u L=2 W=10
M2 Vbiasp Vbiasn Vr 0 N_1u L=2 W=40
M3 Vbiasn Vbiasp VDD VDD P_1u L=2 W=30
M4 Vbiasp Vbiasp VDD VDD P_1u L=2 W=30
Rbias Vr vmeas2 8.83k
MSU1 Vsur Vbiasn 0 0 N_1u L=2 W=10
MSU2 Vsur Vsur VDD VDD P_1u L=100 W=10
MSU3 Vbiasp Vsur Vbiasn 0 N_1u L=1 W=10
*#destroy all
*#run
*#let Iref1=Vmeas1#branch
*#let Iref2=Vmeas2#branch
*#plot Iref1 Iref2
.option scale=1u
.dc VDD 0 6 1m
.end
Output
Design a beta multiplier for 40u A of current
For 40u A of current we calculated resistance value of 4.5K ohm.

Netlist

.include cmosedu_models.txt
VDD VDD 0 DC 5
Vop Vop 0 DC 0
Von VDD Von DC 0
Vmeas1 Vmeas1 0 DC 0
Vmeas2 Vmeas2 0 DC 0
M1 Vbiasn Vbiasn Vmeas1 0 N_1u L=2 W=10
M2 Vbiasp Vbiasn Vr 0 N_1u L=2 W=40
M3 Vbiasn Vbiasp VDD VDD P_1u L=2 W=30
M4 Vbiasp Vbiasp VDD VDD P_1u L=2 W=30
Rbias Vr vmeas2 4.4213k
MSU1 Vsur Vbiasn 0 0 N_1u L=2 W=10
MSU2 Vsur Vsur VDD VDD P_1u L=100 W=10
MSU3 Vbiasp Vsur Vbiasn 0 N_1u L=1 W=10
.dc VDD 0 6 1m
*#destroy all
*#run
*#let Iref1=Vmeas1#branch
*#let Iref2=Vmeas2#branch
*#plot Iref1 Iref2
.option scale=1u
.end
Output

Conclusion

In this Assignment, I have done simulation for beta multiplier for long channel for changing
drain current as a function of changing output resistance and I observed that resistance is
inversely proportional to drain current .For different different current at the output of beta
multiplier we have to choose different resistance value which may conduct the same current
.