dld_proj_writeup.

md - Grip http://localhost:6419/

dld_proj_writeup.md

Overview
An implementation of an NXUR interlocking panel and backend that safely interlocks the area around Queens Plaza within the MTANYCT
BMD/IND system. We do this by allowing the user to spawn virtual trains, route them with the route displayed to the user through signal
aspects, and observe the trains moving down track under control of those signals (displayed by lit LEDs along tracks).

Just like the real signals at the MTA, the system enforces interlocking control, meaning that two conflicting routes cannot be entered at the
same time. For example, if the E train had a clearance to get onto the express track, an F train coming from another direction can't also get
that clearance until the E train either passes or is cancelled.

Queens Plaza Interlocking

Our design focuses on Queens Plaza Interlocking going eastbound, where the E, F, M, and R trains (as well as an unused track for former
'G' trains) converge onto the local and express tracks of the Queens Boulevard Line. This is described using a track map, which indicates
the location of signals (which indicate train permission) and switches (which physically route trains).

In the real MTA system, there are multiple types of signals (automatic block, timer, home, etc). We focused on 'home' signals only, which
are operated by dispatchers and interlocking machines, and indicate whether trains are permitted to move and where they will go. Each
home signal is denoted with a code like "D2 1247 X 452" meaning "track D2, distance along track 1247, crossover number 452" (the
crossover numbers and track distances are arbitrary).

The signal itself conveys up to three aspects: Red (train can't pass), green (train passes, continuing straight), and yellow (train passes,
diverging from the route). For example, at D4 1257 X464 just above the Queens Plaza platform, an 'M' train will get a yellow, sending it
across the crossover onto track D2 for local service, while an 'E' train would get a green, keeping it on track D4. Not all signals have all
aspects - for example E2 1245 X452 can only be set yellow or red, while D2 1248 x452 can only be set green or red.

Trains must also be kept separated in blocks (denoted in gray). Only one train can exist in each of D2-0, D2-1, ... at a time.

Architecture
We use an FPGA and discrete logic gates. The FPGA emulates the knowledge of the dispatcher working at the signalling tower, while the
discrete logic gates implement the interlocking machine the dispatcher would use, as well as the trains, switches, and signals themselves.

1 of 7 1/17/2021, 12:21
dld_proj_writeup.md - Grip http://localhost:6419/

SERDES
The FPGA and discrete logic are connected through a serializer-deserializer system. A chain of parallel-out shift registers is connected to
the FPGA, and a set of latches is connected to the discrete logic. When the FPGA outputs a route, it shifts it into the output registers and
then asserts the strobe for the latches, presenting it to the interlocking logic (both route legality checks and switch/crossover state).

2 of 7 1/17/2021, 12:21
dld_proj_writeup.md - Grip http://localhost:6419/

When the FPGA needs to read data from the user buttons, it asserts the strobes on parallel-in shift registers, and shifts the data out.
Buttons are latched until the FPGA clears them.

3 of 7 1/17/2021, 12:21
dld_proj_writeup.md - Grip http://localhost:6419/

Signal State
The signal state latches ("switches/crossovers/signals on tracks" in architecture diagram) store the current state of all signals in the
interlocking. The storage is composed of latches:

Each latch can be set by the FPGA through the serdes, and is cleared by an "inhibit" signal (denoted IP0 , IP1 , ...). The inhibit signal is set
if the routing would cause a train safety violation (e.g. if the given route conflicts with an existing route already latched in, or if a train is
occupying the track segment controlled by that signal. For example, in the screenshot above, inhibit signals IP2 and IP3 prohibit setting
green and yellow on crossover X460 (note the inputs labeled X460-G-SET and X460-Y-SET above the latch).

The latches feed the signal LEDs shown to the user, as well as the track logic. In the above example, SP12 is the green (proceed) for
crossover X460, SP11 is the yellow (diverge) for crossover X460, and SP8 (the NOR of these two signals) is the red lamp (stop-and-stay) for
that crossover.

Inhibit logic
The inhibit signals are generated by OR-ing all conditions that make that signal unsafe. For example, IP2 , which inhibits a green aspect on
X460, prevents a train from continuing down track D4. It's generated by any of the following conditions:

A train currently in any part of the crossover made by switches X460 and X464, since it would either be leaving or entering track D4
just beyond that signal.
There's a train in the D4-1 block of the track (trains must maintain distance and separation)
Signal X460 is already set for yellow (changing the signal as a train is already approaching is unsafe)

4 of 7 1/17/2021, 12:21
dld_proj_writeup.md - Grip http://localhost:6419/

Track circuits and train simulating

The actual train detection is performed by track circuits. The tracks are composed of large numbers of shift registers:

5 of 7 1/17/2021, 12:21
dld_proj_writeup.md - Grip http://localhost:6419/

Trains are always eight bits long, making the signal logic quite simple: If a train is facing a red signal, it gets "recycled" around the shift
register it's currently in (see callout 1 on figure). If the signal is permissive (yellow or green), the train is allowed through to the next shift
register (see callout 2 on figure). However, as soon as the train's first bit passes the signal, it immediately gets inhibited back to red (just
like in the real subway system). The train is allowed to continue to pass (see callout 3) -- a train behind it will not be able to.

In cases of crossovers, there are shift registers for both the straight-through tracks and the crossover tracks:

Finally, these shift registers have direct connections back to the inhibit logic board, completing the flow of information. Because we know
the length of trains, we can limit ourselves to checking every fourth bit, plus the first/last bit of every track block.

Misc. gallery
Planning for signal inhibit conditions:

Interlocking/inhbit gate optimization:

6 of 7 1/17/2021, 12:21
dld_proj_writeup.md - Grip http://localhost:6419/

FPGA SERDES mapping (subset):

Breadboard layout (allowing us to validate wiring early, and then wire mindlessly):

7 of 7 1/17/2021, 12:21