Annual Conference on New Trends in Information & Communications Technology Applications-(NTICT'2017)

7 - 9 March 2017

Design Of SHA-1 & SHA-2 MIPS Processor Using

FPGA
Safaa S. Omran Laith F. Jumma
Computer Engineering Techniques Computer Engineering Techniques
College of Electrical and Electronic Techniques College of Electrical and Electronic Techniques
Baghdad, Iraq Baghdad, Iraq
Omran_safaa@ymail.com Laith1993@gmail.com

Abstract² According to the wide developments in the area of
communications, there is a demand for secure system for data
transmissions. In this paper, a Hash system SHA-1 and SHA-2
Processor is designed using Xilinx Spartan-3AN and interfaced
with keyboard and Video Graphics Array (VGA) Display. The
implementation of the processor is done by using MIPS
(Microprocessor without Interlocked Pipelines) single cycle by
choosing a certain number of instructions that was necessary to
invoke the SHA-1, SHA-224 and SHA-256 algorithm. A keyboard
in interfaced with the Xilinx Spartan-3AN kit, to enable the user
to enter the data and the result is shown on a VGA Display.
Keywords²VHDL; SHA-1; SHA-2; MIPS Processor
be classified into two stages. The first stage is the Pre-
processing stage and the second is Hash Computation.
A. Pre-processing
SHA-1 and SHA-2 input block size varies depending on
what algorithm is used. In this stage the message is padded
into block size called chunk. The input blocks size of SHA-1,
SHA-224, SHA-256 is equal to 512-bits divider into 16 words
Y[0-15] of 32-bit. Then extending the 16 words Y[0-15]
depending on a certain algorithm. Table 1 shows features of
the two hash functions.

I. INTRODUCTION
A variation on the message authentication code is the one-
way hash function. A hash function accepts a variable-size
message M as input and produces a fixed-size output, referred
to as a hash code H(M).Hash functions are used in conjunction
with symmetric ciphers for digital signatures. In addition, hash
functions are used for message authentication [1].
VHDL (Very High Speed Integrated Circuit Hardware
Description Language) is a hardware description language. It B. Hash Computation
describe the behaviour of an electronic circuit or system, from
Hash Computation various depending on the algorithm
which the physical circuit or system can then be attained [2].
used if it is SHA-1, SHA-224 or SHA-256.
One of the earliest hardware designs of hash function in
reported by selimis in [3]. The authors in [4] propose a x SHA-1 Computation
processor for both SHA-1 and MD5 algorithms, and
implemented on an Altera Apex 20k. While in [5] a high- A message digest is 5 hash variables each of 32 bits are used.
performance SHA-1 design in presented and implemented on It take 80 rounds to completed SHA-1 calculation. SHA-1
a Xilinx Vertex-E FPGA. The authors in [6] implement a algorithm is done as follows:
SHA-1, HAS-160 and MD5 in one chip. In [7] a processor is Fig.1 shows SHA-1 computation
designed to support the algorithm of SHA-1 and SHA-256
hashing. However, in this research SHA-1 SHA-224 and SHA-
256, hash MIPS processor with keyboard and VGA display is
designed and implemented using Xilinx-Spartan-3AN.
II. SHA-1 & SHA-2 ALGORITHMS
The SHA-2 namely SHA-224, and SHA-256 have several
commonalities. SHA-1 and SHA-2 algorithms are one-way
hash functions that process a message to produce a message
digest.
This paper presents an implementation approach for SHA-1,
SHA-224 and SHA-256 hash algorithms. Each algorithm can

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 Annual Conference on New Trends in Information & Communications Technology Applications-(NTICT'2017)
7 - 9 March 2017
The message digest is 8 hash variables each of 32 bits are
used. It take 64 rounds to completed SHA-224 and SHA-
256 calculation. SHA-256 algorithm is done as follows:
In the first step hash variables shown in table and are
initialized.

TABLE II. INITIALIZED SHA-256 VARIABLE

L0 L1 L2 L3
6A09E667 BB67AE85 3C6EF372 A54FF53A
L4 L5 L6 L7
510E527F 9B05688C 1F83D9AB 5BE0CD19

In the second massage word Y[0-15] extended into 64

word Y[16-63]

Where >>> is right rotate and >> is right shift

In the third 8 variable (a to h) is added which is equal to
(L0 to L7)
The fourth step is the main loop which is (a to h) will be
calculated in 80 Round as following:

where K[t] is round constants and (S0,S1,CH,MAJ)

Fig. 1 SHA-1 Computation equation are below
Fig.2 shows the SHA-1 Computation

The final step is add (a to h) with (L0 to L7) which

produce the massage digest of 256-bit.

Fig. 2 SHA-1 Computation

SHA-224 and SHA-256 is identical algorithm except that:

x SHA-224 & SHA-256 Computation

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The massage digest is 256-bit which constructed by
omitting L7.
The initial hash values L0 through L7 are shown in table IV

TABLE III INITIALIZED SHA-224 VARIABLE

L0 L1 L2 L3

C1059ED8 367CD507 3070DD17 F70E5939

L4 L5 L6 L7

FFC00B31 68581511 64F98FA7 BEFA4FA4

Fig. 3 shows a block diagram for SHA-2 computation.
Fig. 3 SHA-2 Computations
III. INSTRUCTION SET ARCHITECTURE
MIPS uses 32-bit for each instructions. MIPS defining three
instruction formats: J-type, I-type, and R-type. R-type
instructions have 3 registers. I-type instructions have 2
registers and a 16-bit immediate. J-type (jump) instructions
have 1 register and a 26-bit immediate.
x R-type Instructions
R-type instructions have 3 operand registers: one as a
destination and two as sources.
It has six fields: rs, rt, op, rd, funct and shamt. Each field is
five or six bits, as indicated in fig. 4a.
x I-Type Instructions
I-type instructions have one immediate operand and two
register operands. It has four fields: rs, op, imm and rt, as
indicated in fig. 4b.
x J-type Instructions
J-type is used only with JMP instructions. J-type uses 26-bit
operand, addr, as indicated in fig. 4c.
Fig. 4 Instruction Format
IV. PROCESSOR DESIGN
In this research a MIPS processor is chosen in our design,
because implementation of MIPS processor is easy.
The general MIPS processor contains 49 instructions, but we
don¶t need all them, so we design a MIPS processor with only
the instruction that requires invoking the algorithm of SHA-1,
SHA224 and SHA-256 using VHDL in Xilinx ISE software
environment.
Since SHA-1, SHA224 and SHA-256 hash variable is 32-bit
so in this paper it design MIPS single-cycle of 32-bit for SHA-
1, SHA224 and SHA-256
The simple design of a 32-bit, single cycle MIPS processor
consists of two parts:
x 32-bit Datapath
x Control unit.
A. 32-bit Datapath
A 32-bit single cycle MIPS requires a 32-bit datapath. It
contains element such as registers, memories, ALUs, sign,
extenders and multiplexers.
A descriptor of each datapath is shown below:
a. PC: is a register represents the address of instruction to
execute which has 32-bit size.
b. Instruction memory: store instruction to execute hash
function and a 32-bit data as the output
c. Register file : consist of 32 register, each has 32-bit in size.
It has two read port and one write port.
d. Data memory : has one input write port (WR) and output
read port (RD).The input is written in memory which specified
by the address (A) if (WE) signal is 1 at the raising edge of
(clk) signal, each memory location has 32-bit size.
e. Sign extension copies a most significant bit of a 16-bit input
size.
f. ALUs is used in order to execute the arithmetic and logical
instruction . ALUs take alucontrol(2:0) as input and generate
corresponding function . Note that there is modify in some
instruction. Table I illustrates function that ALUs can be
performed.
B. Control unit
The control unit received from the current instruction
funct(5:0) and Opcode(31-26) of the datapath which tell it
what to do to execute the instruction.

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Fig.5 Implementation of MIPS Processor with Only Component That Hash Need
Fig .5 shows the complete design of the MIPS processor of
32-bit and table V shows all instructions required to invoke
the SHA-1, SHA-224 and SHA-256 algorithms.
V. KEYBOARD INTERFACE & VGA DISPLAY
The keyboard has a collection of keys and sends scan code.
For example, when press the Z key, the keyboard transmits its
make code (1A) and then when release it send the break code
(F0 1A).
The information transmitted 11-bit ³packet´ that start with a
start bit, 8 data bits, an odd parity bit, and a stop bit, as shown
in Fig 6.

Fig. 6 PS/2 Bus Timing Waveforms

The FPGA application have eight colour corresponding to

VGA port with a three-bit interface as shown in table VI.

In this research take White Resulting black to show the

character and screen background. The patterns of the tiles is 8-
column-by-16-row for each character since the resolution
screen is 640-by-480, 80 tiles. Fig .7 shows the ROM content
of the letter ³E´.

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Fig 7 Font pattern for the letter ³E´.

VI. RESULTS
The word ³abc´ was entered from the keyboard to the Hash
MIPS processor and the result of SHA-1, SHA-224 and SHA-
256 is displayed on VGA display which use Xilinx Spartan-
3an on-board 50 MHz clock oscillator which equates to a 20
ns period as shown in Fig 7. The test simulation for the word
³abc´ is shown in Fig. 8, Fig. 9, Fig. 10 Fig. 11 and Fig 12.

Fig 9 the massage digest of SHA-1 and time require.


Fig .8 the Hash result of a word ³abc´. Fig 10 the massage digest of SHA-256 and time require.

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Fig 11 the massage digest of SHA-224 and time require.
VII. CONCLUSION
A hash SHA-1, SHA-224 and SHA-256 was implemented
using FPGA Spartan-3an. A MIPS processor was designed
using VHDL Xilinx ISE software language with only
instructions that Hash need. This study is a starting point for
future studies and can be extended to invoke the algorithm for
SHA-1, SHA-224 and SHA-256 by using a superscalar MIPS
processor.
Fig. 12 Xilinx Spartan-3an Device Utilization Summary
REFERENCES
[1] William Stallings, Cryptography and Network Security
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[2] Volnei A. Pedroni, Circuit Design with VHDL. London,
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[3] N.Sklavos, and O.koufopavlou G.Selimis, "VLSI
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[4] C.P.Su, C.T.Huamg, and C.W.Wu M.W.Wowg, "An
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[5] A.Kakarountas, A.Miliadonis, and C.Coutis H.Michail,
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